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NSYSU

1. Chang, Jia-hao. Design of Tessellation Unit for 3D Graphic Processor.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

Tessellation shader is one of the advanced graphics rendering functions supported in state-of-the-art graphics standard applications programming interfaces such as OpenGL 4.x and DirextX 11. It provides the programming capability to divide the patches of vertex data into smaller primitives. The tessellation procedure in the graphics pipeline can be divided into three stages: tessellation control shader(TCS), tessellation primitive generation(TPG) and tessellation evaluation shader(TES). This thesis proposes an efficient design of tessellation unit to realize the fixed functions of TPG and the primitive assembly unit(PAU) that can assemble the vertices generated by tessellation into a bunch of triangles. TPG is realized by two-stage pipeline, which includes a setup stage to calculate the vertices of new concentric inner triangles and the edgeâs subdivision vector followed by the other stage to serially generate the vertices on the triangleâs edges based on the vectors obtained from the preceding stage. To avoid the expensive divider unit, the required division operation is substituted by multiplying the pre-computed reciprocal factor stored in on-chip look-up tables. One of the salient features of our proposed TPG implementation is to reduce the number of addition/subtraction operations required for generating inner triangles by two thirds by exploring the feature that the sum of three vertices of all concentric inner triangles will be the same. The entire TPG unit only requires two pairs of adders and one pair of multipliers. Its overall gate count is about 25K, and it can run up to 166.7 MHz under 90nm technology. The PAU proposed in this thesis will assemble triangles by dividing the regions of two successive concentric inner triangles into six groups of triangle fans. Advisors/Committee Members: Shen-Fu Hsiao (chair), Chuen-Yau Chen (chair), Shiann-Rong Kuang (chair), Yun-Nan Chang (committee member).

Subjects/Keywords: tessellation; tessellation primitive generation; OpenGL 4.x; tessellation unit; primitive assembly unit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, J. (2017). Design of Tessellation Unit for 3D Graphic Processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Jia-hao. “Design of Tessellation Unit for 3D Graphic Processor.” 2017. Thesis, NSYSU. Accessed November 20, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Jia-hao. “Design of Tessellation Unit for 3D Graphic Processor.” 2017. Web. 20 Nov 2019.

Vancouver:

Chang J. Design of Tessellation Unit for 3D Graphic Processor. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Nov 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang J. Design of Tessellation Unit for 3D Graphic Processor. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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