subject:(OpenCL)

1. Spliet, R. (author). A comprehensive study of Dynamic Memory Management in OpenCL kernels.

Degree: 2013, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:b26fb6be-a3e1-4968-9044-01fc6a029926

► Traditional (sequential) applications use malloc for a variety of dynamic data structures, like linked lists or trees. GPGPU is gaining attention and popularity because its… (more)

▼ Traditional (sequential) applications use malloc for a variety of dynamic data structures, like linked lists or trees. GPGPU is gaining attention and popularity because its massively-parallel architecture allows for great speed improvement for programs that can be parallelised and implemented for a platform like OpenCL. Programmers who try to port their existing sequential or even parallel program to OpenCL however will soon discover that this standard defines a subset of C with several limitations, one of which is the absence of a malloc() routine that can be called from an OpenCL kernel. This document describes the results of research towards the impact of this limitation by trying to answer the question: ``How should a kernel-side heap allocator be implemented in OpenCL?''. To give an answer to this question, two important aspects are investigated. Firstly we seek the impact from the programmers perspective by trying to understand the use-cases for which a parallel program requires an in-kernel heap allocator. We sought for a wide variety of implementations of parallel algorithms and investigated their memory usage patterns. Secondly we aim to explain the complexity of a dynamic memory allocator by taking a closer look at the limitations imposed by hardware and the OpenCL standard, and trying to find a way to implement a memory allocator in OpenCL. Based on our findings we present KMA, the first dynamic memory allocator for OpenCL kernels. Results from our use-case survey show that there are several cases where a programmer could benefit from an in-kernel malloc routine. Non-regular data-structures are required both for scheduling purposes and for holding intermediate results, and a memory allocator aids in creating these structures. Programmers usually find their way around the lack of a malloc routine, sometimes by creating something on their own that resembles part of one. Although a malloc routine thus is not a hard requirement, it can make the life of programmers a lot easier in these cases. Designing and implementing a memory allocator for OpenCL is far from trivial. Its capabilities are limited by the available hardware and language constraints: hardware does not allow for communication between the OpenCL kernel and the host system, and the OpenCL specification lacks fundamental features like mutex locks. Because of these constraints, even the data-structures we might take for granted, like full-featured doubly-linked-lists, cannot be implemented in OpenCL. We believe a memory allocator should be implemented in two layers. The bottom layer should implement behaviour like the malloc() routine found in C. On top of that data types can be implemented which may use datatype-specific restrictions to optimise the usage of the low-level memory allocator. Our KMA prototype shows that by carefully analysing the limitations of the OpenCL environment it is possible to implement an in-kernel memory allocator, be it limited by the constraints imposed by the GPU platform and OpenCL. Although using KMA comes with a… Advisors/Committee Members: Varbanescu, A.L. (mentor).

Subjects/Keywords: OpenCL

…lost on transfer. 2.4 OpenCL With the introduction of platforms like Cuda[36]… …and OpenCL[27], the GPUs massive-parallel computational power became available for… …execute on the target device. The difference between Cuda and OpenCL is both of technical and… …OpenCL on the other hand is an open standard driven by most major players in the industry… …including AMD, NVIDIA, Intel, ARM, Apple and many others. One of the key properties of OpenCL is…

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APA (6^th Edition):

Spliet, R. (. (2013). A comprehensive study of Dynamic Memory Management in OpenCL kernels. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:b26fb6be-a3e1-4968-9044-01fc6a029926

Chicago Manual of Style (16^th Edition):

Spliet, R (author). “A comprehensive study of Dynamic Memory Management in OpenCL kernels.” 2013. Masters Thesis, Delft University of Technology. Accessed February 27, 2021. http://resolver.tudelft.nl/uuid:b26fb6be-a3e1-4968-9044-01fc6a029926.

MLA Handbook (7^th Edition):

Spliet, R (author). “A comprehensive study of Dynamic Memory Management in OpenCL kernels.” 2013. Web. 27 Feb 2021.

Vancouver:

Spliet R(. A comprehensive study of Dynamic Memory Management in OpenCL kernels. [Internet] [Masters thesis]. Delft University of Technology; 2013. [cited 2021 Feb 27]. Available from: http://resolver.tudelft.nl/uuid:b26fb6be-a3e1-4968-9044-01fc6a029926.

Council of Science Editors:

Spliet R(. A comprehensive study of Dynamic Memory Management in OpenCL kernels. [Masters Thesis]. Delft University of Technology; 2013. Available from: http://resolver.tudelft.nl/uuid:b26fb6be-a3e1-4968-9044-01fc6a029926

University of Alberta

2. Xunhao, Li. Jit4OpenCL: a compiler from Python to OpenCL.

Degree: MS, Department of Computing Science, 2010, University of Alberta

URL: https://era.library.ualberta.ca/files/1v53jx087

► Heterogeneous computing platforms that use GPUs and CPUs in tandem for computation have become an important choice to build low-cost high-performance computing platforms. The computing… (more)

Subjects/Keywords: Python; compiler; OpenCL

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APA (6^th Edition):

Xunhao, L. (2010). Jit4OpenCL: a compiler from Python to OpenCL. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/1v53jx087

Chicago Manual of Style (16^th Edition):

Xunhao, Li. “Jit4OpenCL: a compiler from Python to OpenCL.” 2010. Masters Thesis, University of Alberta. Accessed February 27, 2021. https://era.library.ualberta.ca/files/1v53jx087.

MLA Handbook (7^th Edition):

Xunhao, Li. “Jit4OpenCL: a compiler from Python to OpenCL.” 2010. Web. 27 Feb 2021.

Vancouver:

Xunhao L. Jit4OpenCL: a compiler from Python to OpenCL. [Internet] [Masters thesis]. University of Alberta; 2010. [cited 2021 Feb 27]. Available from: https://era.library.ualberta.ca/files/1v53jx087.

Council of Science Editors:

Xunhao L. Jit4OpenCL: a compiler from Python to OpenCL. [Masters Thesis]. University of Alberta; 2010. Available from: https://era.library.ualberta.ca/files/1v53jx087

University of Debrecen

3. Jánosi, Zoltán. Alkalmazásfejlesztés GPU-ra .

Degree: DE – TEK – Informatikai Kar, 2013, University of Debrecen

URL: http://hdl.handle.net/2437/167193

► Az OpenCL a heterogén programozási platformok kihasználásának egyik legjobb eszköze. Ezen szakdolgozat bemutatja hogyan működik az OpenCL , illetve, hogy miként használhatóak legoptimálisabban az általa… (more)

Subjects/Keywords: OpenCL; GPU; GPGPU

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APA (6^th Edition):

Jánosi, Z. (2013). Alkalmazásfejlesztés GPU-ra . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/167193

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Jánosi, Zoltán. “Alkalmazásfejlesztés GPU-ra .” 2013. Thesis, University of Debrecen. Accessed February 27, 2021. http://hdl.handle.net/2437/167193.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Jánosi, Zoltán. “Alkalmazásfejlesztés GPU-ra .” 2013. Web. 27 Feb 2021.

Vancouver:

Jánosi Z. Alkalmazásfejlesztés GPU-ra . [Internet] [Thesis]. University of Debrecen; 2013. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/2437/167193.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jánosi Z. Alkalmazásfejlesztés GPU-ra . [Thesis]. University of Debrecen; 2013. Available from: http://hdl.handle.net/2437/167193

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Linköping University

4. Anders, Söderholm. GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework.

Degree: Software and Systems, 2016, Linköping University

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-127479

► Today's computer systems often contains several different processing units aside from the CPU. Among these the GPU is a very common processing unit with… (more)

Subjects/Keywords: GPU; OpenCL; algorithms

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APA (6^th Edition):

Anders, S. (2016). GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-127479

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Anders, Söderholm. “GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework.” 2016. Thesis, Linköping University. Accessed February 27, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-127479.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Anders, Söderholm. “GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework.” 2016. Web. 27 Feb 2021.

Vancouver:

Anders S. GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework. [Internet] [Thesis]. Linköping University; 2016. [cited 2021 Feb 27]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-127479.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Anders S. GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework. [Thesis]. Linköping University; 2016. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-127479

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Toronto

5. Chin, Stephen Alexander. Reusable OpenCL FPGA Infrastructure.

Degree: 2012, University of Toronto

URL: http://hdl.handle.net/1807/32567

►

OpenCL has emerged as a standard programming model for heterogeneous systems. Recent work combining OpenCL and FPGAs has focused on high-level synthesis. Building a complete… (more)

Subjects/Keywords: FPGA; OpenCL; SDRAM; computer architecture

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APA (6^th Edition):

Chin, S. A. (2012). Reusable OpenCL FPGA Infrastructure. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/32567

Chicago Manual of Style (16^th Edition):

Chin, Stephen Alexander. “Reusable OpenCL FPGA Infrastructure.” 2012. Masters Thesis, University of Toronto. Accessed February 27, 2021. http://hdl.handle.net/1807/32567.

MLA Handbook (7^th Edition):

Chin, Stephen Alexander. “Reusable OpenCL FPGA Infrastructure.” 2012. Web. 27 Feb 2021.

Vancouver:

Chin SA. Reusable OpenCL FPGA Infrastructure. [Internet] [Masters thesis]. University of Toronto; 2012. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1807/32567.

Council of Science Editors:

Chin SA. Reusable OpenCL FPGA Infrastructure. [Masters Thesis]. University of Toronto; 2012. Available from: http://hdl.handle.net/1807/32567

Northeastern University

6. Momeni, Amir. Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach.

Degree: PhD, Department of Electrical and Computer Engineering, 2017, Northeastern University

URL: http://hdl.handle.net/2047/D20254348

► Field Programmable Gate Arrays (FPGAs) are one major class of architectures commonly used in parallel computing systems. FPGAs provide a massive number (i.e., millions) programmable… (more)

▼ Field Programmable Gate Arrays (FPGAs) are one major class of architectures commonly used in parallel computing systems. FPGAs provide a massive number (i.e., millions) programmable logic blocks and I/O cells, as well as programmable interconnects, which can be configured for a particular application. This reconfigurable architecture is flexible and power efficient, and potentially, provides better floating-point operations per watt rates versus general purpose architectures, such as CPUs and GPUs. However, programming an FPGA can be challenging and time-consuming, requiring hardware description language (HDL) experience and digital design expertise. High-level synthesis (HLS) tools have been designed to ease the FPGA programming task by generating HDL (e.g., Verilog or VHDL) codes from high-level languages (e.g., C/C++, OpenCL). Inparticular, there have been recent developments in OpenCL-based HLS tools (OpenCL-HLS) to enable programmers to construct a customized data-path that can best match a parallel application, relieving the programmer of many implementation details.; Given the availability of OpenCL-HLS tools for FPGAs creates many new opportunities, as well presents new challenges, in order to fully utilize these new capabilities. The primary challenge lies in the difference between the OpenCL parallelism semantics and parallel execution model on FPGA devices. OpenCL is primarily developed for GPU devices, which have many spatially-parallel cores. We need to explore new classes of optimization in order to fully leverage OpenCL execution on FPGAs.; This thesis explores and addresses OpenCL-HLS challenges using three different approaches. In the first approach we consider source-level optimization, where we evaluate the impact of OpenCL source-level decisions on the resulting data-path and FPGA execution efficiency. Our aim is to analyze the correlation between OpenCL parallelism semantics and parallel execution on FPGA devices. We want to be able to guide OpenCL programmers to develop optimized code on an FPGA. We study the impact of different grains (fine and coarse-grained), and forms of parallelism (spatial and temporal), exposed by OpenCL on the generated data-path. We also study the efficiency of the OpenCL Pipe semantic when targeting an FPGA.; In the second approach called synthesis optimization, we introduce novel optimization techniques for synthesis of OpenCL kernels targeted for FPGA devices. We propose a Hardware Thread Reordering (HTR) technique to improve the performance of irregular kernels. The goal is to guide OpenCL-HLS tool developers to design a more efficient data-path for a given OpenCL kernel. Using our HTR technique, we achieve up to a 11X speed-up, with less than a 2X increase in resource utilization.; In our third approach called architectural approach, we propose a novel device named an FP-GPU (field-programmable GPU), a new class of architecture that utilizes the benefits of both GPU and FPGA architectures. FP-GPU utilizes the GPU memory hierarchy, but introduces a novel thread…

Subjects/Keywords: FPGA; GPU; OpenCL; parallelism

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APA (6^th Edition):

Momeni, A. (2017). Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20254348

Chicago Manual of Style (16^th Edition):

Momeni, Amir. “Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach.” 2017. Doctoral Dissertation, Northeastern University. Accessed February 27, 2021. http://hdl.handle.net/2047/D20254348.

MLA Handbook (7^th Edition):

Momeni, Amir. “Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach.” 2017. Web. 27 Feb 2021.

Vancouver:

Momeni A. Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach. [Internet] [Doctoral dissertation]. Northeastern University; 2017. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/2047/D20254348.

Council of Science Editors:

Momeni A. Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach. [Doctoral Dissertation]. Northeastern University; 2017. Available from: http://hdl.handle.net/2047/D20254348

University of Debrecen

7. Erdei, Tímea. Grafikus kártyák alkalmazása a kriptográfiában .

Degree: DE – TEK – Informatikai Kar, 2011, University of Debrecen

URL: http://hdl.handle.net/2437/95296

Az OpenCL programozás röviden és egy program leírása. Advisors/Committee Members: Pethő, Attila (advisor).

Subjects/Keywords: GPU; OpenCL

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APA (6^th Edition):

Erdei, T. (2011). Grafikus kártyák alkalmazása a kriptográfiában . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/95296

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Erdei, Tímea. “Grafikus kártyák alkalmazása a kriptográfiában .” 2011. Thesis, University of Debrecen. Accessed February 27, 2021. http://hdl.handle.net/2437/95296.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Erdei, Tímea. “Grafikus kártyák alkalmazása a kriptográfiában .” 2011. Web. 27 Feb 2021.

Vancouver:

Erdei T. Grafikus kártyák alkalmazása a kriptográfiában . [Internet] [Thesis]. University of Debrecen; 2011. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/2437/95296.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Erdei T. Grafikus kártyák alkalmazása a kriptográfiában . [Thesis]. University of Debrecen; 2011. Available from: http://hdl.handle.net/2437/95296

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Delft University of Technology

8. Van der Wijst, H. (author). An Accelerator based on the ?-VEX Processor: An Exploration using OpenCL.

Degree: 2015, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:3f184afb-241d-4d54-827d-75fcd59211a5

►

In recent years the use of co-processors to accelerate specific tasks is becoming more common. To simplify the use of these accelerators in software, the… (more)

Subjects/Keywords: ?-VEX; rVEX; OpenCL; pocl; accelerator

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APA (6^th Edition):

Van der Wijst, H. (. (2015). An Accelerator based on the ?-VEX Processor: An Exploration using OpenCL. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:3f184afb-241d-4d54-827d-75fcd59211a5

Chicago Manual of Style (16^th Edition):

Van der Wijst, H (author). “An Accelerator based on the ?-VEX Processor: An Exploration using OpenCL.” 2015. Masters Thesis, Delft University of Technology. Accessed February 27, 2021. http://resolver.tudelft.nl/uuid:3f184afb-241d-4d54-827d-75fcd59211a5.

MLA Handbook (7^th Edition):

Van der Wijst, H (author). “An Accelerator based on the ?-VEX Processor: An Exploration using OpenCL.” 2015. Web. 27 Feb 2021.

Vancouver:

Van der Wijst H(. An Accelerator based on the ?-VEX Processor: An Exploration using OpenCL. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2021 Feb 27]. Available from: http://resolver.tudelft.nl/uuid:3f184afb-241d-4d54-827d-75fcd59211a5.

Council of Science Editors:

Van der Wijst H(. An Accelerator based on the ?-VEX Processor: An Exploration using OpenCL. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:3f184afb-241d-4d54-827d-75fcd59211a5

Delft University of Technology

9. Berger, M.E.R. (author). High Performance Histograms on SIMT and SIMD Architectures.

Degree: 2015, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:38dd2dbd-9dca-4a27-8829-06ea069af6b7

►

Using the histogram procedure, this work studies performance determining factors in computing in parallel on SIMD and SIMT devices. Modern graphics pro-cessing units (GPUs) support… (more)

Subjects/Keywords: GPU; CUDA; OpenCL; histogram; atomics

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APA (6^th Edition):

Berger, M. E. R. (. (2015). High Performance Histograms on SIMT and SIMD Architectures. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:38dd2dbd-9dca-4a27-8829-06ea069af6b7

Chicago Manual of Style (16^th Edition):

Berger, M E R (author). “High Performance Histograms on SIMT and SIMD Architectures.” 2015. Masters Thesis, Delft University of Technology. Accessed February 27, 2021. http://resolver.tudelft.nl/uuid:38dd2dbd-9dca-4a27-8829-06ea069af6b7.

MLA Handbook (7^th Edition):

Berger, M E R (author). “High Performance Histograms on SIMT and SIMD Architectures.” 2015. Web. 27 Feb 2021.

Vancouver:

Berger MER(. High Performance Histograms on SIMT and SIMD Architectures. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2021 Feb 27]. Available from: http://resolver.tudelft.nl/uuid:38dd2dbd-9dca-4a27-8829-06ea069af6b7.

Council of Science Editors:

Berger MER(. High Performance Histograms on SIMT and SIMD Architectures. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:38dd2dbd-9dca-4a27-8829-06ea069af6b7

Delft University of Technology

10. Hemminga, S. (author). Programmability Analysis of Image Processing Kernels on Multi-/Many-core Platforms.

Degree: 2011, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:7efbc439-7a08-40f4-8a07-94879de2eba7

►

In the last few years, the computing industry has changed its course from ever higher clock speeds to multi- and many-core systems. These new parallel… (more)

Subjects/Keywords: OpenCL; GPU; GPGPU; Cell BE

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APA (6^th Edition):

Hemminga, S. (. (2011). Programmability Analysis of Image Processing Kernels on Multi-/Many-core Platforms. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:7efbc439-7a08-40f4-8a07-94879de2eba7

Chicago Manual of Style (16^th Edition):

Hemminga, S (author). “Programmability Analysis of Image Processing Kernels on Multi-/Many-core Platforms.” 2011. Masters Thesis, Delft University of Technology. Accessed February 27, 2021. http://resolver.tudelft.nl/uuid:7efbc439-7a08-40f4-8a07-94879de2eba7.

MLA Handbook (7^th Edition):

Hemminga, S (author). “Programmability Analysis of Image Processing Kernels on Multi-/Many-core Platforms.” 2011. Web. 27 Feb 2021.

Vancouver:

Hemminga S(. Programmability Analysis of Image Processing Kernels on Multi-/Many-core Platforms. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2021 Feb 27]. Available from: http://resolver.tudelft.nl/uuid:7efbc439-7a08-40f4-8a07-94879de2eba7.

Council of Science Editors:

Hemminga S(. Programmability Analysis of Image Processing Kernels on Multi-/Many-core Platforms. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:7efbc439-7a08-40f4-8a07-94879de2eba7

University of Windsor

11. Bussiere, Alexander. OpenCL Implimentation of LiDAR Data Processing.

Degree: MA, Electrical and Computer Engineering, 2014, University of Windsor

URL: https://scholar.uwindsor.ca/etd/5243

► When designing a safety system, the faster the response time, the greater the reflexes of the system to hazards. As more commercial interest in… (more)

Subjects/Keywords: Autonomous; LiDAR; OpenCL; Robotics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Bussiere, A. (2014). OpenCL Implimentation of LiDAR Data Processing. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5243

Chicago Manual of Style (16^th Edition):

Bussiere, Alexander. “OpenCL Implimentation of LiDAR Data Processing.” 2014. Masters Thesis, University of Windsor. Accessed February 27, 2021. https://scholar.uwindsor.ca/etd/5243.

MLA Handbook (7^th Edition):

Bussiere, Alexander. “OpenCL Implimentation of LiDAR Data Processing.” 2014. Web. 27 Feb 2021.

Vancouver:

Bussiere A. OpenCL Implimentation of LiDAR Data Processing. [Internet] [Masters thesis]. University of Windsor; 2014. [cited 2021 Feb 27]. Available from: https://scholar.uwindsor.ca/etd/5243.

Council of Science Editors:

Bussiere A. OpenCL Implimentation of LiDAR Data Processing. [Masters Thesis]. University of Windsor; 2014. Available from: https://scholar.uwindsor.ca/etd/5243

Clemson University

12. Rayrikar, Bhushan. Parallel Implementation of the Singular Value Decomposition using OpenCL.

Degree: MS, Computer Engineering, 2011, Clemson University

URL: https://tigerprints.clemson.edu/all_theses/1292

► General-Purpose Graphics Processing Units (GPGPUs) have massively parallel computational capabilities. Low cost and ease of programming make them a popular choice over other parallel architectures… (more)

▼ General-Purpose Graphics Processing Units (GPGPUs) have massively parallel computational capabilities. Low cost and ease of programming make them a popular choice over other parallel architectures such as large clusters and accelerators such as Field-Programmable Gate Arrays (FPGAs). Mature programming frameworks for GPGPUs, such as CUDA from Nvidia and OpenCL from the Khronos Group, reduce the learning curve and development time for programming GPGPU architectures. OpenCL, a relatively new industry standard for parallel computing makes it possible to write a single program for heterogeneous platforms that is portable across multiple platforms including GPGPUs and multi-core processors with minimal coding modifications. GPGPU architectures have been successfully used for accelerating many computationally expensive problems including many linear algebra algorithms, which are inherently parallel in nature. Singular Value Decomposition (SVD) is a computationally expensive linear algebra matrix decomposition technique that has many applications including data compression, facial recognition, and solving a system of equations. As the dimensions of the matrix increase, SVD computation becomes increasingly time consuming. Since SVD is a major part of some algorithms such as Eigenfaces (a facial recognition algorithm based on Principle Component Analysis), the overall runtime for these algorithms depends heavily on the execution time of SVD. Hence, to implement efficient applications based on SVD, for example real-time facial recognition, it is desirable to accelerate the SVD algorithm. In this work, a parallel implementation of Singular Value Decomposition is discussed in detail. It uses many basic linear algebra techniques such as matrix-vector multiplication, vector norms and vector outer products. This work focuses on the implementation techniques, optimization methods (specifically for a GPGPU implementation) and their effect on the overall performance of the algorithm. We present the performance analysis of this algorithm on NVIDIA's Tesla C2050 GPU as compared to the single-threaded serial implementation executed on an Intel 2.66 GHz Q9450 processor. We report speedups up to 20x for the parallel SVD computation. The results discussed in this thesis demonstrate the potential of the computational resources available with GPGPUs. Advisors/Committee Members: Smith, Melissa, Birchfield , Stanley, Gowdy , John.

Subjects/Keywords: GPGPU; OpenCL; SVD; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Rayrikar, B. (2011). Parallel Implementation of the Singular Value Decomposition using OpenCL. (Masters Thesis). Clemson University. Retrieved from https://tigerprints.clemson.edu/all_theses/1292

Chicago Manual of Style (16^th Edition):

Rayrikar, Bhushan. “Parallel Implementation of the Singular Value Decomposition using OpenCL.” 2011. Masters Thesis, Clemson University. Accessed February 27, 2021. https://tigerprints.clemson.edu/all_theses/1292.

MLA Handbook (7^th Edition):

Rayrikar, Bhushan. “Parallel Implementation of the Singular Value Decomposition using OpenCL.” 2011. Web. 27 Feb 2021.

Vancouver:

Rayrikar B. Parallel Implementation of the Singular Value Decomposition using OpenCL. [Internet] [Masters thesis]. Clemson University; 2011. [cited 2021 Feb 27]. Available from: https://tigerprints.clemson.edu/all_theses/1292.

Council of Science Editors:

Rayrikar B. Parallel Implementation of the Singular Value Decomposition using OpenCL. [Masters Thesis]. Clemson University; 2011. Available from: https://tigerprints.clemson.edu/all_theses/1292

Universidad de Chile

13. Pefaur Pumarino, José Tomás. Optimización de software de visualización y detección de patrones de drenaje y terrazas fluviales en superficies de terreno.

Degree: 2016, Universidad de Chile

URL: http://repositorio.uchile.cl/handle/2250/142813

► La Geomorfología fluvial corresponde al estudio de los procesos de formación y sedimentación de los ríos, y de su interacción con el entorno, lo que… (more)

▼ La Geomorfología fluvial corresponde al estudio de los procesos de formación y sedimentación de los ríos, y de su interacción con el entorno, lo que entrega información sobre la "historia de vida" de un terreno. En este contexto, existen dos elementos de estudio interesantes: las redes de drenaje y las terrazas fluviales. Runnel es un software que tiene por objetivo visualizar y detectar patrones de drenaje y terrazas fluviales sobre terrenos representados por grillas o triangulaciones de éstas. Si bien el funcionamiento de Runnel es correcto, éste tiene un gran problema: el tiempo de ejecución de sus principales algoritmos. A medida que el tamaño del terreno crece, el tiempo de ejecución aumenta considerablemente. Con el fin de mejorar este problema, se decidió paralelizar los algoritmos de detección de redes de drenaje: Peucker, Callaghan, RWFlood y Ángulo Diedro. Al mismo tiempo, se decidió implementar una triangulación simplificada, la cual disminuye el número de triángulos, y en consecuencia, se disminuye el tiempo de ejecución de los algoritmos que usan la triangulación. Para lograr la paralelización se utilizó OpenCL, herramienta que permite la ejecución de un código paralelo tanto en GPU como en CPU de forma indistinguible. Para la triangulación simplificada se utilizó un algoritmo basado en la eliminación de uno de los vértices de aquellos triángulos que cumplen una condición predeterminada. Como resultado de la paralelización se obtuvieron mejoras significativas con los algoritmos de Peucker (speed-up mínimo: 1.19 y speed-up máximo: 13.63), Callaghan (speed-up mínimo: 5.87 y speed-up máximo: 19.82) y Ángulo Diedro (speed-up mínimo: 1.43 y speed-up máximo: 23.53). La triangulación simplificada también entregó mejoras en rendimiento, pero con menor impacto que la paralelización (speed-up mínimo: 1.14 y speed-up máximo: 1.94). El único algoritmo que no resultó en mejoras en su tiempo de ejecución (en la mayoría de los casos de prueba) fue el algoritmo RWFlood (speed-up mínimo: 0.16 y speed-up máximo: 2.93). Junto con el desarrollo de los algoritmos paralelos se adquirió conocimiento sobre las diferencias de rendimiento de una CPU con una GPU. Se tuvo que ahondar en la arquitectura de cada una y reconocer el tipo de problema que cada una puede resolver de manera óptima. Se propone como trabajo futuro solucionar el uso excesivo de la memoria en la triangulación, analizar del impacto de la triangulación simplificada en los terrenos, solucionar el problema del tiempo de ejecución de RWFlood y paralelizar otros algoritmos.

Subjects/Keywords: Geomorfología fluvial; Triangulación; Drenaje; opencl

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APA (6^th Edition):

Pefaur Pumarino, J. T. (2016). Optimización de software de visualización y detección de patrones de drenaje y terrazas fluviales en superficies de terreno. (Thesis). Universidad de Chile. Retrieved from http://repositorio.uchile.cl/handle/2250/142813

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Pefaur Pumarino, José Tomás. “Optimización de software de visualización y detección de patrones de drenaje y terrazas fluviales en superficies de terreno.” 2016. Thesis, Universidad de Chile. Accessed February 27, 2021. http://repositorio.uchile.cl/handle/2250/142813.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Pefaur Pumarino, José Tomás. “Optimización de software de visualización y detección de patrones de drenaje y terrazas fluviales en superficies de terreno.” 2016. Web. 27 Feb 2021.

Vancouver:

Pefaur Pumarino JT. Optimización de software de visualización y detección de patrones de drenaje y terrazas fluviales en superficies de terreno. [Internet] [Thesis]. Universidad de Chile; 2016. [cited 2021 Feb 27]. Available from: http://repositorio.uchile.cl/handle/2250/142813.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pefaur Pumarino JT. Optimización de software de visualización y detección de patrones de drenaje y terrazas fluviales en superficies de terreno. [Thesis]. Universidad de Chile; 2016. Available from: http://repositorio.uchile.cl/handle/2250/142813

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Virginia Tech

14. Shagrithaya, Kavya Subraya. Enabling Development of OpenCL Applications on FPGA platforms.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

URL: http://hdl.handle.net/10919/34669

► FPGAs can potentially deliver tremendous acceleration in high-performance server and em- bedded computing applications. Whether used to augment a processor or as a stand-alone device,… (more)

Subjects/Keywords: FPGA; AutoESL; OpenCL; Convey; HPC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Shagrithaya, K. S. (2012). Enabling Development of OpenCL Applications on FPGA platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34669

Chicago Manual of Style (16^th Edition):

Shagrithaya, Kavya Subraya. “Enabling Development of OpenCL Applications on FPGA platforms.” 2012. Masters Thesis, Virginia Tech. Accessed February 27, 2021. http://hdl.handle.net/10919/34669.

MLA Handbook (7^th Edition):

Shagrithaya, Kavya Subraya. “Enabling Development of OpenCL Applications on FPGA platforms.” 2012. Web. 27 Feb 2021.

Vancouver:

Shagrithaya KS. Enabling Development of OpenCL Applications on FPGA platforms. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/10919/34669.

Council of Science Editors:

Shagrithaya KS. Enabling Development of OpenCL Applications on FPGA platforms. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/34669

University of Dayton

15. DeMange, Ashley. OpenCL Acceleration of the KLT Feature Tracker on an FPGA.

Degree: MSin Computer Engineering, Electrical and Computer Engineering, 2017, University of Dayton

URL: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501872686207408

► The Kunade-Lucas-Tomasi (KLT) algorithm is a well known feature tracker that has been implemented on both CPUs and GPUs. When tracking large numbers of features… (more)

Subjects/Keywords: Computer Engineering; KLT; FPGA; OpenCL

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APA (6^th Edition):

DeMange, A. (2017). OpenCL Acceleration of the KLT Feature Tracker on an FPGA. (Masters Thesis). University of Dayton. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501872686207408

Chicago Manual of Style (16^th Edition):

DeMange, Ashley. “OpenCL Acceleration of the KLT Feature Tracker on an FPGA.” 2017. Masters Thesis, University of Dayton. Accessed February 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501872686207408.

MLA Handbook (7^th Edition):

DeMange, Ashley. “OpenCL Acceleration of the KLT Feature Tracker on an FPGA.” 2017. Web. 27 Feb 2021.

Vancouver:

DeMange A. OpenCL Acceleration of the KLT Feature Tracker on an FPGA. [Internet] [Masters thesis]. University of Dayton; 2017. [cited 2021 Feb 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501872686207408.

Council of Science Editors:

DeMange A. OpenCL Acceleration of the KLT Feature Tracker on an FPGA. [Masters Thesis]. University of Dayton; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501872686207408

Brno University of Technology

16. Šnobl, Pavel. Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/61853

► This master's thesis deals with the support for compilation and execution of programs written using OpenCL framework on embedded systems. OpenCL is a system for… (more)

Subjects/Keywords: OpenCL; LLVM; Codasip; SIMD; VLIW; OpenCL; LLVM; Codasip; SIMD; VLIW

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APA (6^th Edition):

Šnobl, P. (2019). Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/61853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Šnobl, Pavel. “Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems.” 2019. Thesis, Brno University of Technology. Accessed February 27, 2021. http://hdl.handle.net/11012/61853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Šnobl, Pavel. “Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems.” 2019. Web. 27 Feb 2021.

Vancouver:

Šnobl P. Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/11012/61853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Šnobl P. Překlad OpenCL aplikací pro vestavěné systémy: Compilation of OpenCL Applications for Embedded Systems. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/61853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

17. Jiránek, Karel. Generování hesel na základě pravidel: Rule-Based Password Generation.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/69706

► The thesis describes password generation based on rules and parallel generation of passwords on GPU with OpenCL framework. The thesis addresses the design of a… (more)

Subjects/Keywords: Generování hesel; Fitcrack; kryptografie; OpenCL; Password generation; Fitcrack; cryptography; OpenCL

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APA (6^th Edition):

Jiránek, K. (2019). Generování hesel na základě pravidel: Rule-Based Password Generation. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/69706

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Jiránek, Karel. “Generování hesel na základě pravidel: Rule-Based Password Generation.” 2019. Thesis, Brno University of Technology. Accessed February 27, 2021. http://hdl.handle.net/11012/69706.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Jiránek, Karel. “Generování hesel na základě pravidel: Rule-Based Password Generation.” 2019. Web. 27 Feb 2021.

Vancouver:

Jiránek K. Generování hesel na základě pravidel: Rule-Based Password Generation. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/11012/69706.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jiránek K. Generování hesel na základě pravidel: Rule-Based Password Generation. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/69706

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Alberta

18. Maier, Andrew J. Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications.

Degree: MS, Department of Electrical and Computer Engineering, 2016, University of Alberta

URL: https://era.library.ualberta.ca/files/cjd472w72q

► Open Computing Language (OpenCL) is a high-level language that allows developers to produce portable software for heterogeneous parallel computing platforms. OpenCL is available for a… (more)

Subjects/Keywords: OpenCL; LDPC; FPGA; Heterogeneous Programming; Parallel Programming

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APA (6^th Edition):

Maier, A. J. (2016). Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/cjd472w72q

Chicago Manual of Style (16^th Edition):

Maier, Andrew J. “Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications.” 2016. Masters Thesis, University of Alberta. Accessed February 27, 2021. https://era.library.ualberta.ca/files/cjd472w72q.

MLA Handbook (7^th Edition):

Maier, Andrew J. “Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications.” 2016. Web. 27 Feb 2021.

Vancouver:

Maier AJ. Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications. [Internet] [Masters thesis]. University of Alberta; 2016. [cited 2021 Feb 27]. Available from: https://era.library.ualberta.ca/files/cjd472w72q.

Council of Science Editors:

Maier AJ. Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications. [Masters Thesis]. University of Alberta; 2016. Available from: https://era.library.ualberta.ca/files/cjd472w72q

University of Toronto

19. Diop, Tahir. Regression Modelling of Power Consumption for Heterogeneous Processors.

Degree: 2013, University of Toronto

URL: http://hdl.handle.net/1807/42818

►

This thesis is composed of two parts, that relate to both parallel and heterogeneous processing. The first describes DistCL, a distributed OpenCL framework that allows… (more)

Subjects/Keywords: Power Modelling; OpenCL; Simulation; Benchmarking; 0544; 0984

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APA (6^th Edition):

Diop, T. (2013). Regression Modelling of Power Consumption for Heterogeneous Processors. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/42818

Chicago Manual of Style (16^th Edition):

Diop, Tahir. “Regression Modelling of Power Consumption for Heterogeneous Processors.” 2013. Masters Thesis, University of Toronto. Accessed February 27, 2021. http://hdl.handle.net/1807/42818.

MLA Handbook (7^th Edition):

Diop, Tahir. “Regression Modelling of Power Consumption for Heterogeneous Processors.” 2013. Web. 27 Feb 2021.

Vancouver:

Diop T. Regression Modelling of Power Consumption for Heterogeneous Processors. [Internet] [Masters thesis]. University of Toronto; 2013. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1807/42818.

Council of Science Editors:

Diop T. Regression Modelling of Power Consumption for Heterogeneous Processors. [Masters Thesis]. University of Toronto; 2013. Available from: http://hdl.handle.net/1807/42818

University of Toronto

20. Gurfinkel, Steven. The Distribution of OpenCL Kernel Execution Across Multiple Devices.

Degree: 2014, University of Toronto

URL: http://hdl.handle.net/1807/67879

►

Many computer systems now include both CPUs and programmable GPUs. OpenCL, a new programming framework, can program individual CPUs or GPUs; however, distributing a problem… (more)

Subjects/Keywords: Distributed; GPGPU; GPU; Heterogeneous; OpenCL; 0464

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Gurfinkel, S. (2014). The Distribution of OpenCL Kernel Execution Across Multiple Devices. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/67879

Chicago Manual of Style (16^th Edition):

Gurfinkel, Steven. “The Distribution of OpenCL Kernel Execution Across Multiple Devices.” 2014. Masters Thesis, University of Toronto. Accessed February 27, 2021. http://hdl.handle.net/1807/67879.

MLA Handbook (7^th Edition):

Gurfinkel, Steven. “The Distribution of OpenCL Kernel Execution Across Multiple Devices.” 2014. Web. 27 Feb 2021.

Vancouver:

Gurfinkel S. The Distribution of OpenCL Kernel Execution Across Multiple Devices. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1807/67879.

Council of Science Editors:

Gurfinkel S. The Distribution of OpenCL Kernel Execution Across Multiple Devices. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/67879

University of Toronto

21. Ahmed, Taneem. OpenCL Framework for a CPU, GPU, and FPGA Platform.

Degree: 2011, University of Toronto

URL: http://hdl.handle.net/1807/30149

►

With the availability of multi-core processors, high capacity FPGAs, and GPUs, a heterogeneous platform with tremendous raw computing capacity can be constructed consisting of any… (more)

Subjects/Keywords: FPGA; Heterogeneous Computing; OpenCL; Reconfigurable Computing; 0544

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ahmed, T. (2011). OpenCL Framework for a CPU, GPU, and FPGA Platform. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/30149

Chicago Manual of Style (16^th Edition):

Ahmed, Taneem. “OpenCL Framework for a CPU, GPU, and FPGA Platform.” 2011. Masters Thesis, University of Toronto. Accessed February 27, 2021. http://hdl.handle.net/1807/30149.

MLA Handbook (7^th Edition):

Ahmed, Taneem. “OpenCL Framework for a CPU, GPU, and FPGA Platform.” 2011. Web. 27 Feb 2021.

Vancouver:

Ahmed T. OpenCL Framework for a CPU, GPU, and FPGA Platform. [Internet] [Masters thesis]. University of Toronto; 2011. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1807/30149.

Council of Science Editors:

Ahmed T. OpenCL Framework for a CPU, GPU, and FPGA Platform. [Masters Thesis]. University of Toronto; 2011. Available from: http://hdl.handle.net/1807/30149

Universidade Nova

22. Rogeiro, João Pedro Martins. Geometry based visualization with OpenCL.

Degree: 2011, Universidade Nova

URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7951

►

Dissertação para obtenção do Grau de Mestre em Engenharia Informática

This work targets the design and implementation of an isosurface extraction solution capable of handling… (more)

Subjects/Keywords: Isosurface extraction; Volume visualization; Marching cubes; OpenCL

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APA (6^th Edition):

Rogeiro, J. P. M. (2011). Geometry based visualization with OpenCL. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7951

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Rogeiro, João Pedro Martins. “Geometry based visualization with OpenCL.” 2011. Thesis, Universidade Nova. Accessed February 27, 2021. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7951.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Rogeiro, João Pedro Martins. “Geometry based visualization with OpenCL.” 2011. Web. 27 Feb 2021.

Vancouver:

Rogeiro JPM. Geometry based visualization with OpenCL. [Internet] [Thesis]. Universidade Nova; 2011. [cited 2021 Feb 27]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7951.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rogeiro JPM. Geometry based visualization with OpenCL. [Thesis]. Universidade Nova; 2011. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7951

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade Nova

23. Marques, Ricardo Jorge dos Santos. Algorithmic skeleton framework for the orchestration of GPU computations.

Degree: 2012, Universidade Nova

URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8382

►

Dissertação para obtenção do Grau de Mestre em Engenharia Informática

The Graphics Processing Unit (GPU) is gaining popularity as a co-processor to the Central Processing… (more)

▼

Dissertação para obtenção do Grau de Mestre em Engenharia Informática

The Graphics Processing Unit (GPU) is gaining popularity as a co-processor to the Central Processing Unit (CPU), due to its ability to surpass the latter’s performance in certain application fields. Nonetheless, harnessing the GPU’s capabilities is a non-trivial exercise that requires good knowledge of parallel programming. Thus, providing ways to extract such computational power has become an emerging research topic. In this context, there have been several proposals in the field of GPGPU (Generalpurpose Computation on Graphics Processing Unit) development. However, most of these still offer a low-level abstraction of the GPU computing model, forcing the developer to adapt application computations in accordance with the SPMD model, as well as to orchestrate the low-level details of the execution. On the other hand, the higher-level approaches have limitations that prevent the full exploitation of GPUs when the purpose goes beyond the simple offloading of a kernel. To this extent, our proposal builds on the recent trend of applying the notion of algorithmic patterns (skeletons) to GPU computing. We propose Marrow, a high-level algorithmic skeleton framework that expands the set of skeletons currently available in this field. Marrow’s skeletons orchestrate the execution of OpenCL computations and introduce optimizations that overlap communication and computation, thus conjoining programming simplicity with performance gains in many application scenarios. Additionally, these skeletons can be combined (nested) to create more complex applications. We evaluated the proposed constructs by confronting them against the comparable skeleton libraries for GPGPU, as well as against hand-tuned OpenCL programs. The results are favourable, indicating that Marrow’s skeletons are both flexible and efficient in the context of GPU computing.

FCT-MCTES - financing the equipment

Advisors/Committee Members: Paulino, Hervé.

Subjects/Keywords: Algorithmic patterns (Skeletons); GPU computing; OpenCL

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APA (6^th Edition):

Marques, R. J. d. S. (2012). Algorithmic skeleton framework for the orchestration of GPU computations. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8382

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Marques, Ricardo Jorge dos Santos. “Algorithmic skeleton framework for the orchestration of GPU computations.” 2012. Thesis, Universidade Nova. Accessed February 27, 2021. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8382.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Marques, Ricardo Jorge dos Santos. “Algorithmic skeleton framework for the orchestration of GPU computations.” 2012. Web. 27 Feb 2021.

Vancouver:

Marques RJdS. Algorithmic skeleton framework for the orchestration of GPU computations. [Internet] [Thesis]. Universidade Nova; 2012. [cited 2021 Feb 27]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8382.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Marques RJdS. Algorithmic skeleton framework for the orchestration of GPU computations. [Thesis]. Universidade Nova; 2012. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8382

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade Nova

24. Severino, Pedro Nuno Pereira. Aceleração da classificação de documentos com recurso a GPU.

Degree: 2012, Universidade Nova

URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8546

►

Dissertação para obtenção do Grau de Mestre em Engenharia Informática

O objectivo desta dissertação é explorar formas de diminuir o tempo gasto na extracção de… (more)

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Dissertação para obtenção do Grau de Mestre em Engenharia Informática

O objectivo desta dissertação é explorar formas de diminuir o tempo gasto na extracção de características relevantes( features) de textos disponíveis na Internet. Esta diminuição é obtida paralelizando parte dos algoritmos usados; as versões paralelizadas são vocacionadas para a execução em GPUs. São concebidas, implementadas e testadas versões paralelas da fase da determinação da relevância de features num sujeito/ objecto a ser analisado. Nesta parte do trabalho a principal contribuição é uma implementação do algoritmo de extracção de features adaptado a GPUs com ênfase nas rotinas de manipulação de grafos. Em objectos mais complexos a implementação atingiu tempos de execução 16 vezes inferiores à implementação sequencial em CPU. Foi também desenvolvido um servidor concorrente que reside no GPU e que oferece um conjunto de serviços relacionados com o processamento das features mais relevantes. Esse servidor faz uma gestão integrada dos recursos de computação existentes no GPU. A avaliação deste servidor foi feita sujeitando-o a diferentes misturas de sujeitos e com um ritmo de chegada de pedidos crescente. Considerando o critériomais relevante o número de pedidos cujo processamento excede um tempo limite, a solução baseada no servidor GPU começa a exceder esse tempo quando o ritmo de chegada de sujeitos ultrapassa os 70 pedidos/s, enquanto que na versão multi CPU isso acontece quando o ritmo atinge perto de 30 pedidos/s. Neste âmbito foi desenvolvida uma infra-estrutura que pode ser reaproveitada sempre que seja conveniente usar o GPU no paradigma do processamento de pedidos em lote. Esta tese foi desenvolvida num contexto empresarial, e do trabalho realizado resultam contributos para o melhoramento dos produtos da empresa, bem como da viabilidade técnica e económica do uso de GPUs em diversos contextos relevantes para a empresa. Neste contexto a versão definitiva da tese omite alguma informação.

Advisors/Committee Members: Medeiros, Pedro.

Subjects/Keywords: OpenCL; Computação paralela; GPU; Classificação de documentos

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Severino, P. N. P. (2012). Aceleração da classificação de documentos com recurso a GPU. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8546

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Severino, Pedro Nuno Pereira. “Aceleração da classificação de documentos com recurso a GPU.” 2012. Thesis, Universidade Nova. Accessed February 27, 2021. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8546.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Severino, Pedro Nuno Pereira. “Aceleração da classificação de documentos com recurso a GPU.” 2012. Web. 27 Feb 2021.

Vancouver:

Severino PNP. Aceleração da classificação de documentos com recurso a GPU. [Internet] [Thesis]. Universidade Nova; 2012. [cited 2021 Feb 27]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8546.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Severino PNP. Aceleração da classificação de documentos com recurso a GPU. [Thesis]. Universidade Nova; 2012. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8546

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade Nova

25. Soldado, Fábio Miguel Cardoso. Heterogeneous computing with an algorithmic skeleton framework.

Degree: 2014, Universidade Nova

URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13245

► The Graphics Processing Unit (GPU) is present in almost every modern day personal computer. Despite its specific purpose design, they have been increasingly used for… (more)

Subjects/Keywords: Algorithmic skeletons; OpenCL; GPGPU; Heterogeneous computing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Soldado, F. M. C. (2014). Heterogeneous computing with an algorithmic skeleton framework. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13245

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Soldado, Fábio Miguel Cardoso. “Heterogeneous computing with an algorithmic skeleton framework.” 2014. Thesis, Universidade Nova. Accessed February 27, 2021. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13245.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Soldado, Fábio Miguel Cardoso. “Heterogeneous computing with an algorithmic skeleton framework.” 2014. Web. 27 Feb 2021.

Vancouver:

Soldado FMC. Heterogeneous computing with an algorithmic skeleton framework. [Internet] [Thesis]. Universidade Nova; 2014. [cited 2021 Feb 27]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13245.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Soldado FMC. Heterogeneous computing with an algorithmic skeleton framework. [Thesis]. Universidade Nova; 2014. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13245

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Toronto

26. Rashid, Rafat. A Dual-engine Fetch/Compute Overlay Processor for FPGAs.

Degree: 2015, University of Toronto

URL: http://hdl.handle.net/1807/69239

►

High-Level-Synthesis (HLS) tools translate a software description of an application into custom FPGA logic, increasing designer productivity vs. Hardware Description Language (HDL) design flows. Overlays… (more)

Subjects/Keywords: FPGA; HLS; OpenCL; Overlay; Processor; Scheduling; 0464

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Rashid, R. (2015). A Dual-engine Fetch/Compute Overlay Processor for FPGAs. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/69239

Chicago Manual of Style (16^th Edition):

Rashid, Rafat. “A Dual-engine Fetch/Compute Overlay Processor for FPGAs.” 2015. Masters Thesis, University of Toronto. Accessed February 27, 2021. http://hdl.handle.net/1807/69239.

MLA Handbook (7^th Edition):

Rashid, Rafat. “A Dual-engine Fetch/Compute Overlay Processor for FPGAs.” 2015. Web. 27 Feb 2021.

Vancouver:

Rashid R. A Dual-engine Fetch/Compute Overlay Processor for FPGAs. [Internet] [Masters thesis]. University of Toronto; 2015. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1807/69239.

Council of Science Editors:

Rashid R. A Dual-engine Fetch/Compute Overlay Processor for FPGAs. [Masters Thesis]. University of Toronto; 2015. Available from: http://hdl.handle.net/1807/69239

27. Fernández Fabeiro, Jorge. Tools for improving performance portability in heterogeneous environments .

Degree: 2017, Universidad da Coruña

URL: http://hdl.handle.net/2183/19307

► [Abstract] Parallel computing is currently partially dominated by the availability of heterogeneous devices. These devices differ from each other in aspects such as the instruction… (more)

▼ [Abstract] Parallel computing is currently partially dominated by the availability of heterogeneous devices. These devices differ from each other in aspects such as the instruction set they execute, the number and the type of computing devices that they offer or the structure of their memory systems. In the last years, langnages, libraries and extensions have appeared to allow to write a parallel code once aud run it in a wide variety of devices, OpenCL being the most widespread solution of this kind. However, functional portability does not imply performance portability. This way, one of the probletns that is still open in this field is to achieve automatic performance portability. That is, the ability to automatically tune a given code for any device where it will be execnted so that it ill obtain a good performance. This thesis develops three different solutions to tackle this problem. The three of them are based on typical source-to-sonrce optimizations for heterogeneous devices. Both the set of optimizations to apply and the way they are applied depend on different optimization parameters, whose values have to be tuned for each specific device. The first solution is OCLoptimizer, a source-to-source optimizer that can optimize annotated OpenCL kemels with the help of configuration files that guide the optimization process. The tool optimizes kernels for a specific device, and it is also able to automate the generation of functional host codes when only a single kernel is optimized. The two remaining solutions are built on top of the Heterogeneous Programming Library (HPL), a C++ framework that provides an easy and portable way to exploit heterogeneous computing systexns. The first of these solutions uses the run-time code generation capabilities of HPL to generate a self-optimizing version of a matrix multiplication that can optimize itself at run-time for an spedfic device. The last solutíon is the development of a built-in just-in-time optirnizer for HPL, that can optirnize, at run-tirne, a HPL code for an specific device. While the first two solutions use search processes to find the best values for the optimization parameters, this Iast alternative relies on heuristics bMed on general optirnization strategies. Advisors/Committee Members: Andrade Canosa, Diego (advisor), Fraguela Rodríguez, Basilio Bernardo (advisor).

Subjects/Keywords: Programación paralela (Informática); OpenCL (Lenguaje de programación)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Fernández Fabeiro, J. (2017). Tools for improving performance portability in heterogeneous environments . (Doctoral Dissertation). Universidad da Coruña. Retrieved from http://hdl.handle.net/2183/19307

Chicago Manual of Style (16^th Edition):

Fernández Fabeiro, Jorge. “Tools for improving performance portability in heterogeneous environments .” 2017. Doctoral Dissertation, Universidad da Coruña. Accessed February 27, 2021. http://hdl.handle.net/2183/19307.

MLA Handbook (7^th Edition):

Fernández Fabeiro, Jorge. “Tools for improving performance portability in heterogeneous environments .” 2017. Web. 27 Feb 2021.

Vancouver:

Fernández Fabeiro J. Tools for improving performance portability in heterogeneous environments . [Internet] [Doctoral dissertation]. Universidad da Coruña; 2017. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/2183/19307.

Council of Science Editors:

Fernández Fabeiro J. Tools for improving performance portability in heterogeneous environments . [Doctoral Dissertation]. Universidad da Coruña; 2017. Available from: http://hdl.handle.net/2183/19307

Rice University

28. Majeti, Deepak. Portable Programming Models for Heterogeneous Platforms.

Degree: PhD, Engineering, 2015, Rice University

URL: http://hdl.handle.net/1911/88096

► With the end of Dennard scaling and emergence of dark silicon, the bets are high on heterogeneous architectures to achieve both application performance and energy… (more)

▼ With the end of Dennard scaling and emergence of dark silicon, the bets are high on heterogeneous architectures to achieve both application performance and energy efficiency. However, diversity in heterogeneous architectures poses severe programming challenges in terms of data layout, memory coherence, task partitioning, data distribution, and sharing of virtual addresses. Existing high-level programming languages are inadequate to address these new architectural features since they lack the necessary abstractions to address the challenges mentioned above. It is necessary for existing languages to be extended minimally with high-level constructs while maintaining existing standards of portability, performance, and productivity. The compiler and runtime together must efficiently map these constructs to a target architecture. We develop Concord, a C++ based programming model that extends the Intel Threading Building Blocks onto integrated heterogeneous CPU+GPU architectures that do not share the same virtual address between CPU and GPU. Concord supports many C++ features including virtual functions. We implement Shared Virtual Memory to map applications with pointer intensive data structures onto heterogeneous architectures that do not share the same virtual address. We introduce Heterogeneous Habanero-C (H2C), an implementation of the Habanero execution model targeting modern heterogeneous architectures with multiple devices. H2C provides high-level constructs to specify the computation, communication and synchronization in a given application. The H2C compiler and runtime frameworks efficiently map these high-level constructs onto the underlying heterogeneous hardware. The highlights of H2C include: a data layout framework to generate code with best data layout suited for a given memory hierarchy; constructs to specify a task partition, leaving the complex analysis of determining the resultant data distribution to the compiler; and a unified event framework that allows a programmer to write applications with a macro data-flow model onto heterogeneous architectures. Experimental results show Concord and H2C provide good portability, productivity, and performance. In the future, we believe heterogeneous architectures will be more diverse and more pervasive. We believe programming systems like H2C and Concord that have a tight integration of language, compiler and runtime are the right way to target current and future heterogeneous systems. Advisors/Committee Members: Sarkar, Vivek (advisor), Mellor-Crummey, John (committee member), Warburton, Timothy C (committee member), Barik, Rajkishore (committee member).

Subjects/Keywords: programming models; heterogeneous architectures; OpenCL; C++; C

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Majeti, D. (2015). Portable Programming Models for Heterogeneous Platforms. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/88096

Chicago Manual of Style (16^th Edition):

Majeti, Deepak. “Portable Programming Models for Heterogeneous Platforms.” 2015. Doctoral Dissertation, Rice University. Accessed February 27, 2021. http://hdl.handle.net/1911/88096.

MLA Handbook (7^th Edition):

Majeti, Deepak. “Portable Programming Models for Heterogeneous Platforms.” 2015. Web. 27 Feb 2021.

Vancouver:

Majeti D. Portable Programming Models for Heterogeneous Platforms. [Internet] [Doctoral dissertation]. Rice University; 2015. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1911/88096.

Council of Science Editors:

Majeti D. Portable Programming Models for Heterogeneous Platforms. [Doctoral Dissertation]. Rice University; 2015. Available from: http://hdl.handle.net/1911/88096

Delft University of Technology

29. Penders, A. (author). Accelerating Graph Analysis with Heterogeneous Systems.

Degree: Software and Computer Technology, 2012, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:7f3eeb52-77bd-4fdb-84a9-ea9ca0a35b94

►

Data analysis is a rising field of interest for computer science research due to the growing amount of information that is digitally available. This increase… (more)

▼

Data analysis is a rising field of interest for computer science research due to the growing amount of information that is digitally available. This increase in data has as direct consequence that any analysis is significantly complex. By using structured representations for the data sets, like graphs, the analysis becomes feasible, but is still time-consuming. In this project, the focus is on the reduction of the computational time for data analysis, with the introduction of accelerators. Accelerators are specialized hardware components that assist the general processing unit in performing (parts of) the task at hand. In particular, we focus on the use of General Purpose Graphical Processing Units (GPGPU) to help speedup the analysis. GPUs are specifically designed for representing and manipulating graphical data which invoke the processing of large chunks of data, GPUs are designed with large numbers of concurrent processing units and thus have a high potential of improving performance. In this project, we show the impact of using GPGPUs for both simple and more complex analysis, varying from small to large data sets, with the use of a programming model called OpenCL. We compare the performance of using accelerators against the traditional CPU-based implementation. Due to the inter-platform portability of the OpenCL model, such comparison can be performed without having to alter the algorithm. The use of accelerators is expected to become beneficial for analysis that require large computational power. For example, search algorithms (that require little to no computation) are not expected to profit from accelerators, while the more complex, centrality analysis is expected to have significantly more benefit from accelerators. Our results clearly shows this shift of performance improvement when algorithms further utilize the potential of accelerators, because the analysis grows in size and/ or complexity.

Computer Engineering

Electrical Engineering, Mathematics and Computer Science

Advisors/Committee Members: Varbanescu, A.L. (mentor).

Subjects/Keywords: GPU; graph; Graph analysis; accelerators; OpenCL; parallel

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Penders, A. (. (2012). Accelerating Graph Analysis with Heterogeneous Systems. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:7f3eeb52-77bd-4fdb-84a9-ea9ca0a35b94

Chicago Manual of Style (16^th Edition):

Penders, A (author). “Accelerating Graph Analysis with Heterogeneous Systems.” 2012. Masters Thesis, Delft University of Technology. Accessed February 27, 2021. http://resolver.tudelft.nl/uuid:7f3eeb52-77bd-4fdb-84a9-ea9ca0a35b94.

MLA Handbook (7^th Edition):

Penders, A (author). “Accelerating Graph Analysis with Heterogeneous Systems.” 2012. Web. 27 Feb 2021.

Vancouver:

Penders A(. Accelerating Graph Analysis with Heterogeneous Systems. [Internet] [Masters thesis]. Delft University of Technology; 2012. [cited 2021 Feb 27]. Available from: http://resolver.tudelft.nl/uuid:7f3eeb52-77bd-4fdb-84a9-ea9ca0a35b94.

Council of Science Editors:

Penders A(. Accelerating Graph Analysis with Heterogeneous Systems. [Masters Thesis]. Delft University of Technology; 2012. Available from: http://resolver.tudelft.nl/uuid:7f3eeb52-77bd-4fdb-84a9-ea9ca0a35b94

University of Toronto

30. Young-Schultz, Tanner Bernard. Hardware Acceleration of Biophotonic Simulations.

Degree: 2020, University of Toronto

URL: http://hdl.handle.net/1807/103585

►

The simulation of light propagation through tissue is important for medical applications like diffuse optical tomography (DOT), bioluminescence imaging (BLI) and photodynamic therapy (PDT). These… (more)

Subjects/Keywords: Biophotonics; FPGA; HPC; Monte Carlo; OpenCL; 0464

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Young-Schultz, T. B. (2020). Hardware Acceleration of Biophotonic Simulations. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/103585

Chicago Manual of Style (16^th Edition):

Young-Schultz, Tanner Bernard. “Hardware Acceleration of Biophotonic Simulations.” 2020. Masters Thesis, University of Toronto. Accessed February 27, 2021. http://hdl.handle.net/1807/103585.

MLA Handbook (7^th Edition):

Young-Schultz, Tanner Bernard. “Hardware Acceleration of Biophotonic Simulations.” 2020. Web. 27 Feb 2021.

Vancouver:

Young-Schultz TB. Hardware Acceleration of Biophotonic Simulations. [Internet] [Masters thesis]. University of Toronto; 2020. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1807/103585.

Council of Science Editors:

Young-Schultz TB. Hardware Acceleration of Biophotonic Simulations. [Masters Thesis]. University of Toronto; 2020. Available from: http://hdl.handle.net/1807/103585

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Open Access Theses and Dissertations