You searched for subject:(OpenCL).
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1.
Spliet, R.
A comprehensive study of Dynamic Memory Management in OpenCL kernels:.
Degree: 2013, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:b26fb6be-a3e1-4968-9044-01fc6a029926 
► Traditional (sequential) applications use malloc for a variety of dynamic data structures, like linked lists or trees. GPGPU is gaining attention and popularity because its…
(more)
▼ Traditional (sequential) applications use malloc for a variety of dynamic data structures, like linked lists or trees. GPGPU is gaining attention and popularity because its massively-parallel architecture allows for great speed improvement for programs that can be parallelised and implemented for a platform like
OpenCL. Programmers who try to port their existing sequential or even parallel program to
OpenCL however will soon discover that this standard defines a subset of C with several limitations, one of which is the absence of a malloc() routine that can be called from an
OpenCL kernel.
This document describes the results of research towards the impact of this limitation by trying to answer the question: ``How should a kernel-side heap allocator be implemented in
OpenCL?''. To give an answer to this question, two important aspects are investigated. Firstly we seek the impact from the programmers perspective by trying to understand the use-cases for which a parallel program requires an in-kernel heap allocator. We sought for a wide variety of implementations of parallel algorithms and investigated their memory usage patterns. Secondly we aim to explain the complexity of a dynamic memory allocator by taking a closer look at the limitations imposed by hardware and the
OpenCL standard, and trying to find a way to implement a memory allocator in
OpenCL. Based on our findings we present KMA, the first dynamic memory allocator for
OpenCL kernels.
Results from our use-case survey show that there are several cases where a programmer could benefit from an in-kernel malloc routine. Non-regular data-structures are required both for scheduling purposes and for holding intermediate results, and a memory allocator aids in creating these structures. Programmers usually find their way around the lack of a malloc routine, sometimes by creating something on their own that resembles part of one. Although a malloc routine thus is not a hard requirement, it can make the life of programmers a lot easier in these cases.
Designing and implementing a memory allocator for
OpenCL is far from trivial. Its capabilities are limited by the available hardware and language constraints: hardware does not allow for communication between the
OpenCL kernel and the host system, and the
OpenCL specification lacks fundamental features like mutex locks. Because of these constraints, even the data-structures we might take for granted, like full-featured doubly-linked-lists, cannot be implemented in
OpenCL.
We believe a memory allocator should be implemented in two layers. The bottom layer should implement behaviour like the malloc() routine found in C. On top of that data types can be implemented which may use datatype-specific restrictions to optimise the usage of the low-level memory allocator. Our KMA prototype shows that by carefully analysing the limitations of the
OpenCL environment it is possible to implement an in-kernel memory allocator, be it limited by the constraints imposed by the GPU platform and
OpenCL. Although using KMA comes with a…
Advisors/Committee Members: Varbanescu, A. L..
Subjects/Keywords: OpenCL
…lost on
transfer.
2.4
OpenCL
With the introduction of platforms like Cuda[36]… …and OpenCL[27], the GPUs massive-parallel
computational power became available for… …execute on the target device.
The difference between Cuda and OpenCL is both of technical and… …OpenCL on the other
hand is an open standard driven by most major players in the industry… …including AMD, NVIDIA,
Intel, ARM, Apple and many others. One of the key properties of OpenCL is…
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APA (6th Edition):
Spliet, R. (2013). A comprehensive study of Dynamic Memory Management in OpenCL kernels:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:b26fb6be-a3e1-4968-9044-01fc6a029926
Chicago Manual of Style (16th Edition):
Spliet, R. “A comprehensive study of Dynamic Memory Management in OpenCL kernels:.” 2013. Masters Thesis, Delft University of Technology. Accessed October 16, 2019.
http://resolver.tudelft.nl/uuid:b26fb6be-a3e1-4968-9044-01fc6a029926.
MLA Handbook (7th Edition):
Spliet, R. “A comprehensive study of Dynamic Memory Management in OpenCL kernels:.” 2013. Web. 16 Oct 2019.
Vancouver:
Spliet R. A comprehensive study of Dynamic Memory Management in OpenCL kernels:. [Internet] [Masters thesis]. Delft University of Technology; 2013. [cited 2019 Oct 16].
Available from: http://resolver.tudelft.nl/uuid:b26fb6be-a3e1-4968-9044-01fc6a029926.
Council of Science Editors:
Spliet R. A comprehensive study of Dynamic Memory Management in OpenCL kernels:. [Masters Thesis]. Delft University of Technology; 2013. Available from: http://resolver.tudelft.nl/uuid:b26fb6be-a3e1-4968-9044-01fc6a029926
University of Alberta
2.
Xunhao, Li.
Jit4OpenCL: a compiler from Python to OpenCL.
Degree: MS, Department of Computing Science, 2010, University of Alberta
URL: https://era.library.ualberta.ca/files/1v53jx087
► Heterogeneous computing platforms that use GPUs and CPUs in tandem for computation have become an important choice to build low-cost high-performance computing platforms. The computing…
(more)
▼ Heterogeneous computing platforms that use GPUs and
CPUs in tandem for computation have become an important choice to
build low-cost high-performance computing platforms. The computing
ability of modern GPUs surpasses that of CPUs can offer for certain
classes of applications. GPUs can deliver several Tera-Flops in
peak performance. However, programmers must adopt a more
complicated and more difficult new programming paradigm. To
alleviate the burden of programming for heterogeneous systems, Garg
and Amaral developed a Python compiling framework that combines an
ahead-of-time compiler called unPython with a just-in-time compiler
called jit4GPU. This compilation framework generates code for
systems with AMD GPUs. We extend the framework to retarget it to
generate OpenCL code, an industry standard that is implemented for
most GPUs. Therefore, by generating OpenCL code, this new compiler,
called jit4OpenCL, enables the execution of the same program in a
wider selection of heterogeneous platforms. To further improve the
target-code performance on nVidia GPUs, we developed an
array-access analysis tool that helps to exploit the data
reusability by utilizing the shared (local) memory space hierarchy
in OpenCL. The thesis presents an experimental performance
evaluation indicating that, in comparison with jit4GPU, jit4OpenCL
has performance degradation because of the current performance of
implementations of OpenCL, and also because of the extra time
needed for the additional just-in-time compilation. However, the
portable code generated by jit4OpenCL still have performance gains
in some applications compared to highly optimized CPU
code.
Subjects/Keywords: Python; compiler; OpenCL
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APA (6th Edition):
Xunhao, L. (2010). Jit4OpenCL: a compiler from Python to OpenCL. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/1v53jx087
Chicago Manual of Style (16th Edition):
Xunhao, Li. “Jit4OpenCL: a compiler from Python to OpenCL.” 2010. Masters Thesis, University of Alberta. Accessed October 16, 2019.
https://era.library.ualberta.ca/files/1v53jx087.
MLA Handbook (7th Edition):
Xunhao, Li. “Jit4OpenCL: a compiler from Python to OpenCL.” 2010. Web. 16 Oct 2019.
Vancouver:
Xunhao L. Jit4OpenCL: a compiler from Python to OpenCL. [Internet] [Masters thesis]. University of Alberta; 2010. [cited 2019 Oct 16].
Available from: https://era.library.ualberta.ca/files/1v53jx087.
Council of Science Editors:
Xunhao L. Jit4OpenCL: a compiler from Python to OpenCL. [Masters Thesis]. University of Alberta; 2010. Available from: https://era.library.ualberta.ca/files/1v53jx087
University of Debrecen
3.
Jánosi, Zoltán.
Alkalmazásfejlesztés GPU-ra
.
Degree: DE – TEK – Informatikai Kar, 2013, University of Debrecen
URL: http://hdl.handle.net/2437/167193
► Az OpenCL a heterogén programozási platformok kihasználásának egyik legjobb eszköze. Ezen szakdolgozat bemutatja hogyan működik az OpenCL , illetve, hogy miként használhatóak legoptimálisabban az általa…
(more)
▼ Az
OpenCL a heterogén programozási platformok kihasználásának egyik legjobb eszköze. Ezen szakdolgozat bemutatja hogyan működik az
OpenCL , illetve, hogy miként használhatóak legoptimálisabban az általa szolgáltatott eszközök. Bemutatja továbbá a DES algoritmus implementálásával, hogy miként skálázódik az
OpenCL-es megvalósítás GPU-n illetve CPU-n jól párhuzamosítható algoritmusok esetén. Magyarázatot ad továbbá arra, hogy miért a GPGPU-k az elsődleges számítási erőforrások napjainkban.
Advisors/Committee Members: Varga, Imre (advisor).
Subjects/Keywords: OpenCL;
GPU;
GPGPU
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APA (6th Edition):
Jánosi, Z. (2013). Alkalmazásfejlesztés GPU-ra
. (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/167193
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Jánosi, Zoltán. “Alkalmazásfejlesztés GPU-ra
.” 2013. Thesis, University of Debrecen. Accessed October 16, 2019.
http://hdl.handle.net/2437/167193.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Jánosi, Zoltán. “Alkalmazásfejlesztés GPU-ra
.” 2013. Web. 16 Oct 2019.
Vancouver:
Jánosi Z. Alkalmazásfejlesztés GPU-ra
. [Internet] [Thesis]. University of Debrecen; 2013. [cited 2019 Oct 16].
Available from: http://hdl.handle.net/2437/167193.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Jánosi Z. Alkalmazásfejlesztés GPU-ra
. [Thesis]. University of Debrecen; 2013. Available from: http://hdl.handle.net/2437/167193
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Linköping University
4.
Anders, Söderholm.
GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework.
Degree: Software and Systems, 2016, Linköping University
URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-127479
► Today's computer systems often contains several different processing units aside from the CPU. Among these the GPU is a very common processing unit with…
(more)
▼ Today's computer systems often contains several different processing units aside from the CPU. Among these the GPU is a very common processing unit with an immense compute power that is available in almost all computer systems. How do we make use of this processing power that lies within our machines? One answer is the OpenCL framework that is designed for just this, to open up the possibilities of using all the different types of processing units in a computer system. This thesis will discuss the advantages and disadvantages of using the integrated GPU available in a basic workstation computer for computation of image processing and sorting algorithms. These tasks are computationally intensive and the authors will analyze if an integrated GPU is up to the task of accelerating the processing of these algorithms. The OpenCL framework makes it possible to run one implementation on different processing units, to provide perspective we will benchmark our implementations on both the GPU and the CPU and compare the results. A heterogeneous approach that combines the two above mentioned processing units will also be tested and discussed. The OpenCL framework is analyzed from a development perspective and what advantages and disadvantages it brings to the development process will be presented.
Subjects/Keywords: GPU; OpenCL; algorithms
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APA (6th Edition):
Anders, S. (2016). GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-127479
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Anders, Söderholm. “GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework.” 2016. Thesis, Linköping University. Accessed October 16, 2019.
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-127479.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Anders, Söderholm. “GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework.” 2016. Web. 16 Oct 2019.
Vancouver:
Anders S. GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework. [Internet] [Thesis]. Linköping University; 2016. [cited 2019 Oct 16].
Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-127479.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Anders S. GPU-accelleration of image rendering and sorting algorithms with the OpenCL framework. [Thesis]. Linköping University; 2016. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-127479
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Dayton
5.
DeMange, Ashley.
OpenCL Acceleration of the KLT Feature Tracker on an
FPGA.
Degree: MSin Computer Engineering, Electrical and Computer Engineering, 2017, University of Dayton
URL: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501872686207408
► The Kunade-Lucas-Tomasi (KLT) algorithm is a well known feature tracker that has been implemented on both CPUs and GPUs. When tracking large numbers of features…
(more)
▼ The Kunade-Lucas-Tomasi (KLT) algorithm is a well
known feature tracker that has been implemented on both CPUs and
GPUs. When tracking large numbers of features in high definition
video, the KLT feature tracker does not execute in close to
real-time. In order to remedy this, the KLT feature tracker has
been implemented on a GPU. However, the GPU requires high energy
costs. The FPGA is a low power device that can be used to
accelerate programs. This research focuses on accelerating the KLT
feature tracker on an Altera Arria 10 FPGA using the parallel,
cross-platform
OpenCL framework. The purpose is to provide a low
power solution that also shows accelerated performance. As a
result, the Arria 10 FPGA is able to obtain over a 50% decrease in
run-time compared to the CPU. The FPGA design was also able to
achieve over 30% power efficiency over the GPU implementation and
98% power efficiency over the CPU implementation.
Advisors/Committee Members: Balster, Eric (Advisor).
Subjects/Keywords: Computer Engineering; KLT; FPGA; OpenCL
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APA (6th Edition):
DeMange, A. (2017). OpenCL Acceleration of the KLT Feature Tracker on an
FPGA. (Masters Thesis). University of Dayton. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501872686207408
Chicago Manual of Style (16th Edition):
DeMange, Ashley. “OpenCL Acceleration of the KLT Feature Tracker on an
FPGA.” 2017. Masters Thesis, University of Dayton. Accessed October 16, 2019.
http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501872686207408.
MLA Handbook (7th Edition):
DeMange, Ashley. “OpenCL Acceleration of the KLT Feature Tracker on an
FPGA.” 2017. Web. 16 Oct 2019.
Vancouver:
DeMange A. OpenCL Acceleration of the KLT Feature Tracker on an
FPGA. [Internet] [Masters thesis]. University of Dayton; 2017. [cited 2019 Oct 16].
Available from: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501872686207408.
Council of Science Editors:
DeMange A. OpenCL Acceleration of the KLT Feature Tracker on an
FPGA. [Masters Thesis]. University of Dayton; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501872686207408
University of Debrecen
6.
Erdei, Tímea.
Grafikus kártyák alkalmazása a kriptográfiában
.
Degree: DE – TEK – Informatikai Kar, 2011, University of Debrecen
URL: http://hdl.handle.net/2437/95296
Az OpenCL programozás röviden és egy program leírása.
Advisors/Committee Members: Pethő, Attila (advisor).Subjects/Keywords: GPU;
OpenCL
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APA (6th Edition):
Erdei, T. (2011). Grafikus kártyák alkalmazása a kriptográfiában
. (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/95296
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Erdei, Tímea. “Grafikus kártyák alkalmazása a kriptográfiában
.” 2011. Thesis, University of Debrecen. Accessed October 16, 2019.
http://hdl.handle.net/2437/95296.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Erdei, Tímea. “Grafikus kártyák alkalmazása a kriptográfiában
.” 2011. Web. 16 Oct 2019.
Vancouver:
Erdei T. Grafikus kártyák alkalmazása a kriptográfiában
. [Internet] [Thesis]. University of Debrecen; 2011. [cited 2019 Oct 16].
Available from: http://hdl.handle.net/2437/95296.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Erdei T. Grafikus kártyák alkalmazása a kriptográfiában
. [Thesis]. University of Debrecen; 2011. Available from: http://hdl.handle.net/2437/95296
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Clemson University
7.
Rayrikar, Bhushan.
Parallel Implementation of the Singular Value Decomposition using OpenCL.
Degree: MS, Computer Engineering, 2011, Clemson University
URL: https://tigerprints.clemson.edu/all_theses/1292
► General-Purpose Graphics Processing Units (GPGPUs) have massively parallel computational capabilities. Low cost and ease of programming make them a popular choice over other parallel architectures…
(more)
▼ General-Purpose Graphics Processing Units (GPGPUs) have massively parallel computational capabilities. Low cost and ease of programming make them a popular choice over other parallel architectures such as large clusters and accelerators such as Field-Programmable Gate Arrays (FPGAs). Mature programming frameworks for GPGPUs, such as CUDA from Nvidia and
OpenCL from the Khronos Group, reduce the learning curve and development time for programming GPGPU architectures.
OpenCL, a relatively new industry standard for parallel computing makes it possible to write a single program for heterogeneous platforms that is portable across multiple platforms including GPGPUs and multi-core processors with minimal coding modifications. GPGPU architectures have been successfully used for accelerating many computationally expensive problems including many linear algebra algorithms, which are inherently parallel in nature. Singular Value Decomposition (SVD) is a computationally expensive linear algebra matrix decomposition technique that has many applications including data compression, facial recognition, and solving a system of equations. As the dimensions of the matrix increase, SVD computation becomes increasingly time consuming. Since SVD is a major part of some algorithms such as Eigenfaces (a facial recognition algorithm based on Principle Component Analysis), the overall runtime for these algorithms depends heavily on the execution time of SVD. Hence, to implement efficient applications based on SVD, for example real-time facial recognition, it is desirable to accelerate the SVD algorithm. In this work, a parallel implementation of Singular Value Decomposition is discussed in detail. It uses many basic linear algebra techniques such as matrix-vector multiplication, vector norms and vector outer products. This work focuses on the implementation techniques, optimization methods (specifically for a GPGPU implementation) and their effect on the overall performance of the algorithm. We present the performance analysis of this algorithm on NVIDIA's Tesla C2050 GPU as compared to the single-threaded serial implementation executed on an Intel 2.66 GHz Q9450 processor. We report speedups up to 20x for the parallel SVD computation. The results discussed in this thesis demonstrate the potential of the computational resources available with GPGPUs.
Advisors/Committee Members: Smith, Melissa, Birchfield , Stanley, Gowdy , John.
Subjects/Keywords: GPGPU; OpenCL; SVD; Computer Engineering
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APA (6th Edition):
Rayrikar, B. (2011). Parallel Implementation of the Singular Value Decomposition using OpenCL. (Masters Thesis). Clemson University. Retrieved from https://tigerprints.clemson.edu/all_theses/1292
Chicago Manual of Style (16th Edition):
Rayrikar, Bhushan. “Parallel Implementation of the Singular Value Decomposition using OpenCL.” 2011. Masters Thesis, Clemson University. Accessed October 16, 2019.
https://tigerprints.clemson.edu/all_theses/1292.
MLA Handbook (7th Edition):
Rayrikar, Bhushan. “Parallel Implementation of the Singular Value Decomposition using OpenCL.” 2011. Web. 16 Oct 2019.
Vancouver:
Rayrikar B. Parallel Implementation of the Singular Value Decomposition using OpenCL. [Internet] [Masters thesis]. Clemson University; 2011. [cited 2019 Oct 16].
Available from: https://tigerprints.clemson.edu/all_theses/1292.
Council of Science Editors:
Rayrikar B. Parallel Implementation of the Singular Value Decomposition using OpenCL. [Masters Thesis]. Clemson University; 2011. Available from: https://tigerprints.clemson.edu/all_theses/1292
Virginia Tech
8.
Shagrithaya, Kavya Subraya.
Enabling Development of OpenCL Applications on FPGA platforms.
Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech
URL: http://hdl.handle.net/10919/34669
► FPGAs can potentially deliver tremendous acceleration in high-performance server and em- bedded computing applications. Whether used to augment a processor or as a stand-alone device,…
(more)
▼ FPGAs can potentially deliver tremendous acceleration in high-performance server and em-
bedded computing applications. Whether used to augment a processor or as a stand-alone
device, these reconfigurable architectures are being deployed in a large number of implemen-
tations owing to the massive amounts of parallelism offered. At the same time, a significant
challenge encountered in their wide-spread acceptance is the laborious efforts required in
programming these devices. The increased development time, level of experience needed by
the developers, lower turns per day and difficulty involved in faster iterations over designs
affect the time-to-market for many solutions. High-level synthesis aims towards increasing
the productivity of FPGAs and bringing them within the reach software developers and
domain experts.
OpenCL is a specification introduced for parallel programming purposes
across platforms. Applications written in
OpenCL consist of two parts - a host program
for initialization and management, and kernels that define the compute intensive tasks. In
this thesis, a compilation flow to generate customized application-specific hardware descrip-
tions from
OpenCL computation kernels is presented. The flow uses Xilinx AutoESL tool to
obtain the design specification for compute cores. An architecture provided integrates the
cores with memory and host interfaces. The host program in the application is compiled and
executed to demonstrate a proof-of-concept implementation towards achieving an end-to-end
flow that provides abstraction of hardware at the front-end.
Advisors/Committee Members: Athanas, Peter M. (committeechair), Schaumont, Patrick Robert (committee member), Plassmann, Paul E. (committee member).
Subjects/Keywords: FPGA; AutoESL; OpenCL; Convey; HPC
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APA (6th Edition):
Shagrithaya, K. S. (2012). Enabling Development of OpenCL Applications on FPGA platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34669
Chicago Manual of Style (16th Edition):
Shagrithaya, Kavya Subraya. “Enabling Development of OpenCL Applications on FPGA platforms.” 2012. Masters Thesis, Virginia Tech. Accessed October 16, 2019.
http://hdl.handle.net/10919/34669.
MLA Handbook (7th Edition):
Shagrithaya, Kavya Subraya. “Enabling Development of OpenCL Applications on FPGA platforms.” 2012. Web. 16 Oct 2019.
Vancouver:
Shagrithaya KS. Enabling Development of OpenCL Applications on FPGA platforms. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2019 Oct 16].
Available from: http://hdl.handle.net/10919/34669.
Council of Science Editors:
Shagrithaya KS. Enabling Development of OpenCL Applications on FPGA platforms. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/34669
Delft University of Technology
9.
Berger, M.E.R.
High Performance Histograms on SIMT and SIMD Architectures:.
Degree: 2015, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:38dd2dbd-9dca-4a27-8829-06ea069af6b7
► Using the histogram procedure, this work studies performance determining factors in computing in parallel on SIMD and SIMT devices. Modern graphics pro-cessing units (GPUs) support…
(more)
▼ Using the histogram procedure, this work studies performance determining factors in computing in parallel on SIMD and SIMT devices.
Modern graphics pro-cessing units (GPUs) support SIMT, multiple threads running the same instruction, whereas central processing units (CPUs) use SIMD, in which one instruction op-erates on multiple operands. As part of this work, a cross-technology framework is developed that allows testing a single-source histogram implementation on multiple devices, providing insight into the performance of various API – hardwareconfigurations. It is shown that in the presence of high contention, the implementation of atomic operations becomes of great influence on performance. This work provides guidelines for the choice between devices based on image features and hardware specifications.
Advisors/Committee Members: Varbanescu, A..
Subjects/Keywords: GPU; CUDA; OpenCL; histogram; atomics
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APA (6th Edition):
Berger, M. E. R. (2015). High Performance Histograms on SIMT and SIMD Architectures:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:38dd2dbd-9dca-4a27-8829-06ea069af6b7
Chicago Manual of Style (16th Edition):
Berger, M E R. “High Performance Histograms on SIMT and SIMD Architectures:.” 2015. Masters Thesis, Delft University of Technology. Accessed October 16, 2019.
http://resolver.tudelft.nl/uuid:38dd2dbd-9dca-4a27-8829-06ea069af6b7.
MLA Handbook (7th Edition):
Berger, M E R. “High Performance Histograms on SIMT and SIMD Architectures:.” 2015. Web. 16 Oct 2019.
Vancouver:
Berger MER. High Performance Histograms on SIMT and SIMD Architectures:. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2019 Oct 16].
Available from: http://resolver.tudelft.nl/uuid:38dd2dbd-9dca-4a27-8829-06ea069af6b7.
Council of Science Editors:
Berger MER. High Performance Histograms on SIMT and SIMD Architectures:. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:38dd2dbd-9dca-4a27-8829-06ea069af6b7
Delft University of Technology
10.
Hemminga, S.
Programmability Analysis of Image Processing Kernels on Multi-/Many-core Platforms
:.
Degree: 2011, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:7efbc439-7a08-40f4-8a07-94879de2eba7
► In the last few years, the computing industry has changed its course from ever higher clock speeds to multi- and many-core systems. These new parallel…
(more)
▼ In the last few years, the computing industry has changed its course from ever higher clock speeds to multi- and many-core systems. These new parallel systems suffer a “programmability gap”: there is a large gap between the performance a platform is theoretically capable of, and what the programmer is able to achieve.
Early programming models were very closely tied to the underlying hardware. A proliferation of programming models has lead to a push for standardisation. This standard became
OpenCL.
In this thesis we investigated how the programmability of many-core systems has evolved in the past years. We started with the hardware-centric Cell SDK and compared it to the new standard
OpenCL. We compared programmability on performance, portability and productivity. We found that
OpenCL is a major improvement in portability and productivity, but that performance is still lacking.
Advisors/Committee Members: Varbanescu, A.L..
Subjects/Keywords: OpenCL; GPU; GPGPU; Cell BE
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APA (6th Edition):
Hemminga, S. (2011). Programmability Analysis of Image Processing Kernels on Multi-/Many-core Platforms
:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:7efbc439-7a08-40f4-8a07-94879de2eba7
Chicago Manual of Style (16th Edition):
Hemminga, S. “Programmability Analysis of Image Processing Kernels on Multi-/Many-core Platforms
:.” 2011. Masters Thesis, Delft University of Technology. Accessed October 16, 2019.
http://resolver.tudelft.nl/uuid:7efbc439-7a08-40f4-8a07-94879de2eba7.
MLA Handbook (7th Edition):
Hemminga, S. “Programmability Analysis of Image Processing Kernels on Multi-/Many-core Platforms
:.” 2011. Web. 16 Oct 2019.
Vancouver:
Hemminga S. Programmability Analysis of Image Processing Kernels on Multi-/Many-core Platforms
:. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2019 Oct 16].
Available from: http://resolver.tudelft.nl/uuid:7efbc439-7a08-40f4-8a07-94879de2eba7.
Council of Science Editors:
Hemminga S. Programmability Analysis of Image Processing Kernels on Multi-/Many-core Platforms
:. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:7efbc439-7a08-40f4-8a07-94879de2eba7
University of Toronto
11.
Chin, Stephen Alexander.
Reusable OpenCL FPGA Infrastructure.
Degree: 2012, University of Toronto
URL: http://hdl.handle.net/1807/32567
► OpenCL has emerged as a standard programming model for heterogeneous systems. Recent work combining OpenCL and FPGAs has focused on high-level synthesis. Building a complete…
(more)
▼ OpenCL has emerged as a standard programming model for heterogeneous systems. Recent work combining OpenCL and FPGAs has focused on high-level synthesis. Building a complete OpenCL FPGA system requires more than just high-level synthesis. This work introduces a reusable OpenCL infrastructure for FPGAs that complements previous work and specifically targets a key architectural element - the memory interface. An Aggregating Memory Controller that aims to maximize bandwidth to external, large, high-latency, high-bandwidth memories and a template Processing Array with soft-processor and hand-coded hardware elements are designed, simulated, and implemented on an FPGA. Two micro-benchmarks were run on both the soft-processor elements and the hand-coded hardware elements to exercise the Aggregating Memory Controller. The micro-benchmarks were simulated as well as implemented in a hardware prototype. Memory bandwidth results for the system show that the external memory interface can be saturated and the high-latency can be effectively hidden using the Aggregating Memory Controller.
MAST
Advisors/Committee Members: Chow, Paul, Electrical and Computer Engineering.
Subjects/Keywords: FPGA; OpenCL; SDRAM; computer architecture
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APA (6th Edition):
Chin, S. A. (2012). Reusable OpenCL FPGA Infrastructure. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/32567
Chicago Manual of Style (16th Edition):
Chin, Stephen Alexander. “Reusable OpenCL FPGA Infrastructure.” 2012. Masters Thesis, University of Toronto. Accessed October 16, 2019.
http://hdl.handle.net/1807/32567.
MLA Handbook (7th Edition):
Chin, Stephen Alexander. “Reusable OpenCL FPGA Infrastructure.” 2012. Web. 16 Oct 2019.
Vancouver:
Chin SA. Reusable OpenCL FPGA Infrastructure. [Internet] [Masters thesis]. University of Toronto; 2012. [cited 2019 Oct 16].
Available from: http://hdl.handle.net/1807/32567.
Council of Science Editors:
Chin SA. Reusable OpenCL FPGA Infrastructure. [Masters Thesis]. University of Toronto; 2012. Available from: http://hdl.handle.net/1807/32567
Northeastern University
12.
Momeni, Amir.
Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach.
Degree: PhD, Department of Electrical and Computer Engineering, 2017, Northeastern University
URL: http://hdl.handle.net/2047/D20254348
► Field Programmable Gate Arrays (FPGAs) are one major class of architectures commonly used in parallel computing systems. FPGAs provide a massive number (i.e., millions) programmable…
(more)
▼ Field Programmable Gate Arrays (FPGAs) are one major class of architectures commonly used in parallel computing systems. FPGAs provide a massive number (i.e., millions) programmable logic blocks and I/O cells, as well as programmable interconnects, which can be configured for a particular application. This reconfigurable architecture is flexible and power efficient, and potentially, provides better floating-point operations per watt rates versus general purpose architectures, such as CPUs and GPUs. However, programming an FPGA can be challenging and time-consuming, requiring hardware description language (HDL) experience and digital design expertise. High-level synthesis (HLS) tools have been designed to ease the FPGA programming task by generating HDL (e.g., Verilog or VHDL) codes from high-level languages (e.g., C/C++, OpenCL). Inparticular, there have been recent developments in OpenCL-based HLS tools (OpenCL-HLS) to enable programmers to construct a customized data-path that can best match a parallel application, relieving the programmer of many implementation details.; Given the availability of OpenCL-HLS tools for FPGAs creates many new opportunities, as well presents new challenges, in order to fully utilize these new capabilities. The primary challenge lies in the difference between the OpenCL parallelism semantics and parallel execution model on FPGA devices. OpenCL is primarily developed for GPU devices, which have many spatially-parallel cores. We need to explore new classes of optimization in order to fully leverage OpenCL execution on FPGAs.; This thesis explores and addresses OpenCL-HLS challenges using three different approaches. In the first approach we consider source-level optimization, where we evaluate the impact of OpenCL source-level decisions on the resulting data-path and FPGA execution efficiency. Our aim is to analyze the correlation between OpenCL parallelism semantics and parallel execution on FPGA devices. We want to be able to guide OpenCL programmers to develop optimized code on an FPGA. We study the impact of different grains (fine and coarse-grained), and forms of parallelism (spatial and temporal), exposed by OpenCL on the generated data-path. We also study the efficiency of the OpenCL Pipe semantic when targeting an FPGA.; In the second approach called synthesis optimization, we introduce novel optimization techniques for synthesis of OpenCL kernels targeted for FPGA devices. We propose a Hardware Thread Reordering (HTR) technique to improve the performance of irregular kernels. The goal is to guide OpenCL-HLS tool developers to design a more efficient data-path for a given OpenCL kernel. Using our HTR technique, we achieve up to a 11X speed-up, with less than a 2X increase in resource utilization.; In our third approach called architectural approach, we propose a novel device named an FP-GPU (field-programmable GPU), a new class of architecture that utilizes the benefits of both GPU and FPGA architectures. FP-GPU utilizes the GPU memory hierarchy, but introduces a novel thread…
Subjects/Keywords: FPGA; GPU; OpenCL; parallelism
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APA (6th Edition):
Momeni, A. (2017). Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20254348
Chicago Manual of Style (16th Edition):
Momeni, Amir. “Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach.” 2017. Doctoral Dissertation, Northeastern University. Accessed October 16, 2019.
http://hdl.handle.net/2047/D20254348.
MLA Handbook (7th Edition):
Momeni, Amir. “Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach.” 2017. Web. 16 Oct 2019.
Vancouver:
Momeni A. Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach. [Internet] [Doctoral dissertation]. Northeastern University; 2017. [cited 2019 Oct 16].
Available from: http://hdl.handle.net/2047/D20254348.
Council of Science Editors:
Momeni A. Exploiting thread-level parallelism on reconfigurable architectures: a cross-layer approach. [Doctoral Dissertation]. Northeastern University; 2017. Available from: http://hdl.handle.net/2047/D20254348
University of Windsor
13.
Bussiere, Alexander.
OpenCL Implimentation of LiDAR Data Processing.
Degree: MA, Electrical and Computer Engineering, 2014, University of Windsor
URL: https://scholar.uwindsor.ca/etd/5243
► When designing a safety system, the faster the response time, the greater the reflexes of the system to hazards. As more commercial interest in…
(more)
▼ When designing a safety system, the faster the response time, the greater the reflexes of the system to hazards. As more commercial interest in autonomous and assisted vehicles grows, the number one concern is safety. If the system cannot react as fast as or faster than an average human, then the public will deem it unsafe. In this thesis, I explore the feasibility of using GPU hardware to perform the algorithms used for determining robotic obstacle avoidance. These obstacle avoidance algorithms are ideally suited to reacting to emergency hazards. The product of this research will be a libarary of
OpenCL accelerated functions designed for processing environmental data from LiDAR sensors. The results show that by adopting algorithms to take advantage of the parallel architecture of GPUs, processing times significantly decrease for large data sets.
Advisors/Committee Members: Maev, Roman.
Subjects/Keywords: Autonomous; LiDAR; OpenCL; Robotics
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APA (6th Edition):
Bussiere, A. (2014). OpenCL Implimentation of LiDAR Data Processing. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5243
Chicago Manual of Style (16th Edition):
Bussiere, Alexander. “OpenCL Implimentation of LiDAR Data Processing.” 2014. Masters Thesis, University of Windsor. Accessed October 16, 2019.
https://scholar.uwindsor.ca/etd/5243.
MLA Handbook (7th Edition):
Bussiere, Alexander. “OpenCL Implimentation of LiDAR Data Processing.” 2014. Web. 16 Oct 2019.
Vancouver:
Bussiere A. OpenCL Implimentation of LiDAR Data Processing. [Internet] [Masters thesis]. University of Windsor; 2014. [cited 2019 Oct 16].
Available from: https://scholar.uwindsor.ca/etd/5243.
Council of Science Editors:
Bussiere A. OpenCL Implimentation of LiDAR Data Processing. [Masters Thesis]. University of Windsor; 2014. Available from: https://scholar.uwindsor.ca/etd/5243
Universidad de Chile
14.
Pefaur Pumarino, José Tomás.
Optimización de software de visualización y detección de patrones de drenaje y terrazas fluviales en superficies de terreno
.
Degree: 2016, Universidad de Chile
URL: http://repositorio.uchile.cl/handle/2250/142813
► La Geomorfología fluvial corresponde al estudio de los procesos de formación y sedimentación de los ríos, y de su interacción con el entorno, lo que…
(more)
▼ La Geomorfología fluvial corresponde al estudio de los procesos de formación y sedimentación de los ríos, y de su interacción con el entorno, lo que entrega información sobre la "historia de vida" de un terreno. En este contexto, existen dos elementos de estudio interesantes: las redes de drenaje y las terrazas fluviales.
Runnel es un software que tiene por objetivo visualizar y detectar patrones de drenaje y terrazas fluviales sobre terrenos representados por grillas o triangulaciones de éstas. Si bien el funcionamiento de Runnel es correcto, éste tiene un gran problema: el tiempo de ejecución de sus principales algoritmos. A medida que el tamaño del terreno crece, el tiempo de ejecución aumenta considerablemente. Con el fin de mejorar este problema, se decidió paralelizar los algoritmos de detección de redes de drenaje: Peucker, Callaghan, RWFlood y Ángulo Diedro. Al mismo tiempo, se decidió implementar una triangulación simplificada, la cual disminuye el número de triángulos, y en consecuencia, se disminuye el tiempo de ejecución de los algoritmos que usan la triangulación.
Para lograr la paralelización se utilizó
OpenCL, herramienta que permite la ejecución de un código paralelo tanto en GPU como en CPU de forma indistinguible. Para la triangulación simplificada se utilizó un algoritmo basado en la eliminación de uno de los vértices de aquellos triángulos que cumplen una condición predeterminada.
Como resultado de la paralelización se obtuvieron mejoras significativas con los algoritmos de Peucker (speed-up mínimo: 1.19 y speed-up máximo: 13.63), Callaghan (speed-up mínimo: 5.87 y speed-up máximo: 19.82) y Ángulo Diedro (speed-up mínimo: 1.43 y speed-up máximo: 23.53). La triangulación simplificada también entregó mejoras en rendimiento, pero con menor impacto que la paralelización (speed-up mínimo: 1.14 y speed-up máximo: 1.94). El único algoritmo que no resultó en mejoras en su tiempo de ejecución (en la mayoría de los casos de prueba) fue el algoritmo RWFlood (speed-up mínimo: 0.16 y speed-up máximo: 2.93).
Junto con el desarrollo de los algoritmos paralelos se adquirió conocimiento sobre las diferencias de rendimiento de una CPU con una GPU. Se tuvo que ahondar en la arquitectura de cada una y reconocer el tipo de problema que cada una puede resolver de manera óptima.
Se propone como trabajo futuro solucionar el uso excesivo de la memoria en la triangulación, analizar del impacto de la triangulación simplificada en los terrenos, solucionar el problema del tiempo de ejecución de RWFlood y paralelizar otros algoritmos.
Advisors/Committee Members: Hitschfeld Kahler, Nancy (advisor).
Subjects/Keywords: Geomorfología fluvial;
Triangulación;
Drenaje;
opencl
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APA ·
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Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Pefaur Pumarino, J. T. (2016). Optimización de software de visualización y detección de patrones de drenaje y terrazas fluviales en superficies de terreno
. (Thesis). Universidad de Chile. Retrieved from http://repositorio.uchile.cl/handle/2250/142813
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Pefaur Pumarino, José Tomás. “Optimización de software de visualización y detección de patrones de drenaje y terrazas fluviales en superficies de terreno
.” 2016. Thesis, Universidad de Chile. Accessed October 16, 2019.
http://repositorio.uchile.cl/handle/2250/142813.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Pefaur Pumarino, José Tomás. “Optimización de software de visualización y detección de patrones de drenaje y terrazas fluviales en superficies de terreno
.” 2016. Web. 16 Oct 2019.
Vancouver:
Pefaur Pumarino JT. Optimización de software de visualización y detección de patrones de drenaje y terrazas fluviales en superficies de terreno
. [Internet] [Thesis]. Universidad de Chile; 2016. [cited 2019 Oct 16].
Available from: http://repositorio.uchile.cl/handle/2250/142813.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Pefaur Pumarino JT. Optimización de software de visualización y detección de patrones de drenaje y terrazas fluviales en superficies de terreno
. [Thesis]. Universidad de Chile; 2016. Available from: http://repositorio.uchile.cl/handle/2250/142813
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Brno University of Technology
15.
Šnobl, Pavel.
Překlad OpenCL aplikací pro vestavěné systémy
.
Degree: 2016, Brno University of Technology
URL: http://hdl.handle.net/11012/61853
► Tato diplomová práce se zabývá podporou pro překlad a spouštění programů napsaných pomocí OpenCL frameworku na vestavěných systémech. OpenCL je systém pro programování heterogenních systémů,…
(more)
▼ Tato diplomová práce se zabývá podporou pro překlad a spouštění programů napsaných pomocí
OpenCL frameworku na vestavěných systémech.
OpenCL je systém pro programování heterogenních systémů, složených z procesorů, grafických akcelerátorů a dalších výpočetních zařízení. Využití má ovšem i na systémech skládajících se pouze z jedné výpočetní jednotky, kde umožňuje zápis paralelních programů (funkční a datový paralelismus) a práci s hierarchickým systémem pamětí. V rámci této práce jsou porovnány jednotlivé dostupné open source implementace
OpenCL a následně je jedna vybraná integrována s překladačem LLVM. Tento překladač je generován v rámci sady nástrojů poskytovaných vývojovým prostředím pro tvorbu procesorů s aplikačně specifickou instrukční sadou zvaným Codasip Studio. Dále jsou navrženy a implementovány optimalizace pro architektury se SIMD instrukcemi a architektury typu VLIW. Výsledek je otestován a demonstrován na sadě testovacích aplikací.; This master's thesis deals with the support for compilation and execution of programs written using
OpenCL framework on embedded systems.
OpenCL is a system for programming heterogeneous systems comprising processors, graphic accelerators and other computing devices. But it also finds usage on systems composed of just one computing unit, where it allows to write parallel programs (task and data parallelism) and work with hierarchical system of memories. In this thesis, various available open source
OpenCL implementations are compared and one selected is then integrated into LLVM compiler infrastructure. This compiler is generated as a part of toolchain provided by application specific instruction set architecture processor developement environment called Codasip Studio. Designed and implemented are also optimizations for architectures with SIMD instructions and VLIW architectures. The result is tested and demonstrated on a set of testing applications.
Advisors/Committee Members: Hruška, Tomáš (advisor).
Subjects/Keywords: OpenCL;
LLVM;
Codasip;
SIMD;
VLIW;
OpenCL;
LLVM;
Codasip;
SIMD;
VLIW
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APA ·
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Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Šnobl, P. (2016). Překlad OpenCL aplikací pro vestavěné systémy
. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/61853
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Šnobl, Pavel. “Překlad OpenCL aplikací pro vestavěné systémy
.” 2016. Thesis, Brno University of Technology. Accessed October 16, 2019.
http://hdl.handle.net/11012/61853.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Šnobl, Pavel. “Překlad OpenCL aplikací pro vestavěné systémy
.” 2016. Web. 16 Oct 2019.
Vancouver:
Šnobl P. Překlad OpenCL aplikací pro vestavěné systémy
. [Internet] [Thesis]. Brno University of Technology; 2016. [cited 2019 Oct 16].
Available from: http://hdl.handle.net/11012/61853.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Šnobl P. Překlad OpenCL aplikací pro vestavěné systémy
. [Thesis]. Brno University of Technology; 2016. Available from: http://hdl.handle.net/11012/61853
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Brno University of Technology
16.
Jiránek, Karel.
Generování hesel na základě pravidel
.
Degree: 2017, Brno University of Technology
URL: http://hdl.handle.net/11012/69706
► Tato práce se zabývá generováním hesel na základě pravidel, paralelním generováním hesel s využitím GPU a frameworku OpenCL. V práci je řešen návrh generátoru hesel…
(more)
▼ Tato práce se zabývá generováním hesel na základě pravidel, paralelním generováním hesel s využitím GPU a frameworku
OpenCL. V práci je řešen návrh generátoru hesel pro nástroj Fitcrack. Modul pro generování využívá strojového učení na reálných heslech ke zkrácení potřebného času k nalezení správného hesla.; The thesis describes password generation based on rules and parallel generation of passwords on GPU with
OpenCL framework. The thesis addresses the design of a password generator for Fitcrack tool. Module for generation of passwords uses machine learning with real passwords to reduce time to find a correct password.
Advisors/Committee Members: Hranický, Radek (advisor).
Subjects/Keywords: Generování hesel;
Fitcrack;
kryptografie;
OpenCL;
Password generation;
Fitcrack;
cryptography;
OpenCL
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APA ·
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Manager
APA (6th Edition):
Jiránek, K. (2017). Generování hesel na základě pravidel
. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/69706
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Jiránek, Karel. “Generování hesel na základě pravidel
.” 2017. Thesis, Brno University of Technology. Accessed October 16, 2019.
http://hdl.handle.net/11012/69706.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Jiránek, Karel. “Generování hesel na základě pravidel
.” 2017. Web. 16 Oct 2019.
Vancouver:
Jiránek K. Generování hesel na základě pravidel
. [Internet] [Thesis]. Brno University of Technology; 2017. [cited 2019 Oct 16].
Available from: http://hdl.handle.net/11012/69706.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Jiránek K. Generování hesel na základě pravidel
. [Thesis]. Brno University of Technology; 2017. Available from: http://hdl.handle.net/11012/69706
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Alberta
17.
Maier, Andrew J.
Design and Optimization of Decoders for Low-Denisty Parity
Check Codes Synthesized from the OpenCL Specifications.
Degree: MS, Department of Electrical and Computer
Engineering, 2016, University of Alberta
URL: https://era.library.ualberta.ca/files/cjd472w72q
► Open Computing Language (OpenCL) is a high-level language that allows developers to produce portable software for heterogeneous parallel computing platforms. OpenCL is available for a…
(more)
▼ Open Computing Language (OpenCL) is a high-level
language that allows developers to produce portable software for
heterogeneous parallel computing platforms. OpenCL is available for
a variety of hardware platforms, with compiler support being
recently expanded to include Field-Programmable Gate Arrays
(FPGAs). This work investigates flexible OpenCL designs for the
iterative min-sum decoding algorithm for both symmetric and
asymmetric Low-Density Parity Check (LDPC) codes over a range of
codeword lengths. The computationally demanding LDPC decoding
algorithm offers several forms of parallelism that could be
exploited by the Altera-Offline-Compiler (AOC version 15.1) for
OpenCL. By starting with the recommended design approaches and
optimizing based on experimentation, the highest throughput
symmetric LDPC decoder produced a maximum corrected codeword
throughput of 68.22 Mbps for 32 decoding iterations at the
compiler-selected FPGA clock frequency of 163.88 MHz for a
length-2048 (3,6)-regular code. Designs for three of the DOCSIS 3.1
[7] standard asymmetric codewords were investigated and implemented
using the AOC. The designs prove that OpenCL on FPGAs can produce
high-throughput results for industry-sized asymmetric LDPC codes
with significantly shorter design time compared to other custom
hardware and software applications.
Subjects/Keywords: OpenCL; LDPC; FPGA; Heterogeneous Programming; Parallel Programming
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APA (6th Edition):
Maier, A. J. (2016). Design and Optimization of Decoders for Low-Denisty Parity
Check Codes Synthesized from the OpenCL Specifications. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/cjd472w72q
Chicago Manual of Style (16th Edition):
Maier, Andrew J. “Design and Optimization of Decoders for Low-Denisty Parity
Check Codes Synthesized from the OpenCL Specifications.” 2016. Masters Thesis, University of Alberta. Accessed October 16, 2019.
https://era.library.ualberta.ca/files/cjd472w72q.
MLA Handbook (7th Edition):
Maier, Andrew J. “Design and Optimization of Decoders for Low-Denisty Parity
Check Codes Synthesized from the OpenCL Specifications.” 2016. Web. 16 Oct 2019.
Vancouver:
Maier AJ. Design and Optimization of Decoders for Low-Denisty Parity
Check Codes Synthesized from the OpenCL Specifications. [Internet] [Masters thesis]. University of Alberta; 2016. [cited 2019 Oct 16].
Available from: https://era.library.ualberta.ca/files/cjd472w72q.
Council of Science Editors:
Maier AJ. Design and Optimization of Decoders for Low-Denisty Parity
Check Codes Synthesized from the OpenCL Specifications. [Masters Thesis]. University of Alberta; 2016. Available from: https://era.library.ualberta.ca/files/cjd472w72q
Université de Montréal
18.
Kemerchou, Nabil.
Logiciel de génération de nombres aléatoires dans OpenCL
.
Degree: 2016, Université de Montréal
URL: http://hdl.handle.net/1866/13473
► clRNG et clProbdist sont deux interfaces de programmation (APIs) que nous avons développées pour la génération de nombres aléatoires uniformes et non uniformes sur des…
(more)
▼ clRNG et clProbdist sont deux interfaces de programmation (APIs) que nous avons développées pour la génération de nombres aléatoires uniformes et non uniformes sur des dispositifs de calculs parallèles en utilisant l’environnement
OpenCL. La première interface permet de créer au niveau d’un ordinateur central (hôte) des objets de type stream considérés comme des générateurs virtuels parallèles qui peuvent être utilisés aussi bien sur l’hôte que sur les dispositifs parallèles (unités de traitement graphique, CPU multinoyaux, etc.) pour la génération de séquences de nombres aléatoires. La seconde interface permet aussi de générer au niveau de ces unités des variables aléatoires selon
différentes lois de probabilité continues et discrètes. Dans ce mémoire, nous allons rappeler des notions de base sur les générateurs de nombres aléatoires, décrire les systèmes hétérogènes ainsi que les techniques de génération parallèle de nombres aléatoires. Nous présenterons aussi les différents modèles composant l’architecture de l’environnement
OpenCL et détaillerons les structures des APIs développées. Nous distinguons pour clRNG les fonctions qui permettent la création des streams, les fonctions qui génèrent les variables aléatoires uniformes ainsi que celles qui manipulent les états des streams. clProbDist contient les fonctions de génération de variables aléatoires non uniformes selon la technique d’inversion ainsi que les fonctions qui permettent de retourner différentes statistiques des lois de distribution implémentées. Nous évaluerons ces interfaces de programmation avec deux simulations qui implémentent un exemple simplifié d’un modèle d’inventaire et un exemple d’une option financière. Enfin, nous fournirons les résultats d’expérimentation sur les performances des générateurs implémentés.
Advisors/Committee Members: L'Écuyer, Pierre (advisor).
Subjects/Keywords: Rng;
Parallélisme;
OpenCL;
Gpu;
Parallel computing
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APA ·
Chicago ·
MLA ·
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to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Kemerchou, N. (2016). Logiciel de génération de nombres aléatoires dans OpenCL
. (Thesis). Université de Montréal. Retrieved from http://hdl.handle.net/1866/13473
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Kemerchou, Nabil. “Logiciel de génération de nombres aléatoires dans OpenCL
.” 2016. Thesis, Université de Montréal. Accessed October 16, 2019.
http://hdl.handle.net/1866/13473.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Kemerchou, Nabil. “Logiciel de génération de nombres aléatoires dans OpenCL
.” 2016. Web. 16 Oct 2019.
Vancouver:
Kemerchou N. Logiciel de génération de nombres aléatoires dans OpenCL
. [Internet] [Thesis]. Université de Montréal; 2016. [cited 2019 Oct 16].
Available from: http://hdl.handle.net/1866/13473.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Kemerchou N. Logiciel de génération de nombres aléatoires dans OpenCL
. [Thesis]. Université de Montréal; 2016. Available from: http://hdl.handle.net/1866/13473
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade Nova
19.
Rogeiro, João Pedro Martins.
Geometry based visualization with OpenCL.
Degree: 2011, Universidade Nova
URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7951
► Dissertação para obtenção do Grau de Mestre em Engenharia Informática
This work targets the design and implementation of an isosurface extraction solution capable of handling…
(more)
▼ Dissertação para obtenção do Grau de Mestre em
Engenharia Informática
This work targets the design and implementation of an isosurface extraction solution capable of handling large datasets. The Marching Cubes algorithm is the method used to extract the isosurfaces. These are graphical representations of points with a constant value (e.g. matter density) within volumetric datasets. A very useful approach to visualize particular regions of such data.
One of the major goals of this work is to get a significant performance improvement,
compared to the currently available CPU solutions. The OpenCL framework is used to
accelerate the solution. This framework is an open standard for parallel programming of
heterogeneous systems recently proposed. Unlike previous programming frameworks
for GPUs such as CUDA, with OpenCL the workload can be distributed among CPUs,
GPUs, DSPs, and other similar microprocessors.
Advisors/Committee Members: Birra, Fernando.
Subjects/Keywords: Isosurface extraction; Volume visualization; Marching cubes; OpenCL
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APA ·
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MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Rogeiro, J. P. M. (2011). Geometry based visualization with OpenCL. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7951
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Rogeiro, João Pedro Martins. “Geometry based visualization with OpenCL.” 2011. Thesis, Universidade Nova. Accessed October 16, 2019.
http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7951.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Rogeiro, João Pedro Martins. “Geometry based visualization with OpenCL.” 2011. Web. 16 Oct 2019.
Vancouver:
Rogeiro JPM. Geometry based visualization with OpenCL. [Internet] [Thesis]. Universidade Nova; 2011. [cited 2019 Oct 16].
Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7951.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Rogeiro JPM. Geometry based visualization with OpenCL. [Thesis]. Universidade Nova; 2011. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7951
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade Nova
20.
Marques, Ricardo Jorge dos Santos.
Algorithmic skeleton framework for the orchestration of GPU computations.
Degree: 2012, Universidade Nova
URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8382
► Dissertação para obtenção do Grau de Mestre em Engenharia Informática
The Graphics Processing Unit (GPU) is gaining popularity as a co-processor to the Central Processing…
(more)
▼ Dissertação para obtenção do Grau de Mestre em
Engenharia Informática
The Graphics Processing Unit (GPU) is gaining popularity as a co-processor to the
Central Processing Unit (CPU), due to its ability to surpass the latter’s performance in certain application fields. Nonetheless, harnessing the GPU’s capabilities is a non-trivial exercise that requires good knowledge of parallel programming. Thus, providing ways to extract such computational power has become an emerging research topic.
In this context, there have been several proposals in the field of GPGPU (Generalpurpose Computation on Graphics Processing Unit) development. However, most of these still offer a low-level abstraction of the GPU computing model, forcing the developer to adapt application computations in accordance with the SPMD model, as well as
to orchestrate the low-level details of the execution. On the other hand, the higher-level approaches have limitations that prevent the full exploitation of GPUs when the purpose goes beyond the simple offloading of a kernel.
To this extent, our proposal builds on the recent trend of applying the notion of algorithmic patterns (skeletons) to GPU computing. We propose Marrow, a high-level algorithmic skeleton framework that expands the set of skeletons currently available in
this field. Marrow’s skeletons orchestrate the execution of OpenCL computations and
introduce optimizations that overlap communication and computation, thus conjoining programming simplicity with performance gains in many application scenarios. Additionally, these skeletons can be combined (nested) to create more complex applications.
We evaluated the proposed constructs by confronting them against the comparable
skeleton libraries for GPGPU, as well as against hand-tuned OpenCL programs. The
results are favourable, indicating that Marrow’s skeletons are both flexible and efficient in the context of GPU computing.
FCT-MCTES - financing the equipment
Advisors/Committee Members: Paulino, Hervé.
Subjects/Keywords: Algorithmic patterns (Skeletons); GPU computing; OpenCL
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APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Marques, R. J. d. S. (2012). Algorithmic skeleton framework for the orchestration of GPU computations. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8382
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Marques, Ricardo Jorge dos Santos. “Algorithmic skeleton framework for the orchestration of GPU computations.” 2012. Thesis, Universidade Nova. Accessed October 16, 2019.
http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8382.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Marques, Ricardo Jorge dos Santos. “Algorithmic skeleton framework for the orchestration of GPU computations.” 2012. Web. 16 Oct 2019.
Vancouver:
Marques RJdS. Algorithmic skeleton framework for the orchestration of GPU computations. [Internet] [Thesis]. Universidade Nova; 2012. [cited 2019 Oct 16].
Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8382.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Marques RJdS. Algorithmic skeleton framework for the orchestration of GPU computations. [Thesis]. Universidade Nova; 2012. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8382
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade Nova
21.
Severino, Pedro Nuno Pereira.
Aceleração da classificação de documentos com recurso a GPU.
Degree: 2012, Universidade Nova
URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8546
► Dissertação para obtenção do Grau de Mestre em Engenharia Informática
O objectivo desta dissertação é explorar formas de diminuir o tempo gasto na extracção de…
(more)
▼ Dissertação para obtenção do Grau de Mestre em
Engenharia Informática
O objectivo desta dissertação é explorar formas de diminuir o tempo gasto na extracção
de características relevantes( features) de textos disponíveis na Internet.
Esta diminuição é obtida paralelizando parte dos algoritmos usados; as versões paralelizadas
são vocacionadas para a execução em GPUs. São concebidas, implementadas
e testadas versões paralelas da fase da determinação da relevância de features num sujeito/
objecto a ser analisado. Nesta parte do trabalho a principal contribuição é uma
implementação do algoritmo de extracção de features adaptado a GPUs com ênfase nas
rotinas de manipulação de grafos. Em objectos mais complexos a implementação atingiu
tempos de execução 16 vezes inferiores à implementação sequencial em CPU.
Foi também desenvolvido um servidor concorrente que reside no GPU e que oferece
um conjunto de serviços relacionados com o processamento das features mais relevantes.
Esse servidor faz uma gestão integrada dos recursos de computação existentes no GPU. A
avaliação deste servidor foi feita sujeitando-o a diferentes misturas de sujeitos e com um
ritmo de chegada de pedidos crescente. Considerando o critériomais relevante o número
de pedidos cujo processamento excede um tempo limite, a solução baseada no servidor
GPU começa a exceder esse tempo quando o ritmo de chegada de sujeitos ultrapassa os
70 pedidos/s, enquanto que na versão multi CPU isso acontece quando o ritmo atinge
perto de 30 pedidos/s. Neste âmbito foi desenvolvida uma infra-estrutura que pode ser
reaproveitada sempre que seja conveniente usar o GPU no paradigma do processamento
de pedidos em lote.
Esta tese foi desenvolvida num contexto empresarial, e do trabalho realizado resultam
contributos para o melhoramento dos produtos da empresa, bem como da viabilidade
técnica e económica do uso de GPUs em diversos contextos relevantes para a empresa.
Neste contexto a versão definitiva da tese omite alguma informação.
Advisors/Committee Members: Medeiros, Pedro.
Subjects/Keywords: OpenCL; Computação paralela; GPU; Classificação de documentos
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to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Severino, P. N. P. (2012). Aceleração da classificação de documentos com recurso a GPU. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8546
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Severino, Pedro Nuno Pereira. “Aceleração da classificação de documentos com recurso a GPU.” 2012. Thesis, Universidade Nova. Accessed October 16, 2019.
http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8546.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Severino, Pedro Nuno Pereira. “Aceleração da classificação de documentos com recurso a GPU.” 2012. Web. 16 Oct 2019.
Vancouver:
Severino PNP. Aceleração da classificação de documentos com recurso a GPU. [Internet] [Thesis]. Universidade Nova; 2012. [cited 2019 Oct 16].
Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8546.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Severino PNP. Aceleração da classificação de documentos com recurso a GPU. [Thesis]. Universidade Nova; 2012. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/8546
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade Nova
22.
Soldado, Fábio Miguel Cardoso.
Heterogeneous computing with an algorithmic skeleton framework.
Degree: 2014, Universidade Nova
URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13245
► The Graphics Processing Unit (GPU) is present in almost every modern day personal computer. Despite its specific purpose design, they have been increasingly used for…
(more)
▼ The Graphics Processing Unit (GPU) is present in almost every modern day personal
computer. Despite its specific purpose design, they have been increasingly used for general
computations with very good results. Hence, there is a growing effort from the community
to seamlessly integrate this kind of devices in everyday computing. However, to
fully exploit the potential of a system comprising GPUs and CPUs, these devices should
be presented to the programmer as a single platform.
The efficient combination of the power of CPU and GPU devices is highly dependent
on each device’s characteristics, resulting in platform specific applications that cannot
be ported to different systems. Also, the most efficient work balance among devices is
highly dependable on the computations to be performed and respective data sizes.
In this work, we propose a solution for heterogeneous environments based on the
abstraction level provided by algorithmic skeletons. Our goal is to take full advantage of
the power of all CPU and GPU devices present in a system, without the need for different
kernel implementations nor explicit work-distribution.To that end, we extended Marrow,
an algorithmic skeleton framework for multi-GPUs, to support CPU computations and
efficiently balance the work-load between devices. Our approach is based on an offline
training execution that identifies the ideal work balance and platform configurations for
a given application and input data size.
The evaluation of this work shows that the combination of CPU and GPU devices can
significantly boost the performance of our benchmarks in the tested environments, when
compared to GPU-only executions.
Advisors/Committee Members: Paulino, Hervé.
Subjects/Keywords: Algorithmic skeletons; OpenCL; GPGPU; Heterogeneous computing
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to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Soldado, F. M. C. (2014). Heterogeneous computing with an algorithmic skeleton framework. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13245
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Soldado, Fábio Miguel Cardoso. “Heterogeneous computing with an algorithmic skeleton framework.” 2014. Thesis, Universidade Nova. Accessed October 16, 2019.
http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13245.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Soldado, Fábio Miguel Cardoso. “Heterogeneous computing with an algorithmic skeleton framework.” 2014. Web. 16 Oct 2019.
Vancouver:
Soldado FMC. Heterogeneous computing with an algorithmic skeleton framework. [Internet] [Thesis]. Universidade Nova; 2014. [cited 2019 Oct 16].
Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13245.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Soldado FMC. Heterogeneous computing with an algorithmic skeleton framework. [Thesis]. Universidade Nova; 2014. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13245
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
23.
Fernández Fabeiro, Jorge.
Tools for improving performance portability in heterogeneous environments
.
Degree: 2017, Universidad da Coruña
URL: http://hdl.handle.net/2183/19307
► [Abstract] Parallel computing is currently partially dominated by the availability of heterogeneous devices. These devices differ from each other in aspects such as the instruction…
(more)
▼ [Abstract]
Parallel computing is currently partially dominated by the availability of heterogeneous
devices. These devices differ from each other in aspects such as the
instruction set they execute, the number and the type of computing devices that
they offer or the structure of their memory systems. In the last years, langnages,
libraries and extensions have appeared to allow to write a parallel code once aud
run it in a wide variety of devices,
OpenCL being the most widespread solution of
this kind. However, functional portability does not imply performance portability.
This way, one of the probletns that is still open in this field is to achieve automatic
performance portability. That is, the ability to automatically tune a given code for
any device where it will be execnted so that it ill obtain a good performance. This
thesis develops three different solutions to tackle this problem. The three of them
are based on typical source-to-sonrce optimizations for heterogeneous devices. Both
the set of optimizations to apply and the way they are applied depend on different
optimization parameters, whose values have to be tuned for each specific device.
The first solution is OCLoptimizer, a source-to-source optimizer that can optimize
annotated
OpenCL kemels with the help of configuration files that guide the
optimization process. The tool optimizes kernels for a specific device, and it is also
able to automate the generation of functional host codes when only a single kernel
is optimized.
The two remaining solutions are built on top of the Heterogeneous Programming
Library (HPL), a C++ framework that provides an easy and portable way to exploit
heterogeneous computing systexns. The first of these solutions uses the run-time
code generation capabilities of HPL to generate a self-optimizing version of a matrix
multiplication that can optimize itself at run-time for an spedfic device. The last solutíon is the development of a built-in just-in-time optirnizer for HPL, that can
optirnize, at run-tirne, a HPL code for an specific device. While the first two solutions
use search processes to find the best values for the optimization parameters, this Iast
alternative relies on heuristics bMed on general optirnization strategies.
Advisors/Committee Members: Andrade Canosa, Diego (advisor), Fraguela Rodríguez, Basilio Bernardo (advisor).
Subjects/Keywords: Programación paralela (Informática);
OpenCL (Lenguaje de programación)
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APA ·
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Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Fernández Fabeiro, J. (2017). Tools for improving performance portability in heterogeneous environments
. (Doctoral Dissertation). Universidad da Coruña. Retrieved from http://hdl.handle.net/2183/19307
Chicago Manual of Style (16th Edition):
Fernández Fabeiro, Jorge. “Tools for improving performance portability in heterogeneous environments
.” 2017. Doctoral Dissertation, Universidad da Coruña. Accessed October 16, 2019.
http://hdl.handle.net/2183/19307.
MLA Handbook (7th Edition):
Fernández Fabeiro, Jorge. “Tools for improving performance portability in heterogeneous environments
.” 2017. Web. 16 Oct 2019.
Vancouver:
Fernández Fabeiro J. Tools for improving performance portability in heterogeneous environments
. [Internet] [Doctoral dissertation]. Universidad da Coruña; 2017. [cited 2019 Oct 16].
Available from: http://hdl.handle.net/2183/19307.
Council of Science Editors:
Fernández Fabeiro J. Tools for improving performance portability in heterogeneous environments
. [Doctoral Dissertation]. Universidad da Coruña; 2017. Available from: http://hdl.handle.net/2183/19307
Delft University of Technology
24.
Raskovic, M.
An OpenCL-based Solution for Portable Bodyscan SAR Processing on Multicore Platforms:.
Degree: 2010, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:f1ed9655-5bdd-4295-ae0d-6552ee66489b
► Multicore systems have become an indispensable part of our everyday life. They represent a viable alternative for increasing processor performance without hitting the memory and…
(more)
▼ Multicore systems have become an indispensable part of our everyday life. They represent a viable alternative for increasing processor performance without hitting the memory and power walls. However, the shift from traditional programming to multicore programming has a critical influence in three dimensions: the applications, the software tools, and the hardware platforms.
In this thesis, we focus on the application dimension, and we investigate the performance potential of a 3D bodyscan SAR processing algorithm running on several multi-core processors. To allow for the processor variety, the solutions are based on
OpenCL, a language that enables inter-platform portability for a large set of multicores. To allow for performance, we choose to mainly evaluate and optimize for NVIDIA GPUs, but also for Intel GPPs and ATI GPU.
Our solutions design and implementation follow a step-by-step strategy.
First, we analyse the application to determine its functionality, data characteristics, and performance requirements. Next, we design and implement a sequential reference solution, and we evaluate its performance. We use this particular solution to design a set of possible parallel solutions, which are also evaluated in terms of performance and platform utilization, using a generic prototyping platform. Further, we select the most promising parallel solution for a first portable
OpenCL implementation. All platform-agnostic basic optimizations, are applied now, towards a new application, with increased performance and no decrease in portability. After these basic optimizations, we show how several platform-specific optimizations can be applied. Basically, in this step, we trade portability for performance. For this work, we specifically target NVIDIA GPUs, and we show the potential performance impact of data and memory-related optimizations on the case-study application.
Finally, we gather all these steps and findings into a generic, empirical strategy that enables programmers to reason about
OpenCL applications in a systematic manner, letting them decide the level of the trade-off between the application portability and performance.
Our main conclusions are twofold. First, we conclude that
OpenCL is a promising standard (and language) for enforcing the implementation of portable multicore applications. Second, we conclude that the bodyscan application is a good fit for running on multicore platforms, and we recommend the GPUs as the target platform for such an application.
For future work, we propose to advance in two directions. First, as generic research, we propose to focus on the strategy validation and refining, as well as on a more abstract way to derive the parallel
OpenCL versions. Second, on the application/technical side, we plan to focus on finding and implementing hardware-dependent optimizations of the
OpenCL solution on various hardware platforms.
Advisors/Committee Members: Sips, H., Varbanescu, A.L..
Subjects/Keywords: milticore; SAR processing; bodyscan; OpenCL; portability
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APA (6th Edition):
Raskovic, M. (2010). An OpenCL-based Solution for Portable Bodyscan SAR Processing on Multicore Platforms:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:f1ed9655-5bdd-4295-ae0d-6552ee66489b
Chicago Manual of Style (16th Edition):
Raskovic, M. “An OpenCL-based Solution for Portable Bodyscan SAR Processing on Multicore Platforms:.” 2010. Masters Thesis, Delft University of Technology. Accessed October 16, 2019.
http://resolver.tudelft.nl/uuid:f1ed9655-5bdd-4295-ae0d-6552ee66489b.
MLA Handbook (7th Edition):
Raskovic, M. “An OpenCL-based Solution for Portable Bodyscan SAR Processing on Multicore Platforms:.” 2010. Web. 16 Oct 2019.
Vancouver:
Raskovic M. An OpenCL-based Solution for Portable Bodyscan SAR Processing on Multicore Platforms:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2019 Oct 16].
Available from: http://resolver.tudelft.nl/uuid:f1ed9655-5bdd-4295-ae0d-6552ee66489b.
Council of Science Editors:
Raskovic M. An OpenCL-based Solution for Portable Bodyscan SAR Processing on Multicore Platforms:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:f1ed9655-5bdd-4295-ae0d-6552ee66489b
Delft University of Technology
25.
Van der Wijst, H.
An Accelerator based on the ρ-VEX Processor: an Exploration using OpenCL:.
Degree: 2015, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:3f184afb-241d-4d54-827d-75fcd59211a5
► In recent years the use of co-processors to accelerate specific tasks is becoming more common. To simplify the use of these accelerators in software, the…
(more)
▼ In recent years the use of co-processors to accelerate specific tasks is becoming more common. To simplify the use of these accelerators in software, the
OpenCL framework has been developed. This framework provides programs a cross-platform interface for using accelerators.
The ρ-VEX processor is a run-time reconfigurable VLIW processor. It allows run-time switching of configurations, executing a large amount of contexts with low issue-width or a low amount of contexts with high issue-width.
This thesis investigates if the ρ-VEX processor can be competitively used as an accelerator using
OpenCL. To answer this question, a design and implementation is made of such an accelerator. By measuring the speed of various components of this implementation, a model is created for the run-time of a kernel. Using this model, a projection is made of the execution time on an accelerator produced as an ASIC.
For the implementation of the accelerator, the ρ-VEX processor is instantiated on an FPGA and connected to the host using the PCI Express bus. A Linux kernel driver has been developed to provide interfaces for user space applications to communicate with the accelerator. These interfaces are used to implement a new device-layer for the pocl
OpenCL framework.
By modeling the execution time, three major contributing factors to the execution time were found: the data transfer throughput, the kernel compile time, and the kernel execution time. It is projected that an accelerator based on the ρ-VEX processor, using similar production technologies and without architectural changes, can achieve 1.2 to 0.11 times the performance of a modern GPU.
Advisors/Committee Members: Wong, J.S.S.M..
Subjects/Keywords: ρ-VEX; rVEX; OpenCL; pocl; accelerator
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APA (6th Edition):
Van der Wijst, H. (2015). An Accelerator based on the ρ-VEX Processor: an Exploration using OpenCL:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:3f184afb-241d-4d54-827d-75fcd59211a5
Chicago Manual of Style (16th Edition):
Van der Wijst, H. “An Accelerator based on the ρ-VEX Processor: an Exploration using OpenCL:.” 2015. Masters Thesis, Delft University of Technology. Accessed October 16, 2019.
http://resolver.tudelft.nl/uuid:3f184afb-241d-4d54-827d-75fcd59211a5.
MLA Handbook (7th Edition):
Van der Wijst, H. “An Accelerator based on the ρ-VEX Processor: an Exploration using OpenCL:.” 2015. Web. 16 Oct 2019.
Vancouver:
Van der Wijst H. An Accelerator based on the ρ-VEX Processor: an Exploration using OpenCL:. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2019 Oct 16].
Available from: http://resolver.tudelft.nl/uuid:3f184afb-241d-4d54-827d-75fcd59211a5.
Council of Science Editors:
Van der Wijst H. An Accelerator based on the ρ-VEX Processor: an Exploration using OpenCL:. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:3f184afb-241d-4d54-827d-75fcd59211a5
Delft University of Technology
26.
Penders, A.
Accelerating Graph Analysis with Heterogeneous Systems:.
Degree: 2012, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:7f3eeb52-77bd-4fdb-84a9-ea9ca0a35b94
► Data analysis is a rising field of interest for computer science research due to the growing amount of information that is digitally available. This increase…
(more)
▼ Data analysis is a rising field of interest for computer science research due to the growing amount of information that is digitally available. This increase in data has as direct consequence that any analysis is significantly complex. By using structured representations for the data sets, like graphs, the analysis becomes feasible, but is still time-consuming. In this project, the focus is on the reduction of the computational time for data analysis, with the introduction of accelerators.
Accelerators are specialized hardware components that assist the general processing unit in performing (parts of) the task at hand. In particular, we focus on the use of General Purpose Graphical Processing Units (GPGPU) to help speedup the analysis. GPUs are specifically designed for representing and manipulating graphical data which invoke the processing of large chunks of data, GPUs are designed with large numbers of concurrent processing units and thus have a high potential of improving performance.
In this project, we show the impact of using GPGPUs for both simple and more complex analysis, varying from small to large data sets, with the use of a programming model called
OpenCL. We compare the performance of using accelerators against the traditional CPU-based implementation. Due to the inter-platform portability of the
OpenCL model, such comparison can be performed without having to alter the algorithm.
The use of accelerators is expected to become beneficial for analysis that require large computational power. For example, search algorithms (that require little to no computation) are not expected to profit from accelerators, while the more complex, centrality analysis is expected to have significantly more benefit from accelerators. Our results clearly shows this shift of performance improvement when algorithms further utilize the potential of accelerators, because the analysis grows in size and/ or complexity.
Advisors/Committee Members: Varbanescu, A.L..
Subjects/Keywords: GPU; graph; Graph analysis; accelerators; OpenCL; parallel
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APA (6th Edition):
Penders, A. (2012). Accelerating Graph Analysis with Heterogeneous Systems:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:7f3eeb52-77bd-4fdb-84a9-ea9ca0a35b94
Chicago Manual of Style (16th Edition):
Penders, A. “Accelerating Graph Analysis with Heterogeneous Systems:.” 2012. Masters Thesis, Delft University of Technology. Accessed October 16, 2019.
http://resolver.tudelft.nl/uuid:7f3eeb52-77bd-4fdb-84a9-ea9ca0a35b94.
MLA Handbook (7th Edition):
Penders, A. “Accelerating Graph Analysis with Heterogeneous Systems:.” 2012. Web. 16 Oct 2019.
Vancouver:
Penders A. Accelerating Graph Analysis with Heterogeneous Systems:. [Internet] [Masters thesis]. Delft University of Technology; 2012. [cited 2019 Oct 16].
Available from: http://resolver.tudelft.nl/uuid:7f3eeb52-77bd-4fdb-84a9-ea9ca0a35b94.
Council of Science Editors:
Penders A. Accelerating Graph Analysis with Heterogeneous Systems:. [Masters Thesis]. Delft University of Technology; 2012. Available from: http://resolver.tudelft.nl/uuid:7f3eeb52-77bd-4fdb-84a9-ea9ca0a35b94
University of Toronto
27.
Diop, Tahir.
Regression Modelling of Power Consumption for Heterogeneous Processors.
Degree: 2013, University of Toronto
URL: http://hdl.handle.net/1807/42818
► This thesis is composed of two parts, that relate to both parallel and heterogeneous processing. The first describes DistCL, a distributed OpenCL framework that allows…
(more)
▼ This thesis is composed of two parts, that relate to both parallel and heterogeneous processing.
The first describes DistCL, a distributed OpenCL framework that allows a cluster of GPUs to be programmed like a single device.
It uses programmer-supplied meta-functions that associate work-items to memory.
DistCL achieves speedups of up to 29x using 32 peers.
By comparing DistCL to SnuCL, we determine that the compute-to-transfer ratio of a benchmark is the best predictor of its performance scaling when distributed.
The second is a statistical power model for the AMD Fusion heterogeneous processor.
We present a systematic methodology to create a representative set of compute micro-benchmarks using data collected from real hardware.
The power model is created with data from both micro-benchmarks and application benchmarks.
The model showed an average predictive error of 6.9% on heterogeneous workloads.
The Multi2Sim heterogeneous simulator was modified to support configurable power modelling.
MAST
Advisors/Committee Members: Anderson, Jason, Jerger, Natalie Enright, Electrical and Computer Engineering.
Subjects/Keywords: Power Modelling; OpenCL; Simulation; Benchmarking; 0544; 0984
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APA ·
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APA (6th Edition):
Diop, T. (2013). Regression Modelling of Power Consumption for Heterogeneous Processors. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/42818
Chicago Manual of Style (16th Edition):
Diop, Tahir. “Regression Modelling of Power Consumption for Heterogeneous Processors.” 2013. Masters Thesis, University of Toronto. Accessed October 16, 2019.
http://hdl.handle.net/1807/42818.
MLA Handbook (7th Edition):
Diop, Tahir. “Regression Modelling of Power Consumption for Heterogeneous Processors.” 2013. Web. 16 Oct 2019.
Vancouver:
Diop T. Regression Modelling of Power Consumption for Heterogeneous Processors. [Internet] [Masters thesis]. University of Toronto; 2013. [cited 2019 Oct 16].
Available from: http://hdl.handle.net/1807/42818.
Council of Science Editors:
Diop T. Regression Modelling of Power Consumption for Heterogeneous Processors. [Masters Thesis]. University of Toronto; 2013. Available from: http://hdl.handle.net/1807/42818
University of Toronto
28.
Gurfinkel, Steven.
The Distribution of OpenCL Kernel Execution Across Multiple Devices.
Degree: 2014, University of Toronto
URL: http://hdl.handle.net/1807/67879
► Many computer systems now include both CPUs and programmable GPUs. OpenCL, a new programming framework, can program individual CPUs or GPUs; however, distributing a problem…
(more)
▼ Many computer systems now include both CPUs and programmable GPUs. OpenCL, a new programming framework, can program individual CPUs or GPUs; however, distributing a problem across multiple devices is more difficult. This thesis contributes three OpenCL runtimes that automatically distribute a problem across multiple devices: DualCL and m2sOpenCL, which distribute tasks across a single system's CPU and GPU, and DistCL, which distributes tasks across a cluster's GPUs. DualCL and DistCL run on existing hardware, m2sOpenCL runs in simulation. On a system with a discrete GPU and a system with integrated CPU and GPU devices, running programs from the Rodinia benchmark suite, DualCL improves performance over a single device, when host memory is used. Running similar benchmarks, m2sOpenCL shows that reducing the overheads present in current systems improves performance. DistCL accelerates unmodified compute intense OpenCL kernels, obtained from Rodinia, AMD samples and elsewhere, when distributing them across a cluster.
M.A.S.
Advisors/Committee Members: Jerger, Natalie Enright, Electrical and Computer Engineering.
Subjects/Keywords: Distributed; GPGPU; GPU; Heterogeneous; OpenCL; 0464
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APA ·
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APA (6th Edition):
Gurfinkel, S. (2014). The Distribution of OpenCL Kernel Execution Across Multiple Devices. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/67879
Chicago Manual of Style (16th Edition):
Gurfinkel, Steven. “The Distribution of OpenCL Kernel Execution Across Multiple Devices.” 2014. Masters Thesis, University of Toronto. Accessed October 16, 2019.
http://hdl.handle.net/1807/67879.
MLA Handbook (7th Edition):
Gurfinkel, Steven. “The Distribution of OpenCL Kernel Execution Across Multiple Devices.” 2014. Web. 16 Oct 2019.
Vancouver:
Gurfinkel S. The Distribution of OpenCL Kernel Execution Across Multiple Devices. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2019 Oct 16].
Available from: http://hdl.handle.net/1807/67879.
Council of Science Editors:
Gurfinkel S. The Distribution of OpenCL Kernel Execution Across Multiple Devices. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/67879
University of Toronto
29.
Ahmed, Taneem.
OpenCL Framework for a CPU, GPU, and FPGA Platform.
Degree: 2011, University of Toronto
URL: http://hdl.handle.net/1807/30149
► With the availability of multi-core processors, high capacity FPGAs, and GPUs, a heterogeneous platform with tremendous raw computing capacity can be constructed consisting of any…
(more)
▼ With the availability of multi-core processors, high capacity FPGAs, and GPUs, a heterogeneous platform with tremendous raw computing capacity can be constructed consisting of any number of these computing elements. However, one of the major challenges for constructing such a platform is the lack of a standardized framework under which an application’s computational task and data can be easily and effectively managed amongst the computing elements. In this thesis work such a framework is developed based on OpenCL (Open Computing Language). An OpenCL API and run time framework, called O4F, was implemented to incorporate FPGAs in a platform with CPUs and GPUs under the OpenCL framework. O4F help explore the possibility of using OpenCL as the framework to incorporate FPGAs with CPUs and GPUs. This thesis details the findings of this first-generation implementation and provides recommendations for future work.
MAST
Advisors/Committee Members: Chow, Paul, Electrical and Computer Engineering.
Subjects/Keywords: FPGA; Heterogeneous Computing; OpenCL; Reconfigurable Computing; 0544
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APA (6th Edition):
Ahmed, T. (2011). OpenCL Framework for a CPU, GPU, and FPGA Platform. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/30149
Chicago Manual of Style (16th Edition):
Ahmed, Taneem. “OpenCL Framework for a CPU, GPU, and FPGA Platform.” 2011. Masters Thesis, University of Toronto. Accessed October 16, 2019.
http://hdl.handle.net/1807/30149.
MLA Handbook (7th Edition):
Ahmed, Taneem. “OpenCL Framework for a CPU, GPU, and FPGA Platform.” 2011. Web. 16 Oct 2019.
Vancouver:
Ahmed T. OpenCL Framework for a CPU, GPU, and FPGA Platform. [Internet] [Masters thesis]. University of Toronto; 2011. [cited 2019 Oct 16].
Available from: http://hdl.handle.net/1807/30149.
Council of Science Editors:
Ahmed T. OpenCL Framework for a CPU, GPU, and FPGA Platform. [Masters Thesis]. University of Toronto; 2011. Available from: http://hdl.handle.net/1807/30149
University of Windsor
30.
Tang, Qing Yun.
FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.
Degree: MA, Electrical and Computer Engineering, 2016, University of Windsor
URL: https://scholar.uwindsor.ca/etd/5669
► FPGAs have shown great promise for accelerating computationally intensive algorithms. However, FPGA-based accelerator design is tedious and time consuming if we rely on traditional HDL…
(more)
▼ FPGAs have shown great promise for accelerating computationally intensive algorithms. However, FPGA-based accelerator design is tedious and time consuming if we rely on traditional HDL based design method. Recent introduction of Altera SDK for
OpenCL (AOCL) high level synthesis tool enables developers to utilize FPGA’s potential without long development time and extensive hardware knowledge.
AOCL is used in this thesis to accelerate computationally intensive algorithms in the field of machine learning and scientific computing. The algorithms studied are k-means clustering, k-nearest neighbour search, N-body simulation and LU decomposition. The performance and power consumption of the algorithms synthesized using AOCL for FPGA are evaluated against state of the art CPU and GPU implementations. The k-means clustering and k-nearest neighbor kernels designed for FPGA significantly out-performed optimized CPU implementations while achieving similar or better power efficiency than that of GPU.
Advisors/Committee Members: Khalid, Mohammed.
Subjects/Keywords: FPGA; Hardware Acceleration; High Level Synthesis; OpenCL
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APA ·
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APA (6th Edition):
Tang, Q. Y. (2016). FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5669
Chicago Manual of Style (16th Edition):
Tang, Qing Yun. “FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.” 2016. Masters Thesis, University of Windsor. Accessed October 16, 2019.
https://scholar.uwindsor.ca/etd/5669.
MLA Handbook (7th Edition):
Tang, Qing Yun. “FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.” 2016. Web. 16 Oct 2019.
Vancouver:
Tang QY. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. [Internet] [Masters thesis]. University of Windsor; 2016. [cited 2019 Oct 16].
Available from: https://scholar.uwindsor.ca/etd/5669.
Council of Science Editors:
Tang QY. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. [Masters Thesis]. University of Windsor; 2016. Available from: https://scholar.uwindsor.ca/etd/5669
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Open Access Theses and Dissertations
