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You searched for subject:(On chip Management And Construction). Showing records 1 – 30 of 562501 total matches.

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Hong Kong University of Science and Technology

1. Qian, Zhiliang. High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization.

Degree: 2014, Hong Kong University of Science and Technology

 With technology scaling down, hundreds and thousands processing elements (PEs) can be integrated on a single chip. Consequently, the embedded systems have led to the… (more)

Subjects/Keywords: Systems on a chip ; Design and construction ; Networks on a chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Qian, Z. (2014). High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Qian, Zhiliang. “High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed April 04, 2020. http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Qian, Zhiliang. “High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization.” 2014. Web. 04 Apr 2020.

Vancouver:

Qian Z. High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2020 Apr 04]. Available from: http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Qian Z. High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: http://repository.ust.hk/ir/Record/1783.1-62809 ; https://doi.org/10.14711/thesis-b1288919 ; http://repository.ust.hk/ir/bitstream/1783.1-62809/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

2. Liu, Weichen. Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip.

Degree: 2011, Hong Kong University of Science and Technology

 As feature sizes continue to shrink with the advancement of nanotechnology, multiprocessor system-on-chip (MPSoC) becomes a promising solution to satisfy the growing demands of future… (more)

Subjects/Keywords: Digital light processing ; Networks on a chip  – Design and construction ; Multiprocessors ; Systems on a chip  – Design and construction ; Integrated circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, W. (2011). Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-7321 ; https://doi.org/10.14711/thesis-b1155165 ; http://lbdiscover.ust.hk/uresolver?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rfr_id=info:sid/HKUST:SPI&rft.genre=article&rft.issn=0258-7025&rft.volume=39&rft.issue=SUPPL.2&rft.date=2011&rft.spage=&rft.aulast=Liu&rft.aufirst=Weichen&rft.atitle=Design+and+optimization+of+high-performance+resilient+network-on-chip+based+multiprocessor+system-on-chip&rft.title=%E4%B8%AD%E5%9B%BD%E6%BF%80%E5%85%89 ; http://repository.ust.hk/ir/bitstream/1783.1-7321/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Weichen. “Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip.” 2011. Thesis, Hong Kong University of Science and Technology. Accessed April 04, 2020. http://repository.ust.hk/ir/Record/1783.1-7321 ; https://doi.org/10.14711/thesis-b1155165 ; http://lbdiscover.ust.hk/uresolver?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rfr_id=info:sid/HKUST:SPI&rft.genre=article&rft.issn=0258-7025&rft.volume=39&rft.issue=SUPPL.2&rft.date=2011&rft.spage=&rft.aulast=Liu&rft.aufirst=Weichen&rft.atitle=Design+and+optimization+of+high-performance+resilient+network-on-chip+based+multiprocessor+system-on-chip&rft.title=%E4%B8%AD%E5%9B%BD%E6%BF%80%E5%85%89 ; http://repository.ust.hk/ir/bitstream/1783.1-7321/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Weichen. “Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip.” 2011. Web. 04 Apr 2020.

Vancouver:

Liu W. Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2011. [cited 2020 Apr 04]. Available from: http://repository.ust.hk/ir/Record/1783.1-7321 ; https://doi.org/10.14711/thesis-b1155165 ; http://lbdiscover.ust.hk/uresolver?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rfr_id=info:sid/HKUST:SPI&rft.genre=article&rft.issn=0258-7025&rft.volume=39&rft.issue=SUPPL.2&rft.date=2011&rft.spage=&rft.aulast=Liu&rft.aufirst=Weichen&rft.atitle=Design+and+optimization+of+high-performance+resilient+network-on-chip+based+multiprocessor+system-on-chip&rft.title=%E4%B8%AD%E5%9B%BD%E6%BF%80%E5%85%89 ; http://repository.ust.hk/ir/bitstream/1783.1-7321/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu W. Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip. [Thesis]. Hong Kong University of Science and Technology; 2011. Available from: http://repository.ust.hk/ir/Record/1783.1-7321 ; https://doi.org/10.14711/thesis-b1155165 ; http://lbdiscover.ust.hk/uresolver?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rfr_id=info:sid/HKUST:SPI&rft.genre=article&rft.issn=0258-7025&rft.volume=39&rft.issue=SUPPL.2&rft.date=2011&rft.spage=&rft.aulast=Liu&rft.aufirst=Weichen&rft.atitle=Design+and+optimization+of+high-performance+resilient+network-on-chip+based+multiprocessor+system-on-chip&rft.title=%E4%B8%AD%E5%9B%BD%E6%BF%80%E5%85%89 ; http://repository.ust.hk/ir/bitstream/1783.1-7321/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

3. Vikas, G. Power Optimal Network-On-Chip Interconnect Design.

Degree: 2010, Indian Institute of Science

 A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power… (more)

Subjects/Keywords: Network On Chip - Design and Construction; Electric Power Networks; Application Specific System On Chip; Routers (Computer Networks); Chip Multi Core Processor; Network-on-Chip Interconnect Design; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vikas, G. (2010). Power Optimal Network-On-Chip Interconnect Design. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1408

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Thesis, Indian Institute of Science. Accessed April 04, 2020. http://hdl.handle.net/2005/1408.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Web. 04 Apr 2020.

Vancouver:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2005/1408.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Thesis]. Indian Institute of Science; 2010. Available from: http://hdl.handle.net/2005/1408

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

4. Vikas, G. Power Optimal Network-On-Chip Interconnect Design.

Degree: 2010, Indian Institute of Science

 A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power… (more)

Subjects/Keywords: Network On Chip - Design and Construction; Electric Power Networks; Application Specific System On Chip; Routers (Computer Networks); Chip Multi Core Processor; Network-on-Chip Interconnect Design; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vikas, G. (2010). Power Optimal Network-On-Chip Interconnect Design. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Thesis, Indian Institute of Science. Accessed April 04, 2020. http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Web. 04 Apr 2020.

Vancouver:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2020 Apr 04]. Available from: http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Thesis]. Indian Institute of Science; 2010. Available from: http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

5. Obaidullah, Muhammad. Application mapping and NoC configuration using hybrid particle swarm optimization.

Degree: 2017, Ryerson University

 Network-on-Chip (NoC) has been proposed as an interconnection framework for connecting large number of cores for a System-on-Chip (SoC). Assuming a mesh-based NoC, we investigate… (more)

Subjects/Keywords: Mathematical optimization.; Networks on a chip  – Design and construction.; Swarm intelligence.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Obaidullah, M. (2017). Application mapping and NoC configuration using hybrid particle swarm optimization. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6881

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Obaidullah, Muhammad. “Application mapping and NoC configuration using hybrid particle swarm optimization.” 2017. Thesis, Ryerson University. Accessed April 04, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A6881.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Obaidullah, Muhammad. “Application mapping and NoC configuration using hybrid particle swarm optimization.” 2017. Web. 04 Apr 2020.

Vancouver:

Obaidullah M. Application mapping and NoC configuration using hybrid particle swarm optimization. [Internet] [Thesis]. Ryerson University; 2017. [cited 2020 Apr 04]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6881.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Obaidullah M. Application mapping and NoC configuration using hybrid particle swarm optimization. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6881

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Portland State University

6. Chung, Haera. Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip.

Degree: PhD, Electrical and Computer Engineering, 2013, Portland State University

  Communication has become a bottleneck for modern microprocessors and multi-core chips because metal wires don't scale. The problem becomes worse as the number of… (more)

Subjects/Keywords: Networks on a chip; Systems on a chip  – Design and construction; Heterogeneous computing; Computer and Systems Architecture; Systems and Communications

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chung, H. (2013). Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/997

Chicago Manual of Style (16th Edition):

Chung, Haera. “Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip.” 2013. Doctoral Dissertation, Portland State University. Accessed April 04, 2020. https://pdxscholar.library.pdx.edu/open_access_etds/997.

MLA Handbook (7th Edition):

Chung, Haera. “Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip.” 2013. Web. 04 Apr 2020.

Vancouver:

Chung H. Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip. [Internet] [Doctoral dissertation]. Portland State University; 2013. [cited 2020 Apr 04]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/997.

Council of Science Editors:

Chung H. Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip. [Doctoral Dissertation]. Portland State University; 2013. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/997


Ryerson University

7. Lai, Xiongliang. Design techniques for passive wireless microsystems.

Degree: 2013, Ryerson University

 The unique advantage of harvesting power wirelessly has evolved passive wireless microsystems to a fast-growing high-impact technology. In this dissertation, several new design techniques are… (more)

Subjects/Keywords: Passive components; Linear integrated circuits  – Design and construction; On-chip charge pumps  – Design and construction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lai, X. (2013). Design techniques for passive wireless microsystems. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A3042

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lai, Xiongliang. “Design techniques for passive wireless microsystems.” 2013. Thesis, Ryerson University. Accessed April 04, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A3042.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lai, Xiongliang. “Design techniques for passive wireless microsystems.” 2013. Web. 04 Apr 2020.

Vancouver:

Lai X. Design techniques for passive wireless microsystems. [Internet] [Thesis]. Ryerson University; 2013. [cited 2020 Apr 04]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A3042.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lai X. Design techniques for passive wireless microsystems. [Thesis]. Ryerson University; 2013. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A3042

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

8. Basavaraj, T. NoC Design & Optimization of Multicore Media Processors.

Degree: 2013, Indian Institute of Science

 Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of… (more)

Subjects/Keywords: Network-On-Chip (NOC); Quality of Service (QOS); Label Switched Network On Chip (LS-NoC); Chip Multiprocessor Designs; Multicore Media Processors; Network-On-Chip (NOC) - Design and Construction; System on Chip (SoC); Link Microarchitectural Exploration, Network-on-Chip (NOC); Tile Exploration - Chip Multiprocessors (CMP); Ford-Fulkerson’s MaxFlow Algorithm; Flow Algorithm; Network-on-Chips; On-Chip Interconnection Networks; Microarchitecture Exploration; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Basavaraj, T. (2013). NoC Design & Optimization of Multicore Media Processors. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2013. Thesis, Indian Institute of Science. Accessed April 04, 2020. http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Basavaraj, T. “NoC Design & Optimization of Multicore Media Processors.” 2013. Web. 04 Apr 2020.

Vancouver:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2020 Apr 04]. Available from: http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Basavaraj T. NoC Design & Optimization of Multicore Media Processors. [Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ernet.in/2005/3296 ; http://etd.ncsi.iisc.ernet.in/abstracts/4158/G25655-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

9. Das, Bishnu Prasad. Random Local Delay Variability : On-chip Measurement And Modeling.

Degree: 2009, Indian Institute of Science

 This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in… (more)

Subjects/Keywords: Electronic Gates - Design; On-chip Management And Construction; Electronic Gate Delay - Modeling; Random Local Delay Variation; On-chip Gate Delay Measurement; Process Voltage And Temperature Gate Delay Model; Electronic Gate Delay - Measurement; Statistical Static Timing Analysis (SSTA); Gate Delay Variability Measurement; Delay Variability; On-chip Measurement; Gate Delay Models; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Das, B. P. (2009). Random Local Delay Variability : On-chip Measurement And Modeling. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Thesis, Indian Institute of Science. Accessed April 04, 2020. http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Web. 04 Apr 2020.

Vancouver:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Columbia University

10. Kim, Doyun. Fully Integrated Digital Low-Drop-Out Regulator Design based on Event-Driven PI Control.

Degree: 2019, Columbia University

 A system-on-chip (SoC) with near-threshold supply voltage (NTV) operation has received a significant amount of attention. Its high energy-efficiency supports a number of low-power emerging… (more)

Subjects/Keywords: Electrical engineering; Systems on a chip; Voltage regulators; Voltage regulators – Design and construction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, D. (2019). Fully Integrated Digital Low-Drop-Out Regulator Design based on Event-Driven PI Control. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/d8-kfrq-qa27

Chicago Manual of Style (16th Edition):

Kim, Doyun. “Fully Integrated Digital Low-Drop-Out Regulator Design based on Event-Driven PI Control.” 2019. Doctoral Dissertation, Columbia University. Accessed April 04, 2020. https://doi.org/10.7916/d8-kfrq-qa27.

MLA Handbook (7th Edition):

Kim, Doyun. “Fully Integrated Digital Low-Drop-Out Regulator Design based on Event-Driven PI Control.” 2019. Web. 04 Apr 2020.

Vancouver:

Kim D. Fully Integrated Digital Low-Drop-Out Regulator Design based on Event-Driven PI Control. [Internet] [Doctoral dissertation]. Columbia University; 2019. [cited 2020 Apr 04]. Available from: https://doi.org/10.7916/d8-kfrq-qa27.

Council of Science Editors:

Kim D. Fully Integrated Digital Low-Drop-Out Regulator Design based on Event-Driven PI Control. [Doctoral Dissertation]. Columbia University; 2019. Available from: https://doi.org/10.7916/d8-kfrq-qa27


Hong Kong University of Science and Technology

11. Wu, Xiaowen. Inter/intra-chip optical network design for manycore processors.

Degree: 2014, Hong Kong University of Science and Technology

 Manycore processor system is becoming an attractive platform for applications seeking both high performance and high energy efficiency. However, huge communication demands among cores and… (more)

Subjects/Keywords: Optical communications ; Design and construction ; Networks on a chip ; Computer networks ; Multiprocessors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, X. (2014). Inter/intra-chip optical network design for manycore processors. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-71593 ; https://doi.org/10.14711/thesis-b1333722 ; http://repository.ust.hk/ir/bitstream/1783.1-71593/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Xiaowen. “Inter/intra-chip optical network design for manycore processors.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed April 04, 2020. http://repository.ust.hk/ir/Record/1783.1-71593 ; https://doi.org/10.14711/thesis-b1333722 ; http://repository.ust.hk/ir/bitstream/1783.1-71593/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Xiaowen. “Inter/intra-chip optical network design for manycore processors.” 2014. Web. 04 Apr 2020.

Vancouver:

Wu X. Inter/intra-chip optical network design for manycore processors. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2020 Apr 04]. Available from: http://repository.ust.hk/ir/Record/1783.1-71593 ; https://doi.org/10.14711/thesis-b1333722 ; http://repository.ust.hk/ir/bitstream/1783.1-71593/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu X. Inter/intra-chip optical network design for manycore processors. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: http://repository.ust.hk/ir/Record/1783.1-71593 ; https://doi.org/10.14711/thesis-b1333722 ; http://repository.ust.hk/ir/bitstream/1783.1-71593/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Portland State University

12. Grimm, Allen Gary. An Exploration Of Heterogeneous Networks On Chip.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2011, Portland State University

  As the the number of cores on a single chip continue to grow, communication increasingly becomes the bottleneck to performance. Networks on Chips (NoC)… (more)

Subjects/Keywords: Multiobjective optimization; Evolutionary algorithm; Network design problem; Heterogeneous computing; Networks on a chip  – Design and construction; Computer networks  – Design and construction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Grimm, A. G. (2011). An Exploration Of Heterogeneous Networks On Chip. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/185

Chicago Manual of Style (16th Edition):

Grimm, Allen Gary. “An Exploration Of Heterogeneous Networks On Chip.” 2011. Masters Thesis, Portland State University. Accessed April 04, 2020. https://pdxscholar.library.pdx.edu/open_access_etds/185.

MLA Handbook (7th Edition):

Grimm, Allen Gary. “An Exploration Of Heterogeneous Networks On Chip.” 2011. Web. 04 Apr 2020.

Vancouver:

Grimm AG. An Exploration Of Heterogeneous Networks On Chip. [Internet] [Masters thesis]. Portland State University; 2011. [cited 2020 Apr 04]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/185.

Council of Science Editors:

Grimm AG. An Exploration Of Heterogeneous Networks On Chip. [Masters Thesis]. Portland State University; 2011. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/185


Texas A&M University

13. Mandal, Suman Kalyan. Dynamic Power Management of High Performance Network on Chip.

Degree: 2012, Texas A&M University

 With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication… (more)

Subjects/Keywords: Power Management; Network on Chip; System on Chip; SOC; NoC

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APA (6th Edition):

Mandal, S. K. (2012). Dynamic Power Management of High Performance Network on Chip. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Thesis, Texas A&M University. Accessed April 04, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Web. 04 Apr 2020.

Vancouver:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

14. Raducu, Rares. SoC for real - time object tracking in 3D space.

Degree: 2014, Ryerson University

 With the rapid growth of workplaces, there is also an increase of the risk employees are exposed to. A high percentage of the injuries suffered… (more)

Subjects/Keywords: Systems on a chip  – Design and construction; Image processing  – Digital techniques; Three-dimensional display systems; Accidents  – Prevention

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APA (6th Edition):

Raducu, R. (2014). SoC for real - time object tracking in 3D space. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A3469

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Raducu, Rares. “SoC for real - time object tracking in 3D space.” 2014. Thesis, Ryerson University. Accessed April 04, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A3469.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Raducu, Rares. “SoC for real - time object tracking in 3D space.” 2014. Web. 04 Apr 2020.

Vancouver:

Raducu R. SoC for real - time object tracking in 3D space. [Internet] [Thesis]. Ryerson University; 2014. [cited 2020 Apr 04]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A3469.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Raducu R. SoC for real - time object tracking in 3D space. [Thesis]. Ryerson University; 2014. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A3469

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of North Texas

15. Burke, Patrick William. A New Look at Retargetable Compilers.

Degree: 2014, University of North Texas

 Consumers demand new and innovative personal computing devices every 2 years when their cellular phone service contracts are renewed. Yet, a 2 year development cycle… (more)

Subjects/Keywords: Retargetable compiler; architecture description; software process; Compilers (Computer programs); Systems on a chip  – Design and construction.; Software failures  – Prevention.

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APA (6th Edition):

Burke, P. W. (2014). A New Look at Retargetable Compilers. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc699988/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Burke, Patrick William. “A New Look at Retargetable Compilers.” 2014. Thesis, University of North Texas. Accessed April 04, 2020. https://digital.library.unt.edu/ark:/67531/metadc699988/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Burke, Patrick William. “A New Look at Retargetable Compilers.” 2014. Web. 04 Apr 2020.

Vancouver:

Burke PW. A New Look at Retargetable Compilers. [Internet] [Thesis]. University of North Texas; 2014. [cited 2020 Apr 04]. Available from: https://digital.library.unt.edu/ark:/67531/metadc699988/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Burke PW. A New Look at Retargetable Compilers. [Thesis]. University of North Texas; 2014. Available from: https://digital.library.unt.edu/ark:/67531/metadc699988/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

16. Lau, Sai Kit ECE. Low-voltage low-dropout regulator for system-on-chip applications.

Degree: 2004, Hong Kong University of Science and Technology

 With the rapid development of system-on-chip (SoC) designs, there is a growing trend towards the integration of IC systems and power-management circuits. Local, on-chip and… (more)

Subjects/Keywords: Voltage regulators ; Design and construction ; Systems on a chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lau, S. K. E. (2004). Low-voltage low-dropout regulator for system-on-chip applications. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-97223 ; https://doi.org/10.14711/thesis-b838713 ; http://repository.ust.hk/ir/bitstream/1783.1-97223/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lau, Sai Kit ECE. “Low-voltage low-dropout regulator for system-on-chip applications.” 2004. Thesis, Hong Kong University of Science and Technology. Accessed April 04, 2020. http://repository.ust.hk/ir/Record/1783.1-97223 ; https://doi.org/10.14711/thesis-b838713 ; http://repository.ust.hk/ir/bitstream/1783.1-97223/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lau, Sai Kit ECE. “Low-voltage low-dropout regulator for system-on-chip applications.” 2004. Web. 04 Apr 2020.

Vancouver:

Lau SKE. Low-voltage low-dropout regulator for system-on-chip applications. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2004. [cited 2020 Apr 04]. Available from: http://repository.ust.hk/ir/Record/1783.1-97223 ; https://doi.org/10.14711/thesis-b838713 ; http://repository.ust.hk/ir/bitstream/1783.1-97223/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lau SKE. Low-voltage low-dropout regulator for system-on-chip applications. [Thesis]. Hong Kong University of Science and Technology; 2004. Available from: http://repository.ust.hk/ir/Record/1783.1-97223 ; https://doi.org/10.14711/thesis-b838713 ; http://repository.ust.hk/ir/bitstream/1783.1-97223/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Michigan State University

17. Xi, Jinwen. A system-level platform-based multi-core system-on-chip simulation framework with retargetable processing element models.

Degree: PhD, Department of Electrical and Computer Engineering, 2007, Michigan State University

Subjects/Keywords: Systems on a chip – Design and construction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xi, J. (2007). A system-level platform-based multi-core system-on-chip simulation framework with retargetable processing element models. (Doctoral Dissertation). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:38578

Chicago Manual of Style (16th Edition):

Xi, Jinwen. “A system-level platform-based multi-core system-on-chip simulation framework with retargetable processing element models.” 2007. Doctoral Dissertation, Michigan State University. Accessed April 04, 2020. http://etd.lib.msu.edu/islandora/object/etd:38578.

MLA Handbook (7th Edition):

Xi, Jinwen. “A system-level platform-based multi-core system-on-chip simulation framework with retargetable processing element models.” 2007. Web. 04 Apr 2020.

Vancouver:

Xi J. A system-level platform-based multi-core system-on-chip simulation framework with retargetable processing element models. [Internet] [Doctoral dissertation]. Michigan State University; 2007. [cited 2020 Apr 04]. Available from: http://etd.lib.msu.edu/islandora/object/etd:38578.

Council of Science Editors:

Xi J. A system-level platform-based multi-core system-on-chip simulation framework with retargetable processing element models. [Doctoral Dissertation]. Michigan State University; 2007. Available from: http://etd.lib.msu.edu/islandora/object/etd:38578


Portland State University

18. Amarnath, Avinash. A Self-Configurable Architecture on an Irregular Reconfigurable Fabric.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2011, Portland State University

  Reconfigurable computing architectures combine the flexibility of software with the performance of custom hardware. Such architectures are of particular interest at the nanoscale level.… (more)

Subjects/Keywords: Reconfigurable computing; Self-configuration; Unstructured fabric; Adaptive computing systems; Systems on a chip  – Design and construction; Nanoelectronics; Complementary Metal oxide semiconductors  – Design and construction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Amarnath, A. (2011). A Self-Configurable Architecture on an Irregular Reconfigurable Fabric. (Masters Thesis). Portland State University. Retrieved from http://pdxscholar.library.pdx.edu/open_access_etds/634

Chicago Manual of Style (16th Edition):

Amarnath, Avinash. “A Self-Configurable Architecture on an Irregular Reconfigurable Fabric.” 2011. Masters Thesis, Portland State University. Accessed April 04, 2020. http://pdxscholar.library.pdx.edu/open_access_etds/634.

MLA Handbook (7th Edition):

Amarnath, Avinash. “A Self-Configurable Architecture on an Irregular Reconfigurable Fabric.” 2011. Web. 04 Apr 2020.

Vancouver:

Amarnath A. A Self-Configurable Architecture on an Irregular Reconfigurable Fabric. [Internet] [Masters thesis]. Portland State University; 2011. [cited 2020 Apr 04]. Available from: http://pdxscholar.library.pdx.edu/open_access_etds/634.

Council of Science Editors:

Amarnath A. A Self-Configurable Architecture on an Irregular Reconfigurable Fabric. [Masters Thesis]. Portland State University; 2011. Available from: http://pdxscholar.library.pdx.edu/open_access_etds/634


NSYSU

19. Lin, Meng-Shun. Integration and Verification of 3D Graphics System with DVFS and Multi-precision Technique.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Nowadays, mobile devices such as smart phone, tablet and laptop have been indispensable in peopleâs daily lives. With the rapid development of technology and for… (more)

Subjects/Keywords: 3D Graphics System; Power Management; Multi-precision; Dynamic Voltage and Frequency Scaling; System on Chip; Virtual Platform

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, M. (2016). Integration and Verification of 3D Graphics System with DVFS and Multi-precision Technique. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0709116-150213

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Meng-Shun. “Integration and Verification of 3D Graphics System with DVFS and Multi-precision Technique.” 2016. Thesis, NSYSU. Accessed April 04, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0709116-150213.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Meng-Shun. “Integration and Verification of 3D Graphics System with DVFS and Multi-precision Technique.” 2016. Web. 04 Apr 2020.

Vancouver:

Lin M. Integration and Verification of 3D Graphics System with DVFS and Multi-precision Technique. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Apr 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0709116-150213.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin M. Integration and Verification of 3D Graphics System with DVFS and Multi-precision Technique. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0709116-150213

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

20. Wang, Lei. High Performance Interconnect System Design for Future Chip Multiprocessors.

Degree: 2013, Texas A&M University

Chip Multi-Processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMP… (more)

Subjects/Keywords: Network-On-Chip; Chip Multiprocessors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, L. (2013). High Performance Interconnect System Design for Future Chip Multiprocessors. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Lei. “High Performance Interconnect System Design for Future Chip Multiprocessors.” 2013. Thesis, Texas A&M University. Accessed April 04, 2020. http://hdl.handle.net/1969.1/149541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Lei. “High Performance Interconnect System Design for Future Chip Multiprocessors.” 2013. Web. 04 Apr 2020.

Vancouver:

Wang L. High Performance Interconnect System Design for Future Chip Multiprocessors. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/1969.1/149541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang L. High Performance Interconnect System Design for Future Chip Multiprocessors. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Cong, Kai. Post-silicon Functional Validation with Virtual Prototypes.

Degree: PhD, Computer Science, 2015, Portland State University

  Post-silicon validation has become a critical stage in the system-on-chip (SoC) development cycle, driven by increasing design complexity, higher level of integration and decreasing… (more)

Subjects/Keywords: Computer software  – Verification; Systems on a chip  – Design and construction; Electronic apparatus and appliances  – Testing; Prototypes; Engineering  – Computer simulation; Other Computer Sciences; Software Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cong, K. (2015). Post-silicon Functional Validation with Virtual Prototypes. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/2333

Chicago Manual of Style (16th Edition):

Cong, Kai. “Post-silicon Functional Validation with Virtual Prototypes.” 2015. Doctoral Dissertation, Portland State University. Accessed April 04, 2020. https://pdxscholar.library.pdx.edu/open_access_etds/2333.

MLA Handbook (7th Edition):

Cong, Kai. “Post-silicon Functional Validation with Virtual Prototypes.” 2015. Web. 04 Apr 2020.

Vancouver:

Cong K. Post-silicon Functional Validation with Virtual Prototypes. [Internet] [Doctoral dissertation]. Portland State University; 2015. [cited 2020 Apr 04]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/2333.

Council of Science Editors:

Cong K. Post-silicon Functional Validation with Virtual Prototypes. [Doctoral Dissertation]. Portland State University; 2015. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/2333


Washington State University

22. [No author]. Evaluating hardware .

Degree: 2006, Washington State University

Subjects/Keywords: Embedded computer systems  – Design and construction.; Systems on a chip.

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APA (6th Edition):

author], [. (2006). Evaluating hardware . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/510

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “Evaluating hardware .” 2006. Thesis, Washington State University. Accessed April 04, 2020. http://hdl.handle.net/2376/510.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “Evaluating hardware .” 2006. Web. 04 Apr 2020.

Vancouver:

author] [. Evaluating hardware . [Internet] [Thesis]. Washington State University; 2006. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2376/510.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. Evaluating hardware . [Thesis]. Washington State University; 2006. Available from: http://hdl.handle.net/2376/510

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

23. Khadem Hamedani, Parisa. Improving Communication in Chip Multiprocessors Using Emerging Technologies and Machine Learning.

Degree: PhD, 2017, University of Toronto

 Technology scaling along with power and thermal limitations ushers the industry to the many-core system era. Thread level parallelism and complex applications demand a communication… (more)

Subjects/Keywords: Critical path of multi-threaded application; Machine learning; Networks-on-chip; On-chip communication; Silicon Photonics; Thermal management; 0464

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Khadem Hamedani, P. (2017). Improving Communication in Chip Multiprocessors Using Emerging Technologies and Machine Learning. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/79015

Chicago Manual of Style (16th Edition):

Khadem Hamedani, Parisa. “Improving Communication in Chip Multiprocessors Using Emerging Technologies and Machine Learning.” 2017. Doctoral Dissertation, University of Toronto. Accessed April 04, 2020. http://hdl.handle.net/1807/79015.

MLA Handbook (7th Edition):

Khadem Hamedani, Parisa. “Improving Communication in Chip Multiprocessors Using Emerging Technologies and Machine Learning.” 2017. Web. 04 Apr 2020.

Vancouver:

Khadem Hamedani P. Improving Communication in Chip Multiprocessors Using Emerging Technologies and Machine Learning. [Internet] [Doctoral dissertation]. University of Toronto; 2017. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/1807/79015.

Council of Science Editors:

Khadem Hamedani P. Improving Communication in Chip Multiprocessors Using Emerging Technologies and Machine Learning. [Doctoral Dissertation]. University of Toronto; 2017. Available from: http://hdl.handle.net/1807/79015


Portland State University

24. Parashar, Neha. Design Space Analysis and a Novel Routing Agorithm for Unstructured Networks-on-Chip.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2010, Portland State University

  Traditionally, on-chip network communication was achieved with shared medium networks where devices shared the transmission medium with only one device driving the network at… (more)

Subjects/Keywords: Networks on a chip; Computer algorithms; Routing (Computer network management)

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APA (6th Edition):

Parashar, N. (2010). Design Space Analysis and a Novel Routing Agorithm for Unstructured Networks-on-Chip. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/89

Chicago Manual of Style (16th Edition):

Parashar, Neha. “Design Space Analysis and a Novel Routing Agorithm for Unstructured Networks-on-Chip.” 2010. Masters Thesis, Portland State University. Accessed April 04, 2020. https://pdxscholar.library.pdx.edu/open_access_etds/89.

MLA Handbook (7th Edition):

Parashar, Neha. “Design Space Analysis and a Novel Routing Agorithm for Unstructured Networks-on-Chip.” 2010. Web. 04 Apr 2020.

Vancouver:

Parashar N. Design Space Analysis and a Novel Routing Agorithm for Unstructured Networks-on-Chip. [Internet] [Masters thesis]. Portland State University; 2010. [cited 2020 Apr 04]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/89.

Council of Science Editors:

Parashar N. Design Space Analysis and a Novel Routing Agorithm for Unstructured Networks-on-Chip. [Masters Thesis]. Portland State University; 2010. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/89


Ryerson University

25. Chui, Stephen. Congestion aware adaptive routing for network-on-chip communication.

Degree: 2016, Ryerson University

 Network-On-Chip (NoC) has surpassed the traditional bus based on-chip communication in offering better performance for data transfers among many processing, peripheral and other cores of… (more)

Subjects/Keywords: Adaptive routing (Computer network management); Networks on a chip.

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APA (6th Edition):

Chui, S. (2016). Congestion aware adaptive routing for network-on-chip communication. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A4895

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chui, Stephen. “Congestion aware adaptive routing for network-on-chip communication.” 2016. Thesis, Ryerson University. Accessed April 04, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A4895.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chui, Stephen. “Congestion aware adaptive routing for network-on-chip communication.” 2016. Web. 04 Apr 2020.

Vancouver:

Chui S. Congestion aware adaptive routing for network-on-chip communication. [Internet] [Thesis]. Ryerson University; 2016. [cited 2020 Apr 04]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A4895.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chui S. Congestion aware adaptive routing for network-on-chip communication. [Thesis]. Ryerson University; 2016. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A4895

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Colorado State University

26. Raparti, Venkata Yaswanth. RELAX: cross-layer resource management for reliable NoC-based 2D and 3D manycore architectures in the dark silicon era.

Degree: PhD, Electrical and Computer Engineering, 2020, Colorado State University

 Emerging 2D and 3D chip-multiprocessors (CMPs) are facing numerous challenges due to technology scaling that impact their reliability, power dissipation, performance, and security. With growing… (more)

Subjects/Keywords: GPGPU; network on chip; resource management; manycore processors; dark silicon; reliability

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Raparti, V. Y. (2020). RELAX: cross-layer resource management for reliable NoC-based 2D and 3D manycore architectures in the dark silicon era. (Doctoral Dissertation). Colorado State University. Retrieved from http://hdl.handle.net/10217/199826

Chicago Manual of Style (16th Edition):

Raparti, Venkata Yaswanth. “RELAX: cross-layer resource management for reliable NoC-based 2D and 3D manycore architectures in the dark silicon era.” 2020. Doctoral Dissertation, Colorado State University. Accessed April 04, 2020. http://hdl.handle.net/10217/199826.

MLA Handbook (7th Edition):

Raparti, Venkata Yaswanth. “RELAX: cross-layer resource management for reliable NoC-based 2D and 3D manycore architectures in the dark silicon era.” 2020. Web. 04 Apr 2020.

Vancouver:

Raparti VY. RELAX: cross-layer resource management for reliable NoC-based 2D and 3D manycore architectures in the dark silicon era. [Internet] [Doctoral dissertation]. Colorado State University; 2020. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/10217/199826.

Council of Science Editors:

Raparti VY. RELAX: cross-layer resource management for reliable NoC-based 2D and 3D manycore architectures in the dark silicon era. [Doctoral Dissertation]. Colorado State University; 2020. Available from: http://hdl.handle.net/10217/199826


Hong Kong University of Science and Technology

27. Huo, Xiao. High performance passive components modeling and integration in RF/microwave systems.

Degree: 2005, Hong Kong University of Science and Technology

 With the increasing market of RF/Microwave product, compact, low power and high performance system integration solutions are needed. Research has been focused on System-On-Chip (SOC)… (more)

Subjects/Keywords: Integrated circuits  – Design and construction ; Systems on a chip ; Radio frequency integrated circuits  – Design and construction ; Microwave circuits  – Design and construction

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APA (6th Edition):

Huo, X. (2005). High performance passive components modeling and integration in RF/microwave systems. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-2411 ; https://doi.org/10.14711/thesis-b857004 ; http://repository.ust.hk/ir/bitstream/1783.1-2411/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huo, Xiao. “High performance passive components modeling and integration in RF/microwave systems.” 2005. Thesis, Hong Kong University of Science and Technology. Accessed April 04, 2020. http://repository.ust.hk/ir/Record/1783.1-2411 ; https://doi.org/10.14711/thesis-b857004 ; http://repository.ust.hk/ir/bitstream/1783.1-2411/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huo, Xiao. “High performance passive components modeling and integration in RF/microwave systems.” 2005. Web. 04 Apr 2020.

Vancouver:

Huo X. High performance passive components modeling and integration in RF/microwave systems. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2005. [cited 2020 Apr 04]. Available from: http://repository.ust.hk/ir/Record/1783.1-2411 ; https://doi.org/10.14711/thesis-b857004 ; http://repository.ust.hk/ir/bitstream/1783.1-2411/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huo X. High performance passive components modeling and integration in RF/microwave systems. [Thesis]. Hong Kong University of Science and Technology; 2005. Available from: http://repository.ust.hk/ir/Record/1783.1-2411 ; https://doi.org/10.14711/thesis-b857004 ; http://repository.ust.hk/ir/bitstream/1783.1-2411/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


New Jersey Institute of Technology

28. Kim, Hansin. Micro pipes – a portable integrated platform for electrochemical sensing using essence architecture.

Degree: MSin Biomedical Engineering - (M.S.), Biomedical Engineering, 2019, New Jersey Institute of Technology

  The field of microfluidics and lab-on-chip (LOC) technology has the potential to have a truly transformative effect in biological engineering. This includes areas such… (more)

Subjects/Keywords: Chip-to-world interface; Improved integration; Lab-on-chip; Biomedical Engineering and Bioengineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, H. (2019). Micro pipes – a portable integrated platform for electrochemical sensing using essence architecture. (Thesis). New Jersey Institute of Technology. Retrieved from https://digitalcommons.njit.edu/theses/1741

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Hansin. “Micro pipes – a portable integrated platform for electrochemical sensing using essence architecture.” 2019. Thesis, New Jersey Institute of Technology. Accessed April 04, 2020. https://digitalcommons.njit.edu/theses/1741.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Hansin. “Micro pipes – a portable integrated platform for electrochemical sensing using essence architecture.” 2019. Web. 04 Apr 2020.

Vancouver:

Kim H. Micro pipes – a portable integrated platform for electrochemical sensing using essence architecture. [Internet] [Thesis]. New Jersey Institute of Technology; 2019. [cited 2020 Apr 04]. Available from: https://digitalcommons.njit.edu/theses/1741.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim H. Micro pipes – a portable integrated platform for electrochemical sensing using essence architecture. [Thesis]. New Jersey Institute of Technology; 2019. Available from: https://digitalcommons.njit.edu/theses/1741

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Nitin. A New Approach to Stable Matching and Networks on Chip Problem;.

Degree: 2013, Jaypee University of Information Technology, Solan

This thesis emphasizes that the Stable Matching problems are the same as the problems of stable configurations of Multi stage Interconnection Networks (MIN). Author has… (more)

Subjects/Keywords: Networks on Chip; Systems on Chip

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APA (6th Edition):

Nitin. (2013). A New Approach to Stable Matching and Networks on Chip Problem;. (Thesis). Jaypee University of Information Technology, Solan. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/11151

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nitin. “A New Approach to Stable Matching and Networks on Chip Problem;.” 2013. Thesis, Jaypee University of Information Technology, Solan. Accessed April 04, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/11151.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nitin. “A New Approach to Stable Matching and Networks on Chip Problem;.” 2013. Web. 04 Apr 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Nitin. A New Approach to Stable Matching and Networks on Chip Problem;. [Internet] [Thesis]. Jaypee University of Information Technology, Solan; 2013. [cited 2020 Apr 04]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11151.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nitin. A New Approach to Stable Matching and Networks on Chip Problem;. [Thesis]. Jaypee University of Information Technology, Solan; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11151

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

30. Yang, Kai-ming. A Ring-like Arbitration Strategy Schedule for Networks-On-Chips.

Degree: PhD, Electrical Engineering, 2013, NSYSU

 Multi-core systems in single chip exploit ILP (Instruction-Level Parallelism) and TLP (Thread-Level Parallelism) to improve the system performance. Therefore, efficiency of transferring data among cores… (more)

Subjects/Keywords: Distributed on-chip network arbitration strategy; Instruction and data stream buffer; Asynchronous circuits; Network-on-chip; Priority selector

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, K. (2013). A Ring-like Arbitration Strategy Schedule for Networks-On-Chips. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618113-150752

Chicago Manual of Style (16th Edition):

Yang, Kai-ming. “A Ring-like Arbitration Strategy Schedule for Networks-On-Chips.” 2013. Doctoral Dissertation, NSYSU. Accessed April 04, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618113-150752.

MLA Handbook (7th Edition):

Yang, Kai-ming. “A Ring-like Arbitration Strategy Schedule for Networks-On-Chips.” 2013. Web. 04 Apr 2020.

Vancouver:

Yang K. A Ring-like Arbitration Strategy Schedule for Networks-On-Chips. [Internet] [Doctoral dissertation]. NSYSU; 2013. [cited 2020 Apr 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618113-150752.

Council of Science Editors:

Yang K. A Ring-like Arbitration Strategy Schedule for Networks-On-Chips. [Doctoral Dissertation]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0618113-150752

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