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You searched for subject:(Network on chip). Showing records 1 – 30 of 307 total matches.

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Texas A&M University

1. Wang, Lei. High Performance Interconnect System Design for Future Chip Multiprocessors.

Degree: PhD, Computer Engineering, 2013, Texas A&M University

Chip Multi-Processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMP… (more)

Subjects/Keywords: Network-On-Chip; Chip Multiprocessors

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APA (6th Edition):

Wang, L. (2013). High Performance Interconnect System Design for Future Chip Multiprocessors. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149541

Chicago Manual of Style (16th Edition):

Wang, Lei. “High Performance Interconnect System Design for Future Chip Multiprocessors.” 2013. Doctoral Dissertation, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/149541.

MLA Handbook (7th Edition):

Wang, Lei. “High Performance Interconnect System Design for Future Chip Multiprocessors.” 2013. Web. 20 Apr 2021.

Vancouver:

Wang L. High Performance Interconnect System Design for Future Chip Multiprocessors. [Internet] [Doctoral dissertation]. Texas A&M University; 2013. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/149541.

Council of Science Editors:

Wang L. High Performance Interconnect System Design for Future Chip Multiprocessors. [Doctoral Dissertation]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149541


Anna University

2. Sudha S. Enhanced reliable and adaptive Routing models for networks on chip;.

Degree: Enhanced reliable and adaptive Routing models for networks on chip, 2014, Anna University

The main objective of this research is to develop a reliable and newlineCongestion aware adaptive routing model to improve the performance of the newlineNetwork on… (more)

Subjects/Keywords: Greedy algorithm; Network on Chip

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APA (6th Edition):

S, S. (2014). Enhanced reliable and adaptive Routing models for networks on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/26114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

S, Sudha. “Enhanced reliable and adaptive Routing models for networks on chip;.” 2014. Thesis, Anna University. Accessed April 20, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/26114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

S, Sudha. “Enhanced reliable and adaptive Routing models for networks on chip;.” 2014. Web. 20 Apr 2021.

Vancouver:

S S. Enhanced reliable and adaptive Routing models for networks on chip;. [Internet] [Thesis]. Anna University; 2014. [cited 2021 Apr 20]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/26114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

S S. Enhanced reliable and adaptive Routing models for networks on chip;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/26114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

3. Patra, Biplab. Hybrid Router Design for High Performance Photonic Network-On-Chip.

Degree: MS, Computer Engineering, 2015, Texas A&M University

 With rising density of cores in Chip-Multiprocessors, traditional metallic interconnects won't be able to cater to the high demand in communication bandwidth at lower power… (more)

Subjects/Keywords: Photonic; Network-on-chip

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APA (6th Edition):

Patra, B. (2015). Hybrid Router Design for High Performance Photonic Network-On-Chip. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/186979

Chicago Manual of Style (16th Edition):

Patra, Biplab. “Hybrid Router Design for High Performance Photonic Network-On-Chip.” 2015. Masters Thesis, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/186979.

MLA Handbook (7th Edition):

Patra, Biplab. “Hybrid Router Design for High Performance Photonic Network-On-Chip.” 2015. Web. 20 Apr 2021.

Vancouver:

Patra B. Hybrid Router Design for High Performance Photonic Network-On-Chip. [Internet] [Masters thesis]. Texas A&M University; 2015. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/186979.

Council of Science Editors:

Patra B. Hybrid Router Design for High Performance Photonic Network-On-Chip. [Masters Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/186979


Texas A&M University

4. Rasheed, Shalimar. A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing.

Degree: MS, Computer Engineering, 2014, Texas A&M University

 Networks-on-Chip (NoCs) offer a scalable means of on-chip communication for future many-core chips. As NoC size increases with core count in future many-core chips, NoC… (more)

Subjects/Keywords: Network-on-Chip; Router

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APA (6th Edition):

Rasheed, S. (2014). A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/152655

Chicago Manual of Style (16th Edition):

Rasheed, Shalimar. “A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing.” 2014. Masters Thesis, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/152655.

MLA Handbook (7th Edition):

Rasheed, Shalimar. “A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing.” 2014. Web. 20 Apr 2021.

Vancouver:

Rasheed S. A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing. [Internet] [Masters thesis]. Texas A&M University; 2014. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/152655.

Council of Science Editors:

Rasheed S. A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing. [Masters Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/152655


Texas A&M University

5. Ieong, Ka Chon. A Virtual Prototype of Scalable Network-on-Chip Design.

Degree: MS, Computer Engineering, 2014, Texas A&M University

 A Virtual Prototype of Network-on-Chip (NoC) that interconnects IPs in System-on-Chip is presented in this thesis. A Virtual Prototype is a software model describing various… (more)

Subjects/Keywords: Virtual Prototype; Network-on-Chip

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APA (6th Edition):

Ieong, K. C. (2014). A Virtual Prototype of Scalable Network-on-Chip Design. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/152730

Chicago Manual of Style (16th Edition):

Ieong, Ka Chon. “A Virtual Prototype of Scalable Network-on-Chip Design.” 2014. Masters Thesis, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/152730.

MLA Handbook (7th Edition):

Ieong, Ka Chon. “A Virtual Prototype of Scalable Network-on-Chip Design.” 2014. Web. 20 Apr 2021.

Vancouver:

Ieong KC. A Virtual Prototype of Scalable Network-on-Chip Design. [Internet] [Masters thesis]. Texas A&M University; 2014. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/152730.

Council of Science Editors:

Ieong KC. A Virtual Prototype of Scalable Network-on-Chip Design. [Masters Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/152730


Texas A&M University

6. Elshennawy, Amr. An Asynchronous Network-On-Chip Router with Low Standby Power.

Degree: MS, Computer Engineering, 2014, Texas A&M University

 The Network-on-Chip (NoC) paradigm is now widely used to interconnect the processing elements (PEs) in a chip multiprocessor (CMP). It has been reported that the… (more)

Subjects/Keywords: Network-on-Chip; Asynchronous; Leakage

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APA (6th Edition):

Elshennawy, A. (2014). An Asynchronous Network-On-Chip Router with Low Standby Power. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/153947

Chicago Manual of Style (16th Edition):

Elshennawy, Amr. “An Asynchronous Network-On-Chip Router with Low Standby Power.” 2014. Masters Thesis, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/153947.

MLA Handbook (7th Edition):

Elshennawy, Amr. “An Asynchronous Network-On-Chip Router with Low Standby Power.” 2014. Web. 20 Apr 2021.

Vancouver:

Elshennawy A. An Asynchronous Network-On-Chip Router with Low Standby Power. [Internet] [Masters thesis]. Texas A&M University; 2014. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/153947.

Council of Science Editors:

Elshennawy A. An Asynchronous Network-On-Chip Router with Low Standby Power. [Masters Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/153947


Texas A&M University

7. Mandal, Ayan. Efficient Design and Clocking for a Network-on-Chip.

Degree: PhD, Computer Engineering, 2013, Texas A&M University

 As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC)… (more)

Subjects/Keywords: Network-on-Chip; Clock; VLSI

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APA (6th Edition):

Mandal, A. (2013). Efficient Design and Clocking for a Network-on-Chip. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149325

Chicago Manual of Style (16th Edition):

Mandal, Ayan. “Efficient Design and Clocking for a Network-on-Chip.” 2013. Doctoral Dissertation, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/149325.

MLA Handbook (7th Edition):

Mandal, Ayan. “Efficient Design and Clocking for a Network-on-Chip.” 2013. Web. 20 Apr 2021.

Vancouver:

Mandal A. Efficient Design and Clocking for a Network-on-Chip. [Internet] [Doctoral dissertation]. Texas A&M University; 2013. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/149325.

Council of Science Editors:

Mandal A. Efficient Design and Clocking for a Network-on-Chip. [Doctoral Dissertation]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149325


North Carolina State University

8. Hu, Jianchen. Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System.

Degree: MS, Electrical Engineering, 2009, North Carolina State University

 As the complexity of SoC design grows, the traditional register transfer level (RTL) centric design flow cannot meet the time to market. In that case,… (more)

Subjects/Keywords: interconnect; TLM; Network-on-chip

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APA (6th Edition):

Hu, J. (2009). Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hu, Jianchen. “Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System.” 2009. Thesis, North Carolina State University. Accessed April 20, 2021. http://www.lib.ncsu.edu/resolver/1840.16/1617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hu, Jianchen. “Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System.” 2009. Web. 20 Apr 2021.

Vancouver:

Hu J. Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System. [Internet] [Thesis]. North Carolina State University; 2009. [cited 2021 Apr 20]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hu J. Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System. [Thesis]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

9. Cebry, Nicholas. Network-on-chip design for a chiplet-based waferscale processor.

Degree: MS, Electrical & Computer Engr, 2020, University of Illinois – Urbana-Champaign

 Motivated by the failing of Moore’s law and Dennard scaling, as well as increasingly large parallel tasks like machine learning and big data analysis, processors… (more)

Subjects/Keywords: network-on-chip; waferscale

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APA (6th Edition):

Cebry, N. (2020). Network-on-chip design for a chiplet-based waferscale processor. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108436

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cebry, Nicholas. “Network-on-chip design for a chiplet-based waferscale processor.” 2020. Thesis, University of Illinois – Urbana-Champaign. Accessed April 20, 2021. http://hdl.handle.net/2142/108436.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cebry, Nicholas. “Network-on-chip design for a chiplet-based waferscale processor.” 2020. Web. 20 Apr 2021.

Vancouver:

Cebry N. Network-on-chip design for a chiplet-based waferscale processor. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/2142/108436.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cebry N. Network-on-chip design for a chiplet-based waferscale processor. [Thesis]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108436

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

10. An, Baik Song. Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems.

Degree: PhD, Computer Science, 2012, Texas A&M University

 High performance systems have been widely adopted in many fields and the demand for better performance is constantly increasing. And the need of powerful yet… (more)

Subjects/Keywords: computer architecture; chip multiprocessor; network-on-chip

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APA (6th Edition):

An, B. S. (2012). Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665

Chicago Manual of Style (16th Edition):

An, Baik Song. “Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems.” 2012. Doctoral Dissertation, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665.

MLA Handbook (7th Edition):

An, Baik Song. “Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems.” 2012. Web. 20 Apr 2021.

Vancouver:

An BS. Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665.

Council of Science Editors:

An BS. Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665


Penn State University

11. Ouyang, Jin. Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors.

Degree: 2012, Penn State University

 The rapid process scaling trend of the silicon industry has provided the resources to concurrently execute multiple instruction sequences on the same chip, a capability… (more)

Subjects/Keywords: Chip-Multiprocessors; Network-on-Chip; Computer Architecture

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APA (6th Edition):

Ouyang, J. (2012). Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/13160

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ouyang, Jin. “Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors.” 2012. Thesis, Penn State University. Accessed April 20, 2021. https://submit-etda.libraries.psu.edu/catalog/13160.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ouyang, Jin. “Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors.” 2012. Web. 20 Apr 2021.

Vancouver:

Ouyang J. Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors. [Internet] [Thesis]. Penn State University; 2012. [cited 2021 Apr 20]. Available from: https://submit-etda.libraries.psu.edu/catalog/13160.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ouyang J. Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors. [Thesis]. Penn State University; 2012. Available from: https://submit-etda.libraries.psu.edu/catalog/13160

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Rochester

12. Carpenter, Aaron (1983 - ). The design and use of high-speed transmission line links for global on-chip communication.

Degree: PhD, 2012, University of Rochester

 As transistors approach the limits of traditional scaling, computer architects can no longer rely on the increase in density and core frequency to improve the… (more)

Subjects/Keywords: Interconnect; Chip multiprocessor; On-chip-network; On-chip communication; Transmission lines

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APA (6th Edition):

Carpenter, A. (. -. ). (2012). The design and use of high-speed transmission line links for global on-chip communication. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/21272

Chicago Manual of Style (16th Edition):

Carpenter, Aaron (1983 - ). “The design and use of high-speed transmission line links for global on-chip communication.” 2012. Doctoral Dissertation, University of Rochester. Accessed April 20, 2021. http://hdl.handle.net/1802/21272.

MLA Handbook (7th Edition):

Carpenter, Aaron (1983 - ). “The design and use of high-speed transmission line links for global on-chip communication.” 2012. Web. 20 Apr 2021.

Vancouver:

Carpenter A(-). The design and use of high-speed transmission line links for global on-chip communication. [Internet] [Doctoral dissertation]. University of Rochester; 2012. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1802/21272.

Council of Science Editors:

Carpenter A(-). The design and use of high-speed transmission line links for global on-chip communication. [Doctoral Dissertation]. University of Rochester; 2012. Available from: http://hdl.handle.net/1802/21272


Texas A&M University

13. Oh, Han Bee. A Structural Analysis of On-Line Fault Detection Mechanisms in Network-On-Chip Architectures.

Degree: MS, Computer Engineering, 2020, Texas A&M University

Network-on-Chip (NoC) communication architectures are widely used as on-chip interconnect in multi-core systems. These systems are increasingly used in safety-critical applications, so it is essential… (more)

Subjects/Keywords: Network-on-Chip; On-line testing

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APA (6th Edition):

Oh, H. B. (2020). A Structural Analysis of On-Line Fault Detection Mechanisms in Network-On-Chip Architectures. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/191802

Chicago Manual of Style (16th Edition):

Oh, Han Bee. “A Structural Analysis of On-Line Fault Detection Mechanisms in Network-On-Chip Architectures.” 2020. Masters Thesis, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/191802.

MLA Handbook (7th Edition):

Oh, Han Bee. “A Structural Analysis of On-Line Fault Detection Mechanisms in Network-On-Chip Architectures.” 2020. Web. 20 Apr 2021.

Vancouver:

Oh HB. A Structural Analysis of On-Line Fault Detection Mechanisms in Network-On-Chip Architectures. [Internet] [Masters thesis]. Texas A&M University; 2020. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/191802.

Council of Science Editors:

Oh HB. A Structural Analysis of On-Line Fault Detection Mechanisms in Network-On-Chip Architectures. [Masters Thesis]. Texas A&M University; 2020. Available from: http://hdl.handle.net/1969.1/191802

14. Magnos Roberto Pizzoni. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.

Degree: 2010, Universidade do Vale do Itajaí

Com a evolução dos processos de fabricação de circuitos, tem sido possível a integração de sistemas completos em um único chip, os quais são construídos… (more)

Subjects/Keywords: System-on-Chip; Network-on-Chip; Avaliação de desempenho; CIENCIA DA COMPUTACAO; Circuitos integrados; System-on-Chip; Network-on-Chip; Performance

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APA (6th Edition):

Pizzoni, M. R. (2010). PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. (Thesis). Universidade do Vale do Itajaí. Retrieved from http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Thesis, Universidade do Vale do Itajaí. Accessed April 20, 2021. http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pizzoni, Magnos Roberto. “PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA.” 2010. Web. 20 Apr 2021.

Vancouver:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Internet] [Thesis]. Universidade do Vale do Itajaí; 2010. [cited 2021 Apr 20]. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pizzoni MR. PLATAFORMA PARA AVALIAÇÃO DE DESEMPENHO DE REDE-EM-CHIP EM FPGA. [Thesis]. Universidade do Vale do Itajaí; 2010. Available from: http://www6.univali.br/tede/tde_busca/arquivo.php?codArquivo=947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

15. Gebhardt, Daniel J. Energy-efficient design of an asynchronous network-on-chip.

Degree: PhD, Computer Science, 2011, University of Utah

 Portable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are… (more)

Subjects/Keywords: Asynchronous circuits; Link pipelining; Network-on-chip; Network simulation; Network traffic; System-on-chip

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APA (6th Edition):

Gebhardt, D. J. (2011). Energy-efficient design of an asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871

Chicago Manual of Style (16th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed April 20, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

MLA Handbook (7th Edition):

Gebhardt, Daniel J. “Energy-efficient design of an asynchronous network-on-chip.” 2011. Web. 20 Apr 2021.

Vancouver:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2021 Apr 20]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871.

Council of Science Editors:

Gebhardt DJ. Energy-efficient design of an asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/568/rec/871


Anna University

16. Saravanakumar U. An investigation on macro and micro Architectures for network on chip;.

Degree: An investigation on macro and micro Architectures for network on chip, 2015, Anna University

As the technology scales down more processors or Processing newlineElements PEs are integrated in the same die and such technology is called as newlineMultiprocessor System… (more)

Subjects/Keywords: Microarchitectural aims; Multiprocessor System on Chip; Network on Chip

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APA (6th Edition):

U, S. (2015). An investigation on macro and micro Architectures for network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Thesis, Anna University. Accessed April 20, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Web. 20 Apr 2021.

Vancouver:

U S. An investigation on macro and micro Architectures for network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Apr 20]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

U S. An investigation on macro and micro Architectures for network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Viswanathan N. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.

Degree: Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters, 2015, Anna University

Three dimensional integration is one of the emerging techniques newlineto find solution for the global interconnect delay challenges faced in the newlineadvanced VLSI ULSI technology… (more)

Subjects/Keywords: Network on Chip; System on Chip; Through Silicon Via

Page 1

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APA (6th Edition):

N, V. (2015). Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Thesis, Anna University. Accessed April 20, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

N, Viswanathan. “Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;.” 2015. Web. 20 Apr 2021.

Vancouver:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Apr 20]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

N V. Certain investigations on vertically Partially connected 3d network On chip topology and arbiter design With optimized parameters;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

18. Malave-Bonet, Javier. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.

Degree: MS, Computer Engineering, 2012, Texas A&M University

Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused… (more)

Subjects/Keywords: Network-on-Chip; Benchmarking; System-on-Chip; Multicore; System C

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APA (6th Edition):

Malave-Bonet, J. (2012). A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Chicago Manual of Style (16th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Masters Thesis, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

MLA Handbook (7th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Web. 20 Apr 2021.

Vancouver:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Council of Science Editors:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662


Texas A&M University

19. Mandal, Suman Kalyan. Dynamic Power Management of High Performance Network on Chip.

Degree: PhD, Computer Engineering, 2012, Texas A&M University

 With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication… (more)

Subjects/Keywords: Power Management; Network on Chip; System on Chip; SOC; NoC

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APA (6th Edition):

Mandal, S. K. (2012). Dynamic Power Management of High Performance Network on Chip. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526

Chicago Manual of Style (16th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Doctoral Dissertation, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

MLA Handbook (7th Edition):

Mandal, Suman Kalyan. “Dynamic Power Management of High Performance Network on Chip.” 2012. Web. 20 Apr 2021.

Vancouver:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526.

Council of Science Editors:

Mandal SK. Dynamic Power Management of High Performance Network on Chip. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10526


University of New South Wales

20. Hussain, Mubashir. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.

Degree: Computer Science & Engineering, 2018, University of New South Wales

 Traditionally, the computing system security has been tackled as a software-level problem. With the globalization of the modern semiconductor industry, the design of a system… (more)

Subjects/Keywords: System-on-Chip; Hardware Trojan; Network-on-Chip; Hardware Security

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APA (6th Edition):

Hussain, M. (2018). Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Doctoral Dissertation, University of New South Wales. Accessed April 20, 2021. http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.

MLA Handbook (7th Edition):

Hussain, Mubashir. “Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip.” 2018. Web. 20 Apr 2021.

Vancouver:

Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2021 Apr 20]. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true.

Council of Science Editors:

Hussain M. Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/60304 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51737/SOURCE02?view=true


Rochester Institute of Technology

21. Sieber, Patrick. Reliability-aware multi-segmented bus architecture for photonic networks-on-chip.

Degree: Computer Engineering, 2013, Rochester Institute of Technology

Network-on-chip (NoC) has emerged as an enabling platform for connecting hundreds of cores on a single chip, allowing for a structured, scalable system when compared… (more)

Subjects/Keywords: Multi-core; Network-on-chip; Photonic

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APA (6th Edition):

Sieber, P. (2013). Reliability-aware multi-segmented bus architecture for photonic networks-on-chip. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/3160

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sieber, Patrick. “Reliability-aware multi-segmented bus architecture for photonic networks-on-chip.” 2013. Thesis, Rochester Institute of Technology. Accessed April 20, 2021. https://scholarworks.rit.edu/theses/3160.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sieber, Patrick. “Reliability-aware multi-segmented bus architecture for photonic networks-on-chip.” 2013. Web. 20 Apr 2021.

Vancouver:

Sieber P. Reliability-aware multi-segmented bus architecture for photonic networks-on-chip. [Internet] [Thesis]. Rochester Institute of Technology; 2013. [cited 2021 Apr 20]. Available from: https://scholarworks.rit.edu/theses/3160.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sieber P. Reliability-aware multi-segmented bus architecture for photonic networks-on-chip. [Thesis]. Rochester Institute of Technology; 2013. Available from: https://scholarworks.rit.edu/theses/3160

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

22. Badr, Mario. Synthetic Traffic Models that Capture Cache Coherent Behaviour.

Degree: 2014, University of Toronto

Modern and future many-core systems represent large and complex architectures. The communication fabrics in these large systems play an important role in their performance and… (more)

Subjects/Keywords: Network on Chip; Performance Modelling; 0537

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APA (6th Edition):

Badr, M. (2014). Synthetic Traffic Models that Capture Cache Coherent Behaviour. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/65537

Chicago Manual of Style (16th Edition):

Badr, Mario. “Synthetic Traffic Models that Capture Cache Coherent Behaviour.” 2014. Masters Thesis, University of Toronto. Accessed April 20, 2021. http://hdl.handle.net/1807/65537.

MLA Handbook (7th Edition):

Badr, Mario. “Synthetic Traffic Models that Capture Cache Coherent Behaviour.” 2014. Web. 20 Apr 2021.

Vancouver:

Badr M. Synthetic Traffic Models that Capture Cache Coherent Behaviour. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1807/65537.

Council of Science Editors:

Badr M. Synthetic Traffic Models that Capture Cache Coherent Behaviour. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/65537


University of Toronto

23. Kannan, Ajaykumar. Enabling Interposer-based Disintegration of Multi-Core Processors.

Degree: 2015, University of Toronto

Silicon interposers enable high-performance processors to integrate a significant amount of in-package memory, thereby providing huge bandwidth gains while reducing the costs of accessing memory.… (more)

Subjects/Keywords: Computer Architecture; Network on Chip; 0464

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APA (6th Edition):

Kannan, A. (2015). Enabling Interposer-based Disintegration of Multi-Core Processors. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/70378

Chicago Manual of Style (16th Edition):

Kannan, Ajaykumar. “Enabling Interposer-based Disintegration of Multi-Core Processors.” 2015. Masters Thesis, University of Toronto. Accessed April 20, 2021. http://hdl.handle.net/1807/70378.

MLA Handbook (7th Edition):

Kannan, Ajaykumar. “Enabling Interposer-based Disintegration of Multi-Core Processors.” 2015. Web. 20 Apr 2021.

Vancouver:

Kannan A. Enabling Interposer-based Disintegration of Multi-Core Processors. [Internet] [Masters thesis]. University of Toronto; 2015. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1807/70378.

Council of Science Editors:

Kannan A. Enabling Interposer-based Disintegration of Multi-Core Processors. [Masters Thesis]. University of Toronto; 2015. Available from: http://hdl.handle.net/1807/70378


University of Toronto

24. Matthew, Misler. An Exploration of On-chip Network-based Thread Migration.

Degree: 2010, University of Toronto

As the number of cores integrated on a single chip continues to increase, communication has the potential to become a severe bottleneck to overall system… (more)

Subjects/Keywords: Network on Chip; Thread migration; 0544

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APA (6th Edition):

Matthew, M. (2010). An Exploration of On-chip Network-based Thread Migration. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/25840

Chicago Manual of Style (16th Edition):

Matthew, Misler. “An Exploration of On-chip Network-based Thread Migration.” 2010. Masters Thesis, University of Toronto. Accessed April 20, 2021. http://hdl.handle.net/1807/25840.

MLA Handbook (7th Edition):

Matthew, Misler. “An Exploration of On-chip Network-based Thread Migration.” 2010. Web. 20 Apr 2021.

Vancouver:

Matthew M. An Exploration of On-chip Network-based Thread Migration. [Internet] [Masters thesis]. University of Toronto; 2010. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1807/25840.

Council of Science Editors:

Matthew M. An Exploration of On-chip Network-based Thread Migration. [Masters Thesis]. University of Toronto; 2010. Available from: http://hdl.handle.net/1807/25840


University of Cincinnati

25. Hariharan, Sriram. Performance Evaluation of the On-Chip Communications in a Network-on-Chip System.

Degree: MS, Engineering : Computer Engineering, 2005, University of Cincinnati

 Future system-on-chip (SoC) designs require predictable, scalable and reusable on-chip interconnect architecture to increase reliability and productivity. Current bus-based interconnect architectures are inherently non-scalable, less… (more)

Subjects/Keywords: Network-on-Chip

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APA (6th Edition):

Hariharan, S. (2005). Performance Evaluation of the On-Chip Communications in a Network-on-Chip System. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109186550

Chicago Manual of Style (16th Edition):

Hariharan, Sriram. “Performance Evaluation of the On-Chip Communications in a Network-on-Chip System.” 2005. Masters Thesis, University of Cincinnati. Accessed April 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109186550.

MLA Handbook (7th Edition):

Hariharan, Sriram. “Performance Evaluation of the On-Chip Communications in a Network-on-Chip System.” 2005. Web. 20 Apr 2021.

Vancouver:

Hariharan S. Performance Evaluation of the On-Chip Communications in a Network-on-Chip System. [Internet] [Masters thesis]. University of Cincinnati; 2005. [cited 2021 Apr 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109186550.

Council of Science Editors:

Hariharan S. Performance Evaluation of the On-Chip Communications in a Network-on-Chip System. [Masters Thesis]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109186550


Texas A&M University

26. Dang, Dharanidhar. Energy-Efficient Photonic Architectures for Large-Scale Data Analytics.

Degree: PhD, Computer Engineering, 2019, Texas A&M University

 With silicon technology reaching its physical limit, conventional computing systems are incapable of offering ever-increasing performance requirement with limited power budget. This has propelled semiconductor… (more)

Subjects/Keywords: Photonics; Network-on-Chip; Deep learning

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APA (6th Edition):

Dang, D. (2019). Energy-Efficient Photonic Architectures for Large-Scale Data Analytics. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/174537

Chicago Manual of Style (16th Edition):

Dang, Dharanidhar. “Energy-Efficient Photonic Architectures for Large-Scale Data Analytics.” 2019. Doctoral Dissertation, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/174537.

MLA Handbook (7th Edition):

Dang, Dharanidhar. “Energy-Efficient Photonic Architectures for Large-Scale Data Analytics.” 2019. Web. 20 Apr 2021.

Vancouver:

Dang D. Energy-Efficient Photonic Architectures for Large-Scale Data Analytics. [Internet] [Doctoral dissertation]. Texas A&M University; 2019. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/174537.

Council of Science Editors:

Dang D. Energy-Efficient Photonic Architectures for Large-Scale Data Analytics. [Doctoral Dissertation]. Texas A&M University; 2019. Available from: http://hdl.handle.net/1969.1/174537

27. FARIAS, Max Santana Rolemberg. Uma abordagem meta-heurística para o mapeamento de tarefas em uma plataforma MPSoC baseada em NoC.

Degree: 2014, Universidade Federal de Pernambuco

CNPq, FACEPE

O crescente número de tarefas em execução em plataformas Multiprocessor Systemson- Chips (MPSoC) exige mais e mais processadores e as plataformas MPSoC que… (more)

Subjects/Keywords: Network on Chip; MPSoC; Mapeamento de Tarefas

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APA (6th Edition):

FARIAS, M. S. R. (2014). Uma abordagem meta-heurística para o mapeamento de tarefas em uma plataforma MPSoC baseada em NoC. (Doctoral Dissertation). Universidade Federal de Pernambuco. Retrieved from https://repositorio.ufpe.br/handle/123456789/12432

Chicago Manual of Style (16th Edition):

FARIAS, Max Santana Rolemberg. “Uma abordagem meta-heurística para o mapeamento de tarefas em uma plataforma MPSoC baseada em NoC.” 2014. Doctoral Dissertation, Universidade Federal de Pernambuco. Accessed April 20, 2021. https://repositorio.ufpe.br/handle/123456789/12432.

MLA Handbook (7th Edition):

FARIAS, Max Santana Rolemberg. “Uma abordagem meta-heurística para o mapeamento de tarefas em uma plataforma MPSoC baseada em NoC.” 2014. Web. 20 Apr 2021.

Vancouver:

FARIAS MSR. Uma abordagem meta-heurística para o mapeamento de tarefas em uma plataforma MPSoC baseada em NoC. [Internet] [Doctoral dissertation]. Universidade Federal de Pernambuco; 2014. [cited 2021 Apr 20]. Available from: https://repositorio.ufpe.br/handle/123456789/12432.

Council of Science Editors:

FARIAS MSR. Uma abordagem meta-heurística para o mapeamento de tarefas em uma plataforma MPSoC baseada em NoC. [Doctoral Dissertation]. Universidade Federal de Pernambuco; 2014. Available from: https://repositorio.ufpe.br/handle/123456789/12432

28. Hélio Fernandes da Cunha Junior. Uma rede Ethernet on chip parametrizável para aplicações DSP em FPGA.

Degree: 2015, University of São Paulo

Com o crescimento acelerado da complexidade das aplicações e softwares que exigem alto desempenho, o hardware e sua arquitetura passou por algumas mudanças para que… (more)

Subjects/Keywords: DSP; Ethernet; FPGA; Network-on-chip; DSP; Ethernet; FPGA; Network-on-chip

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APA (6th Edition):

Junior, H. F. d. C. (2015). Uma rede Ethernet on chip parametrizável para aplicações DSP em FPGA. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/55/55134/tde-05102016-141441/

Chicago Manual of Style (16th Edition):

Junior, Hélio Fernandes da Cunha. “Uma rede Ethernet on chip parametrizável para aplicações DSP em FPGA.” 2015. Masters Thesis, University of São Paulo. Accessed April 20, 2021. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-05102016-141441/.

MLA Handbook (7th Edition):

Junior, Hélio Fernandes da Cunha. “Uma rede Ethernet on chip parametrizável para aplicações DSP em FPGA.” 2015. Web. 20 Apr 2021.

Vancouver:

Junior HFdC. Uma rede Ethernet on chip parametrizável para aplicações DSP em FPGA. [Internet] [Masters thesis]. University of São Paulo; 2015. [cited 2021 Apr 20]. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-05102016-141441/.

Council of Science Editors:

Junior HFdC. Uma rede Ethernet on chip parametrizável para aplicações DSP em FPGA. [Masters Thesis]. University of São Paulo; 2015. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-05102016-141441/


Texas A&M University

29. Jang, Hyunjun. High Performance On-Chip Interconnects Design for Future Many-Core Architectures.

Degree: PhD, Computer Engineering, 2015, Texas A&M University

 Switch-based Network-on-Chip (NoC) is a widely accepted inter-core communication infrastructure for Chip Multiprocessors (CMPs). With the continued advance of CMOS technology, the number of cores… (more)

Subjects/Keywords: Chip Multiprocessors; Network-on-Chip; General Purpose Graphics Processing Units

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APA (6th Edition):

Jang, H. (2015). High Performance On-Chip Interconnects Design for Future Many-Core Architectures. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156384

Chicago Manual of Style (16th Edition):

Jang, Hyunjun. “High Performance On-Chip Interconnects Design for Future Many-Core Architectures.” 2015. Doctoral Dissertation, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/156384.

MLA Handbook (7th Edition):

Jang, Hyunjun. “High Performance On-Chip Interconnects Design for Future Many-Core Architectures.” 2015. Web. 20 Apr 2021.

Vancouver:

Jang H. High Performance On-Chip Interconnects Design for Future Many-Core Architectures. [Internet] [Doctoral dissertation]. Texas A&M University; 2015. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/156384.

Council of Science Editors:

Jang H. High Performance On-Chip Interconnects Design for Future Many-Core Architectures. [Doctoral Dissertation]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/156384


Colorado State University

30. Pimpalkhute, Tejasi. Heterogeneous prioritization for network-on-chip based multi-core systems.

Degree: MS(M.S.), Electrical and Computer Engineering, 2013, Colorado State University

 In chip multi-processor (CMP) systems, communication and memory access both play an important role in influencing the performance achievable by the system. The manner in… (more)

Subjects/Keywords: multi-core systems; off-chip memory; network-on-chip

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APA (6th Edition):

Pimpalkhute, T. (2013). Heterogeneous prioritization for network-on-chip based multi-core systems. (Masters Thesis). Colorado State University. Retrieved from http://hdl.handle.net/10217/81054

Chicago Manual of Style (16th Edition):

Pimpalkhute, Tejasi. “Heterogeneous prioritization for network-on-chip based multi-core systems.” 2013. Masters Thesis, Colorado State University. Accessed April 20, 2021. http://hdl.handle.net/10217/81054.

MLA Handbook (7th Edition):

Pimpalkhute, Tejasi. “Heterogeneous prioritization for network-on-chip based multi-core systems.” 2013. Web. 20 Apr 2021.

Vancouver:

Pimpalkhute T. Heterogeneous prioritization for network-on-chip based multi-core systems. [Internet] [Masters thesis]. Colorado State University; 2013. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/10217/81054.

Council of Science Editors:

Pimpalkhute T. Heterogeneous prioritization for network-on-chip based multi-core systems. [Masters Thesis]. Colorado State University; 2013. Available from: http://hdl.handle.net/10217/81054

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