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You searched for subject:(Near Threshold computing). Showing records 1 – 14 of 14 total matches.

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Texas A&M University

1. Gao, Zhuoyang. Comparative Study on Performance and Variation Tolerance of Low Power Circuit.

Degree: 2015, Texas A&M University

 The demand for low-power electronic devices is increasing rapidly in current VLSI technology. Instead of conventional CMOS circuit operating at nominal supply voltage, several kinds… (more)

Subjects/Keywords: low power; adiabatic circuit; near-threshold computing

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APA (6th Edition):

Gao, Z. (2015). Comparative Study on Performance and Variation Tolerance of Low Power Circuit. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156528

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gao, Zhuoyang. “Comparative Study on Performance and Variation Tolerance of Low Power Circuit.” 2015. Thesis, Texas A&M University. Accessed October 21, 2019. http://hdl.handle.net/1969.1/156528.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gao, Zhuoyang. “Comparative Study on Performance and Variation Tolerance of Low Power Circuit.” 2015. Web. 21 Oct 2019.

Vancouver:

Gao Z. Comparative Study on Performance and Variation Tolerance of Low Power Circuit. [Internet] [Thesis]. Texas A&M University; 2015. [cited 2019 Oct 21]. Available from: http://hdl.handle.net/1969.1/156528.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gao Z. Comparative Study on Performance and Variation Tolerance of Low Power Circuit. [Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/156528

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

2. Seo, Sangwon. Energy-Efficient Computing for Mobile Signal Processing.

Degree: PhD, Electrical Engineering, 2011, University of Michigan

 Mobile devices have rapidly proliferated, and deployment of handheld devices continues to increase at a spectacular rate. As today's devices not only support advanced signal… (more)

Subjects/Keywords: Near-threshold Computing; SIMD Architecture; Software Defined Radio; Electrical Engineering; Engineering

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APA (6th Edition):

Seo, S. (2011). Energy-Efficient Computing for Mobile Signal Processing. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86356

Chicago Manual of Style (16th Edition):

Seo, Sangwon. “Energy-Efficient Computing for Mobile Signal Processing.” 2011. Doctoral Dissertation, University of Michigan. Accessed October 21, 2019. http://hdl.handle.net/2027.42/86356.

MLA Handbook (7th Edition):

Seo, Sangwon. “Energy-Efficient Computing for Mobile Signal Processing.” 2011. Web. 21 Oct 2019.

Vancouver:

Seo S. Energy-Efficient Computing for Mobile Signal Processing. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2019 Oct 21]. Available from: http://hdl.handle.net/2027.42/86356.

Council of Science Editors:

Seo S. Energy-Efficient Computing for Mobile Signal Processing. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86356


Utah State University

3. Rajamanikkam, Chidhambaranathan. Understanding Security Threats of Emerging Computing Architectures and Mitigating Performance Bottlenecks of On-Chip Interconnects in Manycore NTC System.

Degree: PhD, Electrical and Computer Engineering, 2019, Utah State University

  Emerging computing architectures such as, neuromorphic computing and third party intellectual property (3PIP) cores, have attracted significant attention in the recent past. Neuromorphic Computing(more)

Subjects/Keywords: Hardware Security; Neuromorphic Computing; Network-on-Chips; Near-Threshold Computing; Memristors; Electrical and Computer Engineering

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APA (6th Edition):

Rajamanikkam, C. (2019). Understanding Security Threats of Emerging Computing Architectures and Mitigating Performance Bottlenecks of On-Chip Interconnects in Manycore NTC System. (Doctoral Dissertation). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/7453

Chicago Manual of Style (16th Edition):

Rajamanikkam, Chidhambaranathan. “Understanding Security Threats of Emerging Computing Architectures and Mitigating Performance Bottlenecks of On-Chip Interconnects in Manycore NTC System.” 2019. Doctoral Dissertation, Utah State University. Accessed October 21, 2019. https://digitalcommons.usu.edu/etd/7453.

MLA Handbook (7th Edition):

Rajamanikkam, Chidhambaranathan. “Understanding Security Threats of Emerging Computing Architectures and Mitigating Performance Bottlenecks of On-Chip Interconnects in Manycore NTC System.” 2019. Web. 21 Oct 2019.

Vancouver:

Rajamanikkam C. Understanding Security Threats of Emerging Computing Architectures and Mitigating Performance Bottlenecks of On-Chip Interconnects in Manycore NTC System. [Internet] [Doctoral dissertation]. Utah State University; 2019. [cited 2019 Oct 21]. Available from: https://digitalcommons.usu.edu/etd/7453.

Council of Science Editors:

Rajamanikkam C. Understanding Security Threats of Emerging Computing Architectures and Mitigating Performance Bottlenecks of On-Chip Interconnects in Manycore NTC System. [Doctoral Dissertation]. Utah State University; 2019. Available from: https://digitalcommons.usu.edu/etd/7453


Utah State University

4. Mugisha, Dieudonne Manzi. Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime.

Degree: MS, Electrical and Computer Engineering, 2015, Utah State University

Near-Threshold Computing embodies an intriguing choice for mobile processors due to the promise of superior energy efficiency, extending the battery life of these devices… (more)

Subjects/Keywords: Low power computing; Memory system; Near-threshold computing; Process variation; Computer Engineering

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APA (6th Edition):

Mugisha, D. M. (2015). Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime. (Masters Thesis). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/4550

Chicago Manual of Style (16th Edition):

Mugisha, Dieudonne Manzi. “Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime.” 2015. Masters Thesis, Utah State University. Accessed October 21, 2019. https://digitalcommons.usu.edu/etd/4550.

MLA Handbook (7th Edition):

Mugisha, Dieudonne Manzi. “Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime.” 2015. Web. 21 Oct 2019.

Vancouver:

Mugisha DM. Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime. [Internet] [Masters thesis]. Utah State University; 2015. [cited 2019 Oct 21]. Available from: https://digitalcommons.usu.edu/etd/4550.

Council of Science Editors:

Mugisha DM. Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime. [Masters Thesis]. Utah State University; 2015. Available from: https://digitalcommons.usu.edu/etd/4550


UCLA

5. Wendt, James Bradley. Hardware Design Techniques for Securing and Synthesizing Resource-Constrained IoT Systems.

Degree: Computer Science, 2015, UCLA

 The Internet of Things (IoT) paradigm has enabled everyday objects to be instrumented and operated in such a way that they can be queried and… (more)

Subjects/Keywords: Computer science; hardware security; Internet of Things; low power; near-threshold computing; remote trust

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APA (6th Edition):

Wendt, J. B. (2015). Hardware Design Techniques for Securing and Synthesizing Resource-Constrained IoT Systems. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/3w66h943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wendt, James Bradley. “Hardware Design Techniques for Securing and Synthesizing Resource-Constrained IoT Systems.” 2015. Thesis, UCLA. Accessed October 21, 2019. http://www.escholarship.org/uc/item/3w66h943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wendt, James Bradley. “Hardware Design Techniques for Securing and Synthesizing Resource-Constrained IoT Systems.” 2015. Web. 21 Oct 2019.

Vancouver:

Wendt JB. Hardware Design Techniques for Securing and Synthesizing Resource-Constrained IoT Systems. [Internet] [Thesis]. UCLA; 2015. [cited 2019 Oct 21]. Available from: http://www.escholarship.org/uc/item/3w66h943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wendt JB. Hardware Design Techniques for Securing and Synthesizing Resource-Constrained IoT Systems. [Thesis]. UCLA; 2015. Available from: http://www.escholarship.org/uc/item/3w66h943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Utah State University

6. Pal, Asmita. Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit.

Degree: MS, Electrical and Computer Engineering, 2018, Utah State University

  Over the last decade, Graphics Processing Units (GPUs) have been used extensively in gaming consoles, mobile phones, workstations and data centers, as they have… (more)

Subjects/Keywords: GPU; Near Threshold Computing; Process Variation; Register Access Latency; Wavefront Scheduling; Computer Engineering

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APA (6th Edition):

Pal, A. (2018). Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit. (Masters Thesis). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/7155

Chicago Manual of Style (16th Edition):

Pal, Asmita. “Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit.” 2018. Masters Thesis, Utah State University. Accessed October 21, 2019. https://digitalcommons.usu.edu/etd/7155.

MLA Handbook (7th Edition):

Pal, Asmita. “Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit.” 2018. Web. 21 Oct 2019.

Vancouver:

Pal A. Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit. [Internet] [Masters thesis]. Utah State University; 2018. [cited 2019 Oct 21]. Available from: https://digitalcommons.usu.edu/etd/7155.

Council of Science Editors:

Pal A. Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit. [Masters Thesis]. Utah State University; 2018. Available from: https://digitalcommons.usu.edu/etd/7155


University of Michigan

7. Pinckney, Nathaniel Ross. Near-Threshold Computing: Past, Present, and Future.

Degree: PhD, Electrical Engineering, 2015, University of Michigan

 Transistor threshold voltages have stagnated in recent years, deviating from constant-voltage scaling theory and directly limiting supply voltage scaling. To overcome the resulting energy and… (more)

Subjects/Keywords: Near Threshold Computing; Energy Efficiency; Low Power; Voltage Boosting; Electrical Engineering; Engineering

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APA (6th Edition):

Pinckney, N. R. (2015). Near-Threshold Computing: Past, Present, and Future. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/113600

Chicago Manual of Style (16th Edition):

Pinckney, Nathaniel Ross. “Near-Threshold Computing: Past, Present, and Future.” 2015. Doctoral Dissertation, University of Michigan. Accessed October 21, 2019. http://hdl.handle.net/2027.42/113600.

MLA Handbook (7th Edition):

Pinckney, Nathaniel Ross. “Near-Threshold Computing: Past, Present, and Future.” 2015. Web. 21 Oct 2019.

Vancouver:

Pinckney NR. Near-Threshold Computing: Past, Present, and Future. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2019 Oct 21]. Available from: http://hdl.handle.net/2027.42/113600.

Council of Science Editors:

Pinckney NR. Near-Threshold Computing: Past, Present, and Future. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/113600

8. Ragavan, Rengarajan. Error handling and energy estimation for error resilient near-threshold computing : Gestion des erreurs et estimations énergétiques pour les architectures tolérantes aux fautes et proches du seuil.

Degree: Docteur es, Traitement du signal et télécommunications, 2017, Rennes 1; University de Rennes 1

Les techniques de gestion dynamique de la tension (DVS) sont principalement utilisés dans la conception de circuits numériques pour en améliorer l'efficacité énergétique. Cependant, la… (more)

Subjects/Keywords: Gestion des erreurs; Régime proche du seuil; Tolérance aux fautes; Error handling; Near-Threshold computing; Approximate computing

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APA (6th Edition):

Ragavan, R. (2017). Error handling and energy estimation for error resilient near-threshold computing : Gestion des erreurs et estimations énergétiques pour les architectures tolérantes aux fautes et proches du seuil. (Doctoral Dissertation). Rennes 1; University de Rennes 1. Retrieved from http://www.theses.fr/2017REN1S038

Chicago Manual of Style (16th Edition):

Ragavan, Rengarajan. “Error handling and energy estimation for error resilient near-threshold computing : Gestion des erreurs et estimations énergétiques pour les architectures tolérantes aux fautes et proches du seuil.” 2017. Doctoral Dissertation, Rennes 1; University de Rennes 1. Accessed October 21, 2019. http://www.theses.fr/2017REN1S038.

MLA Handbook (7th Edition):

Ragavan, Rengarajan. “Error handling and energy estimation for error resilient near-threshold computing : Gestion des erreurs et estimations énergétiques pour les architectures tolérantes aux fautes et proches du seuil.” 2017. Web. 21 Oct 2019.

Vancouver:

Ragavan R. Error handling and energy estimation for error resilient near-threshold computing : Gestion des erreurs et estimations énergétiques pour les architectures tolérantes aux fautes et proches du seuil. [Internet] [Doctoral dissertation]. Rennes 1; University de Rennes 1; 2017. [cited 2019 Oct 21]. Available from: http://www.theses.fr/2017REN1S038.

Council of Science Editors:

Ragavan R. Error handling and energy estimation for error resilient near-threshold computing : Gestion des erreurs et estimations énergétiques pour les architectures tolérantes aux fautes et proches du seuil. [Doctoral Dissertation]. Rennes 1; University de Rennes 1; 2017. Available from: http://www.theses.fr/2017REN1S038


Utah State University

9. Sanyal, Sourav. Predicting Critical Warps in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis.

Degree: MS, Electrical and Computer Engineering, 2019, Utah State University

  General purpose graphics processing units (GP-GPU), owing to their enormous thread-level parallelism, can significantly improve the power consumption at the near-threshold (NTC) operating region,… (more)

Subjects/Keywords: Process Variation; Near-Threshold Computing; General Purpose Graphics Processing Unit; Warp Criticality Problem; Single Instruction Multiple Data; Computer Engineering

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APA (6th Edition):

Sanyal, S. (2019). Predicting Critical Warps in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis. (Masters Thesis). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/7545

Chicago Manual of Style (16th Edition):

Sanyal, Sourav. “Predicting Critical Warps in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis.” 2019. Masters Thesis, Utah State University. Accessed October 21, 2019. https://digitalcommons.usu.edu/etd/7545.

MLA Handbook (7th Edition):

Sanyal, Sourav. “Predicting Critical Warps in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis.” 2019. Web. 21 Oct 2019.

Vancouver:

Sanyal S. Predicting Critical Warps in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis. [Internet] [Masters thesis]. Utah State University; 2019. [cited 2019 Oct 21]. Available from: https://digitalcommons.usu.edu/etd/7545.

Council of Science Editors:

Sanyal S. Predicting Critical Warps in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis. [Masters Thesis]. Utah State University; 2019. Available from: https://digitalcommons.usu.edu/etd/7545


Utah State University

10. Basu, Prabal. Toward Reliable, Secure, and Energy-Efficient Multi-Core System Design.

Degree: PhD, Electrical and Computer Engineering, 2019, Utah State University

  Computer hardware researchers have perennially focussed on improving the performance of computers while stipulating the energy consumption under a strict budget. While several innovations… (more)

Subjects/Keywords: Network-on-Chip; Power Supply Noise; Near-Threshold Computing; Graphics Processing Unit; Fault Attack; Electrical and Computer Engineering

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APA (6th Edition):

Basu, P. (2019). Toward Reliable, Secure, and Energy-Efficient Multi-Core System Design. (Doctoral Dissertation). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/7517

Chicago Manual of Style (16th Edition):

Basu, Prabal. “Toward Reliable, Secure, and Energy-Efficient Multi-Core System Design.” 2019. Doctoral Dissertation, Utah State University. Accessed October 21, 2019. https://digitalcommons.usu.edu/etd/7517.

MLA Handbook (7th Edition):

Basu, Prabal. “Toward Reliable, Secure, and Energy-Efficient Multi-Core System Design.” 2019. Web. 21 Oct 2019.

Vancouver:

Basu P. Toward Reliable, Secure, and Energy-Efficient Multi-Core System Design. [Internet] [Doctoral dissertation]. Utah State University; 2019. [cited 2019 Oct 21]. Available from: https://digitalcommons.usu.edu/etd/7517.

Council of Science Editors:

Basu P. Toward Reliable, Secure, and Energy-Efficient Multi-Core System Design. [Doctoral Dissertation]. Utah State University; 2019. Available from: https://digitalcommons.usu.edu/etd/7517


University of Illinois – Urbana-Champaign

11. Lin, Yingyan. Energy-efficient systems for information transfer and processing.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Machine learning (ML) systems are finding excellent utility in tackling the data deluge of the big data era thanks to the exponential increase in computing(more)

Subjects/Keywords: Machine learning; Energy efficiency; Analog-to-digital converter; Bit-error-rate optimal analog-to-digital converter (ADC); Convolutional neural networks; Sparsity; Statistical error compensation; Near threshold computing

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APA (6th Edition):

Lin, Y. (2017). Energy-efficient systems for information transfer and processing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98139

Chicago Manual of Style (16th Edition):

Lin, Yingyan. “Energy-efficient systems for information transfer and processing.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 21, 2019. http://hdl.handle.net/2142/98139.

MLA Handbook (7th Edition):

Lin, Yingyan. “Energy-efficient systems for information transfer and processing.” 2017. Web. 21 Oct 2019.

Vancouver:

Lin Y. Energy-efficient systems for information transfer and processing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Oct 21]. Available from: http://hdl.handle.net/2142/98139.

Council of Science Editors:

Lin Y. Energy-efficient systems for information transfer and processing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98139


The Ohio State University

12. Pan, Xiang. Designing Future Low-Power and Secure Processors with Non-Volatile Memory.

Degree: PhD, Computer Science and Engineering, 2017, The Ohio State University

 Non-volatile memories such as Spin-Transfer Torque Random Access Memory (STT-RAM), Phase Change Memory (PCM), Resistive Random Access Memory (ReRAM), etc. are emerging as promising alternatives… (more)

Subjects/Keywords: Computer Science; Computer Engineering; Non-Volatile Memory, STT-RAM, Low-Power Processor Architecture, Cache, Near-Threshold Computing, Process Variation, Security, Secure Processor Design, Cold Boot Attack

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APA (6th Edition):

Pan, X. (2017). Designing Future Low-Power and Secure Processors with Non-Volatile Memory. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1492631536670669

Chicago Manual of Style (16th Edition):

Pan, Xiang. “Designing Future Low-Power and Secure Processors with Non-Volatile Memory.” 2017. Doctoral Dissertation, The Ohio State University. Accessed October 21, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492631536670669.

MLA Handbook (7th Edition):

Pan, Xiang. “Designing Future Low-Power and Secure Processors with Non-Volatile Memory.” 2017. Web. 21 Oct 2019.

Vancouver:

Pan X. Designing Future Low-Power and Secure Processors with Non-Volatile Memory. [Internet] [Doctoral dissertation]. The Ohio State University; 2017. [cited 2019 Oct 21]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1492631536670669.

Council of Science Editors:

Pan X. Designing Future Low-Power and Secure Processors with Non-Volatile Memory. [Doctoral Dissertation]. The Ohio State University; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1492631536670669

13. Fick, David A. Power, Interconnect, and Reliability Techniques for Large Scale Integrated Circuits.

Degree: PhD, Computer Science & Engineering, 2012, University of Michigan

 Historically, consumer computing products have moved to increasingly smaller form factors, from the personal computer, to the laptop, and now to devices such as smart… (more)

Subjects/Keywords: VLSI; Integrated Circuits; Network-on-Chip; 3DIC; Near-threshold Computing; Manycore; Computer Science; Electrical Engineering; Engineering

…multiple layers of silicon. In this chapter, we propose using near-threshold computing (NTC… …large number of cores that operate near the threshold voltage of the process. This improves… …stochastic computing implementation of the filters from Figure 6.2. The nine stochastic streams… …large scale computing and why it is an important research topic. It shows how some of the… …area related to this dissertation. 1.1 Large Scale Computing The first “computer”, as we… 

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APA (6th Edition):

Fick, D. A. (2012). Power, Interconnect, and Reliability Techniques for Large Scale Integrated Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/96066

Chicago Manual of Style (16th Edition):

Fick, David A. “Power, Interconnect, and Reliability Techniques for Large Scale Integrated Circuits.” 2012. Doctoral Dissertation, University of Michigan. Accessed October 21, 2019. http://hdl.handle.net/2027.42/96066.

MLA Handbook (7th Edition):

Fick, David A. “Power, Interconnect, and Reliability Techniques for Large Scale Integrated Circuits.” 2012. Web. 21 Oct 2019.

Vancouver:

Fick DA. Power, Interconnect, and Reliability Techniques for Large Scale Integrated Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2012. [cited 2019 Oct 21]. Available from: http://hdl.handle.net/2027.42/96066.

Council of Science Editors:

Fick DA. Power, Interconnect, and Reliability Techniques for Large Scale Integrated Circuits. [Doctoral Dissertation]. University of Michigan; 2012. Available from: http://hdl.handle.net/2027.42/96066

14. Seok, Mingoo. Extreme Power-Constrained Integrated Circuit Design.

Degree: PhD, Electrical Engineering, 2011, University of Michigan

 Recently sensing systems of cubic millimeter scale have gained significant attention since they may be embedded virtually anywhere. For developing these systems, there are two… (more)

Subjects/Keywords: Sensing System, Biomedical, Implantable, Cubic Millimeter System, Computing; Ultra Low Voltage, Low Voltage, Subthreshold, Near-threshold; CMOS, MOSFET, Circuit Design, Architecture; Power Gating Switch, SRAM, ROM, FFT, Voltage Reference, Multiplier, Technology Selection, Clock Network, Pipeline; Electrical Engineering; Engineering

…Published sub- or near-threshold VLSI designs. . . . . . . . . . . . . 43 3.2 Application… …x29; or near-threshold voltage (for medium-Vth devices) in the target technology… …voltage circuits. The requirements of sub-threshold and near-threshold circuits are different… …Vth Threshold Voltage Vt Thermal Voltage xvii ABSTRACT Extreme Power-Constrained… …energy consumption of integrated circuits. Scaling supply voltage down to near, or below, the… 

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APA (6th Edition):

Seok, M. (2011). Extreme Power-Constrained Integrated Circuit Design. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/84536

Chicago Manual of Style (16th Edition):

Seok, Mingoo. “Extreme Power-Constrained Integrated Circuit Design.” 2011. Doctoral Dissertation, University of Michigan. Accessed October 21, 2019. http://hdl.handle.net/2027.42/84536.

MLA Handbook (7th Edition):

Seok, Mingoo. “Extreme Power-Constrained Integrated Circuit Design.” 2011. Web. 21 Oct 2019.

Vancouver:

Seok M. Extreme Power-Constrained Integrated Circuit Design. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2019 Oct 21]. Available from: http://hdl.handle.net/2027.42/84536.

Council of Science Editors:

Seok M. Extreme Power-Constrained Integrated Circuit Design. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/84536

.