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You searched for subject:(NBTI). Showing records 1 – 30 of 59 total matches.

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NSYSU

1. Lu, I-Jing. Investigation on Reliability and Anomalous Degradation of Low Temperature Poly-Si Thin-Film Transistor.

Degree: Master, Physics, 2009, NSYSU

 In this thesis, we will investigate the degradation of the Low-Temperature-Polycrystalline-Silicon TFTs(LTPS TFTS) under the electrical stress. The devices are offer by Chi Mei Optoelectronics.… (more)

Subjects/Keywords: NBTI; self-heating

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APA (6th Edition):

Lu, I. (2009). Investigation on Reliability and Anomalous Degradation of Low Temperature Poly-Si Thin-Film Transistor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0303109-160315

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, I-Jing. “Investigation on Reliability and Anomalous Degradation of Low Temperature Poly-Si Thin-Film Transistor.” 2009. Thesis, NSYSU. Accessed April 02, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0303109-160315.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, I-Jing. “Investigation on Reliability and Anomalous Degradation of Low Temperature Poly-Si Thin-Film Transistor.” 2009. Web. 02 Apr 2020.

Vancouver:

Lu I. Investigation on Reliability and Anomalous Degradation of Low Temperature Poly-Si Thin-Film Transistor. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Apr 02]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0303109-160315.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu I. Investigation on Reliability and Anomalous Degradation of Low Temperature Poly-Si Thin-Film Transistor. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0303109-160315

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Hsiao, Po-wen. NBTI characteristics of p-MOSFETs under external mechanical stress.

Degree: Master, Physics, 2009, NSYSU

 In this thesis, in order to eliminate process issue, an external mechanical uniaxial tensile and compressive stress applied on p-type metal-oxide-semiconductor field effect transistors (p-MOSFETs)… (more)

Subjects/Keywords: mechanical stress; NBTI; PMOSFET

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APA (6th Edition):

Hsiao, P. (2009). NBTI characteristics of p-MOSFETs under external mechanical stress. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625109-175508

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsiao, Po-wen. “NBTI characteristics of p-MOSFETs under external mechanical stress.” 2009. Thesis, NSYSU. Accessed April 02, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625109-175508.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsiao, Po-wen. “NBTI characteristics of p-MOSFETs under external mechanical stress.” 2009. Web. 02 Apr 2020.

Vancouver:

Hsiao P. NBTI characteristics of p-MOSFETs under external mechanical stress. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Apr 02]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625109-175508.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsiao P. NBTI characteristics of p-MOSFETs under external mechanical stress. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625109-175508

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

3. Follman, Jacob Jay. On the atomic scale defects involved in the negative bias temperature instability in 4H-SiC MOSFETs.

Degree: MS, Materials Science and Engineering, 2013, Penn State University

 We utilize electrically detected magnetic resonance (EDMR) to explore the effects of the negative bias temperature instability (NBTI) in 4H-SiC metal oxide semiconductor field effect… (more)

Subjects/Keywords: NBTI; SiC; MOSFET; EPR; EDMR

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APA (6th Edition):

Follman, J. J. (2013). On the atomic scale defects involved in the negative bias temperature instability in 4H-SiC MOSFETs. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/17654

Chicago Manual of Style (16th Edition):

Follman, Jacob Jay. “On the atomic scale defects involved in the negative bias temperature instability in 4H-SiC MOSFETs.” 2013. Masters Thesis, Penn State University. Accessed April 02, 2020. https://etda.libraries.psu.edu/catalog/17654.

MLA Handbook (7th Edition):

Follman, Jacob Jay. “On the atomic scale defects involved in the negative bias temperature instability in 4H-SiC MOSFETs.” 2013. Web. 02 Apr 2020.

Vancouver:

Follman JJ. On the atomic scale defects involved in the negative bias temperature instability in 4H-SiC MOSFETs. [Internet] [Masters thesis]. Penn State University; 2013. [cited 2020 Apr 02]. Available from: https://etda.libraries.psu.edu/catalog/17654.

Council of Science Editors:

Follman JJ. On the atomic scale defects involved in the negative bias temperature instability in 4H-SiC MOSFETs. [Masters Thesis]. Penn State University; 2013. Available from: https://etda.libraries.psu.edu/catalog/17654


Université de Grenoble

4. Ruiz Amador, Dolly Natalia. Multilevel aging phenomena analysis in complex ultimate CMOS designs : Simulation de vieillissement de circuits CMOS complexes.

Degree: Docteur es, Sciences et technologie industrielles, 2012, Université de Grenoble

L'auteur n'a pas fourni de résumé en français.

Integrated circuits evolution is driven by the trend of increasing operating frequencies and downscaling of the device… (more)

Subjects/Keywords: NBTI; HCI; Vieillissement; Circuits; CMOS; NBTI; HCI; Ageing; Circuits; CMOS; 620

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APA (6th Edition):

Ruiz Amador, D. N. (2012). Multilevel aging phenomena analysis in complex ultimate CMOS designs : Simulation de vieillissement de circuits CMOS complexes. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2012GRENT002

Chicago Manual of Style (16th Edition):

Ruiz Amador, Dolly Natalia. “Multilevel aging phenomena analysis in complex ultimate CMOS designs : Simulation de vieillissement de circuits CMOS complexes.” 2012. Doctoral Dissertation, Université de Grenoble. Accessed April 02, 2020. http://www.theses.fr/2012GRENT002.

MLA Handbook (7th Edition):

Ruiz Amador, Dolly Natalia. “Multilevel aging phenomena analysis in complex ultimate CMOS designs : Simulation de vieillissement de circuits CMOS complexes.” 2012. Web. 02 Apr 2020.

Vancouver:

Ruiz Amador DN. Multilevel aging phenomena analysis in complex ultimate CMOS designs : Simulation de vieillissement de circuits CMOS complexes. [Internet] [Doctoral dissertation]. Université de Grenoble; 2012. [cited 2020 Apr 02]. Available from: http://www.theses.fr/2012GRENT002.

Council of Science Editors:

Ruiz Amador DN. Multilevel aging phenomena analysis in complex ultimate CMOS designs : Simulation de vieillissement de circuits CMOS complexes. [Doctoral Dissertation]. Université de Grenoble; 2012. Available from: http://www.theses.fr/2012GRENT002

5. Rousselin, Thomas. Modélisation et interprétation des effets combinés vieillissement/SEE dans les technologies d'échelles nanométriques appliquées au domaine avionique : Modelisation and analysis of the impact of the combined effects of aging and SEE for nano-scaled technologies in avionics.

Degree: Docteur es, Génie Electrique, 2018, Toulouse, ISAE

L’électronique embarquée dans l’aéronautique, couramment appelé avionique, est chargée d’effectuer des tâches critiques et doit présenter une fiabilité élevée. La technologie Complementary Metal Oxyde Semiconductor… (more)

Subjects/Keywords: Vieillissement; NBTI; SEE; FinFET; Avionique; Aging; NBTI; SEE; FinFET; Avionics

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APA (6th Edition):

Rousselin, T. (2018). Modélisation et interprétation des effets combinés vieillissement/SEE dans les technologies d'échelles nanométriques appliquées au domaine avionique : Modelisation and analysis of the impact of the combined effects of aging and SEE for nano-scaled technologies in avionics. (Doctoral Dissertation). Toulouse, ISAE. Retrieved from http://www.theses.fr/2018ESAE0044

Chicago Manual of Style (16th Edition):

Rousselin, Thomas. “Modélisation et interprétation des effets combinés vieillissement/SEE dans les technologies d'échelles nanométriques appliquées au domaine avionique : Modelisation and analysis of the impact of the combined effects of aging and SEE for nano-scaled technologies in avionics.” 2018. Doctoral Dissertation, Toulouse, ISAE. Accessed April 02, 2020. http://www.theses.fr/2018ESAE0044.

MLA Handbook (7th Edition):

Rousselin, Thomas. “Modélisation et interprétation des effets combinés vieillissement/SEE dans les technologies d'échelles nanométriques appliquées au domaine avionique : Modelisation and analysis of the impact of the combined effects of aging and SEE for nano-scaled technologies in avionics.” 2018. Web. 02 Apr 2020.

Vancouver:

Rousselin T. Modélisation et interprétation des effets combinés vieillissement/SEE dans les technologies d'échelles nanométriques appliquées au domaine avionique : Modelisation and analysis of the impact of the combined effects of aging and SEE for nano-scaled technologies in avionics. [Internet] [Doctoral dissertation]. Toulouse, ISAE; 2018. [cited 2020 Apr 02]. Available from: http://www.theses.fr/2018ESAE0044.

Council of Science Editors:

Rousselin T. Modélisation et interprétation des effets combinés vieillissement/SEE dans les technologies d'échelles nanométriques appliquées au domaine avionique : Modelisation and analysis of the impact of the combined effects of aging and SEE for nano-scaled technologies in avionics. [Doctoral Dissertation]. Toulouse, ISAE; 2018. Available from: http://www.theses.fr/2018ESAE0044


Vanderbilt University

6. Duan, Guoxing. Radiation effects, negative-bias-temperature instability, and low-frequency 1/f noise in SiGe/SiO2/HfO2 pMOS devices.

Degree: PhD, Electrical Engineering, 2016, Vanderbilt University

 The total ionizing dose (TID) response of HfO2-SiO2/SiGe pMOS FinFETs under different irradiation biases has been evaluated. Negative bias irradiation leads to the worst-case degradation.… (more)

Subjects/Keywords: HfO2; SiGe; low frequency noise; NBTI; TID

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APA (6th Edition):

Duan, G. (2016). Radiation effects, negative-bias-temperature instability, and low-frequency 1/f noise in SiGe/SiO2/HfO2 pMOS devices. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-07212016-224032/ ;

Chicago Manual of Style (16th Edition):

Duan, Guoxing. “Radiation effects, negative-bias-temperature instability, and low-frequency 1/f noise in SiGe/SiO2/HfO2 pMOS devices.” 2016. Doctoral Dissertation, Vanderbilt University. Accessed April 02, 2020. http://etd.library.vanderbilt.edu/available/etd-07212016-224032/ ;.

MLA Handbook (7th Edition):

Duan, Guoxing. “Radiation effects, negative-bias-temperature instability, and low-frequency 1/f noise in SiGe/SiO2/HfO2 pMOS devices.” 2016. Web. 02 Apr 2020.

Vancouver:

Duan G. Radiation effects, negative-bias-temperature instability, and low-frequency 1/f noise in SiGe/SiO2/HfO2 pMOS devices. [Internet] [Doctoral dissertation]. Vanderbilt University; 2016. [cited 2020 Apr 02]. Available from: http://etd.library.vanderbilt.edu/available/etd-07212016-224032/ ;.

Council of Science Editors:

Duan G. Radiation effects, negative-bias-temperature instability, and low-frequency 1/f noise in SiGe/SiO2/HfO2 pMOS devices. [Doctoral Dissertation]. Vanderbilt University; 2016. Available from: http://etd.library.vanderbilt.edu/available/etd-07212016-224032/ ;


Arizona State University

7. Zheng, Rui. Aging Predictive Models and Simulation Methods for Analog and Mixed-Signal Circuits.

Degree: MS, Electrical Engineering, 2011, Arizona State University

 Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are important reliability issues impacting analog circuit performance and lifetime. Compact reliability models and efficient… (more)

Subjects/Keywords: Electrical Engineering; aging model; analog; CHC; NBTI

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APA (6th Edition):

Zheng, R. (2011). Aging Predictive Models and Simulation Methods for Analog and Mixed-Signal Circuits. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/9148

Chicago Manual of Style (16th Edition):

Zheng, Rui. “Aging Predictive Models and Simulation Methods for Analog and Mixed-Signal Circuits.” 2011. Masters Thesis, Arizona State University. Accessed April 02, 2020. http://repository.asu.edu/items/9148.

MLA Handbook (7th Edition):

Zheng, Rui. “Aging Predictive Models and Simulation Methods for Analog and Mixed-Signal Circuits.” 2011. Web. 02 Apr 2020.

Vancouver:

Zheng R. Aging Predictive Models and Simulation Methods for Analog and Mixed-Signal Circuits. [Internet] [Masters thesis]. Arizona State University; 2011. [cited 2020 Apr 02]. Available from: http://repository.asu.edu/items/9148.

Council of Science Editors:

Zheng R. Aging Predictive Models and Simulation Methods for Analog and Mixed-Signal Circuits. [Masters Thesis]. Arizona State University; 2011. Available from: http://repository.asu.edu/items/9148


University of New Mexico

8. Mee, Jesse. FUNDAMENTAL ISSUE IN SPACE ELECTRONICS RELIABILITY: NEGATIVE BIAS TEMPERATURE INSTABILITY.

Degree: Electrical and Computer Engineering, 2011, University of New Mexico

 Negative Bias Temperature Instability (NBTI) in silicon based metal-oxide-semiconductor-field-effect-transistors (MOSFETs) has been recognized as a critical reliability issue for advanced space qualified electronics. The phenomenon… (more)

Subjects/Keywords: NBTI; Negative Bias Temperature Instability; Charge Trapping

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APA (6th Edition):

Mee, J. (2011). FUNDAMENTAL ISSUE IN SPACE ELECTRONICS RELIABILITY: NEGATIVE BIAS TEMPERATURE INSTABILITY. (Masters Thesis). University of New Mexico. Retrieved from http://hdl.handle.net/1928/12052

Chicago Manual of Style (16th Edition):

Mee, Jesse. “FUNDAMENTAL ISSUE IN SPACE ELECTRONICS RELIABILITY: NEGATIVE BIAS TEMPERATURE INSTABILITY.” 2011. Masters Thesis, University of New Mexico. Accessed April 02, 2020. http://hdl.handle.net/1928/12052.

MLA Handbook (7th Edition):

Mee, Jesse. “FUNDAMENTAL ISSUE IN SPACE ELECTRONICS RELIABILITY: NEGATIVE BIAS TEMPERATURE INSTABILITY.” 2011. Web. 02 Apr 2020.

Vancouver:

Mee J. FUNDAMENTAL ISSUE IN SPACE ELECTRONICS RELIABILITY: NEGATIVE BIAS TEMPERATURE INSTABILITY. [Internet] [Masters thesis]. University of New Mexico; 2011. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/1928/12052.

Council of Science Editors:

Mee J. FUNDAMENTAL ISSUE IN SPACE ELECTRONICS RELIABILITY: NEGATIVE BIAS TEMPERATURE INSTABILITY. [Masters Thesis]. University of New Mexico; 2011. Available from: http://hdl.handle.net/1928/12052

9. Angot, Damien. Fiabilité et variabilité temporelle des technologies CMOS FDSOI 28-20nm, du transistor au circuit intégré : Reliability and time-dependent variability of FDSOI technologies for the 20-28nm CMOS node from transistor to circuit level.

Degree: Docteur es, Micro et Nanoélectronique, 2014, Aix Marseille Université

La course à la miniaturisation requiert l'introduction d'architectures de transistors innovantes enremplacement des technologies conventionnelles sur substrat de silicium. Ainsi la technologie UTBB-FDSOI permet d'améliorer… (more)

Subjects/Keywords: Utbb-Fdsoi; Variabilité temporelle; Sram; Nbti; Hci; Vmin; Utbb-Fdsoi; Time-Dependent variability; Sram; Nbti; Hci; Vmin

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APA (6th Edition):

Angot, D. (2014). Fiabilité et variabilité temporelle des technologies CMOS FDSOI 28-20nm, du transistor au circuit intégré : Reliability and time-dependent variability of FDSOI technologies for the 20-28nm CMOS node from transistor to circuit level. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2014AIXM4753

Chicago Manual of Style (16th Edition):

Angot, Damien. “Fiabilité et variabilité temporelle des technologies CMOS FDSOI 28-20nm, du transistor au circuit intégré : Reliability and time-dependent variability of FDSOI technologies for the 20-28nm CMOS node from transistor to circuit level.” 2014. Doctoral Dissertation, Aix Marseille Université. Accessed April 02, 2020. http://www.theses.fr/2014AIXM4753.

MLA Handbook (7th Edition):

Angot, Damien. “Fiabilité et variabilité temporelle des technologies CMOS FDSOI 28-20nm, du transistor au circuit intégré : Reliability and time-dependent variability of FDSOI technologies for the 20-28nm CMOS node from transistor to circuit level.” 2014. Web. 02 Apr 2020.

Vancouver:

Angot D. Fiabilité et variabilité temporelle des technologies CMOS FDSOI 28-20nm, du transistor au circuit intégré : Reliability and time-dependent variability of FDSOI technologies for the 20-28nm CMOS node from transistor to circuit level. [Internet] [Doctoral dissertation]. Aix Marseille Université 2014. [cited 2020 Apr 02]. Available from: http://www.theses.fr/2014AIXM4753.

Council of Science Editors:

Angot D. Fiabilité et variabilité temporelle des technologies CMOS FDSOI 28-20nm, du transistor au circuit intégré : Reliability and time-dependent variability of FDSOI technologies for the 20-28nm CMOS node from transistor to circuit level. [Doctoral Dissertation]. Aix Marseille Université 2014. Available from: http://www.theses.fr/2014AIXM4753


Texas A&M University

10. Pappireddy, Madhukarreddy. PRITEXT: Processor Reliability Improvement Through Exercise Technique.

Degree: 2016, Texas A&M University

 With continuous improvements in CMOS technology, transistor sizes are shrinking aggressively every year. Unfortunately, such deep submicron process technologies are severely degraded by several wearout… (more)

Subjects/Keywords: NBTI; processor reliability; PMOS stress; input vector control; ATPG; PRITEXT

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APA (6th Edition):

Pappireddy, M. (2016). PRITEXT: Processor Reliability Improvement Through Exercise Technique. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/157769

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pappireddy, Madhukarreddy. “PRITEXT: Processor Reliability Improvement Through Exercise Technique.” 2016. Thesis, Texas A&M University. Accessed April 02, 2020. http://hdl.handle.net/1969.1/157769.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pappireddy, Madhukarreddy. “PRITEXT: Processor Reliability Improvement Through Exercise Technique.” 2016. Web. 02 Apr 2020.

Vancouver:

Pappireddy M. PRITEXT: Processor Reliability Improvement Through Exercise Technique. [Internet] [Thesis]. Texas A&M University; 2016. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/1969.1/157769.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pappireddy M. PRITEXT: Processor Reliability Improvement Through Exercise Technique. [Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/157769

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Pretoria

11. Maruma, Mpho Given. Effect of composition and thermomechanical processing on the texture evolution, formability and ridging behavior of type AISI 441 ferritic stainless steel.

Degree: Materials Science and Metallurgical Engineering, 2014, University of Pretoria

 Global warming and air pollution are the major problems facing the world today. Therefore strict environmental legislation on the emission of harmful gases from motor… (more)

Subjects/Keywords: Formability; XRD; (NbTi)(C,N); Texture; Cold rolling; Annealing; Ridging; UCTD

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APA (6th Edition):

Maruma, M. G. (2014). Effect of composition and thermomechanical processing on the texture evolution, formability and ridging behavior of type AISI 441 ferritic stainless steel. (Masters Thesis). University of Pretoria. Retrieved from http://hdl.handle.net/2263/40839

Chicago Manual of Style (16th Edition):

Maruma, Mpho Given. “Effect of composition and thermomechanical processing on the texture evolution, formability and ridging behavior of type AISI 441 ferritic stainless steel.” 2014. Masters Thesis, University of Pretoria. Accessed April 02, 2020. http://hdl.handle.net/2263/40839.

MLA Handbook (7th Edition):

Maruma, Mpho Given. “Effect of composition and thermomechanical processing on the texture evolution, formability and ridging behavior of type AISI 441 ferritic stainless steel.” 2014. Web. 02 Apr 2020.

Vancouver:

Maruma MG. Effect of composition and thermomechanical processing on the texture evolution, formability and ridging behavior of type AISI 441 ferritic stainless steel. [Internet] [Masters thesis]. University of Pretoria; 2014. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2263/40839.

Council of Science Editors:

Maruma MG. Effect of composition and thermomechanical processing on the texture evolution, formability and ridging behavior of type AISI 441 ferritic stainless steel. [Masters Thesis]. University of Pretoria; 2014. Available from: http://hdl.handle.net/2263/40839


Penn State University

12. Ricketts, Andrew Jonathan Sylvester. Towards Minimizing the Adverse Effects of.

Degree: PhD, Computer Science and Engineering, 2009, Penn State University

 There are wide power variations across a chip leading to temperature variations. High power density components such as register files and arithmetic logic units will… (more)

Subjects/Keywords: High temperature relaibility; NBTI; temperature induced clock skew

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APA (6th Edition):

Ricketts, A. J. S. (2009). Towards Minimizing the Adverse Effects of. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/10435

Chicago Manual of Style (16th Edition):

Ricketts, Andrew Jonathan Sylvester. “Towards Minimizing the Adverse Effects of.” 2009. Doctoral Dissertation, Penn State University. Accessed April 02, 2020. https://etda.libraries.psu.edu/catalog/10435.

MLA Handbook (7th Edition):

Ricketts, Andrew Jonathan Sylvester. “Towards Minimizing the Adverse Effects of.” 2009. Web. 02 Apr 2020.

Vancouver:

Ricketts AJS. Towards Minimizing the Adverse Effects of. [Internet] [Doctoral dissertation]. Penn State University; 2009. [cited 2020 Apr 02]. Available from: https://etda.libraries.psu.edu/catalog/10435.

Council of Science Editors:

Ricketts AJS. Towards Minimizing the Adverse Effects of. [Doctoral Dissertation]. Penn State University; 2009. Available from: https://etda.libraries.psu.edu/catalog/10435


Penn State University

13. Mangalagiri, Prasanth. A Reliable Design Flow for Platform FPGAs.

Degree: PhD, Computer Science and Engineering, 2010, Penn State University

 Aggressive technology scaling over the years has led to increased levels of integration and heterogeneity in the design fabric of Field Programmable Gate Arrays (FPGAs).… (more)

Subjects/Keywords: FPGA; TDDB; HCI; NBTI; CMOS; Dual Vdd; Thermal Estimation; Electromigration

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APA (6th Edition):

Mangalagiri, P. (2010). A Reliable Design Flow for Platform FPGAs. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/10497

Chicago Manual of Style (16th Edition):

Mangalagiri, Prasanth. “A Reliable Design Flow for Platform FPGAs.” 2010. Doctoral Dissertation, Penn State University. Accessed April 02, 2020. https://etda.libraries.psu.edu/catalog/10497.

MLA Handbook (7th Edition):

Mangalagiri, Prasanth. “A Reliable Design Flow for Platform FPGAs.” 2010. Web. 02 Apr 2020.

Vancouver:

Mangalagiri P. A Reliable Design Flow for Platform FPGAs. [Internet] [Doctoral dissertation]. Penn State University; 2010. [cited 2020 Apr 02]. Available from: https://etda.libraries.psu.edu/catalog/10497.

Council of Science Editors:

Mangalagiri P. A Reliable Design Flow for Platform FPGAs. [Doctoral Dissertation]. Penn State University; 2010. Available from: https://etda.libraries.psu.edu/catalog/10497

14. Dabhoiwala, Mehernosh H. Online Nbti Wear-out Estimation.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

  CMOS feature size scaling has been a source of dramatic performance gains, but it has come at a cost of on-chip wear-out. Negative Bias… (more)

Subjects/Keywords: Online NBTI wear-out estimation; Computer Engineering; Electrical and Computer Engineering

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APA (6th Edition):

Dabhoiwala, M. H. (2013). Online Nbti Wear-out Estimation. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1117

Chicago Manual of Style (16th Edition):

Dabhoiwala, Mehernosh H. “Online Nbti Wear-out Estimation.” 2013. Masters Thesis, University of Massachusetts. Accessed April 02, 2020. https://scholarworks.umass.edu/theses/1117.

MLA Handbook (7th Edition):

Dabhoiwala, Mehernosh H. “Online Nbti Wear-out Estimation.” 2013. Web. 02 Apr 2020.

Vancouver:

Dabhoiwala MH. Online Nbti Wear-out Estimation. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2020 Apr 02]. Available from: https://scholarworks.umass.edu/theses/1117.

Council of Science Editors:

Dabhoiwala MH. Online Nbti Wear-out Estimation. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1117


NSYSU

15. Liu, Hsi-Wen. Electrical Analysis and Reliability in Advanced Metal Oxide Semiconductor Capacitance and Metal Oxide Semiconductor Field Effect Transistors / Fin Field Effect Transistors.

Degree: PhD, Physics, 2018, NSYSU

 Metal-oxide-semiconductor-field-effect transistors (MOSFETs) have the advantages of low manufacturing cost, low power consumption and easy scaling down. They are widely used in the IC industry,… (more)

Subjects/Keywords: supercritical fluid treatment; P/NBTI; reliability; MOSFET; dipole doping; MOSCAP

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APA (6th Edition):

Liu, H. (2018). Electrical Analysis and Reliability in Advanced Metal Oxide Semiconductor Capacitance and Metal Oxide Semiconductor Field Effect Transistors / Fin Field Effect Transistors. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723118-033035

Chicago Manual of Style (16th Edition):

Liu, Hsi-Wen. “Electrical Analysis and Reliability in Advanced Metal Oxide Semiconductor Capacitance and Metal Oxide Semiconductor Field Effect Transistors / Fin Field Effect Transistors.” 2018. Doctoral Dissertation, NSYSU. Accessed April 02, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723118-033035.

MLA Handbook (7th Edition):

Liu, Hsi-Wen. “Electrical Analysis and Reliability in Advanced Metal Oxide Semiconductor Capacitance and Metal Oxide Semiconductor Field Effect Transistors / Fin Field Effect Transistors.” 2018. Web. 02 Apr 2020.

Vancouver:

Liu H. Electrical Analysis and Reliability in Advanced Metal Oxide Semiconductor Capacitance and Metal Oxide Semiconductor Field Effect Transistors / Fin Field Effect Transistors. [Internet] [Doctoral dissertation]. NSYSU; 2018. [cited 2020 Apr 02]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723118-033035.

Council of Science Editors:

Liu H. Electrical Analysis and Reliability in Advanced Metal Oxide Semiconductor Capacitance and Metal Oxide Semiconductor Field Effect Transistors / Fin Field Effect Transistors. [Doctoral Dissertation]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723118-033035


Utah State University

16. Kothawade, Saurahb. Design of Negative Bias Temperature Instability (NBTI) Tolerant Register File.

Degree: MS, Electrical and Computer Engineering, 2012, Utah State University

  Degradation of transistor parameter values due to Negative Bias Temperature Instability (NBTI) has emerged as a major reliability problem in current and future technology… (more)

Subjects/Keywords: negative bias temperature instability; nbti; tolerant; register; Electrical and Computer Engineering

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APA (6th Edition):

Kothawade, S. (2012). Design of Negative Bias Temperature Instability (NBTI) Tolerant Register File. (Masters Thesis). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/1160

Chicago Manual of Style (16th Edition):

Kothawade, Saurahb. “Design of Negative Bias Temperature Instability (NBTI) Tolerant Register File.” 2012. Masters Thesis, Utah State University. Accessed April 02, 2020. https://digitalcommons.usu.edu/etd/1160.

MLA Handbook (7th Edition):

Kothawade, Saurahb. “Design of Negative Bias Temperature Instability (NBTI) Tolerant Register File.” 2012. Web. 02 Apr 2020.

Vancouver:

Kothawade S. Design of Negative Bias Temperature Instability (NBTI) Tolerant Register File. [Internet] [Masters thesis]. Utah State University; 2012. [cited 2020 Apr 02]. Available from: https://digitalcommons.usu.edu/etd/1160.

Council of Science Editors:

Kothawade S. Design of Negative Bias Temperature Instability (NBTI) Tolerant Register File. [Masters Thesis]. Utah State University; 2012. Available from: https://digitalcommons.usu.edu/etd/1160


University of Southern California

17. Abrishami, Hamed. Reliability-aware and low power design techniques.

Degree: PhD, Electrical Engineering, 2011, University of Southern California

 As CMOS transistors are scaled toward ultra deep submicron technologies, circuit reliability will be one of the most important challenges in the following years for… (more)

Subjects/Keywords: reliability; low power; NBTI; SER; subthreshold leakage; statistical

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APA (6th Edition):

Abrishami, H. (2011). Reliability-aware and low power design techniques. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/672333/rec/5521

Chicago Manual of Style (16th Edition):

Abrishami, Hamed. “Reliability-aware and low power design techniques.” 2011. Doctoral Dissertation, University of Southern California. Accessed April 02, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/672333/rec/5521.

MLA Handbook (7th Edition):

Abrishami, Hamed. “Reliability-aware and low power design techniques.” 2011. Web. 02 Apr 2020.

Vancouver:

Abrishami H. Reliability-aware and low power design techniques. [Internet] [Doctoral dissertation]. University of Southern California; 2011. [cited 2020 Apr 02]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/672333/rec/5521.

Council of Science Editors:

Abrishami H. Reliability-aware and low power design techniques. [Doctoral Dissertation]. University of Southern California; 2011. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/672333/rec/5521

18. Naouss, Mohammad. Conception et exploitation d'un banc d'auto-caractérisation pour la prévision de la fiabilité des circuits numériques programmables : Design and operation of an auto-characterization test bench for predicting the reliability of programmable digital circuits.

Degree: Docteur es, Electronique, 2016, Bordeaux

Les circuits logiques programmables (FPGA) bénéficient des technologies les plus avancés de noeuds CMOS, afin de répondre aux demandes croissantes de haute performance et de… (more)

Subjects/Keywords: Fiabilité; NBTI; HCI; CMOS; FPGA; Simulation; Modélisation; VLSI; Transistor; Vieillissement; Caractérisation; Reliability; NBTI; HCI; CMOS; FPGA; Simulation; Modeling; VLSI; Transistor; Aging; Characterization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Naouss, M. (2016). Conception et exploitation d'un banc d'auto-caractérisation pour la prévision de la fiabilité des circuits numériques programmables : Design and operation of an auto-characterization test bench for predicting the reliability of programmable digital circuits. (Doctoral Dissertation). Bordeaux. Retrieved from http://www.theses.fr/2016BORD0159

Chicago Manual of Style (16th Edition):

Naouss, Mohammad. “Conception et exploitation d'un banc d'auto-caractérisation pour la prévision de la fiabilité des circuits numériques programmables : Design and operation of an auto-characterization test bench for predicting the reliability of programmable digital circuits.” 2016. Doctoral Dissertation, Bordeaux. Accessed April 02, 2020. http://www.theses.fr/2016BORD0159.

MLA Handbook (7th Edition):

Naouss, Mohammad. “Conception et exploitation d'un banc d'auto-caractérisation pour la prévision de la fiabilité des circuits numériques programmables : Design and operation of an auto-characterization test bench for predicting the reliability of programmable digital circuits.” 2016. Web. 02 Apr 2020.

Vancouver:

Naouss M. Conception et exploitation d'un banc d'auto-caractérisation pour la prévision de la fiabilité des circuits numériques programmables : Design and operation of an auto-characterization test bench for predicting the reliability of programmable digital circuits. [Internet] [Doctoral dissertation]. Bordeaux; 2016. [cited 2020 Apr 02]. Available from: http://www.theses.fr/2016BORD0159.

Council of Science Editors:

Naouss M. Conception et exploitation d'un banc d'auto-caractérisation pour la prévision de la fiabilité des circuits numériques programmables : Design and operation of an auto-characterization test bench for predicting the reliability of programmable digital circuits. [Doctoral Dissertation]. Bordeaux; 2016. Available from: http://www.theses.fr/2016BORD0159

19. Sivadasan, Ajith. Conception et simulation des circuits numériques en 28nm FDSOI pour la haute fiabilité : Design and Simulation of Digital Circuits in 28nm FDSOI for High Reliability.

Degree: Docteur es, Nano electronique et nano technologies, 2018, Grenoble Alpes

La mise à l'échelle de la technologie CMOS classique augmente les performances des circuits numériques grâce à la possibilité d'incorporation de composants de circuit supplémentaires… (more)

Subjects/Keywords: Fiabilité; Charge de calcul; Modèle de vieillissement; Nbti; Polarisation face arrière; Taux de défaillance; Reliability; Workload; Aging model; Nbti; Body/back biaising; Failure rate; 620

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APA (6th Edition):

Sivadasan, A. (2018). Conception et simulation des circuits numériques en 28nm FDSOI pour la haute fiabilité : Design and Simulation of Digital Circuits in 28nm FDSOI for High Reliability. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2018GREAT118

Chicago Manual of Style (16th Edition):

Sivadasan, Ajith. “Conception et simulation des circuits numériques en 28nm FDSOI pour la haute fiabilité : Design and Simulation of Digital Circuits in 28nm FDSOI for High Reliability.” 2018. Doctoral Dissertation, Grenoble Alpes. Accessed April 02, 2020. http://www.theses.fr/2018GREAT118.

MLA Handbook (7th Edition):

Sivadasan, Ajith. “Conception et simulation des circuits numériques en 28nm FDSOI pour la haute fiabilité : Design and Simulation of Digital Circuits in 28nm FDSOI for High Reliability.” 2018. Web. 02 Apr 2020.

Vancouver:

Sivadasan A. Conception et simulation des circuits numériques en 28nm FDSOI pour la haute fiabilité : Design and Simulation of Digital Circuits in 28nm FDSOI for High Reliability. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2018. [cited 2020 Apr 02]. Available from: http://www.theses.fr/2018GREAT118.

Council of Science Editors:

Sivadasan A. Conception et simulation des circuits numériques en 28nm FDSOI pour la haute fiabilité : Design and Simulation of Digital Circuits in 28nm FDSOI for High Reliability. [Doctoral Dissertation]. Grenoble Alpes; 2018. Available from: http://www.theses.fr/2018GREAT118


Texas A&M University

20. Henrichson, Trenton D. Countering Aging Effects through Field Gate Sizing.

Degree: 2010, Texas A&M University

 Transistor aging through negative bias temperature instability (NBTI) has become a major lifetime constraint in VLSI circuits. We propose a technique that uses antifuses to… (more)

Subjects/Keywords: Transistor Ageing Antifuse NBTI negative bias temperature instability FTS Field Transistor Sizing

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APA (6th Edition):

Henrichson, T. D. (2010). Countering Aging Effects through Field Gate Sizing. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Henrichson, Trenton D. “Countering Aging Effects through Field Gate Sizing.” 2010. Thesis, Texas A&M University. Accessed April 02, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Henrichson, Trenton D. “Countering Aging Effects through Field Gate Sizing.” 2010. Web. 02 Apr 2020.

Vancouver:

Henrichson TD. Countering Aging Effects through Field Gate Sizing. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Henrichson TD. Countering Aging Effects through Field Gate Sizing. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

21. Camargo, Vinícius Valduga de Almeida. Modelagem e simulação de NBTI em circuitos digitais.

Degree: 2012, Universidade do Rio Grande do Sul

A miniaturização dos transistores do tipo MOS traz consigo um aumento na variabilidade de seus parâmetros elétricos, originaria do processo de fabricação e de efeitos… (more)

Subjects/Keywords: Microeletrônica; NBTI; RTS; Circuitos digitais; Modelagem computacional; RTN; Simulação computacional; Circuit simulation; SSTA; Microelectronics

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APA (6th Edition):

Camargo, V. V. d. A. (2012). Modelagem e simulação de NBTI em circuitos digitais. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/131896

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Camargo, Vinícius Valduga de Almeida. “Modelagem e simulação de NBTI em circuitos digitais.” 2012. Thesis, Universidade do Rio Grande do Sul. Accessed April 02, 2020. http://hdl.handle.net/10183/131896.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Camargo, Vinícius Valduga de Almeida. “Modelagem e simulação de NBTI em circuitos digitais.” 2012. Web. 02 Apr 2020.

Vancouver:

Camargo VVdA. Modelagem e simulação de NBTI em circuitos digitais. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2012. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/10183/131896.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Camargo VVdA. Modelagem e simulação de NBTI em circuitos digitais. [Thesis]. Universidade do Rio Grande do Sul; 2012. Available from: http://hdl.handle.net/10183/131896

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

22. Eze, Melvin. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity.

Degree: PhD, Computer Science and Engineering, 2013, Penn State University

 The emergence of System-on-Chip as the dominant chip level architecture in the integrated Circuit industry, has been accompanied by a need to meet the considerable… (more)

Subjects/Keywords: Interconnect; Signal Integrity; Offset Switching; Variable Cycle Timing with Temporal Redundancy; NBTI

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APA (6th Edition):

Eze, M. (2013). Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/19916

Chicago Manual of Style (16th Edition):

Eze, Melvin. “Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity.” 2013. Doctoral Dissertation, Penn State University. Accessed April 02, 2020. https://etda.libraries.psu.edu/catalog/19916.

MLA Handbook (7th Edition):

Eze, Melvin. “Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity.” 2013. Web. 02 Apr 2020.

Vancouver:

Eze M. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity. [Internet] [Doctoral dissertation]. Penn State University; 2013. [cited 2020 Apr 02]. Available from: https://etda.libraries.psu.edu/catalog/19916.

Council of Science Editors:

Eze M. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity. [Doctoral Dissertation]. Penn State University; 2013. Available from: https://etda.libraries.psu.edu/catalog/19916

23. 三宅, 庸資. フィールドテストのための完全デジタル温度電圧モニタに関する研究 : A Fully-Digital Temperature and Voltage Monitor for Field Teat.

Degree: 博士(情報工学), 2017, Kyushu Institute of Technology / 九州工業大学

VLSI の高機能化や高性能化,製造プロセスの微細化など,半導体製造技術の進歩の一方で,物理的な劣化現象が信頼性に影響を及ぼす重大な要因となっている.そのため,劣化による故障を事前に検知し,障害発生による突然のシステムダウンを回避することが重要となる.劣化の進行はシステムの運用状況に依存するため製造テストでの検出は困難であり,劣化により生じる故障に対しては出荷後のフィールドでのテストが有用である.VLSI の劣化現象として回路遅延の増加が知られているが,遅延値は温度や電圧等の環境要因により変動するため,劣化による遅延増加を測定するには,VLSI 動作時の温度と電圧のモニタリングが必要不可欠となる.温度や電圧のオンチップセンサ技術は様々な手法が提案されている.例えば,一般的な温度センサとして実用化されているサーマルダイオード等を利用した温度センサは高い測定精度を実現できるが,アナログ回路を利用しているため,チップ内でのモニタ配置の物理制約が厳しく,チップのホットスポット把握の為に多数箇所へ搭載することが困難である.他にも様々な手法が提案されているが,これらの温度や電圧センサは,システムを長期間稼動させ続けた際に発生する劣化現象への対策が施されていないなど,フィールドテストに用いるセンサとしては不向きである.

本論文では,フィールドにおける高精度なオンチップ温度電圧測定手法を確立させることを目的とし,完全デジタル設計が可能なリングオシレータ(RO: Ring-Oscillator) を核とする温度電圧モニタについて提案する.提案モニタはRO の動作周波数が温度や電圧によって変動する特性を利用する.本論文では,複数種類の特性の異なるRO から構成されるモニタを提案し,各ROの周波数と温度の特性,周波数と電圧の特性に対して,重回帰分析を用いることにより,システム運用時の温度・電圧変動による周波数の変化量からチップ内の温度と電圧が計算可能となることを示す.製造されたVLSI は製造バラツキの影響を受けるため,提案モニタに搭載するRO の動作周波数は製造バラツキの影響を受けて変動し,温度と電圧の測定精度が低下する.製造バラツキの影響により生じる誤差を低減するため,初回測定時における周波数測定値と標準環境での周波数測定値の比率を利用したキャリブレーション手法を提案する.そして,製造バラツキが存在していても,精度良くRO 周波数からチップ内の温度と電圧の測定が可能となることを示す.RO として利用可能な論理回路は様々な種類があり,それらのRO の組合せによって温度と電圧の測定精度が変動する.本論文では,利用可能なRO から温度電圧モニタとして精度の良い3 種類の組合せを選択する手法を提案し,温度と電圧が高精度で測定可能となるROが選択可能なことを示す.提案モニタは完全デジタル設計であるため,標準的なセルライブラリで提供された論理セルだけで構成することができ,設計や製造におけるコストが小さい.また,モニタ自身に対する劣化現象の影響を避けるため,提案モニタを構成するRO は耐NBTI (Negative Bios Temperature Instability) 劣化の構造を実現している.

本論文では,180nm と90nm,45nm のCMOS テクノロジを用いた回路シミュレーションを用いて提案手法の測定精度や有効性の評価を行う.180nm CMOS テクノロジにおいて,0~120℃の温度範囲および1.65~1.95V の電圧範囲で,0.99℃の温度測定精度,4.17mV の電圧測定精度を持ち,温度と電圧を同時に測定可能なデジタルモニタであることを示す.また,回路シミュレーションを用いた評価だけでなく,提案モニタを搭載したチップを設計し,試作を行う.試作チップから得られるRO の温度電圧変化特性を測定し,提案手法を適応することで,チップ内の温度と電圧が測定できることを示す.そして,モニタで測定した温度や電圧の測定結果に対する妥当性の評価を行い,温度電圧モニタとして実現可能であることを示す.提案する温度電圧モニタを用いることで短時間測定可能でかつ小規模なモニタを実現でき,チップの高信頼化のみならず,医療用機器やIoT(Internet of Things)機器の環境モニタ等,様々な応用も期待できる.

九州工業大学博士学位論文 学位記番号:情工博甲第314号 学位授与年月日:平成28年6月30日

第1章 序論|第2章 LSI のテストと信頼性|第3章 リングオシレータを利用した温度電圧測定|第4章 温度電圧モニタ回路|第5章 試作チップによる評価|第6章 結論

平成28年度

Subjects/Keywords: フィールドテスト; デジタル回路; 温度電圧モニタ; リングオシレータ; NBTI劣化

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

三宅, . . (2017). フィールドテストのための完全デジタル温度電圧モニタに関する研究 : A Fully-Digital Temperature and Voltage Monitor for Field Teat. (Thesis). Kyushu Institute of Technology / 九州工業大学. Retrieved from http://hdl.handle.net/10228/00006069

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

三宅, 庸資. “フィールドテストのための完全デジタル温度電圧モニタに関する研究 : A Fully-Digital Temperature and Voltage Monitor for Field Teat.” 2017. Thesis, Kyushu Institute of Technology / 九州工業大学. Accessed April 02, 2020. http://hdl.handle.net/10228/00006069.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

三宅, 庸資. “フィールドテストのための完全デジタル温度電圧モニタに関する研究 : A Fully-Digital Temperature and Voltage Monitor for Field Teat.” 2017. Web. 02 Apr 2020.

Vancouver:

三宅 . フィールドテストのための完全デジタル温度電圧モニタに関する研究 : A Fully-Digital Temperature and Voltage Monitor for Field Teat. [Internet] [Thesis]. Kyushu Institute of Technology / 九州工業大学; 2017. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/10228/00006069.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

三宅 . フィールドテストのための完全デジタル温度電圧モニタに関する研究 : A Fully-Digital Temperature and Voltage Monitor for Field Teat. [Thesis]. Kyushu Institute of Technology / 九州工業大学; 2017. Available from: http://hdl.handle.net/10228/00006069

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Connecticut

24. Kayam, Niranjan R. Experimental Analysis on Aging of Integrated Circuits.

Degree: MS, Electrical Engineering, 2011, University of Connecticut

  As we enter into sub-nanometer technologies in order to increase performance of CMOS devices, reliability issues such as negative bias temperature instability (NBTI), hot… (more)

Subjects/Keywords: NBTI; HCI; Reliability; Stress; Nanometer; Burn-in; frequency; Negative Bias Temperature Instability; Aging

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kayam, N. R. (2011). Experimental Analysis on Aging of Integrated Circuits. (Masters Thesis). University of Connecticut. Retrieved from https://opencommons.uconn.edu/gs_theses/168

Chicago Manual of Style (16th Edition):

Kayam, Niranjan R. “Experimental Analysis on Aging of Integrated Circuits.” 2011. Masters Thesis, University of Connecticut. Accessed April 02, 2020. https://opencommons.uconn.edu/gs_theses/168.

MLA Handbook (7th Edition):

Kayam, Niranjan R. “Experimental Analysis on Aging of Integrated Circuits.” 2011. Web. 02 Apr 2020.

Vancouver:

Kayam NR. Experimental Analysis on Aging of Integrated Circuits. [Internet] [Masters thesis]. University of Connecticut; 2011. [cited 2020 Apr 02]. Available from: https://opencommons.uconn.edu/gs_theses/168.

Council of Science Editors:

Kayam NR. Experimental Analysis on Aging of Integrated Circuits. [Masters Thesis]. University of Connecticut; 2011. Available from: https://opencommons.uconn.edu/gs_theses/168


University of Debrecen

25. Akai, Mercedes Nikoletta. Az irreverzibilis A1 adenozin receptor antagonista FSCPX és a nukleozid transzport gátló NBTI közös hatása tengerimalacpitvaron .

Degree: DE – Általános Orvostudományi Kar, University of Debrecen

 A munkacsoport egy korábbi in silico vizsgálatban lehetséges interakciót fedezett fel az irreverzibilis A1 adenzin receptor antagonista FSCPX és a nukleozid transzport gátló NBTI között.… (more)

Subjects/Keywords: farmakológia; FSCPX; NBTI; A1 adenozin receptor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Akai, M. N. (n.d.). Az irreverzibilis A1 adenozin receptor antagonista FSCPX és a nukleozid transzport gátló NBTI közös hatása tengerimalacpitvaron . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/254772

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Akai, Mercedes Nikoletta. “Az irreverzibilis A1 adenozin receptor antagonista FSCPX és a nukleozid transzport gátló NBTI közös hatása tengerimalacpitvaron .” Thesis, University of Debrecen. Accessed April 02, 2020. http://hdl.handle.net/2437/254772.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Akai, Mercedes Nikoletta. “Az irreverzibilis A1 adenozin receptor antagonista FSCPX és a nukleozid transzport gátló NBTI közös hatása tengerimalacpitvaron .” Web. 02 Apr 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Akai MN. Az irreverzibilis A1 adenozin receptor antagonista FSCPX és a nukleozid transzport gátló NBTI közös hatása tengerimalacpitvaron . [Internet] [Thesis]. University of Debrecen; [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2437/254772.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Akai MN. Az irreverzibilis A1 adenozin receptor antagonista FSCPX és a nukleozid transzport gátló NBTI közös hatása tengerimalacpitvaron . [Thesis]. University of Debrecen; Available from: http://hdl.handle.net/2437/254772

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Utah State University

26. Arunachalam, Srinath. An online wear state monitoring methodology for off-the-shelf embedded processors.

Degree: MS, Electrical and Computer Engineering, 2015, Utah State University

  The continued scaling of transistors has led to an exponential increase in on-chip power density, which has resulted in increasing temperature. In turn, the… (more)

Subjects/Keywords: DVFS; Embedded system; NBTI; Off-the-shelf Reliability; Wear state; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Arunachalam, S. (2015). An online wear state monitoring methodology for off-the-shelf embedded processors. (Masters Thesis). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/4552

Chicago Manual of Style (16th Edition):

Arunachalam, Srinath. “An online wear state monitoring methodology for off-the-shelf embedded processors.” 2015. Masters Thesis, Utah State University. Accessed April 02, 2020. https://digitalcommons.usu.edu/etd/4552.

MLA Handbook (7th Edition):

Arunachalam, Srinath. “An online wear state monitoring methodology for off-the-shelf embedded processors.” 2015. Web. 02 Apr 2020.

Vancouver:

Arunachalam S. An online wear state monitoring methodology for off-the-shelf embedded processors. [Internet] [Masters thesis]. Utah State University; 2015. [cited 2020 Apr 02]. Available from: https://digitalcommons.usu.edu/etd/4552.

Council of Science Editors:

Arunachalam S. An online wear state monitoring methodology for off-the-shelf embedded processors. [Masters Thesis]. Utah State University; 2015. Available from: https://digitalcommons.usu.edu/etd/4552


George Mason University

27. Mishra, Rahul. Study of reliability mechanisms and their interaction in nanoscale CMOSFETs .

Degree: 2008, George Mason University

 This dissertation is a study of device reliability issues and their interactions in nano-scale bulk and SOI CMOSFETs. As integrated circuits (ICs) become smaller and… (more)

Subjects/Keywords: ESD; NBTI; HCI; Interaction; Reliability; MOSFET

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mishra, R. (2008). Study of reliability mechanisms and their interaction in nanoscale CMOSFETs . (Thesis). George Mason University. Retrieved from http://hdl.handle.net/1920/3348

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mishra, Rahul. “Study of reliability mechanisms and their interaction in nanoscale CMOSFETs .” 2008. Thesis, George Mason University. Accessed April 02, 2020. http://hdl.handle.net/1920/3348.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mishra, Rahul. “Study of reliability mechanisms and their interaction in nanoscale CMOSFETs .” 2008. Web. 02 Apr 2020.

Vancouver:

Mishra R. Study of reliability mechanisms and their interaction in nanoscale CMOSFETs . [Internet] [Thesis]. George Mason University; 2008. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/1920/3348.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mishra R. Study of reliability mechanisms and their interaction in nanoscale CMOSFETs . [Thesis]. George Mason University; 2008. Available from: http://hdl.handle.net/1920/3348

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. Schlünder, Christian. Zuverlässigkeit von sub-µm-CMOS-Schaltungen bei Bias-Temperature-Stress (BTS).

Degree: 2006, Technische Universität Dortmund

Subjects/Keywords: Bias Temperature Stress; BTS; Degradation; MOSFET; NBTI; Zuverlässigkeit; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Schlünder, C. (2006). Zuverlässigkeit von sub-µm-CMOS-Schaltungen bei Bias-Temperature-Stress (BTS). (Thesis). Technische Universität Dortmund. Retrieved from http://hdl.handle.net/2003/24191

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Schlünder, Christian. “Zuverlässigkeit von sub-µm-CMOS-Schaltungen bei Bias-Temperature-Stress (BTS).” 2006. Thesis, Technische Universität Dortmund. Accessed April 02, 2020. http://hdl.handle.net/2003/24191.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Schlünder, Christian. “Zuverlässigkeit von sub-µm-CMOS-Schaltungen bei Bias-Temperature-Stress (BTS).” 2006. Web. 02 Apr 2020.

Vancouver:

Schlünder C. Zuverlässigkeit von sub-µm-CMOS-Schaltungen bei Bias-Temperature-Stress (BTS). [Internet] [Thesis]. Technische Universität Dortmund; 2006. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2003/24191.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Schlünder C. Zuverlässigkeit von sub-µm-CMOS-Schaltungen bei Bias-Temperature-Stress (BTS). [Thesis]. Technische Universität Dortmund; 2006. Available from: http://hdl.handle.net/2003/24191

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Matsumoto, Takashi. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響.

Degree: 博士(情報学), 2015, Kyoto University / 京都大学

新制・課程博士

甲第19137号

情博第583号

Subjects/Keywords: CMOS; NBTI; RTN; combinational circuit; gate oxide; reliability; noise

Page 1 Page 2 Page 3 Page 4

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Matsumoto, T. (2015). Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響. (Thesis). Kyoto University / 京都大学. Retrieved from http://hdl.handle.net/2433/199461 ; http://dx.doi.org/10.14989/doctor.k19137

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Matsumoto, Takashi. “Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響.” 2015. Thesis, Kyoto University / 京都大学. Accessed April 02, 2020. http://hdl.handle.net/2433/199461 ; http://dx.doi.org/10.14989/doctor.k19137.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Matsumoto, Takashi. “Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響.” 2015. Web. 02 Apr 2020.

Vancouver:

Matsumoto T. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響. [Internet] [Thesis]. Kyoto University / 京都大学; 2015. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2433/199461 ; http://dx.doi.org/10.14989/doctor.k19137.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Matsumoto T. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響. [Thesis]. Kyoto University / 京都大学; 2015. Available from: http://hdl.handle.net/2433/199461 ; http://dx.doi.org/10.14989/doctor.k19137

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

30. Dal Bem, Vinícius. CMOS digital integrated circuit design faced to NBTI and other nanometric effects.

Degree: 2010, Universidade do Rio Grande do Sul

Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem… (more)

Subjects/Keywords: Microelectronics; Microeletrônica; NBTI; Cmos; CMOS; Nanotechnology; Integrated circuits; Digital design; Logic gate; Aging effects; Reliability; Yield

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dal Bem, V. (2010). CMOS digital integrated circuit design faced to NBTI and other nanometric effects. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/37180

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dal Bem, Vinícius. “CMOS digital integrated circuit design faced to NBTI and other nanometric effects.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed April 02, 2020. http://hdl.handle.net/10183/37180.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dal Bem, Vinícius. “CMOS digital integrated circuit design faced to NBTI and other nanometric effects.” 2010. Web. 02 Apr 2020.

Vancouver:

Dal Bem V. CMOS digital integrated circuit design faced to NBTI and other nanometric effects. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/10183/37180.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dal Bem V. CMOS digital integrated circuit design faced to NBTI and other nanometric effects. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/37180

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2]

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