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You searched for subject:(Multiprocessador em chip). Showing records 1 – 2 of 2 total matches.

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Universidade do Rio Grande do Norte

1. Araújo, Sílvio Roberto Fernandes de. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .

Degree: 2012, Universidade do Rio Grande do Norte

It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it Advisors/Committee Members: Silva, Ivan Saraiva (advisor), CPF:43728090425 (advisor), http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2 (advisor).

Subjects/Keywords: Multiprocessador em chip; MPSoC; Redes em chip; NoC; Algoritmo spiral complement; Sistema IPNoSys; Multiprocessor on chip; MPSoC; Network-on-chip; NoC; Spiral complement algorithm; IPNoSys system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Araújo, S. R. F. d. (2012). Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . (Doctoral Dissertation). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17948

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Doctoral Dissertation, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/17948.

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Web. 31 May 2020.

Vancouver:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Internet] [Doctoral dissertation]. Universidade do Rio Grande do Norte; 2012. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/17948.

Council of Science Editors:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Doctoral Dissertation]. Universidade do Rio Grande do Norte; 2012. Available from: http://repositorio.ufrn.br/handle/123456789/17948


Universidade do Rio Grande do Norte

2. Araújo, Sílvio Roberto Fernandes de. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .

Degree: 2012, Universidade do Rio Grande do Norte

It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it Advisors/Committee Members: Silva, Ivan Saraiva (advisor), CPF:43728090425 (advisor), http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2 (advisor).

Subjects/Keywords: Multiprocessador em chip; MPSoC; Redes em chip; NoC; Algoritmo spiral complement; Sistema IPNoSys; Multiprocessor on chip; MPSoC; Network-on-chip; NoC; Spiral complement algorithm; IPNoSys system

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Araújo, S. R. F. d. (2012). Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/17948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Thesis, Universidade do Rio Grande do Norte. Accessed May 31, 2020. http://repositorio.ufrn.br/handle/123456789/17948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Araújo, Sílvio Roberto Fernandes de. “Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys .” 2012. Web. 31 May 2020.

Vancouver:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2012. [cited 2020 May 31]. Available from: http://repositorio.ufrn.br/handle/123456789/17948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Araújo SRFd. Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys . [Thesis]. Universidade do Rio Grande do Norte; 2012. Available from: http://repositorio.ufrn.br/handle/123456789/17948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.