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You searched for subject:(Multi core systems). Showing records 1 – 30 of 53 total matches.

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University of California – Riverside

1. Benavides, Zachary. Declarative Profiling for Parallel Systems.

Degree: Computer Science, 2018, University of California – Riverside

 The popularity of parallel systems for building high performance software only continues to rise. Programming these systems has always been a challenging task, and ensuring… (more)

Subjects/Keywords: Computer science; distributed systems; multi-core systems; parallelism; profiling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Benavides, Z. (2018). Declarative Profiling for Parallel Systems. (Thesis). University of California – Riverside. Retrieved from http://www.escholarship.org/uc/item/0xc4w974

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Benavides, Zachary. “Declarative Profiling for Parallel Systems.” 2018. Thesis, University of California – Riverside. Accessed February 27, 2021. http://www.escholarship.org/uc/item/0xc4w974.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Benavides, Zachary. “Declarative Profiling for Parallel Systems.” 2018. Web. 27 Feb 2021.

Vancouver:

Benavides Z. Declarative Profiling for Parallel Systems. [Internet] [Thesis]. University of California – Riverside; 2018. [cited 2021 Feb 27]. Available from: http://www.escholarship.org/uc/item/0xc4w974.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Benavides Z. Declarative Profiling for Parallel Systems. [Thesis]. University of California – Riverside; 2018. Available from: http://www.escholarship.org/uc/item/0xc4w974

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

2. Ma, Teng. Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters.

Degree: 2012, University of Tennessee – Knoxville

 Multicore or many-core clusters have become the most prominent form of High Performance Computing (HPC) systems. Hardware complexity and hierarchies not only exist in the… (more)

Subjects/Keywords: MPI; kernel; hierarchical; collective; multi-core; many-core; Computational Engineering; Computer and Systems Architecture

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APA (6th Edition):

Ma, T. (2012). Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/1541

Chicago Manual of Style (16th Edition):

Ma, Teng. “Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters.” 2012. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed February 27, 2021. https://trace.tennessee.edu/utk_graddiss/1541.

MLA Handbook (7th Edition):

Ma, Teng. “Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters.” 2012. Web. 27 Feb 2021.

Vancouver:

Ma T. Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2012. [cited 2021 Feb 27]. Available from: https://trace.tennessee.edu/utk_graddiss/1541.

Council of Science Editors:

Ma T. Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2012. Available from: https://trace.tennessee.edu/utk_graddiss/1541


NSYSU

3. Lei, Kin-fong. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.

Degree: Master, Electrical Engineering, 2010, NSYSU

 In the multi-core systems, the data transfer between cores becomes a major challenge. The on-chip interconnect networks should be low latency, high throughput, scalability, better… (more)

Subjects/Keywords: On-Chip Interconnect Networks; Asynchronous Ring Bus; Multi-Core Systems

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APA (6th Edition):

Lei, K. (2010). Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lei, Kin-fong. “Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.” 2010. Thesis, NSYSU. Accessed February 27, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lei, Kin-fong. “Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.” 2010. Web. 27 Feb 2021.

Vancouver:

Lei K. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Feb 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lei K. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Wong, Chen-Ang. Asynchronous Ring Network Mechanism with A Fair Arbitration Strategy for Network on Chip.

Degree: Master, Electrical Engineering, 2012, NSYSU

 The multi-core systems are usually implemented on homogeneous or heterogeneous cores, in order to design the better NOC (network on chip), it must consider the… (more)

Subjects/Keywords: switch circuit; multi-core systems; arbitration strategy; Arbiter; distributed system

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APA (6th Edition):

Wong, C. (2012). Asynchronous Ring Network Mechanism with A Fair Arbitration Strategy for Network on Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814112-111953

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wong, Chen-Ang. “Asynchronous Ring Network Mechanism with A Fair Arbitration Strategy for Network on Chip.” 2012. Thesis, NSYSU. Accessed February 27, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814112-111953.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wong, Chen-Ang. “Asynchronous Ring Network Mechanism with A Fair Arbitration Strategy for Network on Chip.” 2012. Web. 27 Feb 2021.

Vancouver:

Wong C. Asynchronous Ring Network Mechanism with A Fair Arbitration Strategy for Network on Chip. [Internet] [Thesis]. NSYSU; 2012. [cited 2021 Feb 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814112-111953.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wong C. Asynchronous Ring Network Mechanism with A Fair Arbitration Strategy for Network on Chip. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0814112-111953

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

5. Madineedi, Komala Subhadra. A platform for evaluating embedded multi-core systems.

Degree: 2016, Penn State University

 Multiprocessor system on chip (MPSoC) such as the POWER8 processor is a heterogeneous multi- core architecture. These multi-core architectures contain a host processor and smaller… (more)

Subjects/Keywords: Heterogeneous multi-core systems; Coherent Accelerator Processor Interface (CAPI); OpenRISC cores

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APA (6th Edition):

Madineedi, K. S. (2016). A platform for evaluating embedded multi-core systems. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/tm70mv16z

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Madineedi, Komala Subhadra. “A platform for evaluating embedded multi-core systems.” 2016. Thesis, Penn State University. Accessed February 27, 2021. https://submit-etda.libraries.psu.edu/catalog/tm70mv16z.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Madineedi, Komala Subhadra. “A platform for evaluating embedded multi-core systems.” 2016. Web. 27 Feb 2021.

Vancouver:

Madineedi KS. A platform for evaluating embedded multi-core systems. [Internet] [Thesis]. Penn State University; 2016. [cited 2021 Feb 27]. Available from: https://submit-etda.libraries.psu.edu/catalog/tm70mv16z.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Madineedi KS. A platform for evaluating embedded multi-core systems. [Thesis]. Penn State University; 2016. Available from: https://submit-etda.libraries.psu.edu/catalog/tm70mv16z

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Colorado State University

6. Pimpalkhute, Tejasi. Heterogeneous prioritization for network-on-chip based multi-core systems.

Degree: MS(M.S.), Electrical and Computer Engineering, 2013, Colorado State University

 In chip multi-processor (CMP) systems, communication and memory access both play an important role in influencing the performance achievable by the system. The manner in… (more)

Subjects/Keywords: multi-core systems; off-chip memory; network-on-chip

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APA (6th Edition):

Pimpalkhute, T. (2013). Heterogeneous prioritization for network-on-chip based multi-core systems. (Masters Thesis). Colorado State University. Retrieved from http://hdl.handle.net/10217/81054

Chicago Manual of Style (16th Edition):

Pimpalkhute, Tejasi. “Heterogeneous prioritization for network-on-chip based multi-core systems.” 2013. Masters Thesis, Colorado State University. Accessed February 27, 2021. http://hdl.handle.net/10217/81054.

MLA Handbook (7th Edition):

Pimpalkhute, Tejasi. “Heterogeneous prioritization for network-on-chip based multi-core systems.” 2013. Web. 27 Feb 2021.

Vancouver:

Pimpalkhute T. Heterogeneous prioritization for network-on-chip based multi-core systems. [Internet] [Masters thesis]. Colorado State University; 2013. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/10217/81054.

Council of Science Editors:

Pimpalkhute T. Heterogeneous prioritization for network-on-chip based multi-core systems. [Masters Thesis]. Colorado State University; 2013. Available from: http://hdl.handle.net/10217/81054


Universitat Politècnica de Catalunya

7. Paolieri, Marco. A Multi-core processor for hard real-time systems.

Degree: Departament d'Arquitectura de Computadors, 2011, Universitat Politècnica de Catalunya

 La creciente demanda de nuevas funcionalidades en los sistemas empotrados de tiempo real actuales y futuros en industrias como la automovilística y la de aviación,… (more)

Subjects/Keywords: Real-time; Multi-core; Processor; Embedded systems; Woet; 004

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APA (6th Edition):

Paolieri, M. (2011). A Multi-core processor for hard real-time systems. (Thesis). Universitat Politècnica de Catalunya. Retrieved from http://hdl.handle.net/10803/51578

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Paolieri, Marco. “A Multi-core processor for hard real-time systems.” 2011. Thesis, Universitat Politècnica de Catalunya. Accessed February 27, 2021. http://hdl.handle.net/10803/51578.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Paolieri, Marco. “A Multi-core processor for hard real-time systems.” 2011. Web. 27 Feb 2021.

Vancouver:

Paolieri M. A Multi-core processor for hard real-time systems. [Internet] [Thesis]. Universitat Politècnica de Catalunya; 2011. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/10803/51578.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Paolieri M. A Multi-core processor for hard real-time systems. [Thesis]. Universitat Politècnica de Catalunya; 2011. Available from: http://hdl.handle.net/10803/51578

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

8. Amarnath, R. (author). Techniques for Memory Mapping on Multi-Core Automotive Embedded Systems.

Degree: 2012, Delft University of Technology

The demand to increase performance while conserving power has led to the invention of multi-core systems. The software until now had the convenience of gaining… (more)

Subjects/Keywords: multi-core; NUMA; automotive; memory mapping; algorithms; embedded systems

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APA (6th Edition):

Amarnath, R. (. (2012). Techniques for Memory Mapping on Multi-Core Automotive Embedded Systems. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:7fe80a02-fcf6-4e88-ad99-4dd3cf7ada2d

Chicago Manual of Style (16th Edition):

Amarnath, R (author). “Techniques for Memory Mapping on Multi-Core Automotive Embedded Systems.” 2012. Masters Thesis, Delft University of Technology. Accessed February 27, 2021. http://resolver.tudelft.nl/uuid:7fe80a02-fcf6-4e88-ad99-4dd3cf7ada2d.

MLA Handbook (7th Edition):

Amarnath, R (author). “Techniques for Memory Mapping on Multi-Core Automotive Embedded Systems.” 2012. Web. 27 Feb 2021.

Vancouver:

Amarnath R(. Techniques for Memory Mapping on Multi-Core Automotive Embedded Systems. [Internet] [Masters thesis]. Delft University of Technology; 2012. [cited 2021 Feb 27]. Available from: http://resolver.tudelft.nl/uuid:7fe80a02-fcf6-4e88-ad99-4dd3cf7ada2d.

Council of Science Editors:

Amarnath R(. Techniques for Memory Mapping on Multi-Core Automotive Embedded Systems. [Masters Thesis]. Delft University of Technology; 2012. Available from: http://resolver.tudelft.nl/uuid:7fe80a02-fcf6-4e88-ad99-4dd3cf7ada2d


University of New South Wales

9. Carroll, Aaron. Understanding and reducing smartphone energy consumption.

Degree: Computer Science & Engineering, 2017, University of New South Wales

 Modern smartphones are increasingly performant and feature-rich, but because they are battery powered, remain highly power-constrained. Energy management is the art and science of maximising… (more)

Subjects/Keywords: Operating systems; Power management; Energy management; Multi-core; DVFS

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APA (6th Edition):

Carroll, A. (2017). Understanding and reducing smartphone energy consumption. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/58018 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45287/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Carroll, Aaron. “Understanding and reducing smartphone energy consumption.” 2017. Doctoral Dissertation, University of New South Wales. Accessed February 27, 2021. http://handle.unsw.edu.au/1959.4/58018 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45287/SOURCE02?view=true.

MLA Handbook (7th Edition):

Carroll, Aaron. “Understanding and reducing smartphone energy consumption.” 2017. Web. 27 Feb 2021.

Vancouver:

Carroll A. Understanding and reducing smartphone energy consumption. [Internet] [Doctoral dissertation]. University of New South Wales; 2017. [cited 2021 Feb 27]. Available from: http://handle.unsw.edu.au/1959.4/58018 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45287/SOURCE02?view=true.

Council of Science Editors:

Carroll A. Understanding and reducing smartphone energy consumption. [Doctoral Dissertation]. University of New South Wales; 2017. Available from: http://handle.unsw.edu.au/1959.4/58018 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45287/SOURCE02?view=true


Georgia Tech

10. Xiao, He. A Multi-physics approach to the co-design of 3D multi-core processors.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The three-dimensional integrated circuit (3D IC) is a promising solution for processors in the post-Moore era. The 3D integration stacks multiple dies vertically in a… (more)

Subjects/Keywords: Performance; Energy efficiency; 3D IC; Multi-core systems; Multi-physics analysis; Microarchitecture co-design

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APA (6th Edition):

Xiao, H. (2018). A Multi-physics approach to the co-design of 3D multi-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59810

Chicago Manual of Style (16th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Doctoral Dissertation, Georgia Tech. Accessed February 27, 2021. http://hdl.handle.net/1853/59810.

MLA Handbook (7th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Web. 27 Feb 2021.

Vancouver:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1853/59810.

Council of Science Editors:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59810

11. Iyer, Shankar Vanchesan. REAL-TIME CHALLENGES OF VEHICULAR EMBEDDED SYSTEMS ON MULTI-CORE - A MAPPING STUDY.

Degree: Design and Engineering, 2017, Mälardalen University

  The increasing complexity of vehicular embedded systems has encouraged researchers and practitioners to adopt model-driven engineering in the development of these systems. In particular,… (more)

Subjects/Keywords: vehicular embedded systems; multi-core; real-time challenges; modelling support; Embedded Systems; Inbäddad systemteknik

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APA (6th Edition):

Iyer, S. V. (2017). REAL-TIME CHALLENGES OF VEHICULAR EMBEDDED SYSTEMS ON MULTI-CORE - A MAPPING STUDY. (Thesis). Mälardalen University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-35911

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Iyer, Shankar Vanchesan. “REAL-TIME CHALLENGES OF VEHICULAR EMBEDDED SYSTEMS ON MULTI-CORE - A MAPPING STUDY.” 2017. Thesis, Mälardalen University. Accessed February 27, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-35911.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Iyer, Shankar Vanchesan. “REAL-TIME CHALLENGES OF VEHICULAR EMBEDDED SYSTEMS ON MULTI-CORE - A MAPPING STUDY.” 2017. Web. 27 Feb 2021.

Vancouver:

Iyer SV. REAL-TIME CHALLENGES OF VEHICULAR EMBEDDED SYSTEMS ON MULTI-CORE - A MAPPING STUDY. [Internet] [Thesis]. Mälardalen University; 2017. [cited 2021 Feb 27]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-35911.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Iyer SV. REAL-TIME CHALLENGES OF VEHICULAR EMBEDDED SYSTEMS ON MULTI-CORE - A MAPPING STUDY. [Thesis]. Mälardalen University; 2017. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-35911

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Grosic, Hasan. Optimizing Inter-core Data-propagation Delays in Multi-core Embedded Systems.

Degree: Design and Engineering, 2019, Mälardalen University

  The demand for computing power and performance in real-time embedded systems is continuously increasing since new customer requirements and more advanced features are appearing… (more)

Subjects/Keywords: multi-core; embedded systems; phased execution; bus; offline scheduling; constraint programming; Embedded Systems; Inbäddad systemteknik

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APA (6th Edition):

Grosic, H. (2019). Optimizing Inter-core Data-propagation Delays in Multi-core Embedded Systems. (Thesis). Mälardalen University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-44770

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Grosic, Hasan. “Optimizing Inter-core Data-propagation Delays in Multi-core Embedded Systems.” 2019. Thesis, Mälardalen University. Accessed February 27, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-44770.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Grosic, Hasan. “Optimizing Inter-core Data-propagation Delays in Multi-core Embedded Systems.” 2019. Web. 27 Feb 2021.

Vancouver:

Grosic H. Optimizing Inter-core Data-propagation Delays in Multi-core Embedded Systems. [Internet] [Thesis]. Mälardalen University; 2019. [cited 2021 Feb 27]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-44770.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Grosic H. Optimizing Inter-core Data-propagation Delays in Multi-core Embedded Systems. [Thesis]. Mälardalen University; 2019. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-44770

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Carnegie Mellon University

13. Kim, Hyoseung. Towards Predictable Real-Time Performance on Multi-Core Platforms.

Degree: 2016, Carnegie Mellon University

 Cyber-physical systems (CPS) integrate sensing, computing, communication and actuation capabilities to monitor and control operations in the physical environment. A key requirement of such systems(more)

Subjects/Keywords: Cyber-physical systems; Real-time embedded systems; Safety-critical systems; Multi-core platforms; Operating systems; Virtualization

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APA (6th Edition):

Kim, H. (2016). Towards Predictable Real-Time Performance on Multi-Core Platforms. (Thesis). Carnegie Mellon University. Retrieved from http://repository.cmu.edu/dissertations/836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Hyoseung. “Towards Predictable Real-Time Performance on Multi-Core Platforms.” 2016. Thesis, Carnegie Mellon University. Accessed February 27, 2021. http://repository.cmu.edu/dissertations/836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Hyoseung. “Towards Predictable Real-Time Performance on Multi-Core Platforms.” 2016. Web. 27 Feb 2021.

Vancouver:

Kim H. Towards Predictable Real-Time Performance on Multi-Core Platforms. [Internet] [Thesis]. Carnegie Mellon University; 2016. [cited 2021 Feb 27]. Available from: http://repository.cmu.edu/dissertations/836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim H. Towards Predictable Real-Time Performance on Multi-Core Platforms. [Thesis]. Carnegie Mellon University; 2016. Available from: http://repository.cmu.edu/dissertations/836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Chicago

14. Panerati, Jacopo. Enhancing Self-Adaptive Computing Systems via Artificial Intelligence Techniques and Active Learning.

Degree: 2012, University of Illinois – Chicago

 Autonomic computing (AC) has been proposed as a solution to the increasing complexity of computer systems, threatening to make systems impossible to be managed by… (more)

Subjects/Keywords: multi-core; many-core; artificial intelligence; operating systems; reinforcement learning; active learning; learning; markov decision process; mdp

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APA (6th Edition):

Panerati, J. (2012). Enhancing Self-Adaptive Computing Systems via Artificial Intelligence Techniques and Active Learning. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/9179

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Panerati, Jacopo. “Enhancing Self-Adaptive Computing Systems via Artificial Intelligence Techniques and Active Learning.” 2012. Thesis, University of Illinois – Chicago. Accessed February 27, 2021. http://hdl.handle.net/10027/9179.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Panerati, Jacopo. “Enhancing Self-Adaptive Computing Systems via Artificial Intelligence Techniques and Active Learning.” 2012. Web. 27 Feb 2021.

Vancouver:

Panerati J. Enhancing Self-Adaptive Computing Systems via Artificial Intelligence Techniques and Active Learning. [Internet] [Thesis]. University of Illinois – Chicago; 2012. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/10027/9179.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Panerati J. Enhancing Self-Adaptive Computing Systems via Artificial Intelligence Techniques and Active Learning. [Thesis]. University of Illinois – Chicago; 2012. Available from: http://hdl.handle.net/10027/9179

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

15. Segulja, Cedomir. Roko: Balancing Performance and Usability in Coarse-grain Parallelization.

Degree: 2010, University of Toronto

We present Roko, a system that allows parallelization of sequential C codes with a modest user intervention. The user exposes parallelism at the function level… (more)

Subjects/Keywords: Programming Model; Parallelization; Synchronization; Concurrency Control; Multi-core Systems; FPGA Applications; 0984

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Segulja, C. (2010). Roko: Balancing Performance and Usability in Coarse-grain Parallelization. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/24280

Chicago Manual of Style (16th Edition):

Segulja, Cedomir. “Roko: Balancing Performance and Usability in Coarse-grain Parallelization.” 2010. Masters Thesis, University of Toronto. Accessed February 27, 2021. http://hdl.handle.net/1807/24280.

MLA Handbook (7th Edition):

Segulja, Cedomir. “Roko: Balancing Performance and Usability in Coarse-grain Parallelization.” 2010. Web. 27 Feb 2021.

Vancouver:

Segulja C. Roko: Balancing Performance and Usability in Coarse-grain Parallelization. [Internet] [Masters thesis]. University of Toronto; 2010. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1807/24280.

Council of Science Editors:

Segulja C. Roko: Balancing Performance and Usability in Coarse-grain Parallelization. [Masters Thesis]. University of Toronto; 2010. Available from: http://hdl.handle.net/1807/24280


Delft University of Technology

16. Stokkink, Q.A. (author). Multi-core architecture for anonymous Internet streaming.

Degree: 2017, Delft University of Technology

There are two key components for high throughput distributed anonymizing applications. The first key component is overhead due to message complexity of the utilized algorithms.… (more)

Subjects/Keywords: Multi-core; Distributed Systems; file streaming; peer-to-peer; Tor; multipath; Protocol Buffers; serialization; multiprocessing

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APA (6th Edition):

Stokkink, Q. A. (. (2017). Multi-core architecture for anonymous Internet streaming. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:3c7f869c-44b9-41f7-8deb-36ba284606cd

Chicago Manual of Style (16th Edition):

Stokkink, Q A (author). “Multi-core architecture for anonymous Internet streaming.” 2017. Masters Thesis, Delft University of Technology. Accessed February 27, 2021. http://resolver.tudelft.nl/uuid:3c7f869c-44b9-41f7-8deb-36ba284606cd.

MLA Handbook (7th Edition):

Stokkink, Q A (author). “Multi-core architecture for anonymous Internet streaming.” 2017. Web. 27 Feb 2021.

Vancouver:

Stokkink QA(. Multi-core architecture for anonymous Internet streaming. [Internet] [Masters thesis]. Delft University of Technology; 2017. [cited 2021 Feb 27]. Available from: http://resolver.tudelft.nl/uuid:3c7f869c-44b9-41f7-8deb-36ba284606cd.

Council of Science Editors:

Stokkink QA(. Multi-core architecture for anonymous Internet streaming. [Masters Thesis]. Delft University of Technology; 2017. Available from: http://resolver.tudelft.nl/uuid:3c7f869c-44b9-41f7-8deb-36ba284606cd


Delft University of Technology

17. Marcè i Igual, Joan (author). Schedulability analysis of limited-preemptive moldable gang tasks.

Degree: 2020, Delft University of Technology

Gang scheduling, has long been adopted by the high-performance computing community as a way to reduce the synchronization overhead between related threads. Gang schedulling allows… (more)

Subjects/Keywords: real-time systems; schedulability; multi-core; multiprocessor platforms; job-level fixed-priority; moldable gang tasks

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APA (6th Edition):

Marcè i Igual, J. (. (2020). Schedulability analysis of limited-preemptive moldable gang tasks. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:10466647-1259-44f7-bd75-5de19a115a4e

Chicago Manual of Style (16th Edition):

Marcè i Igual, Joan (author). “Schedulability analysis of limited-preemptive moldable gang tasks.” 2020. Masters Thesis, Delft University of Technology. Accessed February 27, 2021. http://resolver.tudelft.nl/uuid:10466647-1259-44f7-bd75-5de19a115a4e.

MLA Handbook (7th Edition):

Marcè i Igual, Joan (author). “Schedulability analysis of limited-preemptive moldable gang tasks.” 2020. Web. 27 Feb 2021.

Vancouver:

Marcè i Igual J(. Schedulability analysis of limited-preemptive moldable gang tasks. [Internet] [Masters thesis]. Delft University of Technology; 2020. [cited 2021 Feb 27]. Available from: http://resolver.tudelft.nl/uuid:10466647-1259-44f7-bd75-5de19a115a4e.

Council of Science Editors:

Marcè i Igual J(. Schedulability analysis of limited-preemptive moldable gang tasks. [Masters Thesis]. Delft University of Technology; 2020. Available from: http://resolver.tudelft.nl/uuid:10466647-1259-44f7-bd75-5de19a115a4e


University of Illinois – Urbana-Champaign

18. Venkat, Suraj. Development and evaluation of graphical user interface and benchmark creation for cache management on multi-core systems.

Degree: MS, Computer Science, 2017, University of Illinois – Urbana-Champaign

 There is a constant need to improve processor performance on any system. It is vital to be able to visualize performance owing to a caching… (more)

Subjects/Keywords: Graphical user interface; Embedded systems; Real-time systems; Cache management; Multi-core systems; Human-computer interaction; User experience

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APA (6th Edition):

Venkat, S. (2017). Development and evaluation of graphical user interface and benchmark creation for cache management on multi-core systems. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98294

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Venkat, Suraj. “Development and evaluation of graphical user interface and benchmark creation for cache management on multi-core systems.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed February 27, 2021. http://hdl.handle.net/2142/98294.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Venkat, Suraj. “Development and evaluation of graphical user interface and benchmark creation for cache management on multi-core systems.” 2017. Web. 27 Feb 2021.

Vancouver:

Venkat S. Development and evaluation of graphical user interface and benchmark creation for cache management on multi-core systems. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/2142/98294.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Venkat S. Development and evaluation of graphical user interface and benchmark creation for cache management on multi-core systems. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98294

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Houston

19. Liu, Fang 1973-. An Energy-Aware Management Technique for Real-Time Multi-Core Systems.

Degree: MS, Computer Science, 2013, University of Houston

 In this work, we propose a new dynamic migration (DM) heuristic method integrating dynamic voltage scaling (DVS), dynamic power management (DPM) and task migration in… (more)

Subjects/Keywords: Real-time systems; Real-time scheduling; Low-power design; Energy-aware scheduling; Energy-aware systems; Multi-core processors; Computer science

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APA (6th Edition):

Liu, F. 1. (2013). An Energy-Aware Management Technique for Real-Time Multi-Core Systems. (Masters Thesis). University of Houston. Retrieved from http://hdl.handle.net/10657/516

Chicago Manual of Style (16th Edition):

Liu, Fang 1973-. “An Energy-Aware Management Technique for Real-Time Multi-Core Systems.” 2013. Masters Thesis, University of Houston. Accessed February 27, 2021. http://hdl.handle.net/10657/516.

MLA Handbook (7th Edition):

Liu, Fang 1973-. “An Energy-Aware Management Technique for Real-Time Multi-Core Systems.” 2013. Web. 27 Feb 2021.

Vancouver:

Liu F1. An Energy-Aware Management Technique for Real-Time Multi-Core Systems. [Internet] [Masters thesis]. University of Houston; 2013. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/10657/516.

Council of Science Editors:

Liu F1. An Energy-Aware Management Technique for Real-Time Multi-Core Systems. [Masters Thesis]. University of Houston; 2013. Available from: http://hdl.handle.net/10657/516


San Jose State University

20. Sae-eung, Suntorn. Analysis of False Cache Line Sharing Effects on Multicore CPUs.

Degree: MS, Computer Science, 2010, San Jose State University

 False sharing (FS) is a well-known problem occurring in multiprocessor systems. It results in performance degradation on multi-threaded programs running on multiprocessor environments. With the… (more)

Subjects/Keywords: false sharing cache multi-core CPUs; Systems Architecture

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APA (6th Edition):

Sae-eung, S. (2010). Analysis of False Cache Line Sharing Effects on Multicore CPUs. (Masters Thesis). San Jose State University. Retrieved from https://doi.org/10.31979/etd.bv2q-hd7t ; https://scholarworks.sjsu.edu/etd_projects/2

Chicago Manual of Style (16th Edition):

Sae-eung, Suntorn. “Analysis of False Cache Line Sharing Effects on Multicore CPUs.” 2010. Masters Thesis, San Jose State University. Accessed February 27, 2021. https://doi.org/10.31979/etd.bv2q-hd7t ; https://scholarworks.sjsu.edu/etd_projects/2.

MLA Handbook (7th Edition):

Sae-eung, Suntorn. “Analysis of False Cache Line Sharing Effects on Multicore CPUs.” 2010. Web. 27 Feb 2021.

Vancouver:

Sae-eung S. Analysis of False Cache Line Sharing Effects on Multicore CPUs. [Internet] [Masters thesis]. San Jose State University; 2010. [cited 2021 Feb 27]. Available from: https://doi.org/10.31979/etd.bv2q-hd7t ; https://scholarworks.sjsu.edu/etd_projects/2.

Council of Science Editors:

Sae-eung S. Analysis of False Cache Line Sharing Effects on Multicore CPUs. [Masters Thesis]. San Jose State University; 2010. Available from: https://doi.org/10.31979/etd.bv2q-hd7t ; https://scholarworks.sjsu.edu/etd_projects/2


McMaster University

21. NADERI, SHAHI SINA. ANALYSIS AND MITIGATION OF THE NONLINEAR IMPAIRMENTS IN FIBER-OPTIC COMMUNICATION SYSTEMS.

Degree: PhD, 2013, McMaster University

  Fiber-optic communication systems have revolutionized the telecommunications industry and have played a major role in the advent of the Information Age. Thousands of kilometers… (more)

Subjects/Keywords: Fiber-optic communication system; Fiber nonlinearity; WDM system; Multi-core fiber; Signal Processing; Systems and Communications; Signal Processing

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APA (6th Edition):

NADERI, S. S. (2013). ANALYSIS AND MITIGATION OF THE NONLINEAR IMPAIRMENTS IN FIBER-OPTIC COMMUNICATION SYSTEMS. (Doctoral Dissertation). McMaster University. Retrieved from http://hdl.handle.net/11375/13497

Chicago Manual of Style (16th Edition):

NADERI, SHAHI SINA. “ANALYSIS AND MITIGATION OF THE NONLINEAR IMPAIRMENTS IN FIBER-OPTIC COMMUNICATION SYSTEMS.” 2013. Doctoral Dissertation, McMaster University. Accessed February 27, 2021. http://hdl.handle.net/11375/13497.

MLA Handbook (7th Edition):

NADERI, SHAHI SINA. “ANALYSIS AND MITIGATION OF THE NONLINEAR IMPAIRMENTS IN FIBER-OPTIC COMMUNICATION SYSTEMS.” 2013. Web. 27 Feb 2021.

Vancouver:

NADERI SS. ANALYSIS AND MITIGATION OF THE NONLINEAR IMPAIRMENTS IN FIBER-OPTIC COMMUNICATION SYSTEMS. [Internet] [Doctoral dissertation]. McMaster University; 2013. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/11375/13497.

Council of Science Editors:

NADERI SS. ANALYSIS AND MITIGATION OF THE NONLINEAR IMPAIRMENTS IN FIBER-OPTIC COMMUNICATION SYSTEMS. [Doctoral Dissertation]. McMaster University; 2013. Available from: http://hdl.handle.net/11375/13497


Universitat Politècnica de Catalunya

22. Nemirovsky, Daniel A. Improving heterogeneous system efficiency : architecture, scheduling, and machine learning.

Degree: Departament d'Arquitectura de Computadors, 2017, Universitat Politècnica de Catalunya

 Arquitectos de computadores estan empesando a diseñar systemas heterogeneos como una manera efficiente de usar los incrementos en densidades de transistors para ejecutar una gran… (more)

Subjects/Keywords: Computer architecture; Multi core; Heterogeneous systems; Scheduling; Machine learning; Deep learning; Àrees temàtiques de la UPC::Informàtica; 004

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APA (6th Edition):

Nemirovsky, D. A. (2017). Improving heterogeneous system efficiency : architecture, scheduling, and machine learning. (Thesis). Universitat Politècnica de Catalunya. Retrieved from http://hdl.handle.net/10803/461499

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nemirovsky, Daniel A. “Improving heterogeneous system efficiency : architecture, scheduling, and machine learning.” 2017. Thesis, Universitat Politècnica de Catalunya. Accessed February 27, 2021. http://hdl.handle.net/10803/461499.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nemirovsky, Daniel A. “Improving heterogeneous system efficiency : architecture, scheduling, and machine learning.” 2017. Web. 27 Feb 2021.

Vancouver:

Nemirovsky DA. Improving heterogeneous system efficiency : architecture, scheduling, and machine learning. [Internet] [Thesis]. Universitat Politècnica de Catalunya; 2017. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/10803/461499.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nemirovsky DA. Improving heterogeneous system efficiency : architecture, scheduling, and machine learning. [Thesis]. Universitat Politècnica de Catalunya; 2017. Available from: http://hdl.handle.net/10803/461499

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

23. Tang, Yuzhe. Secure and high-performance big-data systems in the cloud.

Degree: PhD, Computer Science, 2014, Georgia Tech

 Cloud computing and big data technology continue to revolutionize how computing and data analysis are delivered today and in the future. To store and process… (more)

Subjects/Keywords: Cloud; Big-data; Security; Efficiency; Performance; Streaming; Multi-core; Index; Key-value stores; Privacy preserving; Performance optimization; Log-structured systems

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APA (6th Edition):

Tang, Y. (2014). Secure and high-performance big-data systems in the cloud. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53995

Chicago Manual of Style (16th Edition):

Tang, Yuzhe. “Secure and high-performance big-data systems in the cloud.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 27, 2021. http://hdl.handle.net/1853/53995.

MLA Handbook (7th Edition):

Tang, Yuzhe. “Secure and high-performance big-data systems in the cloud.” 2014. Web. 27 Feb 2021.

Vancouver:

Tang Y. Secure and high-performance big-data systems in the cloud. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1853/53995.

Council of Science Editors:

Tang Y. Secure and high-performance big-data systems in the cloud. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53995


The Ohio State University

24. Hashmi, Jahanzeb Maqbool. Designing High Performance Shared-Address-Space and Adaptive Communication Middlewares for Next-Generation HPC Systems.

Degree: PhD, Computer Science and Engineering, 2020, The Ohio State University

 Modern High-Performance Computing (HPC) systems are enabling scientists from differentresearch domains such as astrophysics, climate simulations, computational fluid dynamics,drugs discovery, and others, to model and… (more)

Subjects/Keywords: Computer Science; Communication Middlewares, Optimized Design, Process Mapping, HPC, Multi-core, Many-core, Parallel Computing, High-End Systems, Cloud Computing, Zero-copy Communication, Shared Address Space Communication, Emerging Architectures, MPI

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APA (6th Edition):

Hashmi, J. M. (2020). Designing High Performance Shared-Address-Space and Adaptive Communication Middlewares for Next-Generation HPC Systems. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1588038721555713

Chicago Manual of Style (16th Edition):

Hashmi, Jahanzeb Maqbool. “Designing High Performance Shared-Address-Space and Adaptive Communication Middlewares for Next-Generation HPC Systems.” 2020. Doctoral Dissertation, The Ohio State University. Accessed February 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1588038721555713.

MLA Handbook (7th Edition):

Hashmi, Jahanzeb Maqbool. “Designing High Performance Shared-Address-Space and Adaptive Communication Middlewares for Next-Generation HPC Systems.” 2020. Web. 27 Feb 2021.

Vancouver:

Hashmi JM. Designing High Performance Shared-Address-Space and Adaptive Communication Middlewares for Next-Generation HPC Systems. [Internet] [Doctoral dissertation]. The Ohio State University; 2020. [cited 2021 Feb 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1588038721555713.

Council of Science Editors:

Hashmi JM. Designing High Performance Shared-Address-Space and Adaptive Communication Middlewares for Next-Generation HPC Systems. [Doctoral Dissertation]. The Ohio State University; 2020. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1588038721555713

25. Lacoste, Xavier. Scheduling and memory optimizations for sparse direct solver on multi-core/multi-gpu duster systems : Ordonnancement et optimisations mémoire pour un solveur creux par méthodes directes sur des machines hétérogènes.

Degree: Docteur es, Informatique, 2015, Bordeaux

L’évolution courante des machines montre une croissance importante dans le nombre et l’hétérogénéité des unités de calcul. Les développeurs doivent alors trouver des alternatives aux… (more)

Subjects/Keywords: Résolution de systèmes linéaires creux; GPU; Multi-coeur; MPI,; Ordonnanceur à base de tâches; Sparse direct solver; GPU; Multi-core; MPI; Tasks based runtime systems

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APA (6th Edition):

Lacoste, X. (2015). Scheduling and memory optimizations for sparse direct solver on multi-core/multi-gpu duster systems : Ordonnancement et optimisations mémoire pour un solveur creux par méthodes directes sur des machines hétérogènes. (Doctoral Dissertation). Bordeaux. Retrieved from http://www.theses.fr/2015BORD0016

Chicago Manual of Style (16th Edition):

Lacoste, Xavier. “Scheduling and memory optimizations for sparse direct solver on multi-core/multi-gpu duster systems : Ordonnancement et optimisations mémoire pour un solveur creux par méthodes directes sur des machines hétérogènes.” 2015. Doctoral Dissertation, Bordeaux. Accessed February 27, 2021. http://www.theses.fr/2015BORD0016.

MLA Handbook (7th Edition):

Lacoste, Xavier. “Scheduling and memory optimizations for sparse direct solver on multi-core/multi-gpu duster systems : Ordonnancement et optimisations mémoire pour un solveur creux par méthodes directes sur des machines hétérogènes.” 2015. Web. 27 Feb 2021.

Vancouver:

Lacoste X. Scheduling and memory optimizations for sparse direct solver on multi-core/multi-gpu duster systems : Ordonnancement et optimisations mémoire pour un solveur creux par méthodes directes sur des machines hétérogènes. [Internet] [Doctoral dissertation]. Bordeaux; 2015. [cited 2021 Feb 27]. Available from: http://www.theses.fr/2015BORD0016.

Council of Science Editors:

Lacoste X. Scheduling and memory optimizations for sparse direct solver on multi-core/multi-gpu duster systems : Ordonnancement et optimisations mémoire pour un solveur creux par méthodes directes sur des machines hétérogènes. [Doctoral Dissertation]. Bordeaux; 2015. Available from: http://www.theses.fr/2015BORD0016

26. Medina, Roberto. Deployment of mixed criticality and data driven systems on multi-cores architectures : Déploiement de systèmes à flots de données en criticité mixte pour architectures multi-coeurs.

Degree: Docteur es, Informatique, 2019, Université Paris-Saclay (ComUE)

 De nos jours, la conception de systèmes critiques va de plus en plus vers l’intégration de différents composants système sur une unique plate-forme de calcul.… (more)

Subjects/Keywords: Analyse de flots de données; Théorie de l'ordonnancement; Systèmes temps réel; Architecture multi-coeurs; Data flow analysis; Scheduling theory; Real-time Systems; Multi-core architecture

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APA (6th Edition):

Medina, R. (2019). Deployment of mixed criticality and data driven systems on multi-cores architectures : Déploiement de systèmes à flots de données en criticité mixte pour architectures multi-coeurs. (Doctoral Dissertation). Université Paris-Saclay (ComUE). Retrieved from http://www.theses.fr/2019SACLT004

Chicago Manual of Style (16th Edition):

Medina, Roberto. “Deployment of mixed criticality and data driven systems on multi-cores architectures : Déploiement de systèmes à flots de données en criticité mixte pour architectures multi-coeurs.” 2019. Doctoral Dissertation, Université Paris-Saclay (ComUE). Accessed February 27, 2021. http://www.theses.fr/2019SACLT004.

MLA Handbook (7th Edition):

Medina, Roberto. “Deployment of mixed criticality and data driven systems on multi-cores architectures : Déploiement de systèmes à flots de données en criticité mixte pour architectures multi-coeurs.” 2019. Web. 27 Feb 2021.

Vancouver:

Medina R. Deployment of mixed criticality and data driven systems on multi-cores architectures : Déploiement de systèmes à flots de données en criticité mixte pour architectures multi-coeurs. [Internet] [Doctoral dissertation]. Université Paris-Saclay (ComUE); 2019. [cited 2021 Feb 27]. Available from: http://www.theses.fr/2019SACLT004.

Council of Science Editors:

Medina R. Deployment of mixed criticality and data driven systems on multi-cores architectures : Déploiement de systèmes à flots de données en criticité mixte pour architectures multi-coeurs. [Doctoral Dissertation]. Université Paris-Saclay (ComUE); 2019. Available from: http://www.theses.fr/2019SACLT004

27. Mancuso, Renato. Next-generation safety-critical systems on multi-core platforms.

Degree: PhD, Computer Science, 2017, University of Illinois – Urbana-Champaign

Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. In fact, multi-core platforms can deliver large computational power together… (more)

Subjects/Keywords: Real-time systems; Multi-core systems; Commercial-off-the-shelf (COTS); Single-core equivalence; Single-core equivalent; Hardware resource management; Operating system (OS); Real-time operating system (RTOS); Worst case execution time (WCET); Scheduling; Schedulability analysis; Multi-core real-time operating system (RTOS); Profiling; Avionics; Safety-critical; Cyber-physical systems (CPS); Memguard; Colored lockdown; Palloc; Kernel verification; Scratchpad-centric operating system (OS); Scratchpad memories operating system (SPM-OS); Scratchpad scheduling; Direct memory access (DMA) scheduling; Flow-shop task; Flow-shop scheduling; Hardware scheduler; Field-programmable gate array (FPGA) scheduler; Real-time Linux; Automotive; Smart manufacturing; Real-time networking; Embedded systems; Multi-core avionics; Multi-core automotive; Self-driving cars; Multi-core safety-critical; Many-core; Reconfigurable computing; Internet of things; Real-time cloud computing; Provably safe cyber-physical systems (CPS); Multi-core scheduling; Performance isolation; Real-time resource management; Real-time cache; Real-time dynamic random access memory (DRAM); P4080; MPC5777M; Inter-core interference; Interference channels; CAST32; CAST32A; Federal Aviation Administration (FAA); Minimal multicore avionics certification guidance; Multi-core automotive open system architecture (AUTOSAR); DO-178C; DO-178B; Resource partitioning; Multi-core resource partitioning; Predictable execution model (PREM); Multi-core predictable execution model (PREM)

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APA (6th Edition):

Mancuso, R. (2017). Next-generation safety-critical systems on multi-core platforms. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97399

Chicago Manual of Style (16th Edition):

Mancuso, Renato. “Next-generation safety-critical systems on multi-core platforms.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 27, 2021. http://hdl.handle.net/2142/97399.

MLA Handbook (7th Edition):

Mancuso, Renato. “Next-generation safety-critical systems on multi-core platforms.” 2017. Web. 27 Feb 2021.

Vancouver:

Mancuso R. Next-generation safety-critical systems on multi-core platforms. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/2142/97399.

Council of Science Editors:

Mancuso R. Next-generation safety-critical systems on multi-core platforms. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97399


University of Toronto

28. Capalija, Davor. Microarchitecture and FPGA Implementation of the Multi-level Computing Architecture.

Degree: 2008, University of Toronto

We design the microarchitecture of the Multi-Level Computing Architecture (MLCA), focusing on its Control Processor (CP). The design of the microarchitecture of the CP faces… (more)

Subjects/Keywords: Computer architecture; FPGA applications; Microarchitecture; Parallelism; Embedded systems; Multi-core systems; 0984

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APA (6th Edition):

Capalija, D. (2008). Microarchitecture and FPGA Implementation of the Multi-level Computing Architecture. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/11134

Chicago Manual of Style (16th Edition):

Capalija, Davor. “Microarchitecture and FPGA Implementation of the Multi-level Computing Architecture.” 2008. Masters Thesis, University of Toronto. Accessed February 27, 2021. http://hdl.handle.net/1807/11134.

MLA Handbook (7th Edition):

Capalija, Davor. “Microarchitecture and FPGA Implementation of the Multi-level Computing Architecture.” 2008. Web. 27 Feb 2021.

Vancouver:

Capalija D. Microarchitecture and FPGA Implementation of the Multi-level Computing Architecture. [Internet] [Masters thesis]. University of Toronto; 2008. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1807/11134.

Council of Science Editors:

Capalija D. Microarchitecture and FPGA Implementation of the Multi-level Computing Architecture. [Masters Thesis]. University of Toronto; 2008. Available from: http://hdl.handle.net/1807/11134


Delft University of Technology

29. Sabeghi, M. Runtime Support for Heterogeneous Multi-core Systems.

Degree: 2011, Delft University of Technology

Multi-core processing platforms are one of the major steps forward in offering high-performance computing platforms. The idea is to increase the performance by employing more… (more)

Subjects/Keywords: heterogeneous multi-core systems; runtime support; virtualization; reconfigurable systems; scheduling; profiling

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APA (6th Edition):

Sabeghi, M. (2011). Runtime Support for Heterogeneous Multi-core Systems. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:e1391687-ab07-4f62-bc1a-3343dc577f23 ; urn:NBN:nl:ui:24-uuid:e1391687-ab07-4f62-bc1a-3343dc577f23 ; urn:NBN:nl:ui:24-uuid:e1391687-ab07-4f62-bc1a-3343dc577f23 ; http://resolver.tudelft.nl/uuid:e1391687-ab07-4f62-bc1a-3343dc577f23

Chicago Manual of Style (16th Edition):

Sabeghi, M. “Runtime Support for Heterogeneous Multi-core Systems.” 2011. Doctoral Dissertation, Delft University of Technology. Accessed February 27, 2021. http://resolver.tudelft.nl/uuid:e1391687-ab07-4f62-bc1a-3343dc577f23 ; urn:NBN:nl:ui:24-uuid:e1391687-ab07-4f62-bc1a-3343dc577f23 ; urn:NBN:nl:ui:24-uuid:e1391687-ab07-4f62-bc1a-3343dc577f23 ; http://resolver.tudelft.nl/uuid:e1391687-ab07-4f62-bc1a-3343dc577f23.

MLA Handbook (7th Edition):

Sabeghi, M. “Runtime Support for Heterogeneous Multi-core Systems.” 2011. Web. 27 Feb 2021.

Vancouver:

Sabeghi M. Runtime Support for Heterogeneous Multi-core Systems. [Internet] [Doctoral dissertation]. Delft University of Technology; 2011. [cited 2021 Feb 27]. Available from: http://resolver.tudelft.nl/uuid:e1391687-ab07-4f62-bc1a-3343dc577f23 ; urn:NBN:nl:ui:24-uuid:e1391687-ab07-4f62-bc1a-3343dc577f23 ; urn:NBN:nl:ui:24-uuid:e1391687-ab07-4f62-bc1a-3343dc577f23 ; http://resolver.tudelft.nl/uuid:e1391687-ab07-4f62-bc1a-3343dc577f23.

Council of Science Editors:

Sabeghi M. Runtime Support for Heterogeneous Multi-core Systems. [Doctoral Dissertation]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:e1391687-ab07-4f62-bc1a-3343dc577f23 ; urn:NBN:nl:ui:24-uuid:e1391687-ab07-4f62-bc1a-3343dc577f23 ; urn:NBN:nl:ui:24-uuid:e1391687-ab07-4f62-bc1a-3343dc577f23 ; http://resolver.tudelft.nl/uuid:e1391687-ab07-4f62-bc1a-3343dc577f23


Indian Institute of Science

30. Nagendra Gulur, Dwarakanath. Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements.

Degree: PhD, Engineering, 2018, Indian Institute of Science

 Memory system design is increasingly influencing modern multi-core architectures from both performance and power perspectives. Both main memory latency and bandwidth have im-proved at a… (more)

Subjects/Keywords: Multi Core Architecture; ANATOMY-Cache; DRAM; Off-chip Memory; Off-chip Bandwidth; On-chip Memory Systems; Multi-Core Memory System; DRAM Cache; Computer System-performance Evaluation; Memory System Design; Computer Science

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APA (6th Edition):

Nagendra Gulur, D. (2018). Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/4007

Chicago Manual of Style (16th Edition):

Nagendra Gulur, Dwarakanath. “Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements.” 2018. Doctoral Dissertation, Indian Institute of Science. Accessed February 27, 2021. http://etd.iisc.ac.in/handle/2005/4007.

MLA Handbook (7th Edition):

Nagendra Gulur, Dwarakanath. “Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements.” 2018. Web. 27 Feb 2021.

Vancouver:

Nagendra Gulur D. Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2018. [cited 2021 Feb 27]. Available from: http://etd.iisc.ac.in/handle/2005/4007.

Council of Science Editors:

Nagendra Gulur D. Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements. [Doctoral Dissertation]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/4007

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