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Northeastern University

1.
Qi, He.
A high-speed low-power *modulo* 2^n+1 *multiplier* design using carbon-nanotube technology.

Degree: MS, Department of Electrical and Computer Engineering, 2011, Northeastern University

URL: http://hdl.handle.net/2047/d20002537

Modulo 2n+1 multiplier is one of the critical components in the area of digital signal processing, residue arithmetic, and data encryption that demand high-speed and low-power operation. In this thesis, a new circuit implementation of a high-speed low-power modulo 2n+1 multiplier is proposed. It has three major stages: partial product generation stage, partial product reduction stage, and the final adder stage. The major technical contribition to the arts of the thesis is that the partial product reduction stage introduces a new MUX-based compressor to reduce power and increase speed. Secondly, in the final adder stage, the sparse-tree based inverted end-around-carry adder reduces the number of critical path circuit blocks. Finally, a proposed adder is implemented using both 32nm CNTFET (Carbon-Nanotube FET) and bulk CMOS technology for comparison. The CNTFET-based design dramatically decreases the PDP (Power Delay Product) of the circuit. The simulation results demonstrate that the MUX-based compressor reduces the PDP of the partial product reduction stage by 4.24 times compare to the traditional full adder based design. The sparse-architecture solves the wire interconnection problem while slightly reduces the PDP of the final adder stage compare to the Kogge-Stone design. The power consumption of CNTFET-based multiplier is on average of 5.72 times less than its conventional bulk CMOS counterpart, while the PDP of CNTFET is 94 times less than the CMOS one. The proposed multilier circuit and its implementation demonstrates the viability of the ultra-low-power and high performance feature of the promising CNTFET technology.

Subjects/Keywords: electrical engineering; carbon-nanotube technology; modulo 2^n+1 multiplier; MUX-based compressor; sparse-tree adder; Electrical and Computer Engineering; Engineering

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APA (6^{th} Edition):

Qi, H. (2011). A high-speed low-power modulo 2^n+1 multiplier design using carbon-nanotube technology. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20002537

Chicago Manual of Style (16^{th} Edition):

Qi, He. “A high-speed low-power modulo 2^n+1 multiplier design using carbon-nanotube technology.” 2011. Masters Thesis, Northeastern University. Accessed March 04, 2021. http://hdl.handle.net/2047/d20002537.

MLA Handbook (7^{th} Edition):

Qi, He. “A high-speed low-power modulo 2^n+1 multiplier design using carbon-nanotube technology.” 2011. Web. 04 Mar 2021.

Vancouver:

Qi H. A high-speed low-power modulo 2^n+1 multiplier design using carbon-nanotube technology. [Internet] [Masters thesis]. Northeastern University; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2047/d20002537.

Council of Science Editors:

Qi H. A high-speed low-power modulo 2^n+1 multiplier design using carbon-nanotube technology. [Masters Thesis]. Northeastern University; 2011. Available from: http://hdl.handle.net/2047/d20002537

University of Canterbury

2. Al-Hasani, Firas Ali Jawad. Multiple Constant Multiplication Optimization Using Common Subexpression Elimination and Redundant Numbers.

Degree: PhD, Electrical Engineering, 2014, University of Canterbury

URL: http://dx.doi.org/10.26021/3459

The multiple constant multiplication (MCM) operation is a fundamental operation in digital signal processing (DSP) and digital image processing (DIP). Examples of the MCM are in finite impulse response (FIR) and infinite impulse response (IIR) filters, matrix multiplication, and transforms.
The aim of this work is minimizing the complexity of the MCM operation using common subexpression elimination (CSE) technique and redundant number representations. The CSE technique searches and eliminates common digit patterns (subexpressions) among MCM coefficients. More common subexpressions can be found by representing the MCM coefficients using redundant number representations.
A CSE algorithm is proposed that works on a type of redundant numbers called the zero-dominant set (ZDS). The ZDS is an extension over the representations of minimum number of non-zero digits called minimum Hamming weight (MHW). Using the ZDS improves CSE algorithms' performance as compared with using the MHW representations. The disadvantage of using the ZDS is it increases the possibility of overlapping patterns (digit collisions). In this case, one or more digits are shared between a number of patterns. Eliminating a pattern results in losing other patterns because of eliminating the common digits. A pattern preservation algorithm (PPA) is developed to resolve the overlapping patterns in the representations.
A tree and graph encoders are proposed to generate a larger space of number representations. The algorithms generate redundant representations of a value for a given digit set, radix, and wordlength. The tree encoder is modified to search for common subexpressions simultaneously with generating of the representation tree. A complexity measure is proposed to compare between the subexpressions at each node. The algorithm terminates generating the rest of the representation tree when it finds subexpressions with maximum sharing. This reduces the search space while minimizes the hardware complexity.
A combinatoric model of the MCM problem is proposed in this work. The model is obtained by enumerating all the possible solutions of the MCM that resemble a graph called the demand graph. Arc routing on this graph gives the solutions of the MCM problem. A similar arc routing is found in the capacitated arc routing such as the winter salting problem. Ant colony optimization (ACO) meta-heuristics is proposed to traverse the demand graph. The ACO is simulated on a PC using Python programming language. This is to verify the model correctness and the work of the ACO. A parallel simulation of the ACO is carried out on a multi-core super computer using C++ boost graph library.

Subjects/Keywords: Common subexpression elimination (CSE); multiple constant multiplication (MCM); multiplier block (MB); multiplierless multiple constant multiplication; adder step; logic depth (LD); logic operator (LO); lower bound and optimality; graph dependent method; radix number system; redundant number representations; pattern preservation algorithm (PPA); zero-dominant set (ZDS); polynomial ring; radix polynomials; complete residue system modulo radix; congruent relation; tree encoder; graph encoder; subexpression tree algorithm (STA); A-operation; combinatorial model of multiple constant multiplication; demand graph; dynamic capacitated arc routing problem; metaheuristics; ant colony optimization (ACO); max-min ant system (MMAS); parallel computing; computer cluster.

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Al-Hasani, F. A. J. (2014). Multiple Constant Multiplication Optimization Using Common Subexpression Elimination and Redundant Numbers. (Doctoral Dissertation). University of Canterbury. Retrieved from http://dx.doi.org/10.26021/3459

Chicago Manual of Style (16^{th} Edition):

Al-Hasani, Firas Ali Jawad. “Multiple Constant Multiplication Optimization Using Common Subexpression Elimination and Redundant Numbers.” 2014. Doctoral Dissertation, University of Canterbury. Accessed March 04, 2021. http://dx.doi.org/10.26021/3459.

MLA Handbook (7^{th} Edition):

Al-Hasani, Firas Ali Jawad. “Multiple Constant Multiplication Optimization Using Common Subexpression Elimination and Redundant Numbers.” 2014. Web. 04 Mar 2021.

Vancouver:

Al-Hasani FAJ. Multiple Constant Multiplication Optimization Using Common Subexpression Elimination and Redundant Numbers. [Internet] [Doctoral dissertation]. University of Canterbury; 2014. [cited 2021 Mar 04]. Available from: http://dx.doi.org/10.26021/3459.

Council of Science Editors:

Al-Hasani FAJ. Multiple Constant Multiplication Optimization Using Common Subexpression Elimination and Redundant Numbers. [Doctoral Dissertation]. University of Canterbury; 2014. Available from: http://dx.doi.org/10.26021/3459

3. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/99294

System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to design complex, custom hardware that is efficient, but also correct and reliable.
High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency optimizations. This dissertation shows that high-level synthesis also has the power to address validation and reliability challenges through three automated solutions targeting three key stages in the hardware design and use cycle: pre-silicon debugging, post-silicon validation, and post-deployment error detection.
Our solution for rapid pre-silicon debugging of accelerator designs is hybrid tracing: comparing a datapath-level trace of hardware execution with a reference software implementation at a fine temporal and spatial granularity to detect logic bugs. An integrated backtrace process delivers source-code meaning to the hardware designer, pinpointing the location of bug activation and providing a strong hint for potential bug fixes. Experimental results show that we are able to detect and aid in localization of logic bugs from both C/C++ specifications as well as the high-level synthesis engine itself.
A variation of this solution tailored for rapid post-silicon validation of accelerator designs is hybrid hashing: inserting signature generation logic in a hardware design to create a heavily compressed signature stream that captures the internal behavior of the design at a fine temporal and spatial granularity for comparison with a reference set of signatures generated by high-level simulation to detect bugs. Using hybrid hashing, we demonstrate an improvement in error detection latency (time elapsed from when a bug is activated to when it manifests as an observable failure) of two orders of magnitude and a threefold improvement in bug coverage compared to traditional post-silicon validation techniques. Hybrid hashing also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. Hybrid hashing incurs less than 10% area overhead for the accelerator it validates with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by hybrid hashing.
Finally, our solution for post-deployment error detection is modulo-3 shadow datapaths: performing lightweight shadow computations in modulo-3 space for each main computation. We leverage the binding and scheduling…
*Advisors/Committee Members: Chen, Deming (advisor), Chen, Deming (Committee Chair), Hwu, Wen-Mei W (committee member), Wong, Martin D F (committee member), Kim, Nam Sung (committee member).*

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…1
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CHAPTER 2 BACKGROUND
2.1 Execution Signatures . .
2.2 *Modulo* Arithmetic… …12
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CHAPTER 3 RELATED WORK . .
3.1 Hybrid Quick Error Detection
3.2 *Modulo* Shadow… …7.2 Results and Analysis . . . . . . . . . . . . .
*MODULO*-3
. . . . . . . . . . 66… …66
. . . . . . . . . . 77
CHAPTER 8 CHEAPER *MODULO* FUNCTIONAL UNITS . . . . . 82
8.1… …*Modulo* Functional Units Architecture . . . . . . . . . . . . . 82
8.2 Quality of Results…

Record Details Similar Records

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16^{th} Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7^{th} Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 04 Mar 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294