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1. To, Van Khanh. 多項式制約のためのSMTとその応用.

Degree: 博士（情報科学）, 2013, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学

URL: http://hdl.handle.net/10119/11445

Supervisor:小川 瑞史

情報科学研究科

博士

Subjects/Keywords: interval arithmetic; affine arithmetic; SAT Modulo Theories - SMT; polynomial constraints; testing; abstract DPLL

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

To, V. K. (2013). 多項式制約のためのSMTとその応用. (Thesis). Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10119/11445

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

To, Van Khanh. “多項式制約のためのSMTとその応用.” 2013. Thesis, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Accessed March 08, 2021. http://hdl.handle.net/10119/11445.

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

To, Van Khanh. “多項式制約のためのSMTとその応用.” 2013. Web. 08 Mar 2021.

Vancouver:

To VK. 多項式制約のためのSMTとその応用. [Internet] [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; 2013. [cited 2021 Mar 08]. Available from: http://hdl.handle.net/10119/11445.

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

To VK. 多項式制約のためのSMTとその応用. [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; 2013. Available from: http://hdl.handle.net/10119/11445

Not specified: Masters Thesis or Doctoral Dissertation

2.
Bax, Joshua.
Disproving in First-Order Logic with Definitions, *Arithmetic* and Finite Domains
.

Degree: 2017, Australian National University

URL: http://hdl.handle.net/1885/138339

► This thesis explores several methods which enable a first-order reasoner to conclude satisfiability of a formula *modulo* an *arithmetic* theory. The most general method requires…
(more)

Subjects/Keywords: Automated Theorem Proving; First-Order Logic,; Automated Deduction; Satisfiability Modulo Theories; Computational Logic; Superposition; Equational Reasoning; Data Structures; Linear Integer Arithmetic; Presburger Arithmetic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Bax, J. (2017). Disproving in First-Order Logic with Definitions, Arithmetic and Finite Domains . (Thesis). Australian National University. Retrieved from http://hdl.handle.net/1885/138339

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Bax, Joshua. “Disproving in First-Order Logic with Definitions, Arithmetic and Finite Domains .” 2017. Thesis, Australian National University. Accessed March 08, 2021. http://hdl.handle.net/1885/138339.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Bax, Joshua. “Disproving in First-Order Logic with Definitions, Arithmetic and Finite Domains .” 2017. Web. 08 Mar 2021.

Vancouver:

Bax J. Disproving in First-Order Logic with Definitions, Arithmetic and Finite Domains . [Internet] [Thesis]. Australian National University; 2017. [cited 2021 Mar 08]. Available from: http://hdl.handle.net/1885/138339.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bax J. Disproving in First-Order Logic with Definitions, Arithmetic and Finite Domains . [Thesis]. Australian National University; 2017. Available from: http://hdl.handle.net/1885/138339

Not specified: Masters Thesis or Doctoral Dissertation

University of Illinois – Urbana-Champaign

3. Lin, Chen-Hsuan. Design automation for circuit reliability and energy efficiency.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/99237

► This dissertation presents approaches to improve circuit reliability and energy efficiency from different angles, such as verification, logic synthesis, and functional unit design. A variety…
(more)

Subjects/Keywords: Electronic design automation; Reliability; Energy efficiency; Data mining; Satisfiability (SAT) solving; Logic restructuring; Assertion; Negative bias temperature instability (NBTI) effect; Modulo arithmetic; Shadow datapath

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Lin, C. (2017). Design automation for circuit reliability and energy efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99237

Chicago Manual of Style (16^{th} Edition):

Lin, Chen-Hsuan. “Design automation for circuit reliability and energy efficiency.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 08, 2021. http://hdl.handle.net/2142/99237.

MLA Handbook (7^{th} Edition):

Lin, Chen-Hsuan. “Design automation for circuit reliability and energy efficiency.” 2017. Web. 08 Mar 2021.

Vancouver:

Lin C. Design automation for circuit reliability and energy efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 08]. Available from: http://hdl.handle.net/2142/99237.

Council of Science Editors:

Lin C. Design automation for circuit reliability and energy efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99237

McMaster University

4. Lao, Alex. Methodologies for FPGA Implementation of Finite Control Set Model Predictive Control for Electric Motor Drives.

Degree: MASc, 2019, McMaster University

URL: http://hdl.handle.net/11375/25003

►

Model predictive control is a popular research focus in electric motor control as it allows designers to specify optimization goals and exhibits fast transient response.… (more)

Subjects/Keywords: fpga; field programmable gate array; fcs; finite control set; hdl; hardware description language; rtl; register transfer level; numerical precision; satisfiability modulo theories; mpc; model predictive control; word length optimization; electric drive; electric motor; permanent magnet synchronous motor; interval arithmetic; control system; digital control; inverter; fixed point; real time

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Lao, A. (2019). Methodologies for FPGA Implementation of Finite Control Set Model Predictive Control for Electric Motor Drives. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/25003

Chicago Manual of Style (16^{th} Edition):

Lao, Alex. “Methodologies for FPGA Implementation of Finite Control Set Model Predictive Control for Electric Motor Drives.” 2019. Masters Thesis, McMaster University. Accessed March 08, 2021. http://hdl.handle.net/11375/25003.

MLA Handbook (7^{th} Edition):

Lao, Alex. “Methodologies for FPGA Implementation of Finite Control Set Model Predictive Control for Electric Motor Drives.” 2019. Web. 08 Mar 2021.

Vancouver:

Lao A. Methodologies for FPGA Implementation of Finite Control Set Model Predictive Control for Electric Motor Drives. [Internet] [Masters thesis]. McMaster University; 2019. [cited 2021 Mar 08]. Available from: http://hdl.handle.net/11375/25003.

Council of Science Editors:

Lao A. Methodologies for FPGA Implementation of Finite Control Set Model Predictive Control for Electric Motor Drives. [Masters Thesis]. McMaster University; 2019. Available from: http://hdl.handle.net/11375/25003

5. Iguernelala, Mohamed. Strengthening the heart of an SMT-solver : Design and implementation of efficient decision procedures : Renforcement du noyau d’un démonstrateur SMT : Conception et implantation de procédures de décisions efficaces.

Degree: Docteur es, Informatique, 2013, Université Paris-Sud – Paris XI

URL: http://www.theses.fr/2013PA112080

►

Cette thèse s'intéresse à la démonstration automatique de la validité de formules mathématiques issues de la preuve de programmes. Elle se focalise tout particulièrement sur… (more)

Subjects/Keywords: Satisfiabilité Modulo Théories; Démonstrateurs SMT; Procédures de décision; Combinaison de procédures de décision; Shostak; Associativité et commutativité; Réécriture; Complétion AC; Arithmétique linéaire sur les entiers; Simplexe; Fourier-Motzkin; Satisfiability Modulo Theories; SMT solvers; Decision procedures; Combination of decision procedures; Shostak; Associativity and commutativity; Rewriting; AC-completion; Linear integer arithmetic; Simplex; Fourier-Motzkin

…76] are used to decide quantifier-free formulas *modulo* linear rational
*arithmetic*. The… …works . . . . . . . . . . . . . . . . . . . . . . . . . 74
Ground AC Completion *Modulo* a… …78
4.1.1
4.1.2
Rewriting *modulo* AC . . . . . . . . . . . . . . . . . . . . . . . 79
4.1.3… …Reasoning in presence of non-linear multiplication . . . . . . 115
4.7.3
4.8
Matching *modulo* AC… …138
5.2.4
Inequalities of linear integer *arithmetic* . . . . . . . . . . . . . 140
5.2.5…

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Iguernelala, M. (2013). Strengthening the heart of an SMT-solver : Design and implementation of efficient decision procedures : Renforcement du noyau d’un démonstrateur SMT : Conception et implantation de procédures de décisions efficaces. (Doctoral Dissertation). Université Paris-Sud – Paris XI. Retrieved from http://www.theses.fr/2013PA112080

Chicago Manual of Style (16^{th} Edition):

Iguernelala, Mohamed. “Strengthening the heart of an SMT-solver : Design and implementation of efficient decision procedures : Renforcement du noyau d’un démonstrateur SMT : Conception et implantation de procédures de décisions efficaces.” 2013. Doctoral Dissertation, Université Paris-Sud – Paris XI. Accessed March 08, 2021. http://www.theses.fr/2013PA112080.

MLA Handbook (7^{th} Edition):

Iguernelala, Mohamed. “Strengthening the heart of an SMT-solver : Design and implementation of efficient decision procedures : Renforcement du noyau d’un démonstrateur SMT : Conception et implantation de procédures de décisions efficaces.” 2013. Web. 08 Mar 2021.

Vancouver:

Iguernelala M. Strengthening the heart of an SMT-solver : Design and implementation of efficient decision procedures : Renforcement du noyau d’un démonstrateur SMT : Conception et implantation de procédures de décisions efficaces. [Internet] [Doctoral dissertation]. Université Paris-Sud – Paris XI; 2013. [cited 2021 Mar 08]. Available from: http://www.theses.fr/2013PA112080.

Council of Science Editors:

Iguernelala M. Strengthening the heart of an SMT-solver : Design and implementation of efficient decision procedures : Renforcement du noyau d’un démonstrateur SMT : Conception et implantation de procédures de décisions efficaces. [Doctoral Dissertation]. Université Paris-Sud – Paris XI; 2013. Available from: http://www.theses.fr/2013PA112080

6.
Vissa, Pranay.
Toward high-level synthesis of reliable circuits through low-cost *modulo* shadow datapaths.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/78571

► With transistor dimensions shrinking to the atomic scale, a plethora of new reliability problems presents a barrier to continued Moore’s law scaling. Traditional modular redundancy…
(more)

Subjects/Keywords: high-level synthesis; automation; error detection; scheduling; binding; optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath; shadow logic; low cost; high performance; electrical faults; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback recovery

…it incurs low
area cost. Argus [9] is a prototype processor with a *modulo*-3… …*arithmetic*
checker that can detect up to 98.0% and 98.8% of unmasked transient and
permanent errors… …this study, we take a low-cost approach to the error detection problem through *modulo*-3… …*arithmetic* targeting custom hardware through a fully
automated high-level synthesis process… …coverage handling of mixed *arithmetic* and non-*arithmetic* data
paths
4. High coverage of 99.42% of…

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Vissa, P. (2015). Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78571

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Vissa, Pranay. “Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed March 08, 2021. http://hdl.handle.net/2142/78571.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Vissa, Pranay. “Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.” 2015. Web. 08 Mar 2021.

Vancouver:

Vissa P. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Mar 08]. Available from: http://hdl.handle.net/2142/78571.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vissa P. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78571

Not specified: Masters Thesis or Doctoral Dissertation

7. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/99294

► System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety…
(more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…1
. 3
. 8
. 10
CHAPTER 2 BACKGROUND
2.1 Execution Signatures . .
2.2 *Modulo* *Arithmetic*… …architectural
templates for *modulo* *arithmetic* functional units with the goal of automating
the… …n, even if all Hn = 0.
2.2 *Modulo* *Arithmetic*
*Modulo*-b *arithmetic* is *arithmetic* defined in… …lightweight computations can be performed in *modulo* space
as in integer space, *modulo* *arithmetic* can… …defined a homomorphism from integer *arithmetic* to *modulo* *arithmetic*. In other words, given…

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16^{th} Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 08, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7^{th} Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 08 Mar 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 08]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

8. Campbell, Keith A. Low-cost error detection through high-level synthesis.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/89068

► System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a…
(more)

Subjects/Keywords: High-level synthesis; Automation; error detection; scheduling; binding; compiler transformation; compiler optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath, control logic; shadow logic; low cost; high performance; electrical bugs; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback; recovery; post-silicon validation; Accelerators; system on a chip; signature generation; execution signatures; execution hashing; logic bugs; nondeterministic bugs; masked errors; circuit reliability; hot spots; wear out; silent data corruption; observability; detection latency; mixed datapath; diversity; checkpoint corruption; error injection; error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); hybrid hardware/software; execution tracing; address conversion; undefined behavior; High-Level Synthesis (HLS) engine bugs; detection coverage

…redundant, but smaller “shadow” datapath
based on *modulo* *arithmetic* to detect reliability problems… …observability to detect masked errors is also important.
9
1.4 *Modulo* *Arithmetic*
*Modulo*-b… …*modulo*-b
space as in integer space, *modulo*-b *arithmetic* can be used as a way to
independently… …*arithmetic* to *modulo*-b *arithmetic*. In
other words, given integers {x, y, z} and… …indicates that the *arithmetic* is performed
in *modulo*-b space. Thus for Equations (1.1)…

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Campbell, K. A. (2015). Low-cost error detection through high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89068

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed March 08, 2021. http://hdl.handle.net/2142/89068.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Web. 08 Mar 2021.

Vancouver:

Campbell KA. Low-cost error detection through high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Mar 08]. Available from: http://hdl.handle.net/2142/89068.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Campbell KA. Low-cost error detection through high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89068

Not specified: Masters Thesis or Doctoral Dissertation