subject:(Model checking)

Penn State University

1. Zhang, Can. A model checking approach to countering the dynamics of infection propagation over network.

Degree: 2016, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/28899

► With the outbreak of Ebola over the past year, attention has been paid on predicting and resolving the propagation of infectious disease over network of… (more)

Subjects/Keywords: Model checking

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APA (6^th Edition):

Zhang, C. (2016). A model checking approach to countering the dynamics of infection propagation over network. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/28899

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zhang, Can. “A model checking approach to countering the dynamics of infection propagation over network.” 2016. Thesis, Penn State University. Accessed March 07, 2021. https://submit-etda.libraries.psu.edu/catalog/28899.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zhang, Can. “A model checking approach to countering the dynamics of infection propagation over network.” 2016. Web. 07 Mar 2021.

Vancouver:

Zhang C. A model checking approach to countering the dynamics of infection propagation over network. [Internet] [Thesis]. Penn State University; 2016. [cited 2021 Mar 07]. Available from: https://submit-etda.libraries.psu.edu/catalog/28899.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang C. A model checking approach to countering the dynamics of infection propagation over network. [Thesis]. Penn State University; 2016. Available from: https://submit-etda.libraries.psu.edu/catalog/28899

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Università della Svizzera italiana

2. de Sá Alt, Leonardo. Controlled and effective interpolation.

Degree: 2016, Università della Svizzera italiana

URL: http://doc.rero.ch/record/309121

► Model checking is a well established technique to verify systems, exhaustively and automatically. The state space explosion, known as the main difficulty in model checking… (more)

▼ Model checking is a well established technique to verify systems, exhaustively and automatically. The state space explosion, known as the main difficulty in model checking scalability, has been successfully approached by symbolic model checking which represents programs using logic, usually at the propositional or first order theories level. Craig interpolation is one of the most successful abstraction techniques used in symbolic methods. Interpolants can be efficiently generated from proofs of unsatisfiability, and have been used as means of over-approximation to generate inductive invariants, refinement predicates, and function summaries. However, interpolation is still not fully understood. For several theories it is only possible to generate one interpolant, giving the interpolation-based application no chance of further optimization via interpolation. For the theories that have interpolation systems that are able to generate different interpolants, it is not understood what makes one interpolant better than another, and how to generate the most suitable ones for a particular verification task. The goal of this thesis is to address the problems of how to generate multiple interpolants for theories that still lack this flexibility in their interpolation algorithms, and how to aim at good interpolants. This thesis extends the state-of-the-art by introducing novel interpolation frameworks for different theories. For propositional logic, this work provides a thorough theoretical analysis showing which properties are desirable in a labeling function for the Labeled Interpolation Systems framework (LIS). The Proof-Sensitive labeling function is presented, and we prove that it generates interpolants with the smallest number of Boolean connectives in the entire LIS framework. Two variants that aim at controlling the logical strength of propositional interpolants while maintaining a small size are given. The new interpolation algorithms are compared to previous ones from the literature in different model checking settings, showing that they consistently lead to a better overall verification performance. The Equalities and Uninterpreted Functions (EUF)-interpolation system, presented in this thesis, is a duality-based interpolation framework capable of generating multiple interpolants for a single proof of unsatisfiability, and provides control over the logical strength of the interpolants it generates using labeling functions. The labeling functions can be theoretically compared with respect to their strength, and we prove that two of them generate the interpolants with the smallest number of equalities. Our experiments follow the theory, showing that the generated interpolants indeed have different logical strength. We combine propositional and EUF interpolation in a model checking setting, and show that the strength of the interpolation algorithms for different theories has to be aligned in order to generate smaller interpolants. This work also introduces the Linear Real Arithmetic (LRA)-interpolation system, an… Advisors/Committee Members: Natasha (Dir.).

Subjects/Keywords: Model checking

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APA (6^th Edition):

de Sá Alt, L. (2016). Controlled and effective interpolation. (Thesis). Università della Svizzera italiana. Retrieved from http://doc.rero.ch/record/309121

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

de Sá Alt, Leonardo. “Controlled and effective interpolation.” 2016. Thesis, Università della Svizzera italiana. Accessed March 07, 2021. http://doc.rero.ch/record/309121.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

de Sá Alt, Leonardo. “Controlled and effective interpolation.” 2016. Web. 07 Mar 2021.

Vancouver:

de Sá Alt L. Controlled and effective interpolation. [Internet] [Thesis]. Università della Svizzera italiana; 2016. [cited 2021 Mar 07]. Available from: http://doc.rero.ch/record/309121.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

de Sá Alt L. Controlled and effective interpolation. [Thesis]. Università della Svizzera italiana; 2016. Available from: http://doc.rero.ch/record/309121

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

3. Pellegrino, Giancarlo. Détection d'anomalies logiques dans les logiciels d'entreprise multi-partis à travers des tests de sécurité : Detection of logic flaws in multi-party business applications via security testing.

Degree: Docteur es, Informatique et réseaux, 2013, Paris, ENST

URL: http://www.theses.fr/2013ENST0064

►

Les logiciels multi-partis sont des applications distribuées sur le web qui mettent en oeuvre des fonctions collaboratives. Ces applications sont les principales cibles des attaquants… (more)

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Les logiciels multi-partis sont des applications distribuées sur le web qui mettent en oeuvre des fonctions collaboratives. Ces applications sont les principales cibles des attaquants qui exploitent des vulnérabilités logicielles dans le cadre d'activités malveillantes. Récemment, un type moins connu de vulnérabilité, les anomalies logiques, a attiré l'attention des chercheurs. Sur la base d'informations tirées de la documentation des applications, il est possible d'appliquer deux techniques de test: la vérification du modèle, autrement appelé ``model checking'', et les tests de sécurité de type ``boîte noire''. Le champs d'application du model checking ne prend pas en suffisamment en compte les implémentations actuelles, tandis que les tests de type boîte noire ne sont pas assez sophistiqués pour découvrir les vulnérabilités logique. Dans cette thèse, nous présentons deux techniques d'analyse modernes visant à résoudre les inconvénients de l'état de l'art. Pour commencer, nous présentons la vérification de deux protocoles de sécurité utilisant la technique du model checking. Ensuite, nous nous concentrons sur l'extension du model checking pour soutenir les tests automatisés d'implémentations. La seconde technique consiste en une analyse boîte noire qui combine l'inférence du modèle, l'extraction du processus et du flot de donnée, ainsi qu'une génération de tests basés sur les modèles d'attaque d'une application. En conclusion, nous discutons de l'application de techniques développées au cours de cette thèse sur des applications issues d'un contexte industrielle.

Multi-party business applications are distributed computer programs implementing collaborative business functions. These applications are one of the main target of attackers who exploit vulnerabilities in order to perform malicious activities. The most prevalent classes of vulnerabilities are the consequence of insufficient validation of the user-provided input. However, the less-known class of logic vulnerabilities recently attracted the attention of researcher. According to the availability of software documentation, two testing techniques can be used: design verification via model checking, and black-box security testing. However, the former offers no support to test real implementations and the latter lacks the sophistication to detect logic flaws. In this thesis, we present two novel security testing techniques to detect logic flaws in multi-party business applicatons that tackle the shortcomings of the existing techniques. First, we present the verification via model checking of two security protocols. We then address the challenge of extending the results of the model checker to automatically test protocol implementations. Second, we present a novel black-box security testing technique that combines model inference, extraction of workflow and data flow patterns, and an attack pattern-based test case generation algorithm. Finally, we discuss the application of the technique developed in this thesis in an industrial setting. We used these techniques…

Advisors/Committee Members: Balzarotti, Davide (thesis director).

Subjects/Keywords: Authentification unique; Model checking; SSO; Model checking

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APA (6^th Edition):

Pellegrino, G. (2013). Détection d'anomalies logiques dans les logiciels d'entreprise multi-partis à travers des tests de sécurité : Detection of logic flaws in multi-party business applications via security testing. (Doctoral Dissertation). Paris, ENST. Retrieved from http://www.theses.fr/2013ENST0064

Chicago Manual of Style (16^th Edition):

Pellegrino, Giancarlo. “Détection d'anomalies logiques dans les logiciels d'entreprise multi-partis à travers des tests de sécurité : Detection of logic flaws in multi-party business applications via security testing.” 2013. Doctoral Dissertation, Paris, ENST. Accessed March 07, 2021. http://www.theses.fr/2013ENST0064.

MLA Handbook (7^th Edition):

Pellegrino, Giancarlo. “Détection d'anomalies logiques dans les logiciels d'entreprise multi-partis à travers des tests de sécurité : Detection of logic flaws in multi-party business applications via security testing.” 2013. Web. 07 Mar 2021.

Vancouver:

Pellegrino G. Détection d'anomalies logiques dans les logiciels d'entreprise multi-partis à travers des tests de sécurité : Detection of logic flaws in multi-party business applications via security testing. [Internet] [Doctoral dissertation]. Paris, ENST; 2013. [cited 2021 Mar 07]. Available from: http://www.theses.fr/2013ENST0064.

Council of Science Editors:

Pellegrino G. Détection d'anomalies logiques dans les logiciels d'entreprise multi-partis à travers des tests de sécurité : Detection of logic flaws in multi-party business applications via security testing. [Doctoral Dissertation]. Paris, ENST; 2013. Available from: http://www.theses.fr/2013ENST0064

University of Toronto

4. Berryhill, Ryan. Novel Approaches to Hardware Safety Checking and Certificate Minimization.

Degree: PhD, 2020, University of Toronto

URL: http://hdl.handle.net/1807/103653

► Verification is an ever-growing challenge in hardware design due to the complexity of modern designs. As a result, formal verification methodologies are seeing rapid adoption… (more)

▼ Verification is an ever-growing challenge in hardware design due to the complexity of modern designs. As a result, formal verification methodologies are seeing rapid adoption in the industry. Formal verification of safety properties is an essential verification task and a key component of algorithms that verify other types of properties. Due to the computational resources required, scalability is a significant concern in this area. Additionally, when a safety property passes verification, safety verification algorithms return only a machine-checkable certificate, which may leave the user with little confidence that the property passes for the “right” reasons rather than, for instance, because the property itself is written incorrectly. This dissertation presents contributions aimed at improving the scalability of formal safety verification algorithms and addressing the lack of feedback from such algorithms. The first contribution is an algorithm called Truss that extends the state-of-the-art safety verification algorithm IC3 with novel heuristics and reasoning capabilities to achieve better runtime performance. Experiments demonstrate a significant speedup relative to the state of the art. The second contribution is a set of techniques to minimize machine-checkable certificates of safety produced by IC3 and similar algorithms. Given such a certificate represented by a Boolean formula, the algorithms find minimal subformulas that are also valid certificates, called minimal safe inductive subformulas (MSISes). Experiments are presented comparing the techniques and demonstrating theireffectiveness. The third contribution is a set of techniques to produce and minimize inductive validity cores (IVCs), which are abstractions of the circuit that are sufficient to prove the given property. Several techniques are presented to compute all minimal IVCs for a safety property and are evaluated experimentally. The final contribution is a set of results related to the computational complexity of the certificate minimization problems noted above. Results are presented showing that two decision problems related to MSIS computation are D P -complete and Σ P2 -complete, respectively, while similar problems for MIVC computation are in PSPACE. The results are also extended to cover a more general class of problems related to finding minimal subsets subject to a monotone predicate (MSMPs). Advisors/Committee Members: Veneris, Andreas, Electrical and Computer Engineering.

Subjects/Keywords: Model Checking; Safety Checking; Verification; 0464

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Berryhill, R. (2020). Novel Approaches to Hardware Safety Checking and Certificate Minimization. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/103653

Chicago Manual of Style (16^th Edition):

Berryhill, Ryan. “Novel Approaches to Hardware Safety Checking and Certificate Minimization.” 2020. Doctoral Dissertation, University of Toronto. Accessed March 07, 2021. http://hdl.handle.net/1807/103653.

MLA Handbook (7^th Edition):

Berryhill, Ryan. “Novel Approaches to Hardware Safety Checking and Certificate Minimization.” 2020. Web. 07 Mar 2021.

Vancouver:

Berryhill R. Novel Approaches to Hardware Safety Checking and Certificate Minimization. [Internet] [Doctoral dissertation]. University of Toronto; 2020. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1807/103653.

Council of Science Editors:

Berryhill R. Novel Approaches to Hardware Safety Checking and Certificate Minimization. [Doctoral Dissertation]. University of Toronto; 2020. Available from: http://hdl.handle.net/1807/103653

Brno University of Technology

5. Chalk, Matěj. Nástroj pro abstraktní regulární model checking: Tool for Abstract Regular Model Checking.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/84907

► Formal verification methods offer a large potential to provide automated software correctness checking (based on sound mathematical roots), which is of vital importance. One such… (more)

Subjects/Keywords: formální verifikace; model checking; regulární model checking; abstraktní regulární model checking; automaty; převodníky; symbolické automaty; formal verification; model checking; regular model checking; abstract regular model checking; automata; transducers; symbolic automata

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APA (6^th Edition):

Chalk, M. (2019). Nástroj pro abstraktní regulární model checking: Tool for Abstract Regular Model Checking. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/84907

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chalk, Matěj. “Nástroj pro abstraktní regulární model checking: Tool for Abstract Regular Model Checking.” 2019. Thesis, Brno University of Technology. Accessed March 07, 2021. http://hdl.handle.net/11012/84907.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chalk, Matěj. “Nástroj pro abstraktní regulární model checking: Tool for Abstract Regular Model Checking.” 2019. Web. 07 Mar 2021.

Vancouver:

Chalk M. Nástroj pro abstraktní regulární model checking: Tool for Abstract Regular Model Checking. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/11012/84907.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chalk M. Nástroj pro abstraktní regulární model checking: Tool for Abstract Regular Model Checking. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/84907

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Kang, Eun-Young. Abstractions booléennes pour la vérification des systèmes temps-réel : Tools supported real-time system verification with combination of abstraction/deduction and Model checking.

Degree: Docteur es, Informatique, 2007, Université Henri Poincaré – Nancy I

URL: http://www.theses.fr/2007NAN10089

►

Cette thèse présente un schéma formel et efficace pour la vérification de systèmes temps-réel. Ce schéma repose sur la combinaison par abstraction de techniques déductives… (more)

▼

Cette thèse présente un schéma formel et efficace pour la vérification de systèmes temps-réel. Ce schéma repose sur la combinaison par abstraction de techniques déductives et de model checking, et cette combinaison permet de contourner les limites de chacune de ces techniques. La méthode utilise le raffinement itératif abstrait (IAR) pour le calcul d'abstractions finies. Etant donné un système de transitions et un ensemble fini de prédicats, la méthode détermine une abstraction booléenne dont les états correspondent à des ensembles de prédicats. La correction de l'abstraction par rapport au système d'origine est garantie en établissant un ensemble de conditions de vérification, issues de la procédure IAR. Ces conditions sont à démontrer à l'aide d'un prouveur de théorèmes. Les propriétés de sûreté et de vivacité sont ensuite vérifiées par rapport au modèle abstrait. La procédure IAR termine lorsque toutes les conditions sont vérifiées. Dans le cas contraire, une analyse plus fine détermine si le modèle abstrait doit être affiné en considérant davantage de prédicats. Nous identifions une classe de diagrammes de prédicats appelés PDT (predicate diagram for timed system) qui décrivent l'abstraction et qui peuvent être utilisés pour la vérification de systèmes temporisés et paramétrés.

This thesis provides an efficient formal scheme for the tool-supported real-time system verification by combination of abstraction-based deductive and model checking techniques in order to handle the limitations of the applied verification techniques. This method is based on IAR (Iterative Abstract Refinement) to compute finite state abstractions. Given a transition system and a finite set of predicates, this method determines a finite abstraction, where each state of the abstract state space is a true assignment to the abstraction predicates. A theorem prover can be used to verify that the finite abstract model is a correct abstraction of a given system by checking conformance between an abstract and a concrete model by establishing/proving that a set of verification conditions are obtained during the IAR procedure. Then the safety/liveness properties are checked over the abstract model. If the verification condition holds successfully, IAR terminates its procedure. Otherwise more analysis is applied to identify if the abstract model needs to be more precise by adding extra predicates. As abstraction form, we adopt a class of predicate diagrams and define a variant of predicate diagram PDT (Predicate Diagram for Timed systems) that can be used to verify real-time and parameterized systems.

Advisors/Committee Members: Merz, Stephan (thesis director).

Subjects/Keywords: Model checking

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APA (6^th Edition):

Kang, E. (2007). Abstractions booléennes pour la vérification des systèmes temps-réel : Tools supported real-time system verification with combination of abstraction/deduction and Model checking. (Doctoral Dissertation). Université Henri Poincaré – Nancy I. Retrieved from http://www.theses.fr/2007NAN10089

Chicago Manual of Style (16^th Edition):

Kang, Eun-Young. “Abstractions booléennes pour la vérification des systèmes temps-réel : Tools supported real-time system verification with combination of abstraction/deduction and Model checking.” 2007. Doctoral Dissertation, Université Henri Poincaré – Nancy I. Accessed March 07, 2021. http://www.theses.fr/2007NAN10089.

MLA Handbook (7^th Edition):

Kang, Eun-Young. “Abstractions booléennes pour la vérification des systèmes temps-réel : Tools supported real-time system verification with combination of abstraction/deduction and Model checking.” 2007. Web. 07 Mar 2021.

Vancouver:

Kang E. Abstractions booléennes pour la vérification des systèmes temps-réel : Tools supported real-time system verification with combination of abstraction/deduction and Model checking. [Internet] [Doctoral dissertation]. Université Henri Poincaré – Nancy I; 2007. [cited 2021 Mar 07]. Available from: http://www.theses.fr/2007NAN10089.

Council of Science Editors:

Kang E. Abstractions booléennes pour la vérification des systèmes temps-réel : Tools supported real-time system verification with combination of abstraction/deduction and Model checking. [Doctoral Dissertation]. Université Henri Poincaré – Nancy I; 2007. Available from: http://www.theses.fr/2007NAN10089

University of Limerick

7. Pantelic, Vera. Inspection of concurrent systems: combining tables, theorem proving and model checking.

Degree: 2006, University of Limerick

URL: http://hdl.handle.net/10344/159

►

non-peer-reviewed

A process for rigorous inspection of concurrent systems using tabular specification was developed and applied to the classic Readers/Writers concurrent program by Jin in… (more)

Subjects/Keywords: model checking

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APA (6^th Edition):

Pantelic, V. (2006). Inspection of concurrent systems: combining tables, theorem proving and model checking. (Thesis). University of Limerick. Retrieved from http://hdl.handle.net/10344/159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Pantelic, Vera. “Inspection of concurrent systems: combining tables, theorem proving and model checking.” 2006. Thesis, University of Limerick. Accessed March 07, 2021. http://hdl.handle.net/10344/159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Pantelic, Vera. “Inspection of concurrent systems: combining tables, theorem proving and model checking.” 2006. Web. 07 Mar 2021.

Vancouver:

Pantelic V. Inspection of concurrent systems: combining tables, theorem proving and model checking. [Internet] [Thesis]. University of Limerick; 2006. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10344/159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pantelic V. Inspection of concurrent systems: combining tables, theorem proving and model checking. [Thesis]. University of Limerick; 2006. Available from: http://hdl.handle.net/10344/159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Virginia Tech

8. Adhikari, Kiran. Verifying a Quantitative Relaxation of Linearizability via Refinement.

Degree: MS, Computer Engineering, 2013, Virginia Tech

URL: http://hdl.handle.net/10919/23222

► Concurrent data structures have found increasingly widespread use in both multicore and distributed computing environments, thereby escalating the priority for verifying their correctness. The thread… (more)

Subjects/Keywords: Quasi Linearizability; Refinement; Model Checking

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APA (6^th Edition):

Adhikari, K. (2013). Verifying a Quantitative Relaxation of Linearizability via Refinement. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23222

Chicago Manual of Style (16^th Edition):

Adhikari, Kiran. “Verifying a Quantitative Relaxation of Linearizability via Refinement.” 2013. Masters Thesis, Virginia Tech. Accessed March 07, 2021. http://hdl.handle.net/10919/23222.

MLA Handbook (7^th Edition):

Adhikari, Kiran. “Verifying a Quantitative Relaxation of Linearizability via Refinement.” 2013. Web. 07 Mar 2021.

Vancouver:

Adhikari K. Verifying a Quantitative Relaxation of Linearizability via Refinement. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10919/23222.

Council of Science Editors:

Adhikari K. Verifying a Quantitative Relaxation of Linearizability via Refinement. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23222

University of Canterbury

9. Keating, Daniel. Model Checking Time Triggered CAN Protocols.

Degree: M. Eng., Electrical Engineering, 2011, University of Canterbury

URL: http://dx.doi.org/10.26021/3492

► Model checking is used to aid in the design and verification of complex concurrent systems. An abstracted finite state model of a system and a… (more)

▼ Model checking is used to aid in the design and verification of complex concurrent systems. An abstracted finite state model of a system and a set of mathematically based correctness properties based on the design specifications are defined. The model checker then performs an exhaustive state space search of the model, checking that the correctness properties hold at each step. This thesis describes how the SPIN model checker has been used to find and correct problems in the software design of a distributed marine vessel control system currently under development at a control systems specialist in New Zealand. The system under development is a mission critical control system used on large marine vessels. Hence, the requirement to study its architecture and verify the implementation of the system. The model checking work reported here focused on analysing the implementation of the Time-Triggered Controller-Area-Network (TTCAN) protocol, as this is used as the backbone for communications between devices and thus is a crucial part of their control system. A model of the ISO TTCAN protocol has been created using the SPIN model checker. This was based on work previously done by Leen and Heffernan modelling the protocol with the UPPAAL model checker [Leen and Heffernan 2002a]. In the process of building the ISO TTCAN model, a set of general techniques were developed for model checking TTCAN-like protocols. The techniques developed include modelling the progression of time efficiently in SPIN, TTCAN message transmission, TTCAN error handling, and CAN bus arbitration. These techniques then form the basis of a set of models developed to check the sponsoring organisation’s implementation of TTCAN as well as the fault tolerance schemes added to the system. Descriptions of the models and properties developed to check the correctness of the TTCAN implementation are given, and verification results are presented and discussed. This application of model checking to an industrial design problem has been successful in identifying a number of potential issues early in the design phase. In cases where problems are identified, the sequences of events leading to the problems are described, and potential solutions are suggested and modelled to check their effect of the system.

Subjects/Keywords: TTCAN; CAN; model checking; SPIN

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APA (6^th Edition):

Keating, D. (2011). Model Checking Time Triggered CAN Protocols. (Masters Thesis). University of Canterbury. Retrieved from http://dx.doi.org/10.26021/3492

Chicago Manual of Style (16^th Edition):

Keating, Daniel. “Model Checking Time Triggered CAN Protocols.” 2011. Masters Thesis, University of Canterbury. Accessed March 07, 2021. http://dx.doi.org/10.26021/3492.

MLA Handbook (7^th Edition):

Keating, Daniel. “Model Checking Time Triggered CAN Protocols.” 2011. Web. 07 Mar 2021.

Vancouver:

Keating D. Model Checking Time Triggered CAN Protocols. [Internet] [Masters thesis]. University of Canterbury; 2011. [cited 2021 Mar 07]. Available from: http://dx.doi.org/10.26021/3492.

Council of Science Editors:

Keating D. Model Checking Time Triggered CAN Protocols. [Masters Thesis]. University of Canterbury; 2011. Available from: http://dx.doi.org/10.26021/3492

Princeton University

10. Ahn, Sunha. AUTOMATED FIRMWARE VERIFICATION USING FIRMWARE-HARDWARE INTERACTION PATTERNS .

Degree: PhD, 2016, Princeton University

URL: http://arks.princeton.edu/ark:/88435/dsp01s4655k00v

► Firmware refers to low-level software that is tied to a specific hardware platform. For instance, low-level drivers that physically interface with the peripherals are an… (more)

▼ Firmware refers to low-level software that is tied to a specific hardware platform. For instance, low-level drivers that physically interface with the peripherals are an example of firmware. An emerging trend in system design is to implement complex system management functions in firmware rather than hardware. For example, firmware has grown to include software that manages critical hardware platform functions such as power management. As the scale and the importance of firmware is increasing, its validation becomes a critical part of system validation. Firmware validation relies on having good models of the interacting hardware components because firmware needs to be shipped with the hardware and shares many of the same critical design concerns as the hardware. This is generally addressed through co-simulating C/C++ based firmware code and HDL~(including SystemC) hardware models, which are usually not available until the late design stages. However, co-simulation tends to be slow, and is further exacerbated by the large number of possible interleavings between the concurrent firmware and hardware threads. Typically, in co-simulation, the thread scheduler, such as the SystemC scheduler, only explores a small number of possible firmware-hardware interleavings and thus may miss critical bugs. A firmware function is mostly reactive: it continuously provides a service, with a clear start and end, in response to inputs from its interacting software or hardware layer~(i.e., the environment). Thus, a firmware function is often inherently associated with an infinite loop structure. This often makes it impossible to guarantee the completeness of the verification results. To this end, I address two key problems in this thesis. First, I describe how to co-design firmware with the system components at the service function level, also referred to as the transaction level. Second, I discuss how to validate firmware interactions with their connected hardware modules while pruning the verification search space and ensuring complete verification. To solve these problems, this thesis first introduces a specific Service-Function Transaction-Level Model (TLM) for modeling firmware and interacting hardware components. I capture the particular structure of the proposed TLMs through cross-transaction interaction patterns, such as statelessness, i.e., when variable values are not retained between transaction executions, or producer-consumer relationships. Using the TLM, this thesis presents a scalable firmware validation approach that is based on automatically generating a test set with the goal of complete path coverage for firmware. Instead of explicitly exploring all the interleavings of the concurrent transactions, this thesis exploits the interaction patterns to automatically generate a sequential program, which is test-equivalent to the target firmware transaction and can be used with a standard single-threaded concolic test generator. The tests generated can… Advisors/Committee Members: Malik, Sharad (advisor).

Subjects/Keywords: Firmware; Model checking; Testing; Verifiation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ahn, S. (2016). AUTOMATED FIRMWARE VERIFICATION USING FIRMWARE-HARDWARE INTERACTION PATTERNS . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01s4655k00v

Chicago Manual of Style (16^th Edition):

Ahn, Sunha. “AUTOMATED FIRMWARE VERIFICATION USING FIRMWARE-HARDWARE INTERACTION PATTERNS .” 2016. Doctoral Dissertation, Princeton University. Accessed March 07, 2021. http://arks.princeton.edu/ark:/88435/dsp01s4655k00v.

MLA Handbook (7^th Edition):

Ahn, Sunha. “AUTOMATED FIRMWARE VERIFICATION USING FIRMWARE-HARDWARE INTERACTION PATTERNS .” 2016. Web. 07 Mar 2021.

Vancouver:

Ahn S. AUTOMATED FIRMWARE VERIFICATION USING FIRMWARE-HARDWARE INTERACTION PATTERNS . [Internet] [Doctoral dissertation]. Princeton University; 2016. [cited 2021 Mar 07]. Available from: http://arks.princeton.edu/ark:/88435/dsp01s4655k00v.

Council of Science Editors:

Ahn S. AUTOMATED FIRMWARE VERIFICATION USING FIRMWARE-HARDWARE INTERACTION PATTERNS . [Doctoral Dissertation]. Princeton University; 2016. Available from: http://arks.princeton.edu/ark:/88435/dsp01s4655k00v

11. Sakho, Mouhamadou Tafsir. ⌈-Pomset pour la modélisation et la vérification de systèmes parallèles : ⌈-Pomset for modelling and verifying parallel systems.

Degree: Docteur es, Mathématiques-Informatique, 2014, Orléans; Université polytechnique de l'Ouest Africain (Dakar, Sénégal)

URL: http://www.theses.fr/2014ORLE2068

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Un comportement distribué peut être décrit avec un multi-ensemble partiellement ordonné (pomset). Bien que compacts et très intuitifs, ces modèles sont difficiles à vérifier. La… (more)

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Un comportement distribué peut être décrit avec un multi-ensemble partiellement ordonné (pomset). Bien que compacts et très intuitifs, ces modèles sont difficiles à vérifier. La principale technique utilisée dans cette thèse est de ramener les problèmes de décision de la logique MSO sur les pomsets à des problèmes de décision sur les mots. Les problèmes considérés sont la satisfiabilité et la vérification. Le problème de la vérification pour une formule donnée et un pomset consiste à décider si une interprétation est vraie, et le problème de satisfiabilité consiste à décider si un pomset répondant à la formule existe. Le problème de satisfiabilité de MSO sur pomsets est indécidable. Une procédure de semi-décision peut apporter des solutions pour de nombreux cas, en dépit du fait qu'elle peut ne pas terminer. Nous proposons un nouveau modèle, que l'on appelle ⌈-Pomset, pouvant rendre l'exploration des pomsets possible. Par conséquent, si une formule est satisfiable alors notre approche mènera éventuellement à la détection d'une solution. De plus, en utilisant les ⌈-Pomsets comme modèles pour systèmes concurrents, le model-checking de formules ordre partiel sur systèmes concurrents est décidable. Certaines expérimentations ont été faites en utilisant l'outil MONA. Nous avons comparé aussi la puissance expressive de certains modèles classiques de la concurrence comme les traces de Mazurkiewicz avec les ⌈-Pomsets.

Multiset of partially ordered events (pomset) can describe distributed behavior. Although very intuitive and compact, these models are difficult to verify. The main technique used in this thesis is to bring back decision problems for MSO over pomsets to problems for MSO over words. The problems considered are satisfiability and verification. The verification problem for a formula and a given pomset consists in deciding whether such an interpretation exists, and the satisfiability problem consists in deciding whether a pomset satisfying the formula exists. The satisfiability problem of MSO over pomsets is undecidable. A semi-decision procedures can provide solutions for many cases despite the fact that they may not terminate. We propose a new model, so called ⌈-Pomset, making the exploration of pomsets space possible. Consequently, if a formula is satisfiable then our approach will eventually lead to the detection of a solution. Moreover, using ⌈-Pomsets as models for concurrent systems, the model checking of partial order formulas on concurrent systems is decidable. Some experiments have been made using MONA. We compare also the expressive power of some classical model of concurrency such as Mazurkiewicz traces with our ⌈-Pomsets.

Advisors/Committee Members: Couvreur, Jean-Michel (thesis director), Seydi, Hamet (thesis director).

Subjects/Keywords: Pomset; Model-checking; Satisfiabilité; Traces; Pomset; Model-checking; Satisfiability; Trace; 004.3

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Sakho, M. T. (2014). ⌈-Pomset pour la modélisation et la vérification de systèmes parallèles : ⌈-Pomset for modelling and verifying parallel systems. (Doctoral Dissertation). Orléans; Université polytechnique de l'Ouest Africain (Dakar, Sénégal). Retrieved from http://www.theses.fr/2014ORLE2068

Chicago Manual of Style (16^th Edition):

Sakho, Mouhamadou Tafsir. “⌈-Pomset pour la modélisation et la vérification de systèmes parallèles : ⌈-Pomset for modelling and verifying parallel systems.” 2014. Doctoral Dissertation, Orléans; Université polytechnique de l'Ouest Africain (Dakar, Sénégal). Accessed March 07, 2021. http://www.theses.fr/2014ORLE2068.

MLA Handbook (7^th Edition):

Sakho, Mouhamadou Tafsir. “⌈-Pomset pour la modélisation et la vérification de systèmes parallèles : ⌈-Pomset for modelling and verifying parallel systems.” 2014. Web. 07 Mar 2021.

Vancouver:

Sakho MT. ⌈-Pomset pour la modélisation et la vérification de systèmes parallèles : ⌈-Pomset for modelling and verifying parallel systems. [Internet] [Doctoral dissertation]. Orléans; Université polytechnique de l'Ouest Africain (Dakar, Sénégal); 2014. [cited 2021 Mar 07]. Available from: http://www.theses.fr/2014ORLE2068.

Council of Science Editors:

Sakho MT. ⌈-Pomset pour la modélisation et la vérification de systèmes parallèles : ⌈-Pomset for modelling and verifying parallel systems. [Doctoral Dissertation]. Orléans; Université polytechnique de l'Ouest Africain (Dakar, Sénégal); 2014. Available from: http://www.theses.fr/2014ORLE2068

12. Bozianu, Rodica. Synthesis of Interactive Reactive Systems : Synthèse des systèmes réactifs interactifs.

Degree: Docteur es, Informatique, 2016, Université Paris-Est

URL: http://www.theses.fr/2016PESC1026

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Nous étudions le problème de la synthèse automatique de programmes dans des architectures multi-composants tels qu'elles respectent les spécifications par construction. Le principal objectif de… (more)

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Nous étudions le problème de la synthèse automatique de programmes dans des architectures multi-composants tels qu'elles respectent les spécifications par construction. Le principal objectif de cette thèse est de développer des procédures pour résoudre le problème de synthèse qui peut conduire à des implémentations efficaces. Chaque composant a une observation partielle sur l'état global du système multi-composants. Le problème est alors de fournir des protocoles basés sur les observations tel que les composants synthétisés assurent les spécifications pour tout le comportement de leur environnement. L'environnement peut être antagoniste, ou peut avoir ses propres objectifs et se comporter de façon rationnelle. Nous étudions d'abord le problème de synthèse lorsque l'environnement est présumé antagoniste. Pour ce contexte, nous proposons une procédure "Safraless" pour la synthèse d'un composant partiellement informé et un environnement omniscient à partir de spécications KLTL+. Elle est implémentée dans l'outil Acacia-K. Ensuite, nous étudions le problème de synthèse lorsque les composants de l'environnement ont leurs propres objectifs et sont rationnels. Pour le cadre plus simple de l'information parfaite, nous fournissons des complexités serrées pour des objectifs omega-réguliers particuliers. Pour le cas de l'information imparfaite, nous prouvons que le problème de la synthèse rationnelle est indécidable en général, mais nous regagnons la décidabilité si on demande à synthétiser un composant avec observation partielle contre un environnement multi-composante, omniscient et rationnel

We study the problem of automatic synthesis of programs in multi-component architectures such that they satisfy the specifications by construction. The main goal of the thesis is to develop procedures to solve the synthesis problem that may lead to efficient implementations.Each component may have partial observation on the global state of the multi-component system.Therefore, the synthesis problem asks to provide observation-based protocols for the components that have to be synthesized that ensure that specifications hold on all interactions with their environment.The environment may be antagonist, or may have its own objectives and behave rationally.We first study the synthesis problem when the environment is presumed to be completely antagonist. For this setting, we propose a "Safraless" procedure for the synthesis of one partially informed component and an omniscient environment from KLTL+ specifications. It is implemented in the tool Acacia-K. Secondly, we study the synthesis problem when the components in the environment have their own objectives and are rational. For the more relaxed setting of perfect information, we provide tight complexities for particular omega-regular objectives. Then, for the case of imperfect information, we prove that the rational synthesis problem is undecidable in general, but we gain decidability if is asked to synthesize only one component against a rational omniscient environment

Advisors/Committee Members: Dima, Catalin (thesis director).

Subjects/Keywords: Synthèse; Model Checking; Verification; Jeux; Synthesis; Model Checking; Verification; Games

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Bozianu, R. (2016). Synthesis of Interactive Reactive Systems : Synthèse des systèmes réactifs interactifs. (Doctoral Dissertation). Université Paris-Est. Retrieved from http://www.theses.fr/2016PESC1026

Chicago Manual of Style (16^th Edition):

Bozianu, Rodica. “Synthesis of Interactive Reactive Systems : Synthèse des systèmes réactifs interactifs.” 2016. Doctoral Dissertation, Université Paris-Est. Accessed March 07, 2021. http://www.theses.fr/2016PESC1026.

MLA Handbook (7^th Edition):

Bozianu, Rodica. “Synthesis of Interactive Reactive Systems : Synthèse des systèmes réactifs interactifs.” 2016. Web. 07 Mar 2021.

Vancouver:

Bozianu R. Synthesis of Interactive Reactive Systems : Synthèse des systèmes réactifs interactifs. [Internet] [Doctoral dissertation]. Université Paris-Est; 2016. [cited 2021 Mar 07]. Available from: http://www.theses.fr/2016PESC1026.

Council of Science Editors:

Bozianu R. Synthesis of Interactive Reactive Systems : Synthèse des systèmes réactifs interactifs. [Doctoral Dissertation]. Université Paris-Est; 2016. Available from: http://www.theses.fr/2016PESC1026

13. Fronc, Lukasz. Compilation de réseaux de Petri : modèles haut niveau et symétries de processus : Compilation of Petri nets : high-level models and process symmetries.

Degree: Docteur es, Informatique, 2013, Evry-Val d'Essonne

URL: http://www.theses.fr/2013EVRY0034

►

Cette thèse s'intéresse à la vérification de systèmes automatisables par model-checking. La question sous-jacente autour de laquelle se construit la contribution est la recherche d'un… (more)

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Cette thèse s'intéresse à la vérification de systèmes automatisables par model-checking. La question sous-jacente autour de laquelle se construit la contribution est la recherche d'un compromis entre différents objectifs potentiellement contradictoires : la décidabilité des systèmes à vérifier, l'expressivité des formalismes de modélisation, l'efficacité de la vérification, et la certification des outils utilisés. Dans ce but, on choisit de baser la modélisation sur des réseaux de Petri annotés par des langages de programmation réels. Cela implique la semi-décidabilité de la plupart des questions puisque la responsabilité de la terminaison est remise entre les mains du modélisateur (tout comme la terminaison des programmes est de la responsabilité du programmeur). Afin d'exploiter efficacement ces annotations, on choisit ensuite une approche de compilation de modèle qui permet de générer des programmes efficaces dans le langage des annotations, qui sont alors exécutées de la manière la plus efficace. De plus, la compilation est optimisée en tirant partie des spécificités de chaque modèle et nous utilisons l'approche de model-checking explicite qui autorise cette richesse d'annotations tout en facilitant le diagnostique et en restant compatible avec la simulation (les modèles compilés peuvent servir à de la simulation efficace). Enfin, pour combattre l'explosion combinatoire, nous utilisons des techniques de réductions de symétries qui permettent de réduire les temps d'exploration et l'espace mémoire nécessaire.

This work focuses on verification of automated systems using model-checking techniques. We focus on a compromise between potentially contradictory goals: decidability of systems to be verified, expressivity of modeling formalisms, efficiency of verification, and certification of used tools. To do so, we use high level Petri nets annotated by real programming languages. This implies the semi-decidability of most of problems because termination is left to the modeler (like termination of programs is left to the programmer). To handle these models, we choose a compilation approach which produces programs in the model annotation language, this allows to execute them efficiently. Moreover, this compilation is optimizing using model peculiarities. However, this rich expressivity leads to the use of explicit model-checking which allows to have rich model annotations but also allows to easily recover errors from verification, and remains compatible with simulation (these compiled models can be used for efficient simulation). Finally, to tackle the state space explosion problem, we use reduction by symmetries techniques which allow to reduce exploration times and state spaces.

Advisors/Committee Members: Klaudel, Hanna (thesis director), Pommereau, Franck (thesis director).

Subjects/Keywords: Model-checking; Model-checking; High-level Petri nets; Compilation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Fronc, L. (2013). Compilation de réseaux de Petri : modèles haut niveau et symétries de processus : Compilation of Petri nets : high-level models and process symmetries. (Doctoral Dissertation). Evry-Val d'Essonne. Retrieved from http://www.theses.fr/2013EVRY0034

Chicago Manual of Style (16^th Edition):

Fronc, Lukasz. “Compilation de réseaux de Petri : modèles haut niveau et symétries de processus : Compilation of Petri nets : high-level models and process symmetries.” 2013. Doctoral Dissertation, Evry-Val d'Essonne. Accessed March 07, 2021. http://www.theses.fr/2013EVRY0034.

MLA Handbook (7^th Edition):

Fronc, Lukasz. “Compilation de réseaux de Petri : modèles haut niveau et symétries de processus : Compilation of Petri nets : high-level models and process symmetries.” 2013. Web. 07 Mar 2021.

Vancouver:

Fronc L. Compilation de réseaux de Petri : modèles haut niveau et symétries de processus : Compilation of Petri nets : high-level models and process symmetries. [Internet] [Doctoral dissertation]. Evry-Val d'Essonne; 2013. [cited 2021 Mar 07]. Available from: http://www.theses.fr/2013EVRY0034.

Council of Science Editors:

Fronc L. Compilation de réseaux de Petri : modèles haut niveau et symétries de processus : Compilation of Petri nets : high-level models and process symmetries. [Doctoral Dissertation]. Evry-Val d'Essonne; 2013. Available from: http://www.theses.fr/2013EVRY0034

14. Declerck, David. Vérification par model-checking de programmes concurrents paramétrés sur des modèles mémoires faibles : Verification via Model Checking of Parameterized Concurrent Programs on Weak Memory Models.

Degree: Docteur es, Informatique, 2018, Université Paris-Saclay (ComUE)

URL: http://www.theses.fr/2018SACLS336

►

Les multiprocesseurs et microprocesseurs multicœurs modernes mettent en oeuvre des modèles mémoires dits faibles ou relâchés, dans dans lesquels l'ordre apparent des opérations mémoire ne… (more)

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Les multiprocesseurs et microprocesseurs multicœurs modernes mettent en oeuvre des modèles mémoires dits faibles ou relâchés, dans dans lesquels l'ordre apparent des opérations mémoire ne suit pas la cohérence séquentielle (SC) proposée par Leslie Lamport. Tout programme concurrent s'exécutant sur une telle architecture et conçu avec un modèle SC en tête risque de montrer à l'exécution de nouveaux comportements, dont certains sont potentiellement des comportements incorrects. Par exemple, un algorithme d'exclusion mutuelle correct avec une sémantique par entrelacement pourrait ne plus garantir l'exclusion mutuelle lorsqu'il est mis en oeuvre sur une architecture plus relâchée. Raisonner sur la sémantique de tels programmes s'avère très difficile. Par ailleurs, bon nombre d'algorithmes concurrents sont conçus pour fonctionner indépendamment du nombre de processus mis en oeuvre. On voudrait donc pouvoir s'assurer de la correction d'algorithmes concurrents, quel que soit le nombre de processus impliqués. Pour ce faire, on s'appuie sur le cadre du Model Checking Modulo Theories (MCMT), développé par Ghilardi et Ranise, qui permet la vérification de propriétés de sûreté de programmes concurrents paramétrés, c'est-à-dire mettant en oeuvre un nombre arbitraire de processus. On étend cette technologie avec une théorie permettant de raisonner sur des modèles mémoires faibles. Le résultat ce ces travaux est une extension du model checker Cubicle, appelée Cubicle-W, permettant de vérifier des propriétés de systèmes de transitions paramétrés s'exécutant sur un modèle mémoire faible similaire à TSO.

Modern multiprocessors and microprocesseurs implement weak or relaxed memory models, in which the apparent order of memory operation does not follow the sequential consistency (SC) proposed by Leslie Lamport. Any concurrent program running on such architecture and designed with an SC model in mind may exhibit new behaviors during its execution, some of which may potentially be incorrect. For instance, a mutual exclusion algorithm, correct under an interleaving semantics, may no longer guarantee mutual exclusion when implemented on a weaker architecture. Reasoning about the semantics of such programs is a difficult task. Moreover, most concurrent algorithms are designed for an arbitrary number of processus. We would like to ensure the correctness of concurrent algorithms, regardless of the number of processes involved. For this purpose, we rely on the Model Checking Modulo Theories (MCMT) framework, developed by Ghilardi and Ranise, which allows for the verification of safety properties of parameterized concurrent programs, that is to say, programs involving an arbitrary number of processes. We extend this technology with a theory for reasoning about weak memory models. The result of this work is an extension of the Cubicle model checker called Cubicle-W, which allows the verification of safety properties of parameterized transition systems running under a weak memory model similar to TSO.

Advisors/Committee Members: Zaïdi, Fatiha (thesis director).

Subjects/Keywords: Mémoire faible; Model checking; Vérification; Weak memory; Model checking; Verification

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Declerck, D. (2018). Vérification par model-checking de programmes concurrents paramétrés sur des modèles mémoires faibles : Verification via Model Checking of Parameterized Concurrent Programs on Weak Memory Models. (Doctoral Dissertation). Université Paris-Saclay (ComUE). Retrieved from http://www.theses.fr/2018SACLS336

Chicago Manual of Style (16^th Edition):

Declerck, David. “Vérification par model-checking de programmes concurrents paramétrés sur des modèles mémoires faibles : Verification via Model Checking of Parameterized Concurrent Programs on Weak Memory Models.” 2018. Doctoral Dissertation, Université Paris-Saclay (ComUE). Accessed March 07, 2021. http://www.theses.fr/2018SACLS336.

MLA Handbook (7^th Edition):

Declerck, David. “Vérification par model-checking de programmes concurrents paramétrés sur des modèles mémoires faibles : Verification via Model Checking of Parameterized Concurrent Programs on Weak Memory Models.” 2018. Web. 07 Mar 2021.

Vancouver:

Declerck D. Vérification par model-checking de programmes concurrents paramétrés sur des modèles mémoires faibles : Verification via Model Checking of Parameterized Concurrent Programs on Weak Memory Models. [Internet] [Doctoral dissertation]. Université Paris-Saclay (ComUE); 2018. [cited 2021 Mar 07]. Available from: http://www.theses.fr/2018SACLS336.

Council of Science Editors:

Declerck D. Vérification par model-checking de programmes concurrents paramétrés sur des modèles mémoires faibles : Verification via Model Checking of Parameterized Concurrent Programs on Weak Memory Models. [Doctoral Dissertation]. Université Paris-Saclay (ComUE); 2018. Available from: http://www.theses.fr/2018SACLS336

Tampere University

15. Biswas, Prasun. Model-to-Model Transformation Of Nuclear Industry I&C Logic To Assist Model Checking .

Degree: 2020, Tampere University

URL: https://trepo.tuni.fi/handle/10024/121539

► The demand for electricity has increased proportionately with massive urbanisation and in-dustrialisation. Nuclear energy is a strong candidate which can be one of the solutions… (more)

▼ The demand for electricity has increased proportionately with massive urbanisation and in-dustrialisation. Nuclear energy is a strong candidate which can be one of the solutions to ca-ter to this massive demand for energy. Nuclear resources have the benefit of enormous ener-gy density, low carbon footprint, cheap operating cost and production reliability. Even though it is deemed as a dependable and economically viable option, it is limited by safety concerns, unfortunate accidents can cause monumental and long-lasting consequences. On the other hand, if critically examined, thoroughly tested and flawlessly implemented, the decision-makers can opt for nuclear source. Thus utilising nuclear resources will call for an error-proof instrumentation and control system to observe and ensure safe operation. Model verification plays a vital role in critical analysis of I & C system, it checks all the possibilities the system may reach, and thus provide a model to develop an I&C safety system. An industrial operation may suffer from unknown component failure and design error, but its safety-critical system must be able to strictly prohibit these undesired events in the system before causing any major accident. “Model Checking” is a mathematical deterministic tool for logic design verification, which has been proven to be effective for detecting design errors in the system. Granted that, Instrumentation and control system starts with logic design at the preliminary phase, a model checking tool can efficiently identify design faults by exhaustive analysis. NuSMV is such a tool, which provides simpler syntax, that can represent the system as logical states with simple data structures. Analysts write SMV files to represent the system available as proprietary non-standard machine-readable diagrams. This thesis proposes an automation step towards diagram import in a verification tool and implements an intermediate data representation. This thesis provides a perception of various technologies relevant to broader authentication process of a safety system covering from design to verification tools. The state-of-the-art model-checking practice is discussed briefly. Subsequently, a number of logical instrumenta-tion and control diagrams, drawn in Microsoft VISIO tool, are analysed and processed to au-tomatically create an intermediate component network consisting of Function Block elements. A significant effort is spent to partially generate NuSMV code from the retrieved component data to assist the model checking of the system. Finally, the thesis is concluded with a synop-sis of the work done and future development scope.

Subjects/Keywords: Model Transformation ; Formal Verification ; Model Checking ; NuSMV

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Biswas, P. (2020). Model-to-Model Transformation Of Nuclear Industry I&C Logic To Assist Model Checking . (Masters Thesis). Tampere University. Retrieved from https://trepo.tuni.fi/handle/10024/121539

Chicago Manual of Style (16^th Edition):

Biswas, Prasun. “Model-to-Model Transformation Of Nuclear Industry I&C Logic To Assist Model Checking .” 2020. Masters Thesis, Tampere University. Accessed March 07, 2021. https://trepo.tuni.fi/handle/10024/121539.

MLA Handbook (7^th Edition):

Biswas, Prasun. “Model-to-Model Transformation Of Nuclear Industry I&C Logic To Assist Model Checking .” 2020. Web. 07 Mar 2021.

Vancouver:

Biswas P. Model-to-Model Transformation Of Nuclear Industry I&C Logic To Assist Model Checking . [Internet] [Masters thesis]. Tampere University; 2020. [cited 2021 Mar 07]. Available from: https://trepo.tuni.fi/handle/10024/121539.

Council of Science Editors:

Biswas P. Model-to-Model Transformation Of Nuclear Industry I&C Logic To Assist Model Checking . [Masters Thesis]. Tampere University; 2020. Available from: https://trepo.tuni.fi/handle/10024/121539

University of Melbourne

16. Nguyen, Cattram. Diagnostic methods for checking multiple imputation models.

Degree: 2014, University of Melbourne

URL: http://hdl.handle.net/11343/45205

► Multiple imputation is an increasingly popular method for handling missing data. A key task in the imputation process is the specification of a model for… (more)

▼ Multiple imputation is an increasingly popular method for handling missing data. A key task in the imputation process is the specification of a model for generating imputations. The validity of imputation-based inferences depends on the adequacy of this imputation model. Constructing imputation models is not straightforward and requires careful decision-making. The imputer must decide, for example, which variables to include in the imputation model and what functional form these variables should take. In many cases, there is no consensus in the literature to inform the modelling decisions. If the imputation model is poorly specified, such as through the omission of important variables, this can lead to biased results. It is therefore important that researchers check the goodness-of-fit of their imputation models. Despite the popularity of multiple imputation, the checking of imputation models is not widespread. This may primarily be due to the scarcity of guidelines and computational tools for performing imputation diagnostics. Although some diagnostic methods have been proposed in the literature, very few studies have formally evaluated whether the proposed techniques are useful for identifying problems with imputation models. Thus, we have found ourselves in an environment where the wide availability of multiple imputation is coupled with a lack of software and guidelines for assessing the adequacy of the models used in this process. The current research addressed this knowledge gap by evaluating diagnostic methods for checking imputation models. This included an examination of proposed methods including graphical diagnostics, the Kolmogorov-Smirnov test and posterior predictive checking. These techniques were evaluated using simulation experiments and they were illustrated using data from the Longitudinal Study of Australian Children. The investigations in this thesis revealed both advantages and disadvantages of all evaluated diagnostics. The graphical checks were useful for exploring the imputed values, but it was challenging to apply them routinely to all imputed variables, especially when working on large-scale datasets. The Kolmogorov-Smirnov diagnostic was straightforward to implement, but it had limited usefulness when the data were missing at random, an assumption which is commonly made when performing multiple imputation. Posterior predictive checking was preferable to methods that focus on the plausibility of imputations, because it checks the fit of the model with respect to quantities of scientific interest. Posterior predictive checking was able to successfully identify model misspecifications such as the omission of the outcome variable from the imputation model. However, users of posterior predictive checking need to be aware of the shortcomings of this approach, particularly its reduced usefulness in the presence of large amounts of missing data. Given that all of the evaluated methods were imperfect, there is the need for further development and evaluation of diagnostic techniques…

Subjects/Keywords: missing data; multiple imputation, posterior predictive checking; diagnostics; model checking

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Nguyen, C. (2014). Diagnostic methods for checking multiple imputation models. (Doctoral Dissertation). University of Melbourne. Retrieved from http://hdl.handle.net/11343/45205

Chicago Manual of Style (16^th Edition):

Nguyen, Cattram. “Diagnostic methods for checking multiple imputation models.” 2014. Doctoral Dissertation, University of Melbourne. Accessed March 07, 2021. http://hdl.handle.net/11343/45205.

MLA Handbook (7^th Edition):

Nguyen, Cattram. “Diagnostic methods for checking multiple imputation models.” 2014. Web. 07 Mar 2021.

Vancouver:

Nguyen C. Diagnostic methods for checking multiple imputation models. [Internet] [Doctoral dissertation]. University of Melbourne; 2014. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/11343/45205.

Council of Science Editors:

Nguyen C. Diagnostic methods for checking multiple imputation models. [Doctoral Dissertation]. University of Melbourne; 2014. Available from: http://hdl.handle.net/11343/45205

17. Chai, Xinwei. Reachability Analysis and Revision of Dynamics of Biological Regulatory Networks : Analyse d’accessibilité et révision de la dynamique dans les réseaux de régulations biologiques.

Degree: Docteur es, Informatique, 2019, Ecole centrale de Nantes

URL: http://www.theses.fr/2019ECDN0014

►

Les systèmes concurrents sont un bon choix pour ajuster les données et analyser les mécanismes sous-jacents pour leur sémantique simple mais expressive. Cependant, l’apprentissage et… (more)

▼

Les systèmes concurrents sont un bon choix pour ajuster les données et analyser les mécanismes sous-jacents pour leur sémantique simple mais expressive. Cependant, l’apprentissage et l’analyse de tels systèmes concurrents sont difficiles pour ce qui concerne les calculs. Lorsqu’il s’agit de grands ensembles de données, les techniques les plus récentes semblent insuffisantes, que ce soit en termes d’efficacité ou de précision. Ici, nous proposons un cadre de modélisation raffiné ABAN (Asynchronous Binary Automata Network) et développons des outils pour analyser l’atteignabilité : PermReach (Reachability via Permutation search) et ASPReach (Reachability via Answer Set Programming). Nous proposons ensuite deux méthodes de construction et d’apprentissage des modèles: CRAC (Completion via Reachability And Correlations) et M2RIT (Model Revision via Reachability and Interpretation Transitions) en utilisant des données continues et discrètes pour s’ajuster au modèle et des propriétés d’accessibilité afin de contraindre les modèles en sortie.

Concurrent systems become a good choice to fit the data and analyze the underlying mechanics for their simple but expressive semantics. However, learning and analyzing such concurrent systems are computationally difficult. When dealing with big data sets, the state-of-the-art techniques appear to be insufficient, either in term of efficiency or in term of precision. In this thesis, we propose a refined modeling framework ABAN (Asynchronous Binary Automata Network) and develop reachability analysis techniques based on ABAN: PermReach (Reachability via Permutation search) and ASPReach (Reachability via Answer Set Programming). Then we propose two model learning/constructing methods: CRAC (Completion via Reachability And Correlations) and M2RIT (Model Revision via Reachability and Interpretation Transitions) using continuous and discrete data to fit the model and using reachability properties to constrain the output models.

Advisors/Committee Members: Roux, Olivier (thesis director).

Subjects/Keywords: Bioinformatique; Model checking; Heuristique; Révision de modèles; Bioinformatics; Model checking; Heuristics; Model revision

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chai, X. (2019). Reachability Analysis and Revision of Dynamics of Biological Regulatory Networks : Analyse d’accessibilité et révision de la dynamique dans les réseaux de régulations biologiques. (Doctoral Dissertation). Ecole centrale de Nantes. Retrieved from http://www.theses.fr/2019ECDN0014

Chicago Manual of Style (16^th Edition):

Chai, Xinwei. “Reachability Analysis and Revision of Dynamics of Biological Regulatory Networks : Analyse d’accessibilité et révision de la dynamique dans les réseaux de régulations biologiques.” 2019. Doctoral Dissertation, Ecole centrale de Nantes. Accessed March 07, 2021. http://www.theses.fr/2019ECDN0014.

MLA Handbook (7^th Edition):

Chai, Xinwei. “Reachability Analysis and Revision of Dynamics of Biological Regulatory Networks : Analyse d’accessibilité et révision de la dynamique dans les réseaux de régulations biologiques.” 2019. Web. 07 Mar 2021.

Vancouver:

Chai X. Reachability Analysis and Revision of Dynamics of Biological Regulatory Networks : Analyse d’accessibilité et révision de la dynamique dans les réseaux de régulations biologiques. [Internet] [Doctoral dissertation]. Ecole centrale de Nantes; 2019. [cited 2021 Mar 07]. Available from: http://www.theses.fr/2019ECDN0014.

Council of Science Editors:

Chai X. Reachability Analysis and Revision of Dynamics of Biological Regulatory Networks : Analyse d’accessibilité et révision de la dynamique dans les réseaux de régulations biologiques. [Doctoral Dissertation]. Ecole centrale de Nantes; 2019. Available from: http://www.theses.fr/2019ECDN0014

18. Oliveira, João Paulo dos Santos. Rabbit: A novel approach to find data-races during state-space exploration .

Degree: 2012, Universidade Federal de Pernambuco

URL: http://repositorio.ufpe.br/handle/123456789/10891

► Data-races are an important kind of error in concurrent shared-memory programs. Software model checking is a popular approach to find them. This research proposes a… (more)

Subjects/Keywords: Concorrency; Software Verification; Model Checking; Race conditions

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APA (6^th Edition):

Oliveira, J. P. d. S. (2012). Rabbit: A novel approach to find data-races during state-space exploration . (Thesis). Universidade Federal de Pernambuco. Retrieved from http://repositorio.ufpe.br/handle/123456789/10891

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Oliveira, João Paulo dos Santos. “Rabbit: A novel approach to find data-races during state-space exploration .” 2012. Thesis, Universidade Federal de Pernambuco. Accessed March 07, 2021. http://repositorio.ufpe.br/handle/123456789/10891.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Oliveira, João Paulo dos Santos. “Rabbit: A novel approach to find data-races during state-space exploration .” 2012. Web. 07 Mar 2021.

Vancouver:

Oliveira JPdS. Rabbit: A novel approach to find data-races during state-space exploration . [Internet] [Thesis]. Universidade Federal de Pernambuco; 2012. [cited 2021 Mar 07]. Available from: http://repositorio.ufpe.br/handle/123456789/10891.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Oliveira JPdS. Rabbit: A novel approach to find data-races during state-space exploration . [Thesis]. Universidade Federal de Pernambuco; 2012. Available from: http://repositorio.ufpe.br/handle/123456789/10891

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

19. Li, Yi. Linux Device Driver Synthesis and Verification.

Degree: MS, Computer Science, 2015, Vanderbilt University

URL: http://hdl.handle.net/1803/14577

► The device driver is a program which provides a software interface to a hardware device, enabling operating systems and other computer programs to access hardware… (more)

Subjects/Keywords: driver synthesis; model checking; domain specific language

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Li, Y. (2015). Linux Device Driver Synthesis and Verification. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14577

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Li, Yi. “Linux Device Driver Synthesis and Verification.” 2015. Thesis, Vanderbilt University. Accessed March 07, 2021. http://hdl.handle.net/1803/14577.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Li, Yi. “Linux Device Driver Synthesis and Verification.” 2015. Web. 07 Mar 2021.

Vancouver:

Li Y. Linux Device Driver Synthesis and Verification. [Internet] [Thesis]. Vanderbilt University; 2015. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1803/14577.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li Y. Linux Device Driver Synthesis and Verification. [Thesis]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/14577

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. Naujokat, Stefan. Automatische Generierung von Prozessen im jABC.

Degree: 2009, Technische Universität Dortmund

URL: http://hdl.handle.net/2003/29822

► Serviceorientierung ist ein zentrales Element zur Wiederverwendung in der Softwareentwicklung und die Modellierung von ausführbaren Prozessen aus Services (Orchestrierung) ermöglicht auch Anwendungsexperten, die in der… (more)

Subjects/Keywords: Datenflussanalyse; Lose Spezifikation; Model checking; Prozesssynthese; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Naujokat, S. (2009). Automatische Generierung von Prozessen im jABC. (Thesis). Technische Universität Dortmund. Retrieved from http://hdl.handle.net/2003/29822

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Naujokat, Stefan. “Automatische Generierung von Prozessen im jABC.” 2009. Thesis, Technische Universität Dortmund. Accessed March 07, 2021. http://hdl.handle.net/2003/29822.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Naujokat, Stefan. “Automatische Generierung von Prozessen im jABC.” 2009. Web. 07 Mar 2021.

Vancouver:

Naujokat S. Automatische Generierung von Prozessen im jABC. [Internet] [Thesis]. Technische Universität Dortmund; 2009. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/2003/29822.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Naujokat S. Automatische Generierung von Prozessen im jABC. [Thesis]. Technische Universität Dortmund; 2009. Available from: http://hdl.handle.net/2003/29822

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Friggens, David. On the Use of Model Checking for the Bounded and Unbounded Verification of Nonblocking Concurrent Data Structures.

Degree: 2013, Victoria University of Wellington

URL: http://hdl.handle.net/10063/2702

► Concurrent data structure algorithms have traditionally been designed using locks to regulate the behaviour of interacting threads, thus restricting access to parts of the shared… (more)

▼ Concurrent data structure algorithms have traditionally been designed using locks to regulate the behaviour of interacting threads, thus restricting access to parts of the shared memory to only one thread at a time. Since locks can lead to issues of performance and scalability, there has been interest in designing so-called nonblocking algorithms that do not use locks. However, designing and reasoning about concurrent systems is difficult, and is even more so for nonblocking systems, as evidenced by the number of incorrect algorithms in the literature. This thesis explores how the technique of model checking can aid the testing and verification of nonblocking data structure algorithms. Model checking is an automated verification method for finite state systems, and is able to produce counterexamples when verification fails. For verification, concurrent data structures are considered to be infinite state systems, as there is no bound on the number of interacting threads, the number of elements in the data structure, nor the number of possible distinct data values. Thus, in order to analyse concurrent data structures with model checking, we must either place finite bounds upon them, or employ an abstraction technique that will construct a finite system with the same properties. First, we discuss how nonblocking data structures can be best represented for model checking, and how to specify the properties we are interested in verifying. These properties are the safety property linearisability, and the progress properties wait-freedom, lock-freedom and obstructionfreedom. Second, we investigate using model checking for exhaustive testing, by verifying bounded (and hence finite state) instances of nonblocking data structures, parameterised by the number of threads, the number of distinct data values, and the size of storage memory (e.g. array length, or maximum number of linked list nodes). It is widely held, based on anecdotal evidence, that most bugs occur in small instances. We investigate the smallest bounds needed to falsify a number of incorrect algorithms, which supports this hypothesis. We also investigate verifying a number of correct algorithms for a range of bounds. If an algorithm can be verified for bounds significantly higher than the minimum bounds needed for falsification, then we argue it provides a high degree of confidence in the general correctness of the algorithm. However, with the available hardware we were not able to verify any of the algorithms to high enough bounds to claim such confidence. Third, we investigate using model checking to verify nonblocking data structures by employing the technique of canonical abstraction to construct finite state representations of the unbounded algorithms. Canonical abstraction represents abstract states as 3-valued logical structures, and allows the initial coarse abstraction to be refined as necessary by adding derived predicates. We introduce several novel derived predicates and show how these allow linearisability to be verified for linked list based… Advisors/Committee Members: Groves, LIndsay.

Subjects/Keywords: Nonblocking algorithms; Model checking; Canonical abstraction

1 more image…

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Friggens, D. (2013). On the Use of Model Checking for the Bounded and Unbounded Verification of Nonblocking Concurrent Data Structures. (Doctoral Dissertation). Victoria University of Wellington. Retrieved from http://hdl.handle.net/10063/2702

Chicago Manual of Style (16^th Edition):

Friggens, David. “On the Use of Model Checking for the Bounded and Unbounded Verification of Nonblocking Concurrent Data Structures.” 2013. Doctoral Dissertation, Victoria University of Wellington. Accessed March 07, 2021. http://hdl.handle.net/10063/2702.

MLA Handbook (7^th Edition):

Friggens, David. “On the Use of Model Checking for the Bounded and Unbounded Verification of Nonblocking Concurrent Data Structures.” 2013. Web. 07 Mar 2021.

Vancouver:

Friggens D. On the Use of Model Checking for the Bounded and Unbounded Verification of Nonblocking Concurrent Data Structures. [Internet] [Doctoral dissertation]. Victoria University of Wellington; 2013. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10063/2702.

Council of Science Editors:

Friggens D. On the Use of Model Checking for the Bounded and Unbounded Verification of Nonblocking Concurrent Data Structures. [Doctoral Dissertation]. Victoria University of Wellington; 2013. Available from: http://hdl.handle.net/10063/2702

22. Naujokat, Stefan. Automatische Generierung von Prozessen im jABC.

Degree: 2012, Technische Universität Dortmund

URL: http://dx.doi.org/10.17877/DE290R-10351

► Serviceorientierung ist ein zentrales Element zur Wiederverwendung in der Softwareentwicklung und die Modellierung von ausführbaren Prozessen aus Services (Orchestrierung) ermöglicht auch Anwendungsexperten, die in der… (more)

Subjects/Keywords: Datenflussanalyse; Lose Spezifikation; Model checking; Prozesssynthese; 004

Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Naujokat, S. (2012). Automatische Generierung von Prozessen im jABC. (Masters Thesis). Technische Universität Dortmund. Retrieved from http://dx.doi.org/10.17877/DE290R-10351

Chicago Manual of Style (16^th Edition):

Naujokat, Stefan. “Automatische Generierung von Prozessen im jABC.” 2012. Masters Thesis, Technische Universität Dortmund. Accessed March 07, 2021. http://dx.doi.org/10.17877/DE290R-10351.

MLA Handbook (7^th Edition):

Naujokat, Stefan. “Automatische Generierung von Prozessen im jABC.” 2012. Web. 07 Mar 2021.

Vancouver:

Naujokat S. Automatische Generierung von Prozessen im jABC. [Internet] [Masters thesis]. Technische Universität Dortmund; 2012. [cited 2021 Mar 07]. Available from: http://dx.doi.org/10.17877/DE290R-10351.

Council of Science Editors:

Naujokat S. Automatische Generierung von Prozessen im jABC. [Masters Thesis]. Technische Universität Dortmund; 2012. Available from: http://dx.doi.org/10.17877/DE290R-10351

23. Lopes, Arnaud Da Costa. Propriétés de jeux multi-agents : Multi-agent games properties.

Degree: Docteur es, Informatique, 2011, Cachan, Ecole normale supérieure

URL: http://www.theses.fr/2011DENS0034

►

Nous etendons les logiques temporelles du temps alternant ATL et ATL* au moyen de contextes strategiques et de contraintes sur la memoire : la premiere… (more)

▼

Nous etendons les logiques temporelles du temps alternant ATL et ATL* au moyen de contextes strategiques et de contraintes sur la memoire : la premiere extension permet aux agents de s'en tenir a leurs strategies lors de l'evaluation des formules, contrairement a ATL ou chaque quantificateur de strategies ecrase les strategies anterieurement selectionnees. La seconde extension permet aux quantificateurs de strategies de se restreindre aux strategies sans memoire ou avec memoire bornee. Nous avons l'etudie l'expressivite de nos logiques. Nous montrons qu'elles expriment des proprietes importantes comme l'exstence d'equilibres, et nous les comparons formellement a d'autres formalismes proches (ATL, ATL*, Game Logic, Strategy Logic, ...). Nous avons aborde les problemes de model-checking. Nous donnons un algorithme PSPACE pour la logique n'impliquant que des strategies sans memoire, et un algorithme EXPSPACE pour le cas des strategies a memoire bornee. Dans le cas general, malgre leur forte expresssivite, nous prouvons que leur model-checking reste decidable par un algorithme a base d'automates d'arbres alternants qui permet d'evaluer une formule sur la classe complete des CGS avec n joueurs.

We extend the alternating-time temporal logics ATL and ATL* with strategy contexts and memory constraints: the first extension make agents commit to their strategies during the evaluation of formulas, contrary to plain ATL where strategy quantifiers reset previously selected strategies. The second extension allows strategy quantifiers to restrict to memoryless or bounded-memory strategies. We consider expressiveness issues. We show that our logics can express important properties such as equilibria, and we formally compare them with other similar formalisms (ATL, ATL*, Game Logic, Strategy Logic, ...). We address the problem of model-checking for our logics, especially we provide a PSPACE algorithm for the sublogics involving only memoryless strategies and an EXPSPACE algorithm for the bounded-memory case. In the general case, despite the high expressiveness of these logics, we prove that their model-checking problems remain decidable by designing a tree-automata-based algorithm for model-checking ATLsc on the full class of n-player concurrent game structures.

Advisors/Committee Members: Zielonka, Wieslaw (thesis director), Laroussinie, François (thesis director).

Subjects/Keywords: Logique temporelle; Vérification formelle; Model-checking

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lopes, A. D. C. (2011). Propriétés de jeux multi-agents : Multi-agent games properties. (Doctoral Dissertation). Cachan, Ecole normale supérieure. Retrieved from http://www.theses.fr/2011DENS0034

Chicago Manual of Style (16^th Edition):

Lopes, Arnaud Da Costa. “Propriétés de jeux multi-agents : Multi-agent games properties.” 2011. Doctoral Dissertation, Cachan, Ecole normale supérieure. Accessed March 07, 2021. http://www.theses.fr/2011DENS0034.

MLA Handbook (7^th Edition):

Lopes, Arnaud Da Costa. “Propriétés de jeux multi-agents : Multi-agent games properties.” 2011. Web. 07 Mar 2021.

Vancouver:

Lopes ADC. Propriétés de jeux multi-agents : Multi-agent games properties. [Internet] [Doctoral dissertation]. Cachan, Ecole normale supérieure; 2011. [cited 2021 Mar 07]. Available from: http://www.theses.fr/2011DENS0034.

Council of Science Editors:

Lopes ADC. Propriétés de jeux multi-agents : Multi-agent games properties. [Doctoral Dissertation]. Cachan, Ecole normale supérieure; 2011. Available from: http://www.theses.fr/2011DENS0034

University of Waikato

24. Shaw, Adrian Mark. Partial Order Reduction with Compositional Verification .

Degree: 2014, University of Waikato

URL: http://hdl.handle.net/10289/9001

► This thesis expands the usage of partial order reduction methods in reducing the state space of large models in model checking. The work done can… (more)

Subjects/Keywords: Partial order reduction; Model checking; compositional verification

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Shaw, A. M. (2014). Partial Order Reduction with Compositional Verification . (Masters Thesis). University of Waikato. Retrieved from http://hdl.handle.net/10289/9001

Chicago Manual of Style (16^th Edition):

Shaw, Adrian Mark. “Partial Order Reduction with Compositional Verification .” 2014. Masters Thesis, University of Waikato. Accessed March 07, 2021. http://hdl.handle.net/10289/9001.

MLA Handbook (7^th Edition):

Shaw, Adrian Mark. “Partial Order Reduction with Compositional Verification .” 2014. Web. 07 Mar 2021.

Vancouver:

Shaw AM. Partial Order Reduction with Compositional Verification . [Internet] [Masters thesis]. University of Waikato; 2014. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10289/9001.

Council of Science Editors:

Shaw AM. Partial Order Reduction with Compositional Verification . [Masters Thesis]. University of Waikato; 2014. Available from: http://hdl.handle.net/10289/9001

Universidade Nova

25. Beyene, Tewodros Awgichew. Constraint-based verification of imperative programs.

Degree: 2011, Universidade Nova

URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7965

►

work presented in the context of the European Master’s program in Computational Logic, as the partial requirement for obtaining Master of Science degree in Computational… (more)

Subjects/Keywords: Program verification; Model checking; Constraint programming

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Beyene, T. A. (2011). Constraint-based verification of imperative programs. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7965

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Beyene, Tewodros Awgichew. “Constraint-based verification of imperative programs.” 2011. Thesis, Universidade Nova. Accessed March 07, 2021. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7965.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Beyene, Tewodros Awgichew. “Constraint-based verification of imperative programs.” 2011. Web. 07 Mar 2021.

Vancouver:

Beyene TA. Constraint-based verification of imperative programs. [Internet] [Thesis]. Universidade Nova; 2011. [cited 2021 Mar 07]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7965.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Beyene TA. Constraint-based verification of imperative programs. [Thesis]. Universidade Nova; 2011. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/7965

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Université de Bordeaux I

26. Chucri, Farès. Exploiting model structure in CEGAR verification method : Exploiter la structure des modèles pour la vérification par la méthode CEGAR.

Degree: Docteur es, Informatique, 2012, Université de Bordeaux I

URL: http://www.theses.fr/2012BOR14641

►

Cette thèse a eu pour but l'étude et la mise en oeuvre des méthodes de vérification par abstraction pour les modèles AltaRica. A cette effet,… (more)

Subjects/Keywords: Verification; Raffinement; Abstraction; Model Checking; Cegar; Abstraction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chucri, F. (2012). Exploiting model structure in CEGAR verification method : Exploiter la structure des modèles pour la vérification par la méthode CEGAR. (Doctoral Dissertation). Université de Bordeaux I. Retrieved from http://www.theses.fr/2012BOR14641

Chicago Manual of Style (16^th Edition):

Chucri, Farès. “Exploiting model structure in CEGAR verification method : Exploiter la structure des modèles pour la vérification par la méthode CEGAR.” 2012. Doctoral Dissertation, Université de Bordeaux I. Accessed March 07, 2021. http://www.theses.fr/2012BOR14641.

MLA Handbook (7^th Edition):

Chucri, Farès. “Exploiting model structure in CEGAR verification method : Exploiter la structure des modèles pour la vérification par la méthode CEGAR.” 2012. Web. 07 Mar 2021.

Vancouver:

Chucri F. Exploiting model structure in CEGAR verification method : Exploiter la structure des modèles pour la vérification par la méthode CEGAR. [Internet] [Doctoral dissertation]. Université de Bordeaux I; 2012. [cited 2021 Mar 07]. Available from: http://www.theses.fr/2012BOR14641.

Council of Science Editors:

Chucri F. Exploiting model structure in CEGAR verification method : Exploiter la structure des modèles pour la vérification par la méthode CEGAR. [Doctoral Dissertation]. Université de Bordeaux I; 2012. Available from: http://www.theses.fr/2012BOR14641

Colorado State University

27. Al Lail, Mustafa. Unified modeling language framework for specifying and analyzing temporal properties, A.

Degree: PhD, Computer Science, 2018, Colorado State University

URL: http://hdl.handle.net/10217/191492

► In the context of Model-Driven Engineering (MDE), designers use the Unified Modeling Language (UML) to create models that drive the entire development process. Once UML… (more)

Subjects/Keywords: properties; temporal; verification; specification; model checking; UML

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Al Lail, M. (2018). Unified modeling language framework for specifying and analyzing temporal properties, A. (Doctoral Dissertation). Colorado State University. Retrieved from http://hdl.handle.net/10217/191492

Chicago Manual of Style (16^th Edition):

Al Lail, Mustafa. “Unified modeling language framework for specifying and analyzing temporal properties, A.” 2018. Doctoral Dissertation, Colorado State University. Accessed March 07, 2021. http://hdl.handle.net/10217/191492.

MLA Handbook (7^th Edition):

Al Lail, Mustafa. “Unified modeling language framework for specifying and analyzing temporal properties, A.” 2018. Web. 07 Mar 2021.

Vancouver:

Al Lail M. Unified modeling language framework for specifying and analyzing temporal properties, A. [Internet] [Doctoral dissertation]. Colorado State University; 2018. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10217/191492.

Council of Science Editors:

Al Lail M. Unified modeling language framework for specifying and analyzing temporal properties, A. [Doctoral Dissertation]. Colorado State University; 2018. Available from: http://hdl.handle.net/10217/191492

University of Colorado

28. Hassan, Zyad. Incremental, Inductive Model Checking.

Degree: PhD, Electrical, Computer & Energy Engineering, 2014, University of Colorado

URL: https://scholar.colorado.edu/ecen_gradetds/86

► Model checking has become a widely adopted approach for the verification of hardware designs. The ever increasing complexity of these designs creates a continuous… (more)

▼ Model checking has become a widely adopted approach for the verification of hardware designs. The ever increasing complexity of these designs creates a continuous need for faster model checkers that are capable of verifying designs within reasonable time frames to reduce time to market. IC3, the recently developed, very successful algorithm for model checking safety properties, introduced a new approach to model checking: incremental, inductive verification (IIV). The IIV approach possesses several attractive traits, such as stability and not relying on high-effort reasoning, that make its usage in model checking very appealing, which motivated the development of another algorithm that follows the IIV approach for model checking ω-regular languages. The algorithm, Fair, has been shown to be capable of dealing with designs beyond the reach of its predecessors. This thesis explores IIV as a promising approach to model checking. After identifying IIV's main elements, the thesis presents an IIV-based model checking algorithm for CTL: the first practical SAT-based algorithm for branching time properties. The algorithm, IICTL, is shown to complement state-of-the-art BDD-based CTL algorithms on a large set of benchmarks. In addition to fulfilling the need for a SAT-based CTL algorithm, IICTL highlights ways in which IIV algorithms can be improved; one of these ways is addressing counterexamples to generalization, which is explored in the context of IC3 and is shown to improve the algorithm's performance considerably. The thesis then addresses an important question: for properties that fall into the scope of more than one IIV algorithm, do these algorithms behave identically? The question is answered negatively, pointing out that the IIV framework admits multiple strategies and that there is a wide spectrum of possible algorithms that all follow the IIV approach. For example, all properties in the common fragment of LTL and CTL—an important class of properties—can be checked with Fair and IICTL. However, empirical evidence presented in the thesis suggests that neither algorithm is always superior to the other, which points out the importance of being flexible in deciding the strategy to apply to a given problem. Advisors/Committee Members: Fabio Somenzi, Aaron R. Bradley, Pavol Cerny, Sriram Sankaranarayanan, Niklas Sorensson.

Subjects/Keywords: Formal Verification; Model Checking; Satisfiability; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hassan, Z. (2014). Incremental, Inductive Model Checking. (Doctoral Dissertation). University of Colorado. Retrieved from https://scholar.colorado.edu/ecen_gradetds/86

Chicago Manual of Style (16^th Edition):

Hassan, Zyad. “Incremental, Inductive Model Checking.” 2014. Doctoral Dissertation, University of Colorado. Accessed March 07, 2021. https://scholar.colorado.edu/ecen_gradetds/86.

MLA Handbook (7^th Edition):

Hassan, Zyad. “Incremental, Inductive Model Checking.” 2014. Web. 07 Mar 2021.

Vancouver:

Hassan Z. Incremental, Inductive Model Checking. [Internet] [Doctoral dissertation]. University of Colorado; 2014. [cited 2021 Mar 07]. Available from: https://scholar.colorado.edu/ecen_gradetds/86.

Council of Science Editors:

Hassan Z. Incremental, Inductive Model Checking. [Doctoral Dissertation]. University of Colorado; 2014. Available from: https://scholar.colorado.edu/ecen_gradetds/86

University of Edinburgh

29. Lehtinen, Maria Karoliina. Syntactic complexity in the modal μ calculus.

Degree: PhD, 2017, University of Edinburgh

URL: http://hdl.handle.net/1842/29520

► This thesis studies how to eliminate syntactic complexity in Lμ, the modal μ calculus. Lμ is a verification logic in which a least fixpoint operator… (more)

▼ This thesis studies how to eliminate syntactic complexity in Lμ, the modal μ calculus. Lμ is a verification logic in which a least fixpoint operator μ, and its dual v, add recursion to a simple modal logic. The number of alternations between μ and v is a measure of complexity called the formula’s index: the lower the index, the easier a formula is to model-check. The central question of this thesis is a long standing one, the Lμ index problem: given a formula, what is the least index of any equivalent formula, that is to say, its semantic index? I take a syntactic approach, focused on simplifying formulas. The core decidability results are (i) alternative, syntax-focused decidability proofs for ML and Pμ 1 , the low complexity classes of μ; and (ii) a proof that Ʃμ 2 , the fragment of Lμ with one alternation, is decidable for formulas in the dual class Pμ 2 . Beyond its algorithmic contributions, this thesis aims to deepen our understanding of the index problem and the tools at our disposal. I study disjunctive form and related syntactic restrictions, and how they affect the index problem. The main technical results are that the transformation into disjunctive form preserves Pμ 2 -indices but not μ 2 -indices, and that some properties of binary trees are expressible with a lower index using disjunctive formulas than non-deterministic automata. The latter is part of a thorough account of how the Lμ index problem and the Rabin–Mostowski index problem for parity automata are related. In the final part of the thesis, I revisit the relationship between the index problem and parity games. The syntactic index of a formula is an upper bound on the descriptive complexity of its model-checking parity games. I show that the semantic index of a formula Ψ is bounded above by the descriptive complexity of the model-checking games for Ψ. I then study whether this bound is strict: if a formula Ψ is equivalent to a formula in an alternation class C, does a formula of C suffice to describe the winning regions of the model-checking games of Ψ? I prove that this is the case for ML, Pμ 1 , Ʃμ 2 , and the disjunctive fragment of any alternation class. I discuss the practical implications of these results and propose a uniform approach to the index problem, which subsumes the previously described decision procedures for low alternation classes. In brief, this thesis can be read as a guide on how to approach a seemingly complex Lμ formula. Along the way it studies what makes this such a difficult problem and proposes novel approaches to both simplifying individual formulas and deciding further fragments of the alternation hierarchy.

Subjects/Keywords: verification logic; Lµ; model-checking; Lµ formula

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lehtinen, M. K. (2017). Syntactic complexity in the modal μ calculus. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/29520

Chicago Manual of Style (16^th Edition):

Lehtinen, Maria Karoliina. “Syntactic complexity in the modal μ calculus.” 2017. Doctoral Dissertation, University of Edinburgh. Accessed March 07, 2021. http://hdl.handle.net/1842/29520.

MLA Handbook (7^th Edition):

Lehtinen, Maria Karoliina. “Syntactic complexity in the modal μ calculus.” 2017. Web. 07 Mar 2021.

Vancouver:

Lehtinen MK. Syntactic complexity in the modal μ calculus. [Internet] [Doctoral dissertation]. University of Edinburgh; 2017. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1842/29520.

Council of Science Editors:

Lehtinen MK. Syntactic complexity in the modal μ calculus. [Doctoral Dissertation]. University of Edinburgh; 2017. Available from: http://hdl.handle.net/1842/29520

Iowa State University

30. Suvorov, Yuly. A model checking approach for analyzing and identifying intervention policies to counter infection propagation over networks.

Degree: 2011, Iowa State University

URL: https://lib.dr.iastate.edu/etd/10431

► The spread of infections (disease, ideas, fires, etc.) in a network (group of people, electronic network, forest, etc.) can be modeled by the evolution of… (more)

Subjects/Keywords: Disease; Infection; Model Checking; Policies; Computer Sciences

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Suvorov, Y. (2011). A model checking approach for analyzing and identifying intervention policies to counter infection propagation over networks. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/10431

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Suvorov, Yuly. “A model checking approach for analyzing and identifying intervention policies to counter infection propagation over networks.” 2011. Thesis, Iowa State University. Accessed March 07, 2021. https://lib.dr.iastate.edu/etd/10431.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Suvorov, Yuly. “A model checking approach for analyzing and identifying intervention policies to counter infection propagation over networks.” 2011. Web. 07 Mar 2021.

Vancouver:

Suvorov Y. A model checking approach for analyzing and identifying intervention policies to counter infection propagation over networks. [Internet] [Thesis]. Iowa State University; 2011. [cited 2021 Mar 07]. Available from: https://lib.dr.iastate.edu/etd/10431.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Suvorov Y. A model checking approach for analyzing and identifying intervention policies to counter infection propagation over networks. [Thesis]. Iowa State University; 2011. Available from: https://lib.dr.iastate.edu/etd/10431

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Open Access Theses and Dissertations