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You searched for subject:(Mismatch in Successive Approximation Analog to Digital Converters). Showing records 1 – 30 of 127422 total matches.

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University of Michigan

1. Collins, Nicholas. Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs.

Degree: PhD, Electrical Engineering, 2017, University of Michigan

 During the past decade, SAR ADCs have enjoyed increasing prominence due to their inherently scaling-friendly architecture. Several recent SAR ADC innovations focus on decreasing power… (more)

Subjects/Keywords: Mismatch in SAR ADCs; Mismatch in Successive Approximation Analog-to-Digital Converters; Electrical Engineering; Engineering

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APA (6th Edition):

Collins, N. (2017). Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/138630

Chicago Manual of Style (16th Edition):

Collins, Nicholas. “Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs.” 2017. Doctoral Dissertation, University of Michigan. Accessed October 19, 2019. http://hdl.handle.net/2027.42/138630.

MLA Handbook (7th Edition):

Collins, Nicholas. “Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs.” 2017. Web. 19 Oct 2019.

Vancouver:

Collins N. Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/2027.42/138630.

Council of Science Editors:

Collins N. Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/138630


Oregon State University

2. Leung, Jerry. Data driven optimization in SAR ADC.

Degree: MS, Electrical and Computer Engineering, 2014, Oregon State University

 Recent publications show that successive approximation register (SAR) analog to digital converters (ADC) are capable of achieving high efficiency over other ADC topologies. Furthermore, techniques… (more)

Subjects/Keywords: SAR; Successive approximation analog-to-digital converters

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APA (6th Edition):

Leung, J. (2014). Data driven optimization in SAR ADC. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/54631

Chicago Manual of Style (16th Edition):

Leung, Jerry. “Data driven optimization in SAR ADC.” 2014. Masters Thesis, Oregon State University. Accessed October 19, 2019. http://hdl.handle.net/1957/54631.

MLA Handbook (7th Edition):

Leung, Jerry. “Data driven optimization in SAR ADC.” 2014. Web. 19 Oct 2019.

Vancouver:

Leung J. Data driven optimization in SAR ADC. [Internet] [Masters thesis]. Oregon State University; 2014. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/1957/54631.

Council of Science Editors:

Leung J. Data driven optimization in SAR ADC. [Masters Thesis]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/54631


Southern Illinois University

3. Sekar, Ramgopal. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.

Degree: MS, Electrical and Computer Engineering, 2010, Southern Illinois University

  In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC… (more)

Subjects/Keywords: Analog to Digital Converters; Low Power Design; Successive Approximation Register ADC

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APA (6th Edition):

Sekar, R. (2010). LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. (Masters Thesis). Southern Illinois University. Retrieved from http://opensiuc.lib.siu.edu/theses/350

Chicago Manual of Style (16th Edition):

Sekar, Ramgopal. “LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.” 2010. Masters Thesis, Southern Illinois University. Accessed October 19, 2019. http://opensiuc.lib.siu.edu/theses/350.

MLA Handbook (7th Edition):

Sekar, Ramgopal. “LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.” 2010. Web. 19 Oct 2019.

Vancouver:

Sekar R. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. [Internet] [Masters thesis]. Southern Illinois University; 2010. [cited 2019 Oct 19]. Available from: http://opensiuc.lib.siu.edu/theses/350.

Council of Science Editors:

Sekar R. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. [Masters Thesis]. Southern Illinois University; 2010. Available from: http://opensiuc.lib.siu.edu/theses/350


Hong Kong University of Science and Technology

4. Wu, Chao ECE. A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC.

Degree: 2018, Hong Kong University of Science and Technology

 High-speed high-precision analog-to-digital converters (ADCs) are widely used in the fields of image processing, information storage and wireless communication. To achieve high speed and high… (more)

Subjects/Keywords: Analog-to-digital converters; Successive approximation analog-to-digital converters; Signal processing; Digital techniques; Real-time data processing; Electronic data processing

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APA (6th Edition):

Wu, C. E. (2018). A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-991012615563203412 ; http://repository.ust.hk/ir/bitstream/1783.1-93162/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Chao ECE. “A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC.” 2018. Thesis, Hong Kong University of Science and Technology. Accessed October 19, 2019. https://doi.org/10.14711/thesis-991012615563203412 ; http://repository.ust.hk/ir/bitstream/1783.1-93162/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Chao ECE. “A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC.” 2018. Web. 19 Oct 2019.

Vancouver:

Wu CE. A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2018. [cited 2019 Oct 19]. Available from: https://doi.org/10.14711/thesis-991012615563203412 ; http://repository.ust.hk/ir/bitstream/1783.1-93162/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu CE. A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC. [Thesis]. Hong Kong University of Science and Technology; 2018. Available from: https://doi.org/10.14711/thesis-991012615563203412 ; http://repository.ust.hk/ir/bitstream/1783.1-93162/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

5. Liu, Wenbo. Low-power high-performance SAR ADC design with digital calibration techniques.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized… (more)

Subjects/Keywords: successive-approximation-register (SAR) analog-to-digital converters (ADC); redundancy; sub-radix-2; Nonlinearity; digital calibration; linear equalizer; generalized linear equalizer; perturbation; bit-wise correlation; channel mismatch; time-interleaved analog-to-digital converters (ADC)

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APA (6th Edition):

Liu, W. (2011). Low-power high-performance SAR ADC design with digital calibration techniques. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18623

Chicago Manual of Style (16th Edition):

Liu, Wenbo. “Low-power high-performance SAR ADC design with digital calibration techniques.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 19, 2019. http://hdl.handle.net/2142/18623.

MLA Handbook (7th Edition):

Liu, Wenbo. “Low-power high-performance SAR ADC design with digital calibration techniques.” 2011. Web. 19 Oct 2019.

Vancouver:

Liu W. Low-power high-performance SAR ADC design with digital calibration techniques. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/2142/18623.

Council of Science Editors:

Liu W. Low-power high-performance SAR ADC design with digital calibration techniques. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18623


Universidade do Rio Grande do Sul

6. Lanot, Alisson Jamie Cruz. Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga.

Degree: 2014, Universidade do Rio Grande do Sul

Conversores A/D do tipo aproximações sucessivas (SAR) baseados em redistribuição de carga são frequentemente utilizados em aplicações envolvendo a aquisição de sinais, principalmente as que… (more)

Subjects/Keywords: Analog to digital converters; Conversor analogico/digital; Circuitos integrados; Successive approximation register; Single event effects; Single event transients; Fault mitigation techniques

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APA (6th Edition):

Lanot, A. J. C. (2014). Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/114478

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lanot, Alisson Jamie Cruz. “Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed October 19, 2019. http://hdl.handle.net/10183/114478.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lanot, Alisson Jamie Cruz. “Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga.” 2014. Web. 19 Oct 2019.

Vancouver:

Lanot AJC. Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/10183/114478.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lanot AJC. Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/114478

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

7. Shah, Aarti Mahesh Kumar. Successive-approximation-register based quantizer design for high-speed delta-sigma modulators.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 High-speed delta-sigma modulators are in high demand for applications such as wire-line and wireless communications, medical imaging, RF receivers and high-definition video processing. A high-speed… (more)

Subjects/Keywords: Analog-to-digital converters; High speed successive approximation register (SAR); Delta-sigma modulators; Quantizer; Medium resolution successive approximation register (SAR); Time-interleaved successive approximation register (TI SAR); Time-interleaved analog-to-digital converter (ADC); Higher order delta-sigma modulator design; Delta-sigma simulink models; Successive approximation register analog-to-digital converter (SAR ADC) design

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APA (6th Edition):

Shah, A. M. K. (2017). Successive-approximation-register based quantizer design for high-speed delta-sigma modulators. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97465

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shah, Aarti Mahesh Kumar. “Successive-approximation-register based quantizer design for high-speed delta-sigma modulators.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed October 19, 2019. http://hdl.handle.net/2142/97465.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shah, Aarti Mahesh Kumar. “Successive-approximation-register based quantizer design for high-speed delta-sigma modulators.” 2017. Web. 19 Oct 2019.

Vancouver:

Shah AMK. Successive-approximation-register based quantizer design for high-speed delta-sigma modulators. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/2142/97465.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shah AMK. Successive-approximation-register based quantizer design for high-speed delta-sigma modulators. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97465

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

8. Gao, Yang. An Energy Efficient Asynchronous Time-Domain Comparator.

Degree: 2013, Texas A&M University

 In energy-limited applications, such as wearable battery powered systems and implantable circuits for biological applications, ultra-low power analog-to-digital converters (ADCs) are essential for sustaining long… (more)

Subjects/Keywords: Analog-to-digital converter; asynchronous circuits; comparator; successive approximation

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APA (6th Edition):

Gao, Y. (2013). An Energy Efficient Asynchronous Time-Domain Comparator. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149314

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gao, Yang. “An Energy Efficient Asynchronous Time-Domain Comparator.” 2013. Thesis, Texas A&M University. Accessed October 19, 2019. http://hdl.handle.net/1969.1/149314.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gao, Yang. “An Energy Efficient Asynchronous Time-Domain Comparator.” 2013. Web. 19 Oct 2019.

Vancouver:

Gao Y. An Energy Efficient Asynchronous Time-Domain Comparator. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/1969.1/149314.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gao Y. An Energy Efficient Asynchronous Time-Domain Comparator. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149314

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Thirunakkarasu, Shankar. Self-Calibration And Digital-Trimming Of Successive Approximation Analog-To-Digital Converters.

Degree: Electrical Engineering, 2014, Arizona State University

Subjects/Keywords: Electrical engineering; Analog-to-digital (A/D) conversion; data converters; digital trimming; mismatch correction; self-calibration; successive approximation

…Description Language xi PREFACE Successive Approximation Register Analog-to-Digital Converter… …Capacitive Digital-to-Analog Converter (CDAC) of Successive Approximation Register… …realization of Analog to Digital 1 Converters. Some of these approaches include Flash, Multi-Step… …required in order to reconstruct the original analog signal reliably in digital domain. On the… …precision comes from the matching requirements in a Capacitive Digital to Analog Converter… 

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APA (6th Edition):

Thirunakkarasu, S. (2014). Self-Calibration And Digital-Trimming Of Successive Approximation Analog-To-Digital Converters. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/25930

Chicago Manual of Style (16th Edition):

Thirunakkarasu, Shankar. “Self-Calibration And Digital-Trimming Of Successive Approximation Analog-To-Digital Converters.” 2014. Doctoral Dissertation, Arizona State University. Accessed October 19, 2019. http://repository.asu.edu/items/25930.

MLA Handbook (7th Edition):

Thirunakkarasu, Shankar. “Self-Calibration And Digital-Trimming Of Successive Approximation Analog-To-Digital Converters.” 2014. Web. 19 Oct 2019.

Vancouver:

Thirunakkarasu S. Self-Calibration And Digital-Trimming Of Successive Approximation Analog-To-Digital Converters. [Internet] [Doctoral dissertation]. Arizona State University; 2014. [cited 2019 Oct 19]. Available from: http://repository.asu.edu/items/25930.

Council of Science Editors:

Thirunakkarasu S. Self-Calibration And Digital-Trimming Of Successive Approximation Analog-To-Digital Converters. [Doctoral Dissertation]. Arizona State University; 2014. Available from: http://repository.asu.edu/items/25930


University of Michigan

10. Fredenburg, Jeffrey Alan. Noise-Shaping SAR ADCs.

Degree: PhD, Electrical Engineering, 2015, University of Michigan

 This work investigates hybrid analog-to-digital converters (ADCs) that combine the phenomenal energy efficiency of successive-approximation (SAR) ADCs with the resolution enhancement strategies used by noise-shaping… (more)

Subjects/Keywords: Analog-to-Digital Converter; Noise-shaping SAR; Successive-approximation ADC; Analog Circuits; Electrical Engineering; Engineering

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APA (6th Edition):

Fredenburg, J. A. (2015). Noise-Shaping SAR ADCs. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/113647

Chicago Manual of Style (16th Edition):

Fredenburg, Jeffrey Alan. “Noise-Shaping SAR ADCs.” 2015. Doctoral Dissertation, University of Michigan. Accessed October 19, 2019. http://hdl.handle.net/2027.42/113647.

MLA Handbook (7th Edition):

Fredenburg, Jeffrey Alan. “Noise-Shaping SAR ADCs.” 2015. Web. 19 Oct 2019.

Vancouver:

Fredenburg JA. Noise-Shaping SAR ADCs. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/2027.42/113647.

Council of Science Editors:

Fredenburg JA. Noise-Shaping SAR ADCs. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/113647

11. Li, Wei. Low-power successive approximation analog to digital converter with digital calibration.

Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University

 IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies… (more)

Subjects/Keywords: ADC; Successive approximation analog-to-digital converters  – Calibration

…Background Calibration Technique for Successive Approximation Analog-to-Digital Converters,” Int… …70 Low-Power Successive Approximation Analog to Digital Converter with Digital… …plays an important role in signal processing by performing analog-to-digital conversion… …grows, human beings are still living in an analog world. To make DSP possible, analog signals… …digital world. When the activity of analog-to-digital conversion happens, energy is consumed… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, W. (2014). Low-power successive approximation analog to digital converter with digital calibration. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/46788

Chicago Manual of Style (16th Edition):

Li, Wei. “Low-power successive approximation analog to digital converter with digital calibration.” 2014. Doctoral Dissertation, Oregon State University. Accessed October 19, 2019. http://hdl.handle.net/1957/46788.

MLA Handbook (7th Edition):

Li, Wei. “Low-power successive approximation analog to digital converter with digital calibration.” 2014. Web. 19 Oct 2019.

Vancouver:

Li W. Low-power successive approximation analog to digital converter with digital calibration. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/1957/46788.

Council of Science Editors:

Li W. Low-power successive approximation analog to digital converter with digital calibration. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/46788


Universidade Federal de Santa Maria

12. Taimur Gibran Rabuske Kuntz. TÉCNICAS PARA REDUÇÃO DE CONSUMO EM CONVERSORES ANALÓGICO-DIGITAIS POR APROXIMAÇÃO SUCESSIVA E COMPARTILHAMENTO DE CARGA.

Degree: 2012, Universidade Federal de Santa Maria

New trends and emerging technologies motivate the design of analog-to-digital converters (ADCs) which must fit in increasingly constrained environments. Within this context, one design metric… (more)

Subjects/Keywords: Compartilhamento de carga; Conversores por registrador de aproximação sucessiva; Eficiência energética; Conversores analógico-digitais; CIENCIA DA COMPUTACAO; Analog-to-digital conveters; energy efficiency; successive approximation register converters; charge sharing

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APA (6th Edition):

Kuntz, T. G. R. (2012). TÉCNICAS PARA REDUÇÃO DE CONSUMO EM CONVERSORES ANALÓGICO-DIGITAIS POR APROXIMAÇÃO SUCESSIVA E COMPARTILHAMENTO DE CARGA. (Thesis). Universidade Federal de Santa Maria. Retrieved from http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=4227

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kuntz, Taimur Gibran Rabuske. “TÉCNICAS PARA REDUÇÃO DE CONSUMO EM CONVERSORES ANALÓGICO-DIGITAIS POR APROXIMAÇÃO SUCESSIVA E COMPARTILHAMENTO DE CARGA.” 2012. Thesis, Universidade Federal de Santa Maria. Accessed October 19, 2019. http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=4227.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kuntz, Taimur Gibran Rabuske. “TÉCNICAS PARA REDUÇÃO DE CONSUMO EM CONVERSORES ANALÓGICO-DIGITAIS POR APROXIMAÇÃO SUCESSIVA E COMPARTILHAMENTO DE CARGA.” 2012. Web. 19 Oct 2019.

Vancouver:

Kuntz TGR. TÉCNICAS PARA REDUÇÃO DE CONSUMO EM CONVERSORES ANALÓGICO-DIGITAIS POR APROXIMAÇÃO SUCESSIVA E COMPARTILHAMENTO DE CARGA. [Internet] [Thesis]. Universidade Federal de Santa Maria; 2012. [cited 2019 Oct 19]. Available from: http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=4227.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kuntz TGR. TÉCNICAS PARA REDUÇÃO DE CONSUMO EM CONVERSORES ANALÓGICO-DIGITAIS POR APROXIMAÇÃO SUCESSIVA E COMPARTILHAMENTO DE CARGA. [Thesis]. Universidade Federal de Santa Maria; 2012. Available from: http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=4227

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. LI YONG FU. DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS.

Degree: 2014, National University of Singapore

Subjects/Keywords: Low-Power; Low-Voltage; Successive-Approximation; Analog-to-Digital Converters; Digital-to-Analog Converters

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APA (6th Edition):

FU, L. Y. (2014). DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/118434

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

FU, LI YONG. “DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS.” 2014. Thesis, National University of Singapore. Accessed October 19, 2019. http://scholarbank.nus.edu.sg/handle/10635/118434.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

FU, LI YONG. “DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS.” 2014. Web. 19 Oct 2019.

Vancouver:

FU LY. DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS. [Internet] [Thesis]. National University of Singapore; 2014. [cited 2019 Oct 19]. Available from: http://scholarbank.nus.edu.sg/handle/10635/118434.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

FU LY. DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS. [Thesis]. National University of Singapore; 2014. Available from: http://scholarbank.nus.edu.sg/handle/10635/118434

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

14. Lin, Jiaming. Design techniques for low power high speed successive approximation analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs,… (more)

Subjects/Keywords: successive approximation ADC; Successive approximation analog-to-digital converters  – Design and construction

…69 Design Techniques for Low Power High Speed Successive Approximation Analog-to-Digital… …signal) and the digital world (digital signal), the analog-to-digital converter… …quantize the continuous analog signal into the numerical digital words. According to the sampling… …analog blocks as well as digital blocks, it is one of the most important cost issues to remove… …increased by a factor equal to the number of parallel ADCs. fs/N ANALOG DE-MUX 1 ADC DIGITAL… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, J. (2013). Design techniques for low power high speed successive approximation analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/40996

Chicago Manual of Style (16th Edition):

Lin, Jiaming. “Design techniques for low power high speed successive approximation analog-to-digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 19, 2019. http://hdl.handle.net/1957/40996.

MLA Handbook (7th Edition):

Lin, Jiaming. “Design techniques for low power high speed successive approximation analog-to-digital converters.” 2013. Web. 19 Oct 2019.

Vancouver:

Lin J. Design techniques for low power high speed successive approximation analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/1957/40996.

Council of Science Editors:

Lin J. Design techniques for low power high speed successive approximation analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/40996


NSYSU

15. Lo, Ching-Wen. High Speed SAR Analog to Digital Converter Design.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In this thesis, the circuits are designing with TSMC 90nm CMOS process and 1.2V of supply voltage. The speed and resolution of ADC are 8-bit… (more)

Subjects/Keywords: Bootstrapped switch; Dynamic Comparator; Successive Approximation; Low power; Analog-to-Digital Converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lo, C. (2014). High Speed SAR Analog to Digital Converter Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lo, Ching-Wen. “High Speed SAR Analog to Digital Converter Design.” 2014. Thesis, NSYSU. Accessed October 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lo, Ching-Wen. “High Speed SAR Analog to Digital Converter Design.” 2014. Web. 19 Oct 2019.

Vancouver:

Lo C. High Speed SAR Analog to Digital Converter Design. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Oct 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lo C. High Speed SAR Analog to Digital Converter Design. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

16. Chen, Guan-Ting. A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 In this thesis, a 10-bit resolution analog-to-digital converter with 100MHz sampling frequency is proposed. In terms of design, in order to improve the conversion speed,… (more)

Subjects/Keywords: 2b/Cycle; Non-binary Error Correction; Alternate Technique; Successive Approximation Register; Analog to Digital Converter

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APA (6th Edition):

Chen, G. (2018). A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Guan-Ting. “A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle.” 2018. Thesis, NSYSU. Accessed October 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Guan-Ting. “A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle.” 2018. Web. 19 Oct 2019.

Vancouver:

Chen G. A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Oct 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen G. A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. Chen, Yan-Lin. A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 In this thesis, a 10-bit, 10 MS/s dual-mode analog-to-digital converter with a 1.8 V supply voltage is implemented by using the TSMC 0.18ï­m process technology.… (more)

Subjects/Keywords: Dual-Mode; Edge Image; Image Sensor; Analog to Digital Converter; Successive Approximation Register

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APA (6th Edition):

Chen, Y. (2018). A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Yan-Lin. “A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor.” 2018. Thesis, NSYSU. Accessed October 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Yan-Lin. “A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor.” 2018. Web. 19 Oct 2019.

Vancouver:

Chen Y. A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Oct 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

18. Wang, Jingguang. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.

Degree: MS, Electrical and Computer Engineering, 2008, Oregon State University

 Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC… (more)

Subjects/Keywords: ADC; Analog-to-digital converters

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, J. (2008). Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/10041

Chicago Manual of Style (16th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Masters Thesis, Oregon State University. Accessed October 19, 2019. http://hdl.handle.net/1957/10041.

MLA Handbook (7th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Web. 19 Oct 2019.

Vancouver:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Internet] [Masters thesis]. Oregon State University; 2008. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/1957/10041.

Council of Science Editors:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Masters Thesis]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/10041


Oregon State University

19. Hu, Yue. Efficient use of time information in analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University

 Time-domain data conversion has recently drawn increased research attention for its highly digital nature in favor of process technology scaling. Also, as the time information… (more)

Subjects/Keywords: Analog-to-digital converters

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APA (6th Edition):

Hu, Y. (2014). Efficient use of time information in analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/52553

Chicago Manual of Style (16th Edition):

Hu, Yue. “Efficient use of time information in analog-to-digital converters.” 2014. Doctoral Dissertation, Oregon State University. Accessed October 19, 2019. http://hdl.handle.net/1957/52553.

MLA Handbook (7th Edition):

Hu, Yue. “Efficient use of time information in analog-to-digital converters.” 2014. Web. 19 Oct 2019.

Vancouver:

Hu Y. Efficient use of time information in analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/1957/52553.

Council of Science Editors:

Hu Y. Efficient use of time information in analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/52553


Oregon State University

20. Tong, Tao. Design techniques for successive approximation register analog-to-digital converters.

Degree: MS, Electrical and Computer Engineering, 2011, Oregon State University

Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently,… (more)

Subjects/Keywords: analog-to-digital converters

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APA (6th Edition):

Tong, T. (2011). Design techniques for successive approximation register analog-to-digital converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/22662

Chicago Manual of Style (16th Edition):

Tong, Tao. “Design techniques for successive approximation register analog-to-digital converters.” 2011. Masters Thesis, Oregon State University. Accessed October 19, 2019. http://hdl.handle.net/1957/22662.

MLA Handbook (7th Edition):

Tong, Tao. “Design techniques for successive approximation register analog-to-digital converters.” 2011. Web. 19 Oct 2019.

Vancouver:

Tong T. Design techniques for successive approximation register analog-to-digital converters. [Internet] [Masters thesis]. Oregon State University; 2011. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/1957/22662.

Council of Science Editors:

Tong T. Design techniques for successive approximation register analog-to-digital converters. [Masters Thesis]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/22662


NSYSU

21. Bai, Je-Wei. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 In this thesis, a 10-bit, 80 MS/s analog-to-digital converter with a 1 V supply voltage is implemented by using the TSMC 90nm process technology. This… (more)

Subjects/Keywords: non-binary digital error correction; digital error correction; 2b/Cycle; Successive Approximation Register; Analog to Digital Converter

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APA (6th Edition):

Bai, J. (2016). A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bai, Je-Wei. “A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.” 2016. Thesis, NSYSU. Accessed October 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bai, Je-Wei. “A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.” 2016. Web. 19 Oct 2019.

Vancouver:

Bai J. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. [Internet] [Thesis]. NSYSU; 2016. [cited 2019 Oct 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bai J. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

22. Maghari, Nima. Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Delta-sigma analog-to-digital converters (ADCs) are suitable for many applications due to several advantages such as relaxed anti-aliasing filter, high signal-to noise and distortion ratio (SNDR)… (more)

Subjects/Keywords: Analog Ciruits; Analog-to-digital converters

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APA (6th Edition):

Maghari, N. (2010). Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/18851

Chicago Manual of Style (16th Edition):

Maghari, Nima. “Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 19, 2019. http://hdl.handle.net/1957/18851.

MLA Handbook (7th Edition):

Maghari, Nima. “Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters.” 2010. Web. 19 Oct 2019.

Vancouver:

Maghari N. Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/1957/18851.

Council of Science Editors:

Maghari N. Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/18851


Oregon State University

23. Nishida, Yoshio. Improved design techniques for analog and mixed circuits.

Degree: PhD, Electrical and Computer Engineering, 2008, Oregon State University

 Although the digital revolution can realize many of past analog components in the digital forms, our world is surrounded with analog signals such as voice,… (more)

Subjects/Keywords: analog; Analog-to-digital converters  – Design

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APA (6th Edition):

Nishida, Y. (2008). Improved design techniques for analog and mixed circuits. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/7985

Chicago Manual of Style (16th Edition):

Nishida, Yoshio. “Improved design techniques for analog and mixed circuits.” 2008. Doctoral Dissertation, Oregon State University. Accessed October 19, 2019. http://hdl.handle.net/1957/7985.

MLA Handbook (7th Edition):

Nishida, Yoshio. “Improved design techniques for analog and mixed circuits.” 2008. Web. 19 Oct 2019.

Vancouver:

Nishida Y. Improved design techniques for analog and mixed circuits. [Internet] [Doctoral dissertation]. Oregon State University; 2008. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/1957/7985.

Council of Science Editors:

Nishida Y. Improved design techniques for analog and mixed circuits. [Doctoral Dissertation]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/7985


Ryerson University

24. Park, Young Jun. Time-interleaved pulse-shrinking and all-digital time-to-digital converters.

Degree: 2017, Ryerson University

 This dissertation deals with the design of sub-per-stage delay time-to-digital converters (TDCs). Two classes of TDCs namely pulse-shrinking TDCs and TDCs are investigated. In pulse-shrinking… (more)

Subjects/Keywords: Analog-to-digital converters; Digital-to-analog converters

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APA (6th Edition):

Park, Y. J. (2017). Time-interleaved pulse-shrinking and all-digital time-to-digital converters. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Young Jun. “Time-interleaved pulse-shrinking and all-digital time-to-digital converters.” 2017. Thesis, Ryerson University. Accessed October 19, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A6433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Young Jun. “Time-interleaved pulse-shrinking and all-digital time-to-digital converters.” 2017. Web. 19 Oct 2019.

Vancouver:

Park YJ. Time-interleaved pulse-shrinking and all-digital time-to-digital converters. [Internet] [Thesis]. Ryerson University; 2017. [cited 2019 Oct 19]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park YJ. Time-interleaved pulse-shrinking and all-digital time-to-digital converters. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

25. Chung, Meng-hsun. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt… (more)

Subjects/Keywords: Analog-to-Digital Converter; ADC; Binary-Search ADC; Successive Approximation; SAR ADC; Time-Interleaved; Non-overlapping circuit

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APA (6th Edition):

Chung, M. (2015). A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed October 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 19 Oct 2019.

Vancouver:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Oct 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

26. Zhang, Dai. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.

Degree: Electrical Engineering, 2009, Linköping University

Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system.… (more)

Subjects/Keywords: Analog-to-digital converter (ADC); charge redistribution; CMOS; low power; low supply voltage; successive approximation; latched comparator; Electrical engineering; Elektroteknik

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APA (6th Edition):

Zhang, D. (2009). Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Dai. “Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.” 2009. Thesis, Linköping University. Accessed October 19, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Dai. “Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.” 2009. Web. 19 Oct 2019.

Vancouver:

Zhang D. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. [Internet] [Thesis]. Linköping University; 2009. [cited 2019 Oct 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang D. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. [Thesis]. Linköping University; 2009. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Boston University

27. Yang, Jiao. Design of a low power 8-bit A/D converter for wireless neural recorder applications.

Degree: MS, Electrical & Computer Engineering, 2017, Boston University

 Human brain and related topics like neuron spikes and their active potentials have become more and more attractive to people these days, as these issues… (more)

Subjects/Keywords: Electrical engineering; Energy-saving capacitor array; Low power design; Neural recorder applications; Successive approximation register analog-to-digital converter (SAR-ADC)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, J. (2017). Design of a low power 8-bit A/D converter for wireless neural recorder applications. (Masters Thesis). Boston University. Retrieved from http://hdl.handle.net/2144/23685

Chicago Manual of Style (16th Edition):

Yang, Jiao. “Design of a low power 8-bit A/D converter for wireless neural recorder applications.” 2017. Masters Thesis, Boston University. Accessed October 19, 2019. http://hdl.handle.net/2144/23685.

MLA Handbook (7th Edition):

Yang, Jiao. “Design of a low power 8-bit A/D converter for wireless neural recorder applications.” 2017. Web. 19 Oct 2019.

Vancouver:

Yang J. Design of a low power 8-bit A/D converter for wireless neural recorder applications. [Internet] [Masters thesis]. Boston University; 2017. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/2144/23685.

Council of Science Editors:

Yang J. Design of a low power 8-bit A/D converter for wireless neural recorder applications. [Masters Thesis]. Boston University; 2017. Available from: http://hdl.handle.net/2144/23685


Tokyo Institute of Technology / 東京工業大学

28. Lin, James Tzu-Chin. Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters.

Degree: 博士(学術), 2014, Tokyo Institute of Technology / 東京工業大学

 This thesis presents a design strategy for ultra-low-voltage (ULV) high-speed analog-to-digital converters (ADCs). To verify the proposed design strategy, three unique ULV high-speed ADCs and… (more)

Subjects/Keywords: analog-to-digital converters (ADCs); charge-steering; dynamic amplifier; high-speed; interpolation; ultra-low-voltage (ULV); flash ADCs; successive approximation register (SAR) ADCs; pipelined ADCs; pipelined-SAR ADCs; FoM-delay (FD) product

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, J. T. (2014). Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters. (Thesis). Tokyo Institute of Technology / 東京工業大学. Retrieved from http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676125

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, James Tzu-Chin. “Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters.” 2014. Thesis, Tokyo Institute of Technology / 東京工業大学. Accessed October 19, 2019. http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676125.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, James Tzu-Chin. “Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters.” 2014. Web. 19 Oct 2019.

Vancouver:

Lin JT. Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters. [Internet] [Thesis]. Tokyo Institute of Technology / 東京工業大学; 2014. [cited 2019 Oct 19]. Available from: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676125.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin JT. Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters. [Thesis]. Tokyo Institute of Technology / 東京工業大学; 2014. Available from: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676125

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Tokyo Institute of Technology / 東京工業大学

29. Lin, James Tzu-Chin. Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters.

Degree: 博士(学術), 2014, Tokyo Institute of Technology / 東京工業大学

 This thesis presents a design strategy for ultra-low-voltage (ULV) high-speed analog-to-digital converters (ADCs). To verify the proposed design strategy, three unique ULV high-speed ADCs and… (more)

Subjects/Keywords: analog-to-digital converters (ADCs); charge-steering; dynamic amplifier; high-speed; interpolation; ultra-low-voltage (ULV); flash ADCs; successive approximation register (SAR) ADCs; pipelined ADCs; pipelined-SAR ADCs; FoM-delay (FD) product

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, J. T. (2014). Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters. (Thesis). Tokyo Institute of Technology / 東京工業大学. Retrieved from http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676122

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, James Tzu-Chin. “Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters.” 2014. Thesis, Tokyo Institute of Technology / 東京工業大学. Accessed October 19, 2019. http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676122.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, James Tzu-Chin. “Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters.” 2014. Web. 19 Oct 2019.

Vancouver:

Lin JT. Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters. [Internet] [Thesis]. Tokyo Institute of Technology / 東京工業大学; 2014. [cited 2019 Oct 19]. Available from: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676122.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin JT. Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters : Design of Ultra-Low-Voltage High-Speed Analog-to-Digital Converters. [Thesis]. Tokyo Institute of Technology / 東京工業大学; 2014. Available from: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100676122

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Jiang, Tao. Design techniques for low-power multi-GS/s analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are… (more)

Subjects/Keywords: high-speed; Successive approximation analog-to-digital converters  – Design and construction

…conversion, and analog-to-digital converters (ADC) have been widely employed in various… …80 Design Techniques for Low-Power Multi-GS/s Analog-to-Digital Converters 1… …growing tendency to process the analog signal in the digital domain after appropriate data… …ADC to convert the analog signal to digital data, which can be stored in memory as much as… …is shown in Figure 1.5, with the assistant of an ADC to convert the analog incoming signal… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jiang, T. (2013). Design techniques for low-power multi-GS/s analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/39396

Chicago Manual of Style (16th Edition):

Jiang, Tao. “Design techniques for low-power multi-GS/s analog-to-digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 19, 2019. http://hdl.handle.net/1957/39396.

MLA Handbook (7th Edition):

Jiang, Tao. “Design techniques for low-power multi-GS/s analog-to-digital converters.” 2013. Web. 19 Oct 2019.

Vancouver:

Jiang T. Design techniques for low-power multi-GS/s analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/1957/39396.

Council of Science Editors:

Jiang T. Design techniques for low-power multi-GS/s analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39396

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