subject:(Microprocessor)

University of Notre Dame

1. Thomas R. Szarek. On the Use Of Microcontrollers for Data Acquisition in an Introductory Measurments Course</h1>.

Degree: Aerospace and Mechanical Engineering, 2003, University of Notre Dame

URL: https://curate.nd.edu/show/z029p269t3p

► A microcontroller-based, miniature data acquisition system was developed for use in a sophomore-level Introduction to Measurement course. This board demonstrates that principles of proper… (more)

Subjects/Keywords: microprocessor

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APA (6^th Edition):

Szarek, T. R. (2003). On the Use Of Microcontrollers for Data Acquisition in an Introductory Measurments Course</h1>. (Thesis). University of Notre Dame. Retrieved from https://curate.nd.edu/show/z029p269t3p

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Szarek, Thomas R.. “On the Use Of Microcontrollers for Data Acquisition in an Introductory Measurments Course</h1>.” 2003. Thesis, University of Notre Dame. Accessed March 06, 2021. https://curate.nd.edu/show/z029p269t3p.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Szarek, Thomas R.. “On the Use Of Microcontrollers for Data Acquisition in an Introductory Measurments Course</h1>.” 2003. Web. 06 Mar 2021.

Vancouver:

Szarek TR. On the Use Of Microcontrollers for Data Acquisition in an Introductory Measurments Course</h1>. [Internet] [Thesis]. University of Notre Dame; 2003. [cited 2021 Mar 06]. Available from: https://curate.nd.edu/show/z029p269t3p.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Szarek TR. On the Use Of Microcontrollers for Data Acquisition in an Introductory Measurments Course</h1>. [Thesis]. University of Notre Dame; 2003. Available from: https://curate.nd.edu/show/z029p269t3p

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Southern California

2. Hom, Ivan Jackson. A methodology for the hardware/software co-design of embedded systems.

Degree: PhD, Electrical Engineering, 2007, University of Southern California

URL: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/547887/rec/245

► The design of hardware and software for embedded systems is well understood. But the compatibility problems between the two parts increases the time and effort… (more)

▼ The design of hardware and software for embedded systems is well understood. But the compatibility problems between the two parts increases the time and effort of exploring the system design space. This research lies at the interface between the hardware and software design to reduce incompatibilities. This research has contributions in hardware verification and automatically retargetable software.; This research is unique because the microarchitecture of the embedded system is an input to the methodology rather than a fixed structure. The semantics of the instruction set architecture are described as an ISA extension language added to the architectural description. The extensions are considered assertions, are verified in the microprocessor hardware and are constraints in the automatic retargeting of the software.; The architectural verification portion of this research considers both the structure and timing of data and control in the microprocessor datapath. A technique named structural correctness verifies the structure of the datapath has the required number and types of operand paths, execution units and control signals. Structural correctness is based on a path searching technique. Another technique named Hardware Token Graph (HTG) semantic model and simulation rules verifies the timing synchronization of data and control. The microprocessor states represent the location of data and control passing through the datapath at clock edges. The semantic model is analyzed using a simulation reachability analysis. The generated reachability tree is examined for the desired states which correspond to the correct operation of the microprocessor.; The software portion of this research describes an automatically retargetable optimizing assembler. A novel technique for software optimizations performs integrated instruction scheduling and register allocation under resource-conflict and data-dependency constraints. The software instruction scheduling is based on a priority schedule technique, and the register allocation is based on a linear scan allocation.; An implementation of this methodology has been developed named RAVE (Retargetable optimizing Assembler with architectural VErification). RAVE has been applied to instruction set trade-off analysis for edge detection and DNA sequencing applications to demonstrate its utility with promising results. Advisors/Committee Members: Parker, Alice C. (Committee Chair), Beerel, Peter A. (Committee Member), Diniz, Pedro (Committee Member).

Subjects/Keywords: microprocessor

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APA (6^th Edition):

Hom, I. J. (2007). A methodology for the hardware/software co-design of embedded systems. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/547887/rec/245

Chicago Manual of Style (16^th Edition):

Hom, Ivan Jackson. “A methodology for the hardware/software co-design of embedded systems.” 2007. Doctoral Dissertation, University of Southern California. Accessed March 06, 2021. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/547887/rec/245.

MLA Handbook (7^th Edition):

Hom, Ivan Jackson. “A methodology for the hardware/software co-design of embedded systems.” 2007. Web. 06 Mar 2021.

Vancouver:

Hom IJ. A methodology for the hardware/software co-design of embedded systems. [Internet] [Doctoral dissertation]. University of Southern California; 2007. [cited 2021 Mar 06]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/547887/rec/245.

Council of Science Editors:

Hom IJ. A methodology for the hardware/software co-design of embedded systems. [Doctoral Dissertation]. University of Southern California; 2007. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/547887/rec/245

Texas Tech University

3. Pakala, Pavan. Cache resident self testing on passive loopback board.

Degree: Electrical and Computer Engineering, 2011, Texas Tech University

URL: http://hdl.handle.net/2346/ETD-TTU-2011-08-1788

► Testing of devices is an important factor in the semiconductor industry. There is a constant effort by major semiconductor companies to bring down test cost… (more)

Subjects/Keywords: Cache; Testing; Microprocessor

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APA (6^th Edition):

Pakala, P. (2011). Cache resident self testing on passive loopback board. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/ETD-TTU-2011-08-1788

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Pakala, Pavan. “Cache resident self testing on passive loopback board.” 2011. Thesis, Texas Tech University. Accessed March 06, 2021. http://hdl.handle.net/2346/ETD-TTU-2011-08-1788.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Pakala, Pavan. “Cache resident self testing on passive loopback board.” 2011. Web. 06 Mar 2021.

Vancouver:

Pakala P. Cache resident self testing on passive loopback board. [Internet] [Thesis]. Texas Tech University; 2011. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/2346/ETD-TTU-2011-08-1788.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pakala P. Cache resident self testing on passive loopback board. [Thesis]. Texas Tech University; 2011. Available from: http://hdl.handle.net/2346/ETD-TTU-2011-08-1788

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Singh, Virendra. Instruction-based self-testing of performance oriented faults in modern processors : 高性能プロセッサにおける性能関連故障に対する命令レベル自己テスト; コウセイノウプロセッサニオケルセイノウカンレンコショウニタイスルメイレイレベルジコテスト.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

URL: http://hdl.handle.net/10061/2885

Subjects/Keywords: Microprocessor testing

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APA (6^th Edition):

Singh, V. (n.d.). Instruction-based self-testing of performance oriented faults in modern processors : 高性能プロセッサにおける性能関連故障に対する命令レベル自己テスト; コウセイノウプロセッサニオケルセイノウカンレンコショウニタイスルメイレイレベルジコテスト. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/2885

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Singh, Virendra. “Instruction-based self-testing of performance oriented faults in modern processors : 高性能プロセッサにおける性能関連故障に対する命令レベル自己テスト; コウセイノウプロセッサニオケルセイノウカンレンコショウニタイスルメイレイレベルジコテスト.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed March 06, 2021. http://hdl.handle.net/10061/2885.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Singh, Virendra. “Instruction-based self-testing of performance oriented faults in modern processors : 高性能プロセッサにおける性能関連故障に対する命令レベル自己テスト; コウセイノウプロセッサニオケルセイノウカンレンコショウニタイスルメイレイレベルジコテスト.” Web. 06 Mar 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Singh V. Instruction-based self-testing of performance oriented faults in modern processors : 高性能プロセッサにおける性能関連故障に対する命令レベル自己テスト; コウセイノウプロセッサニオケルセイノウカンレンコショウニタイスルメイレイレベルジコテスト. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10061/2885.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Singh V. Instruction-based self-testing of performance oriented faults in modern processors : 高性能プロセッサにおける性能関連故障に対する命令レベル自己テスト; コウセイノウプロセッサニオケルセイノウカンレンコショウニタイスルメイレイレベルジコテスト. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/2885

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

California State University – Sacramento

5. Singh, Ikraj. Net monitoring system of hand motion capture through accelerometer.

Degree: MS, Electrical and Electronic Engineering, 2011, California State University – Sacramento

URL: http://hdl.handle.net/10211.9/1356

► Internet plays very important role in our lives. Internet brings the whole world to our desktop. The next step would be when we will control… (more)

Subjects/Keywords: Internet accessible device; Rabbit microprocessor

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APA (6^th Edition):

Singh, I. (2011). Net monitoring system of hand motion capture through accelerometer. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/1356

Chicago Manual of Style (16^th Edition):

Singh, Ikraj. “Net monitoring system of hand motion capture through accelerometer.” 2011. Masters Thesis, California State University – Sacramento. Accessed March 06, 2021. http://hdl.handle.net/10211.9/1356.

MLA Handbook (7^th Edition):

Singh, Ikraj. “Net monitoring system of hand motion capture through accelerometer.” 2011. Web. 06 Mar 2021.

Vancouver:

Singh I. Net monitoring system of hand motion capture through accelerometer. [Internet] [Masters thesis]. California State University – Sacramento; 2011. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10211.9/1356.

Council of Science Editors:

Singh I. Net monitoring system of hand motion capture through accelerometer. [Masters Thesis]. California State University – Sacramento; 2011. Available from: http://hdl.handle.net/10211.9/1356

Iowa State University

6. Gorti, Naga Pavan Kumar. Application aware performance, power consumption, and reliability tradeoff.

Degree: 2014, Iowa State University

URL: https://lib.dr.iastate.edu/etd/13933

► There has been an unprecedented increase in the drive for microprocessor performance. This drive is motivated by the increase in software complexity, opportunity to solve… (more)

▼ There has been an unprecedented increase in the drive for microprocessor performance. This drive is motivated by the increase in software complexity, opportunity to solve previously unattempted problems especially in scientific domain, and a need to crunch the ever growing `Big Data' to enable a multitude of technological advances to benefit mankind. A consequence of these phenomena is the ever increasing transistor count in deployed computing systems. Although technology scaling leads to lower power consumption per transistor, the overall system level power consumption is on the rise. This leads to a variety of power supply related issues. As the chip die area is not increasing significantly, and the supply voltage reduction is not keeping on par with the reduction in device dimensions, an increase in power density is observed. This manifests as an increased temperature profile on the chip floorplan. A rise in temperature necessitates aggressive and costly cooling mechanisms adding to the design complexity and manufacturing efforts. It also triggers various failure mechanisms leading to reduction in the expected chip lifetime/reliability. Given the conflicting trends in Performance, Power consumption, and chip Reliability (PPR), it is imperative to balance them in a fine-grained fashion to meet system level goals and expectations. Sole dependence on the advancements in manufacturing technology is no longer sufficient. Alternate venues for PPR management are being increasingly paid attention to. On the other hand, the PPR demands are usually time dependent. For example, the constraint on power consumption in a green data center is dictated by the energy reserve. The demand on performance in a cloud based platform depends on the agreed Quality of Service (QOS) requirements. The reliability of a microprocessor is dependent on the deployment domain. The goal of our research is to address the issue of growing microprocessor power consumption subject to performance and/or reliability goals. Through our developed schemes, we tailor the execution context to match application requirements. This leads to judicious use of power while adhering to aforementioned constraints. It is to be noted that the actual demands on performance, power consumption, and reliability are highly variant, and depend upon executing applications and operating conditions. As such, we develop schemes to cater to these variant demands. To meet these demands efficiently, the solutions developed are tailored to current hardware-software interaction characteristics. Two techniques that are very relevant in this area, namely dynamic voltage and frequency scaling (DVFS) and microarchitectural adaptation, are leveraged to produce expected PPR characteristics when executing a wide variety of tasks. In this dissertation, we demonstrate how the expected chip lifetime can be augmented in a real-time setting using DVFS while paying heed to performance constraints modeled as QoS requirements. Individual tasks in a task queue are assigned specific voltage and…

Subjects/Keywords: Application aware computing; Dynamic voltage and frequency scaling; Microarchitectural adaptation; Microprocessor performance; Microprocessor power consumption; Microprocessor reliability; Computer Engineering

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APA (6^th Edition):

Gorti, N. P. K. (2014). Application aware performance, power consumption, and reliability tradeoff. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/13933

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Gorti, Naga Pavan Kumar. “Application aware performance, power consumption, and reliability tradeoff.” 2014. Thesis, Iowa State University. Accessed March 06, 2021. https://lib.dr.iastate.edu/etd/13933.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Gorti, Naga Pavan Kumar. “Application aware performance, power consumption, and reliability tradeoff.” 2014. Web. 06 Mar 2021.

Vancouver:

Gorti NPK. Application aware performance, power consumption, and reliability tradeoff. [Internet] [Thesis]. Iowa State University; 2014. [cited 2021 Mar 06]. Available from: https://lib.dr.iastate.edu/etd/13933.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gorti NPK. Application aware performance, power consumption, and reliability tradeoff. [Thesis]. Iowa State University; 2014. Available from: https://lib.dr.iastate.edu/etd/13933

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Kaushik, kalpana. Design and development of microprocessor based data acquisition and control system; -.

Degree: Physics, 1991, INFLIBNET

URL: http://shodhganga.inflibnet.ac.in/handle/10603/41066

None

Bibliography given

Advisors/Committee Members: Varma, H V.

Subjects/Keywords: Data acquisition; Microprocessor

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APA (6^th Edition):

Kaushik, k. (1991). Design and development of microprocessor based data acquisition and control system; -. (Thesis). INFLIBNET. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/41066

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Kaushik, kalpana. “Design and development of microprocessor based data acquisition and control system; -.” 1991. Thesis, INFLIBNET. Accessed March 06, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/41066.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Kaushik, kalpana. “Design and development of microprocessor based data acquisition and control system; -.” 1991. Web. 06 Mar 2021.

Vancouver:

Kaushik k. Design and development of microprocessor based data acquisition and control system; -. [Internet] [Thesis]. INFLIBNET; 1991. [cited 2021 Mar 06]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/41066.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kaushik k. Design and development of microprocessor based data acquisition and control system; -. [Thesis]. INFLIBNET; 1991. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/41066

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Durham University

8. Flaxman, J. W. Multi-microprocessor power system simulation.

Degree: PhD, 1987, Durham University

URL: http://etheses.dur.ac.uk/6762/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.379728

► This thesis presents the results of research performed into the simulation of electrical power systems using a set of microprocessors operating in parallel , The… (more)

Subjects/Keywords: 621.39; Microprocessor simulation

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APA (6^th Edition):

Flaxman, J. W. (1987). Multi-microprocessor power system simulation. (Doctoral Dissertation). Durham University. Retrieved from http://etheses.dur.ac.uk/6762/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.379728

Chicago Manual of Style (16^th Edition):

Flaxman, J W. “Multi-microprocessor power system simulation.” 1987. Doctoral Dissertation, Durham University. Accessed March 06, 2021. http://etheses.dur.ac.uk/6762/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.379728.

MLA Handbook (7^th Edition):

Flaxman, J W. “Multi-microprocessor power system simulation.” 1987. Web. 06 Mar 2021.

Vancouver:

Flaxman JW. Multi-microprocessor power system simulation. [Internet] [Doctoral dissertation]. Durham University; 1987. [cited 2021 Mar 06]. Available from: http://etheses.dur.ac.uk/6762/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.379728.

Council of Science Editors:

Flaxman JW. Multi-microprocessor power system simulation. [Doctoral Dissertation]. Durham University; 1987. Available from: http://etheses.dur.ac.uk/6762/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.379728

Texas Tech University

9. Syu, Chien-chi. A multiple MC68000 microcomputer system.

Degree: Computer Science, 1986, Texas Tech University

URL: http://hdl.handle.net/2346/19271

► In this thesis, the design, construction and evaluation of a multiple processor microcomputer system are presented. The design logic of the system is discussed through… (more)

Subjects/Keywords: Motorola 68000 (Microprocessor)

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APA (6^th Edition):

Syu, C. (1986). A multiple MC68000 microcomputer system. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/19271

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Syu, Chien-chi. “A multiple MC68000 microcomputer system.” 1986. Thesis, Texas Tech University. Accessed March 06, 2021. http://hdl.handle.net/2346/19271.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Syu, Chien-chi. “A multiple MC68000 microcomputer system.” 1986. Web. 06 Mar 2021.

Vancouver:

Syu C. A multiple MC68000 microcomputer system. [Internet] [Thesis]. Texas Tech University; 1986. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/2346/19271.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Syu C. A multiple MC68000 microcomputer system. [Thesis]. Texas Tech University; 1986. Available from: http://hdl.handle.net/2346/19271

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

10. Velím, Michael. Luxmetr: Luxmeter.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/60495

► This thesis deals with the matter of measuring working light with the aim to design a luxmeter with the range of 50 – 1000 lx.… (more)

Subjects/Keywords: Luxmetr; fotodioda; mikroprocesor; Luxmeter; photodiode; microprocessor

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APA (6^th Edition):

Velím, M. (2019). Luxmetr: Luxmeter. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/60495

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Velím, Michael. “Luxmetr: Luxmeter.” 2019. Thesis, Brno University of Technology. Accessed March 06, 2021. http://hdl.handle.net/11012/60495.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Velím, Michael. “Luxmetr: Luxmeter.” 2019. Web. 06 Mar 2021.

Vancouver:

Velím M. Luxmetr: Luxmeter. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/11012/60495.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Velím M. Luxmetr: Luxmeter. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/60495

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

11. Hána, Jan. Výukový laboratorní přípravek pro mikroprocesorovou techniku: Educational laboratory kit for microprocessor technique.

Degree: 2018, Brno University of Technology

URL: http://hdl.handle.net/11012/2314

Thesis deals with support of educational courses focused to single chip microprocessors in secondary schools. It includes a text introducing students to the use of single microprocessor and provides examples to their applications. Advisors/Committee Members: Kolouch, Jaromír (advisor), Chmelař, Milan (referee).

Subjects/Keywords: Mikroprocesor; Atmega162; Modul; Microprocessor; Atmega162; Module

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APA (6^th Edition):

Hána, J. (2018). Výukový laboratorní přípravek pro mikroprocesorovou techniku: Educational laboratory kit for microprocessor technique. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/2314

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hána, Jan. “Výukový laboratorní přípravek pro mikroprocesorovou techniku: Educational laboratory kit for microprocessor technique.” 2018. Thesis, Brno University of Technology. Accessed March 06, 2021. http://hdl.handle.net/11012/2314.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hána, Jan. “Výukový laboratorní přípravek pro mikroprocesorovou techniku: Educational laboratory kit for microprocessor technique.” 2018. Web. 06 Mar 2021.

Vancouver:

Hána J. Výukový laboratorní přípravek pro mikroprocesorovou techniku: Educational laboratory kit for microprocessor technique. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/11012/2314.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hána J. Výukový laboratorní přípravek pro mikroprocesorovou techniku: Educational laboratory kit for microprocessor technique. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/2314

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

12. Fadrný, Jaroslav. Měřič rychlosti RC modelů aut: RC car model speedmeter.

Degree: 2018, Brno University of Technology

URL: http://hdl.handle.net/11012/9999

► The aim of bachelor´s thesis is to design a device to measure speed, acceleration and overload for RC model car. The device measured data will… (more)

Subjects/Keywords: Telemetrie; Akcelerometr; Mikroprocesor; Telemetry; Accelerometer; Microprocessor

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APA (6^th Edition):

Fadrný, J. (2018). Měřič rychlosti RC modelů aut: RC car model speedmeter. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/9999

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Fadrný, Jaroslav. “Měřič rychlosti RC modelů aut: RC car model speedmeter.” 2018. Thesis, Brno University of Technology. Accessed March 06, 2021. http://hdl.handle.net/11012/9999.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Fadrný, Jaroslav. “Měřič rychlosti RC modelů aut: RC car model speedmeter.” 2018. Web. 06 Mar 2021.

Vancouver:

Fadrný J. Měřič rychlosti RC modelů aut: RC car model speedmeter. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/11012/9999.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fadrný J. Měřič rychlosti RC modelů aut: RC car model speedmeter. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/9999

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Queens University

13. Hoshino, Robert. Investigating the Feasibility of Asynchronous Design Methodologies in Large-scale Microprocessor Systems .

Degree: Electrical and Computer Engineering, 2007, Queens University

URL: http://hdl.handle.net/1974/949

► Microprocessor systems have been advancing at a phenomenal rate, with each new generation introducing improved fabrication processes and architectural innovations. Unfortunately, traditional fabrication techniques cannot… (more)

▼ Microprocessor systems have been advancing at a phenomenal rate, with each new generation introducing improved fabrication processes and architectural innovations. Unfortunately, traditional fabrication techniques cannot sustain this exponential growth indefinitely. Thus, additional research into conventional design methodologies, such as those involving asynchronous design techniques, is essential to maintain the current trend. The primary objective of this research was to explore the viability of asynchronous design techniques as an alternative to current synchronous design methods. In order to simulate the design complexities involved in a real-world system, the MIPS-II R2000 pipelined microprocessor was selected as the basis for comparison. All of the experimental processors were designed in VHDL on an FPGA using the Altera Quartus II design package. The processors were tested using timing simulations with various benchmarks to determine the advantages and disadvantages of each design technique. Four distinct asynchronous processors with varying handshaking and synchronization methods were designed and compared to the baseline synchronous processor. Although, in theory, each of the asynchronous design variations had its merits, it was clear that not all of them were well suited for practical use in a large-scale microprocessor environment. Three of the asynchronous processors suffered from an excessive amount of synchronization overhead that drastically reduced their overall system performance to the point where they performed considerably worse than the baseline synchronous processor. However, one asynchronous processor performed considerably better: with only a 1.5 percent increase in logic complexity, it outperformed the baseline synchronous processor by over 10 percent on a sorting test benchmark and had a maximum theoretical speedup of over 36 percent. Therefore, it is evident that asynchronous designs have the potential to improve the performance of traditional synchronous systems. However, designing efficient and hazard-free asynchronous logic on an FPGA proved to be challenging and time-consuming. With additional research and further design tool improvements to facilitate the creation of optimized glitch-free logic, asynchronous design methodologies may become a viable alternative to traditional synchronous designs and contribute to the current trend of microprocessor advancement.

Subjects/Keywords: Asynchronous ; Microprocessor ; MIPS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hoshino, R. (2007). Investigating the Feasibility of Asynchronous Design Methodologies in Large-scale Microprocessor Systems . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/949

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hoshino, Robert. “Investigating the Feasibility of Asynchronous Design Methodologies in Large-scale Microprocessor Systems .” 2007. Thesis, Queens University. Accessed March 06, 2021. http://hdl.handle.net/1974/949.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hoshino, Robert. “Investigating the Feasibility of Asynchronous Design Methodologies in Large-scale Microprocessor Systems .” 2007. Web. 06 Mar 2021.

Vancouver:

Hoshino R. Investigating the Feasibility of Asynchronous Design Methodologies in Large-scale Microprocessor Systems . [Internet] [Thesis]. Queens University; 2007. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1974/949.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hoshino R. Investigating the Feasibility of Asynchronous Design Methodologies in Large-scale Microprocessor Systems . [Thesis]. Queens University; 2007. Available from: http://hdl.handle.net/1974/949

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade do Rio Grande do Sul

14. Wilke, Gustavo Reis. Analysis and optimization of mesh-based clock distribution architectures.

Degree: 2008, Universidade do Rio Grande do Sul

URL: http://hdl.handle.net/10183/15507

►

Variações ambientais e de processo representam um grande desafio a ser vencido pelas redes de distribuição de relógio. O efeito das variações nos atrasos da… (more)

▼

Variações ambientais e de processo representam um grande desafio a ser vencido pelas redes de distribuição de relógio. O efeito das variações nos atrasos da rede de distribuição de relógio não pode ser previsto com precisão e portanto não podem ser diretamente considerados no projeto das redes de distribuição de relógio. Estruturas baseadas em clock meshes (i.e. clock mesh, clock spines e crosslinks) são a maneira mais eficiente de proteger a rede de relógio do efeito das variações nos atrasos. Clock meshes tem sido utilizados por bastante tempo no projeto de microprocessadores e recentemente foram incluídos no fluxo de síntese de ASICs. Embora o uso de clock meshes esteja aumentando há uma grande necessidade por métodos de analise e otimização dos mesmos. Essa tese propõe soluções para ambos os problemas. Uma metodologia para permitir a simulação elétrica de clock meshes grandes é proposta. O método proposto permite que a simulação dos clock meshes seja paralelizada com um erro menor que 1%. Duas metodologias de otimização também são propostas nessa tese. A primeira consiste em um algoritmo para dimensionamento para os mesh buffers. Esse algoritmo permite que o clock skew e o consumo de potência sejam reduzidos ao custo de aumentar o clock slew. O segundo método de otimização proposto consiste em um novo projeto para os mesh buffers. O novo mesh buffer é capaz de reduzir o clock skew em 22% e o consumo de potencia em 59%.

Process and environmental variations are a great challenge to clock network designers. Variations effect on the clock network delays can not be predicted, hence it can not be directly accounted in the design stage. Clock mesh-based structures (i.e. clock mesh, clock spines and crosslinks) are the most effective way to tolerate variation effects on delays. Clock meshes have been used for a long time in microprocessor designs and recently became supported by commercial tools in the ASIC design flow. Although clock meshes have been known for some time and its use in ASIC design is increasing, there is a lack of good analysis and optimization strategies for clock meshes. This thesis tackles both problems. Chapter 1 presents a basic introduction to clock distribution and important definitions. A review of existent clock dsitribution design strategies is presented in chapter 2. A study about the clock distribution architecture used in several microprocessor and a comparison between mesh-based and pure tree clock distribution architectures is shown in chapter 3.2. A methodology for enabling and speeding up the simulation of large clock meshes is presented in chapter 4. The proposed analysis methodology was shown to enable the parallel evaluation of large clock meshes with an error smaller than 1%. Chapter 5 presents two optimization strategies, a new mesh buffer design and a mesh buffer sizing algorithm. The new mesh buffer design was proposed improving clock skew by 22% and clock power by 59%. The mesh buffer sizing algorithm can reduce clock skew by 33%, power consumption by 20% with at the cost of…

Advisors/Committee Members: Reis, Ricardo Augusto da Luz.

Subjects/Keywords: Clock; Microeletrônica; Clock mesh; Sistemas digitais; Skew; High performance; Microprocessor; Variability

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APA (6^th Edition):

Wilke, G. R. (2008). Analysis and optimization of mesh-based clock distribution architectures. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/15507

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wilke, Gustavo Reis. “Analysis and optimization of mesh-based clock distribution architectures.” 2008. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021. http://hdl.handle.net/10183/15507.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wilke, Gustavo Reis. “Analysis and optimization of mesh-based clock distribution architectures.” 2008. Web. 06 Mar 2021.

Vancouver:

Wilke GR. Analysis and optimization of mesh-based clock distribution architectures. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2008. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10183/15507.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wilke GR. Analysis and optimization of mesh-based clock distribution architectures. [Thesis]. Universidade do Rio Grande do Sul; 2008. Available from: http://hdl.handle.net/10183/15507

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade do Rio Grande do Sul

15. Flach, Guilherme Augusto. Clock mesh optimization.

Degree: 2010, Universidade do Rio Grande do Sul

URL: http://hdl.handle.net/10183/34773

►

Malhas de relógio são arquiteturas de rede de relógio adequadas para distribuir confiavelmente o sinal de relógio na presença de variações de processo e ambientais.… (more)

▼

Malhas de relógio são arquiteturas de rede de relógio adequadas para distribuir confiavelmente o sinal de relógio na presença de variações de processo e ambientais. Tal propriedade se torna muito importante nas tecnologias submicrônicas onde variações têm um papel importante. A confiabilidade da malha de relógio é devido aos caminhos redundantes conectando o sinal de relógio até os receptores de forma que variações afetando um caminho possam ser compensadas pelos outros caminhos. A confiabilidade vem ao custo de mais consumo de potência e fiação. Desta forma fica claro o balanceamento necessário entre distribuir confiavelmente o sinal de relógio (mais redundância) e o consumo de potência e aumento de fiação. O clock skew é definido como a diferença entre os tempos de chegada do sinal de clock nos seus receptores. Quanto maior é o clock skew, mais lento o circuito precisa operar. Além de diminuir a velocidade do circuito, um valor alto de clock skew aumenta a probabilidade de o circuito não funcionar devido às variações. Neste trabalho, nos focamos no problema de clock skew. Inicialmente extraímos informações úteis de como o comprimento da fiação e a capacitância variam a medida que o tamanho da malha varia. São apresentadas fórmulas analíticas que encontram o tamanho ótimo para ambos objetivos e é apresentado um estudo de como o clock skew varia a medida que nos afastamos do tamanho ótimo da malha de relógio. Um método para a redução de clock skew através do deslocamento dos buffers também é apresentado. Tal melhoria no clock skew não afeta o consumo de potência já que o tamanho dos buffers e a malha não são alterados.

Clock meshes are a suitable clock network architecture for reliably distributing the clock signal under process and environmental variations. This property becomes very important in the deep sub-micron technology where variations play a main role. The clock mesh reliability is due to redundant paths connecting clock buffers to clock sinks, so that variations affecting one path can be compensated by other paths. This comes at cost of more power consumption and wiring resources. Therefore it is clear the tradeoff between reliably distributing the clock signal (more redundancy) and the power and resource consumption. The clock skew is defined as the difference in the arrival time of clock signal at clock sinks. The higher is the clock skew, the slower is the circuit. Besides slowing down the circuit operation, a high clock skew increases the probability of circuit malfunction due to variations. In this work we focus on the clock skew problem. We first extract some useful information on how the clock wirelength and capacitance change as the mesh size changes. We present analytical formulas to find the optimum mesh size for both goals and study how the clock skew varies as we move further away from the optimum mesh size. We also present a method for reducing the clock mesh skew by sliding buffers from the position where they are traditionally placed. This improvement comes at no increasing cost of power…

Advisors/Committee Members: Johann, Marcelo de Oliveira.

Subjects/Keywords: Clock; Microeletrônica; Clock mesh; Microprocessadores; Skew; Performance; Microprocessor; Variability; Microelectronic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Flach, G. A. (2010). Clock mesh optimization. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/34773

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Flach, Guilherme Augusto. “Clock mesh optimization.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021. http://hdl.handle.net/10183/34773.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Flach, Guilherme Augusto. “Clock mesh optimization.” 2010. Web. 06 Mar 2021.

Vancouver:

Flach GA. Clock mesh optimization. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10183/34773.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Flach GA. Clock mesh optimization. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/34773

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

16. Sung, Yu-Wen. Microarchitecture Evaluations and Improvements of ARM Microprocessorâs Architecture Features.

Degree: Master, Computer Science and Engineering, 2003, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0903103-071552

► All of the communication, IA, and the cellular phone need the capabilities which can be provided by the ARM microprocessor that has the advantages with… (more)

Subjects/Keywords: Architecture; Evaluation; Improvement; Microprocessor; ARM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Sung, Y. (2003). Microarchitecture Evaluations and Improvements of ARM Microprocessorâs Architecture Features. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0903103-071552

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Sung, Yu-Wen. “Microarchitecture Evaluations and Improvements of ARM Microprocessorâs Architecture Features.” 2003. Thesis, NSYSU. Accessed March 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0903103-071552.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Sung, Yu-Wen. “Microarchitecture Evaluations and Improvements of ARM Microprocessorâs Architecture Features.” 2003. Web. 06 Mar 2021.

Vancouver:

Sung Y. Microarchitecture Evaluations and Improvements of ARM Microprocessorâs Architecture Features. [Internet] [Thesis]. NSYSU; 2003. [cited 2021 Mar 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0903103-071552.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sung Y. Microarchitecture Evaluations and Improvements of ARM Microprocessorâs Architecture Features. [Thesis]. NSYSU; 2003. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0903103-071552

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

17. Chen, Yi-Chieh. A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713

► We present an integrated development environment (IDE) with GUI for generating and evaluating the fault-tolerant microprocessor. Designer can select from hardware options (dual-core for microprocessor,… (more)

Subjects/Keywords: Fault-Tolerant; Microprocessor; Memory; Fault Injection; Fault Coverage

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APA (6^th Edition):

Chen, Y. (2015). A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Yi-Chieh. “A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches.” 2015. Thesis, NSYSU. Accessed March 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Yi-Chieh. “A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches.” 2015. Web. 06 Mar 2021.

Vancouver:

Chen Y. A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Mar 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

18. Lin, Chun-Shou. Design and verification of an ARM10-like Processor and its System Integration.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403

► With the advanced of the technique, we can design more IP in the same area space chip. The embedded system has more powerful about its… (more)

Subjects/Keywords: Integration; Embedded in circuit emulator (EICE); Microprocessor; Verification; Cache/MMU; Coprocessor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, C. (2012). Design and verification of an ARM10-like Processor and its System Integration. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Chun-Shou. “Design and verification of an ARM10-like Processor and its System Integration.” 2012. Thesis, NSYSU. Accessed March 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Chun-Shou. “Design and verification of an ARM10-like Processor and its System Integration.” 2012. Web. 06 Mar 2021.

Vancouver:

Lin C. Design and verification of an ARM10-like Processor and its System Integration. [Internet] [Thesis]. NSYSU; 2012. [cited 2021 Mar 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Design and verification of an ARM10-like Processor and its System Integration. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Poulose Jacob,K. Some Studies and New Results on Multi Microprocessor Applications.

Degree: Electronics, 1991, Cochin University of Science and Technology

URL: http://dyuthi.cusat.ac.in/purl/2195

►

One of the fastest expanding areas of computer exploitation is in embedded systems, whose prime function is not that of computing, but which nevertheless require… (more)

Subjects/Keywords: Multi microprocessor applications; Microprocessors

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APA (6^th Edition):

Jacob,K, P. (1991). Some Studies and New Results on Multi Microprocessor Applications. (Thesis). Cochin University of Science and Technology. Retrieved from http://dyuthi.cusat.ac.in/purl/2195

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Jacob,K, Poulose. “Some Studies and New Results on Multi Microprocessor Applications.” 1991. Thesis, Cochin University of Science and Technology. Accessed March 06, 2021. http://dyuthi.cusat.ac.in/purl/2195.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Jacob,K, Poulose. “Some Studies and New Results on Multi Microprocessor Applications.” 1991. Web. 06 Mar 2021.

Vancouver:

Jacob,K P. Some Studies and New Results on Multi Microprocessor Applications. [Internet] [Thesis]. Cochin University of Science and Technology; 1991. [cited 2021 Mar 06]. Available from: http://dyuthi.cusat.ac.in/purl/2195.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jacob,K P. Some Studies and New Results on Multi Microprocessor Applications. [Thesis]. Cochin University of Science and Technology; 1991. Available from: http://dyuthi.cusat.ac.in/purl/2195

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Rochester Institute of Technology

20. Iyer, Ramakrishnan. Software simulation of MC68000.

Degree: MS, Computer Science (GCCIS), 1986, Rochester Institute of Technology

URL: https://scholarworks.rit.edu/theses/900

► The introduction of the Motorola MC68000 family of microprocessors ushered in a new era of microprocessors. These are single-chip microprocessors designed to function as… (more)

Subjects/Keywords: Computer simulation; Motorola 68000 (Microprocessor)

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APA (6^th Edition):

Iyer, R. (1986). Software simulation of MC68000. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/900

Chicago Manual of Style (16^th Edition):

Iyer, Ramakrishnan. “Software simulation of MC68000.” 1986. Masters Thesis, Rochester Institute of Technology. Accessed March 06, 2021. https://scholarworks.rit.edu/theses/900.

MLA Handbook (7^th Edition):

Iyer, Ramakrishnan. “Software simulation of MC68000.” 1986. Web. 06 Mar 2021.

Vancouver:

Iyer R. Software simulation of MC68000. [Internet] [Masters thesis]. Rochester Institute of Technology; 1986. [cited 2021 Mar 06]. Available from: https://scholarworks.rit.edu/theses/900.

Council of Science Editors:

Iyer R. Software simulation of MC68000. [Masters Thesis]. Rochester Institute of Technology; 1986. Available from: https://scholarworks.rit.edu/theses/900

Rochester Institute of Technology

21. Chapman, William A. A Simulator for the Intel 8086 microprocessor.

Degree: Electrical Engineering, 1988, Rochester Institute of Technology

URL: https://scholarworks.rit.edu/theses/6866

► This project was originally suggested by J. Schueckler as an aid to teaching students the Intel 8086 Assembly Language. The need for such a… (more)

Subjects/Keywords: Intel 8086 microprocessor; Pascal; Simulators

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chapman, W. A. (1988). A Simulator for the Intel 8086 microprocessor. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/6866

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chapman, William A. “A Simulator for the Intel 8086 microprocessor.” 1988. Thesis, Rochester Institute of Technology. Accessed March 06, 2021. https://scholarworks.rit.edu/theses/6866.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chapman, William A. “A Simulator for the Intel 8086 microprocessor.” 1988. Web. 06 Mar 2021.

Vancouver:

Chapman WA. A Simulator for the Intel 8086 microprocessor. [Internet] [Thesis]. Rochester Institute of Technology; 1988. [cited 2021 Mar 06]. Available from: https://scholarworks.rit.edu/theses/6866.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chapman WA. A Simulator for the Intel 8086 microprocessor. [Thesis]. Rochester Institute of Technology; 1988. Available from: https://scholarworks.rit.edu/theses/6866

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Utah

22. Wallace, William Dean. New concepts for achieving accuracy and reliability in blood-gas analysis;.

Degree: PhD, Biomedical Informatics;, 1982, University of Utah

URL: http://content.lib.utah.edu/cdm/singleitem/collection/etd1/id/1479/rec/879

► Blood-gas analysis must be accurate because small changes in the measured variables of blood oxygen and carbon dioxide can be clinically significant. Reliability and accuracy… (more)

Subjects/Keywords: Instrumentation; Microprocessor; Blood-gas Instruments

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APA (6^th Edition):

Wallace, W. D. (1982). New concepts for achieving accuracy and reliability in blood-gas analysis;. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd1/id/1479/rec/879

Chicago Manual of Style (16^th Edition):

Wallace, William Dean. “New concepts for achieving accuracy and reliability in blood-gas analysis;.” 1982. Doctoral Dissertation, University of Utah. Accessed March 06, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd1/id/1479/rec/879.

MLA Handbook (7^th Edition):

Wallace, William Dean. “New concepts for achieving accuracy and reliability in blood-gas analysis;.” 1982. Web. 06 Mar 2021.

Vancouver:

Wallace WD. New concepts for achieving accuracy and reliability in blood-gas analysis;. [Internet] [Doctoral dissertation]. University of Utah; 1982. [cited 2021 Mar 06]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd1/id/1479/rec/879.

Council of Science Editors:

Wallace WD. New concepts for achieving accuracy and reliability in blood-gas analysis;. [Doctoral Dissertation]. University of Utah; 1982. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd1/id/1479/rec/879

University of Oulu

23. Vallius, T. (Tero). An embedded object approach to embedded system development.

Degree: 2009, University of Oulu

URL: http://urn.fi/urn:isbn:9789514292941

► Abstract Building an embedded system from an idea to a product is a slow and expensive process requiring a lot of expertise. Depending on the… (more)

▼ Abstract Building an embedded system from an idea to a product is a slow and expensive process requiring a lot of expertise. Depending on the developer’s expertise, the required quantity and price level of the final product, and the time and money available for development, the developer can build a device from different granularity of components, ranging from ready-made platforms, kits, and modules to individual components. Generally, solutions requiring less expertise, time and money produce products with higher production costs. The main contribution of this thesis is the EOC (Embedded Object Concept) and Atomi II Framework. EOC utilizes common object-oriented methods used in software by applying them to small electronic modules, which create complete functional entities. The conceptual idea of the embedded objects is implemented with the Atomi II framework, which contains several techniques for making the EOC a commercially feasible implementation. The EOC and the Atomi II Framework decreases the difficulty level of making embedded systems by enabling a use of ready-made modules to build systems. It enables automatic conversion of a device made from such modules into an integrated PCB, lowering production costs compared to other modular approaches. Furthermore, it also enables an automatic production tester generation due to its modularity. These properties lower the number of skills required for building an embedded system and quicken the path from an idea to a commercially applicable device. A developer can also build custom modules of his own if he possesses the required expertise. The test cases demonstrate the Atomi II Framework techniques in real world applications, and demonstrate the capabilities of Atomi objects. According to our test cases and estimations, an Atomi based device becomes approximately 10% more expensive than a device built from individual components, but saves up to 50% time, making it feasible to manufacture up to 10-50k quantities with this approach.

Subjects/Keywords: embedded systems; microprocessor applications; modularity; object-oriented design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Vallius, T. (. (2009). An embedded object approach to embedded system development. (Doctoral Dissertation). University of Oulu. Retrieved from http://urn.fi/urn:isbn:9789514292941

Chicago Manual of Style (16^th Edition):

Vallius, T (Tero). “An embedded object approach to embedded system development.” 2009. Doctoral Dissertation, University of Oulu. Accessed March 06, 2021. http://urn.fi/urn:isbn:9789514292941.

MLA Handbook (7^th Edition):

Vallius, T (Tero). “An embedded object approach to embedded system development.” 2009. Web. 06 Mar 2021.

Vancouver:

Vallius T(. An embedded object approach to embedded system development. [Internet] [Doctoral dissertation]. University of Oulu; 2009. [cited 2021 Mar 06]. Available from: http://urn.fi/urn:isbn:9789514292941.

Council of Science Editors:

Vallius T(. An embedded object approach to embedded system development. [Doctoral Dissertation]. University of Oulu; 2009. Available from: http://urn.fi/urn:isbn:9789514292941

Anna University

24. Dhurga devi J. Investigations on performance Improvements of self biased Adaptive bandwidth PLLS;.

Degree: Investigations on performance Improvements of self biased Adaptive bandwidth PLLS, 2015, Anna University

URL: http://shodhganga.inflibnet.ac.in/handle/10603/49446

►

The present research work attempts a number of modifications of newlinethe well established self biased adaptive bandwidth Phase Locked Loop newline PLLs These modifications are… (more)

Subjects/Keywords: Delay Locked Loop; Microprocessor clock generation; Phase Locked Loop

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APA (6^th Edition):

J, D. d. (2015). Investigations on performance Improvements of self biased Adaptive bandwidth PLLS;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/49446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

J, Dhurga devi. “Investigations on performance Improvements of self biased Adaptive bandwidth PLLS;.” 2015. Thesis, Anna University. Accessed March 06, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/49446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

J, Dhurga devi. “Investigations on performance Improvements of self biased Adaptive bandwidth PLLS;.” 2015. Web. 06 Mar 2021.

Vancouver:

J Dd. Investigations on performance Improvements of self biased Adaptive bandwidth PLLS;. [Internet] [Thesis]. Anna University; 2015. [cited 2021 Mar 06]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/49446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

J Dd. Investigations on performance Improvements of self biased Adaptive bandwidth PLLS;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/49446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Penn State University

25. Kanani, Jesal Hiren. Cryptographic Module for Wireless Sensor Nodes Complying with FIPS 140-2 .

Degree: 2009, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/9697

► Cryptography is one of the leading techniques today for ensuring safety in a communications system. Apart from the military use, the information revolution caused by… (more)

▼ Cryptography is one of the leading techniques today for ensuring safety in a communications system. Apart from the military use, the information revolution caused by the recent development of computer science has yielded higher and higher demand for the commercial use of cryptography. As a result many ciphering algorithms have been developed in the past and are being continuously researched. Modern ciphering modules include techniques of implementing these crypto algorithms into them in the form of either hardware or software or both, the end result being a safe and secure communication channel. Looking at the growing research done in this field along with new ways of breaking ciphers, the National Institute for Standard and Technology (NIST) published a standard called the Federal Information Processing Standard (FIPS) in January 1994. The FIPS calls for a uniform pattern that is to be used by federal organizations during the implementation of cryptographic-based security systems that deals with sensitive and valuable data. The standard provides security requirements covering areas related to secure design and implementation of a cryptographic module. It provides four increasing, quantitative levels of security intended to cover a wide range of potential applications and environments. The thesis presents a framework for a Cryptographic Module for wireless sensor nodes complying with FIPS 140-2. The module will be installed on Navy ships along with existing wireless sensor nodes and hence comes the FIPS validation requirement. The module is being implemented on a Texas Instrument MSP430 micro-processor and the IAR embedded workbench programming and compiling. Since the crypto module needs to comply with the FIPS, the ciphering algorithm used is the Advanced Encryption Standard (AES) as it is a FIPS approved algorithm. Given the requirements, the module will be primarily responsible for the I/O of binary data to and from the master controller and ciphering and deciphering of this data using the AES ciphering algorithm along with various authentication and error checking techniques. The presented architecture and hence the crypto module can be used for several other applications except the mentioned use with sensor nodes and can be made commercially available by the company supporting its development. Advisors/Committee Members: Sven G Bilen, Thesis Advisor/Co-Advisor, Sven G Bilen, Thesis Advisor/Co-Advisor, Julio Urbina, Thesis Advisor/Co-Advisor.

Subjects/Keywords: Microprocessor; embedded; Cryptography; MSP430; AES

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APA (6^th Edition):

Kanani, J. H. (2009). Cryptographic Module for Wireless Sensor Nodes Complying with FIPS 140-2 . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/9697

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Kanani, Jesal Hiren. “Cryptographic Module for Wireless Sensor Nodes Complying with FIPS 140-2 .” 2009. Thesis, Penn State University. Accessed March 06, 2021. https://submit-etda.libraries.psu.edu/catalog/9697.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Kanani, Jesal Hiren. “Cryptographic Module for Wireless Sensor Nodes Complying with FIPS 140-2 .” 2009. Web. 06 Mar 2021.

Vancouver:

Kanani JH. Cryptographic Module for Wireless Sensor Nodes Complying with FIPS 140-2 . [Internet] [Thesis]. Penn State University; 2009. [cited 2021 Mar 06]. Available from: https://submit-etda.libraries.psu.edu/catalog/9697.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kanani JH. Cryptographic Module for Wireless Sensor Nodes Complying with FIPS 140-2 . [Thesis]. Penn State University; 2009. Available from: https://submit-etda.libraries.psu.edu/catalog/9697

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Penn State University

26. Quarles, Kaycee Andrea. The Impact of Primary MicroRNA Structure on Recognition by the Microprocessor Complex in MicroRNA Maturation.

Degree: 2015, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/24430

► Since their discovery over a decade ago, thousands of microRNAs (miRNAs) have been found across all multicellular organisms. These RNAs in combination with small interfering… (more)

▼ Since their discovery over a decade ago, thousands of microRNAs (miRNAs) have been found across all multicellular organisms. These RNAs in combination with small interfering RNAs (siRNAs) make up the RNA silencing pathway, also called the RNA interference (RNAi) pathway. Mature miRNAs are ~22-nucleotide-long, single-stranded non-coding RNAs that participate in various cellular, developmental, and differentiation processes via post-transcriptional regulation of gene expression for more than 90% of human genes. Therefore, these key RNAs have been linked to several disease states including cancer, neurodegenerative diseases, cardiac disease, diabetes, and numerous viral diseases. Recently, they have become a key target for the medical RNA therapeutics community. The human canonical miRNA maturation pathway involves a series of cleavage steps beginning in the nucleus and ending in the cytoplasm, where the final mature miRNA down-regulates gene expression via “silencing” messenger RNA translation. Therefore, these small RNAs down-regulate the expression of every protein within an organism; thus, potentially controlling all bodily processes. The first processing step in the nucleus involves cleavage of the miRNA precursor by the Microprocessor complex, consisting minimally of the RNase III enzyme Drosha and the double-stranded RNA (dsRNA) binding protein DGCR8. The second processing step involves an analogous complex consisting minimally of the RNase III enzyme Dicer and the dsRNA binding protein TRBP. This pathway is unique because all of these mentioned proteins contain dsRNA binding domains (dsRBDs) that help to recognize the miRNA precursors in the cell. However, much is still unknown about the processing of these miRNA precursors into their final mature forms. Although it is known that both Drosha and DGCR8 are required for Microprocessor activity, the molecular mechanism of RNA substrate recognition by these proteins is still not fully known. In particular, the means by which Drosha locates and recognizes the exact cleavage site on the RNA plays a critical role in Microprocessor efficiency and must be known to fully understand miRNA biogenesis. Literature suggests that the recognition and cleavage of miRNA precursors is in part based on unique structural characteristics of the RNA, which guide the proteins to their cut-site locations. However, there are currently no experimentally-determined structures of entire miRNA precursors. Therefore, it is necessary to biochemically determine native solution structures of these RNAs as they would be seen by the Microprocessor if the maturation process at the molecular level is to be characterized. Atomic resolution methods for RNA structure determination pose several challenges that are not yet overcome; however, a variety of RNA secondary structure mapping and RNA modeling techniques have proven successful for determining structures of other large RNAs comparable to those encountered in this pathway. Therefore, a primary aim for this thesis was to combine these approaches… Advisors/Committee Members: Scott A Showalter, Dissertation Advisor/Co-Advisor, Philip C. Bevilacqua, Committee Member, Christine Dolan Keating, Committee Member, Katsuhiko Murakami, Committee Member.

Subjects/Keywords: RNA structure; Microprocessor; microRNA; protein binding; DGCR8; EMSA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Quarles, K. A. (2015). The Impact of Primary MicroRNA Structure on Recognition by the Microprocessor Complex in MicroRNA Maturation. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/24430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Quarles, Kaycee Andrea. “The Impact of Primary MicroRNA Structure on Recognition by the Microprocessor Complex in MicroRNA Maturation.” 2015. Thesis, Penn State University. Accessed March 06, 2021. https://submit-etda.libraries.psu.edu/catalog/24430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Quarles, Kaycee Andrea. “The Impact of Primary MicroRNA Structure on Recognition by the Microprocessor Complex in MicroRNA Maturation.” 2015. Web. 06 Mar 2021.

Vancouver:

Quarles KA. The Impact of Primary MicroRNA Structure on Recognition by the Microprocessor Complex in MicroRNA Maturation. [Internet] [Thesis]. Penn State University; 2015. [cited 2021 Mar 06]. Available from: https://submit-etda.libraries.psu.edu/catalog/24430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Quarles KA. The Impact of Primary MicroRNA Structure on Recognition by the Microprocessor Complex in MicroRNA Maturation. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/24430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

North Carolina State University

27. Cancheevaram, Jai Kumaran Kuppuswamy. Design and Performance Characterization of a Test System for Microprocessor Hot Spot Cooling using Thin-film Superlattice Thermoelectrics.

Degree: MS, Computer Engineering, 2004, North Carolina State University

URL: http://www.lib.ncsu.edu/resolver/1840.16/808

► The constant need for higher performance, increased levels of functional integration, as well as die size optimization has led to preferential clustering of higher power… (more)

▼ The constant need for higher performance, increased levels of functional integration, as well as die size optimization has led to preferential clustering of higher power units on microprocessors. This causes higher heat flux concentrations in certain areas of the die and lower heat fluxes in certain other regions, which manifest themselves as large temperature gradients on the die surface. These local power densities are commonly referred to as 'hot spots'. The thermal cooling solution provided must effectively ensure that junction/die temperatures on the processor does not exceed the rated 90-110 °C range, to guarantee device performance and reliability. The focus of this work is to present Thin-film Superlattice Thermoelectrics [TFST] as an excellent solution for microprocessor die Hot spot cooling. TFSTs have measured Figure of Merit [ZT] values of ~2.4 at 300K for p-type superlattices, with potential to pump heat flux of up to 700Wcm-2. Furthermore, these devices have fast response times, which makes them achieve steady state cooling in 15μs. This is vital in preventing thermal runaway and subsequent failure of microprocessors during rapid load transients. The primary contribution of this thesis is a test setup and experimental procedure, for characterization of an integrated TFST-processor system. First I identified and isolated potential hot spots on the processor using infrared (IR) images of the die during operation. The IR images were conclusive in determining the area of these hot spots and their magnitudes in terms of maximum temperatures reached. Next I calculated the power dissipated by the processor on the basis of the heat absorbed by the cooling system. This involved building a calorimetric system, which cools the processor by circulating water. The system was calibrated with a known load and found to measure within +3 watts of the actual power dissipated, for a processor thermal design power of 30 watts. Using this system, calculations of heat dissipated by the processor under both normal clocking and over clocking cases are presented. The final step in integrating the TFST with the processor involved mounting the TFST module onto the processor hot spot and ensuring safe operation. The TFST module itself was powered by a custom-modified Howland Current source circuit, which regulated the amount of cooling. Further contributions of this thesis include evaluating the efficiency of the TFST and the resulting impact on microprocessor performance and reliability. The temperature at interface of the TFST module and hot spot was monitored during several stages of CPU operation. Thermal transients at the hot spots is presented in the results show that active heat spreading using TFST significantly reduces the thermal cooling budget and alleviates constraints on the cooling solution. In future, with more efficient TFST modules with higher ZT values, these hot spots may be completely eliminated. Advisors/Committee Members: Dr. Winser E. Alexander, Committee Chair (advisor), Dr. John F. Muth, Committee Member (advisor), Dr. Ronald O. Scattergood, Committee Member (advisor).

Subjects/Keywords: microprocessor cooling hot spot thermoelectrics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Cancheevaram, J. K. K. (2004). Design and Performance Characterization of a Test System for Microprocessor Hot Spot Cooling using Thin-film Superlattice Thermoelectrics. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/808

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Cancheevaram, Jai Kumaran Kuppuswamy. “Design and Performance Characterization of a Test System for Microprocessor Hot Spot Cooling using Thin-film Superlattice Thermoelectrics.” 2004. Thesis, North Carolina State University. Accessed March 06, 2021. http://www.lib.ncsu.edu/resolver/1840.16/808.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Cancheevaram, Jai Kumaran Kuppuswamy. “Design and Performance Characterization of a Test System for Microprocessor Hot Spot Cooling using Thin-film Superlattice Thermoelectrics.” 2004. Web. 06 Mar 2021.

Vancouver:

Cancheevaram JKK. Design and Performance Characterization of a Test System for Microprocessor Hot Spot Cooling using Thin-film Superlattice Thermoelectrics. [Internet] [Thesis]. North Carolina State University; 2004. [cited 2021 Mar 06]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/808.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cancheevaram JKK. Design and Performance Characterization of a Test System for Microprocessor Hot Spot Cooling using Thin-film Superlattice Thermoelectrics. [Thesis]. North Carolina State University; 2004. Available from: http://www.lib.ncsu.edu/resolver/1840.16/808

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vilnius Gediminas Technical University

28. Žardin, Marek. Mikroprocesoriniai optimizatoriai ir programinė įranga.

Degree: Master, Electronics and Electrical Engineering, 2004, Vilnius Gediminas Technical University

URL: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2004~D_20040617_125548-24316 ;

► The optimizator of the microprocessor is designed in this final work. The optimizator is based on the AT90S8535 controller. Introduction reviews the peculiarities of the… (more)

Subjects/Keywords: Stačiakampis simpleksas; Optimizatoriai; Microprocessor optimizators

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APA (6^th Edition):

Žardin, Marek. (2004). Mikroprocesoriniai optimizatoriai ir programinė įranga. (Masters Thesis). Vilnius Gediminas Technical University. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2004~D_20040617_125548-24316 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16^th Edition):

Žardin, Marek. “Mikroprocesoriniai optimizatoriai ir programinė įranga.” 2004. Masters Thesis, Vilnius Gediminas Technical University. Accessed March 06, 2021. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2004~D_20040617_125548-24316 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7^th Edition):

Žardin, Marek. “Mikroprocesoriniai optimizatoriai ir programinė įranga.” 2004. Web. 06 Mar 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Žardin, Marek. Mikroprocesoriniai optimizatoriai ir programinė įranga. [Internet] [Masters thesis]. Vilnius Gediminas Technical University; 2004. [cited 2021 Mar 06]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2004~D_20040617_125548-24316 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

Žardin, Marek. Mikroprocesoriniai optimizatoriai ir programinė įranga. [Masters Thesis]. Vilnius Gediminas Technical University; 2004. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2004~D_20040617_125548-24316 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

29. Albizu, Urtzi Agirre. Electronic Redesign of an Industrial Lift.

Degree: 2016, Instituto Politécnico do Porto

URL: http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/8265

► This project, realized at the company ABER Ltd, describes the process followed for the developing of an electronic control system for a hydraulic elevator. The… (more)

Subjects/Keywords: Hydraulic; Elevator; Electronics; Control; Microprocessor; Raspberry Pi; Construções Mecânicas

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Albizu, U. A. (2016). Electronic Redesign of an Industrial Lift. (Thesis). Instituto Politécnico do Porto. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/8265

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Albizu, Urtzi Agirre. “Electronic Redesign of an Industrial Lift.” 2016. Thesis, Instituto Politécnico do Porto. Accessed March 06, 2021. http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/8265.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Albizu, Urtzi Agirre. “Electronic Redesign of an Industrial Lift.” 2016. Web. 06 Mar 2021.

Vancouver:

Albizu UA. Electronic Redesign of an Industrial Lift. [Internet] [Thesis]. Instituto Politécnico do Porto; 2016. [cited 2021 Mar 06]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/8265.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Albizu UA. Electronic Redesign of an Industrial Lift. [Thesis]. Instituto Politécnico do Porto; 2016. Available from: http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/8265

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Pontifical Catholic University of Rio de Janeiro

30. PEDRO PAULO ROCHA. [en] DATA ACQUISITION SYSTEM FOR SOIL MECHANICS TESTING.

Degree: 2009, Pontifical Catholic University of Rio de Janeiro

URL: http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14434

►

[pt] A aquisição de dados vem alcançando rápido desenvolvimento com o advento da tecnologia da tecnologia de circuitos integrados e de microprocessadores. Os sistemas de… (more)

▼

[pt] A aquisição de dados vem alcançando rápido desenvolvimento com o advento da tecnologia da tecnologia de circuitos integrados e de microprocessadores. Os sistemas de controle de Processo e de Ensaios nos quais a aquisição de dados constitui uma tarefa preliminar básica, se tornaram mais confiáveis, mais compactos e economicamente atraentes. O presente trabalho envolve os Sistemas de aquisição de dados. Abordamos a importância e as aplicações dos computadores em Processos e Ensaios, fazemos uma análise geral das características e configurações dos Sistemas de Aquisição de dados, discutimos as possíveis realizações e apresentamos o desenvolvimento para o caso particular de Ensaios de Mecânica de solos no laboratório da PUC. Foi feito um levantamento criterioso dos requisitos para esta aplicação específica e prevista conexão posterior a periféricos. A filosofia adotada no desenvolvimento foi a obtenção do máximo de simplificação e aumento de confiabilidade compatível com as especificações requeridas para este tipo de ensaio.

[en] Data Acquisition is fast reaching na advanced state of development with the advent of integrated circuits and microprocessor tecnology. The test and control process systems, where Data Acquisition constitutes the basic preliminary task, have become more reliable, more compact and economically more attractive. This work involves Data Acquisition Systems. The importance of computers and their applications in Process Control and in Laboratory Tests is discussed along with a genaral analysis of Data Acquisition System’s characteristics and configurations. Finally the possible solutions for the specific case of soil mechanics testing, including for use in soil Puc’s Laboratory is discussed. Careful considerations was made of the requirements for this application and an eventual future connection of periferals. The philosophy adopted in such development was aimed toward improved simplication and reliability, in order to comply with specifications required for this type of application.

Advisors/Committee Members: JOSE AUGUSTO M. MENDONÇA.

Subjects/Keywords: [pt] MICROPROCESSADOR; [en] MICROPROCESSOR; [pt] CIRCUITOS INTEGRADOS; [pt] AQUISICAO INTEGRADA

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APA (6^th Edition):

ROCHA, P. P. (2009). [en] DATA ACQUISITION SYSTEM FOR SOIL MECHANICS TESTING. (Thesis). Pontifical Catholic University of Rio de Janeiro. Retrieved from http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14434

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

ROCHA, PEDRO PAULO. “[en] DATA ACQUISITION SYSTEM FOR SOIL MECHANICS TESTING.” 2009. Thesis, Pontifical Catholic University of Rio de Janeiro. Accessed March 06, 2021. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14434.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

ROCHA, PEDRO PAULO. “[en] DATA ACQUISITION SYSTEM FOR SOIL MECHANICS TESTING.” 2009. Web. 06 Mar 2021.

Vancouver:

ROCHA PP. [en] DATA ACQUISITION SYSTEM FOR SOIL MECHANICS TESTING. [Internet] [Thesis]. Pontifical Catholic University of Rio de Janeiro; 2009. [cited 2021 Mar 06]. Available from: http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14434.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

ROCHA PP. [en] DATA ACQUISITION SYSTEM FOR SOIL MECHANICS TESTING. [Thesis]. Pontifical Catholic University of Rio de Janeiro; 2009. Available from: http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14434

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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Open Access Theses and Dissertations