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You searched for subject:(Microelectronic). Showing records 1 – 30 of 173 total matches.

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University of Hong Kong

1. 박용화; Park, Yonghua. Packaging designs for geometrical shaping light emitting diodes.

Degree: M. Phil., 2017, University of Hong Kong

 Over more than two decades, Gallium-nitride (GaN)-based light-emitting diodes (LEDs) have successfully penetrated many applications starting with point light sources, general indoor lightings, LED displays… (more)

Subjects/Keywords: Microelectronic packaging; Light emitting diodes

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APA (6th Edition):

박용화; Park, Y. (2017). Packaging designs for geometrical shaping light emitting diodes. (Masters Thesis). University of Hong Kong. Retrieved from http://hdl.handle.net/10722/249925

Chicago Manual of Style (16th Edition):

박용화; Park, Yonghua. “Packaging designs for geometrical shaping light emitting diodes.” 2017. Masters Thesis, University of Hong Kong. Accessed April 05, 2020. http://hdl.handle.net/10722/249925.

MLA Handbook (7th Edition):

박용화; Park, Yonghua. “Packaging designs for geometrical shaping light emitting diodes.” 2017. Web. 05 Apr 2020.

Vancouver:

박용화; Park Y. Packaging designs for geometrical shaping light emitting diodes. [Internet] [Masters thesis]. University of Hong Kong; 2017. [cited 2020 Apr 05]. Available from: http://hdl.handle.net/10722/249925.

Council of Science Editors:

박용화; Park Y. Packaging designs for geometrical shaping light emitting diodes. [Masters Thesis]. University of Hong Kong; 2017. Available from: http://hdl.handle.net/10722/249925


Rochester Institute of Technology

2. Langley, Robert. Design and process development of an integrated phosphor field emission device.

Degree: Microelectronic Engineering, 1997, Rochester Institute of Technology

 An Integrated Phosphor Field Emission Device (IPFED) has been fabricated at the Rochester Institute of Technology for the purpose of developing a new, flat panel… (more)

Subjects/Keywords: Microelectronic engineering

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APA (6th Edition):

Langley, R. (1997). Design and process development of an integrated phosphor field emission device. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/7136

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Langley, Robert. “Design and process development of an integrated phosphor field emission device.” 1997. Thesis, Rochester Institute of Technology. Accessed April 05, 2020. https://scholarworks.rit.edu/theses/7136.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Langley, Robert. “Design and process development of an integrated phosphor field emission device.” 1997. Web. 05 Apr 2020.

Vancouver:

Langley R. Design and process development of an integrated phosphor field emission device. [Internet] [Thesis]. Rochester Institute of Technology; 1997. [cited 2020 Apr 05]. Available from: https://scholarworks.rit.edu/theses/7136.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Langley R. Design and process development of an integrated phosphor field emission device. [Thesis]. Rochester Institute of Technology; 1997. Available from: https://scholarworks.rit.edu/theses/7136

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

3. Capasso, Keith. Process development and reliability of thin gate oxides.

Degree: Microelectronic Engineering, 1999, Rochester Institute of Technology

 The Semiconductor Industry Association's (SIA) current National Technological Roadmap calls for the development of a suitable dielectric material for use in gate oxide for the… (more)

Subjects/Keywords: Microelectronic engineering

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APA (6th Edition):

Capasso, K. (1999). Process development and reliability of thin gate oxides. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/7377

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Capasso, Keith. “Process development and reliability of thin gate oxides.” 1999. Thesis, Rochester Institute of Technology. Accessed April 05, 2020. https://scholarworks.rit.edu/theses/7377.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Capasso, Keith. “Process development and reliability of thin gate oxides.” 1999. Web. 05 Apr 2020.

Vancouver:

Capasso K. Process development and reliability of thin gate oxides. [Internet] [Thesis]. Rochester Institute of Technology; 1999. [cited 2020 Apr 05]. Available from: https://scholarworks.rit.edu/theses/7377.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Capasso K. Process development and reliability of thin gate oxides. [Thesis]. Rochester Institute of Technology; 1999. Available from: https://scholarworks.rit.edu/theses/7377

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

4. Bhaskaran, Suraj. Design of RIT's sub-micron CMOS process.

Degree: Microelectronic Engineering, 2000, Rochester Institute of Technology

 The design and simulation of RIT's sub-micron CMOS process is studied in this work. The work has demonstrated a process capable of producing working transistors… (more)

Subjects/Keywords: Microelectronic engineering

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APA (6th Edition):

Bhaskaran, S. (2000). Design of RIT's sub-micron CMOS process. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/1209

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bhaskaran, Suraj. “Design of RIT's sub-micron CMOS process.” 2000. Thesis, Rochester Institute of Technology. Accessed April 05, 2020. https://scholarworks.rit.edu/theses/1209.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bhaskaran, Suraj. “Design of RIT's sub-micron CMOS process.” 2000. Web. 05 Apr 2020.

Vancouver:

Bhaskaran S. Design of RIT's sub-micron CMOS process. [Internet] [Thesis]. Rochester Institute of Technology; 2000. [cited 2020 Apr 05]. Available from: https://scholarworks.rit.edu/theses/1209.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bhaskaran S. Design of RIT's sub-micron CMOS process. [Thesis]. Rochester Institute of Technology; 2000. Available from: https://scholarworks.rit.edu/theses/1209

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

5. Schippers, Michael. Process design for charge-injection based imaging array fabrication.

Degree: Microelectronic Engineering, 1996, Rochester Institute of Technology

 Charge-injection devices (CID's) have been around almost as long as charge-coupled devices (CCD's), yet have generally been overlooked for solid state imaging applications due to… (more)

Subjects/Keywords: Microelectronic manufacturing

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APA (6th Edition):

Schippers, M. (1996). Process design for charge-injection based imaging array fabrication. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/7152

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Schippers, Michael. “Process design for charge-injection based imaging array fabrication.” 1996. Thesis, Rochester Institute of Technology. Accessed April 05, 2020. https://scholarworks.rit.edu/theses/7152.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Schippers, Michael. “Process design for charge-injection based imaging array fabrication.” 1996. Web. 05 Apr 2020.

Vancouver:

Schippers M. Process design for charge-injection based imaging array fabrication. [Internet] [Thesis]. Rochester Institute of Technology; 1996. [cited 2020 Apr 05]. Available from: https://scholarworks.rit.edu/theses/7152.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Schippers M. Process design for charge-injection based imaging array fabrication. [Thesis]. Rochester Institute of Technology; 1996. Available from: https://scholarworks.rit.edu/theses/7152

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

6. Faisst, Charles, Jr. Modeling and fabrication of optically resonant periodic structures.

Degree: Microelectronic Engineering, 2002, Rochester Institute of Technology

 Optically resonant periodic electrode (ORPEL) structures developed for use as an optical modulator at telecommunication wavelengths using standard microelectronic processes have been successfully fabricated. These… (more)

Subjects/Keywords: Microelectronic engineering

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APA (6th Edition):

Faisst, Charles, J. (2002). Modeling and fabrication of optically resonant periodic structures. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/7248

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Faisst, Charles, Jr. “Modeling and fabrication of optically resonant periodic structures.” 2002. Thesis, Rochester Institute of Technology. Accessed April 05, 2020. https://scholarworks.rit.edu/theses/7248.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Faisst, Charles, Jr. “Modeling and fabrication of optically resonant periodic structures.” 2002. Web. 05 Apr 2020.

Vancouver:

Faisst, Charles J. Modeling and fabrication of optically resonant periodic structures. [Internet] [Thesis]. Rochester Institute of Technology; 2002. [cited 2020 Apr 05]. Available from: https://scholarworks.rit.edu/theses/7248.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Faisst, Charles J. Modeling and fabrication of optically resonant periodic structures. [Thesis]. Rochester Institute of Technology; 2002. Available from: https://scholarworks.rit.edu/theses/7248

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

7. Guan, Chunhua. Characterization and selecting criteria of die attach film (DAF) for adhesive die bonding packages.

Degree: 2013, Hong Kong University of Science and Technology

 Nowadays, die attach glue is widely used in adhesive die bonding packages, for its high heat dissipation ability and good resistance against thermal fatigue. However,… (more)

Subjects/Keywords: Microelectronic packaging ; Electronic packaging ; Adhesives

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APA (6th Edition):

Guan, C. (2013). Characterization and selecting criteria of die attach film (DAF) for adhesive die bonding packages. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-7883 ; https://doi.org/10.14711/thesis-b1213720 ; http://repository.ust.hk/ir/bitstream/1783.1-7883/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Guan, Chunhua. “Characterization and selecting criteria of die attach film (DAF) for adhesive die bonding packages.” 2013. Thesis, Hong Kong University of Science and Technology. Accessed April 05, 2020. http://repository.ust.hk/ir/Record/1783.1-7883 ; https://doi.org/10.14711/thesis-b1213720 ; http://repository.ust.hk/ir/bitstream/1783.1-7883/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Guan, Chunhua. “Characterization and selecting criteria of die attach film (DAF) for adhesive die bonding packages.” 2013. Web. 05 Apr 2020.

Vancouver:

Guan C. Characterization and selecting criteria of die attach film (DAF) for adhesive die bonding packages. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2020 Apr 05]. Available from: http://repository.ust.hk/ir/Record/1783.1-7883 ; https://doi.org/10.14711/thesis-b1213720 ; http://repository.ust.hk/ir/bitstream/1783.1-7883/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guan C. Characterization and selecting criteria of die attach film (DAF) for adhesive die bonding packages. [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: http://repository.ust.hk/ir/Record/1783.1-7883 ; https://doi.org/10.14711/thesis-b1213720 ; http://repository.ust.hk/ir/bitstream/1783.1-7883/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

8. Wang, Su. Fast filling of through silicon vias (TSV) and related reliability studies.

Degree: 2013, Hong Kong University of Science and Technology

 There is an increasing demand for electronic devices with smaller sizes, higher performances and increased functionality. The formation of vertical interconnects or through silicon vias… (more)

Subjects/Keywords: Microelectronic packaging ; Reliability ; Electroplating

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APA (6th Edition):

Wang, S. (2013). Fast filling of through silicon vias (TSV) and related reliability studies. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-62263 ; https://doi.org/10.14711/thesis-b1251530 ; http://repository.ust.hk/ir/bitstream/1783.1-62263/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Su. “Fast filling of through silicon vias (TSV) and related reliability studies.” 2013. Thesis, Hong Kong University of Science and Technology. Accessed April 05, 2020. http://repository.ust.hk/ir/Record/1783.1-62263 ; https://doi.org/10.14711/thesis-b1251530 ; http://repository.ust.hk/ir/bitstream/1783.1-62263/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Su. “Fast filling of through silicon vias (TSV) and related reliability studies.” 2013. Web. 05 Apr 2020.

Vancouver:

Wang S. Fast filling of through silicon vias (TSV) and related reliability studies. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2020 Apr 05]. Available from: http://repository.ust.hk/ir/Record/1783.1-62263 ; https://doi.org/10.14711/thesis-b1251530 ; http://repository.ust.hk/ir/bitstream/1783.1-62263/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang S. Fast filling of through silicon vias (TSV) and related reliability studies. [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: http://repository.ust.hk/ir/Record/1783.1-62263 ; https://doi.org/10.14711/thesis-b1251530 ; http://repository.ust.hk/ir/bitstream/1783.1-62263/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

9. Han, Jiale. Wire sweep study of package array mold during transfer molding process.

Degree: 2012, Hong Kong University of Science and Technology

 In order to maximize production rate, an increasing number of electronic packages are manufactured in a package array mold, such as Small Outline Transistor (SOT)… (more)

Subjects/Keywords: Microelectronic packaging  – Mathematical models

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APA (6th Edition):

Han, J. (2012). Wire sweep study of package array mold during transfer molding process. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-7579 ; https://doi.org/10.14711/thesis-b1180182 ; http://repository.ust.hk/ir/bitstream/1783.1-7579/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Han, Jiale. “Wire sweep study of package array mold during transfer molding process.” 2012. Thesis, Hong Kong University of Science and Technology. Accessed April 05, 2020. http://repository.ust.hk/ir/Record/1783.1-7579 ; https://doi.org/10.14711/thesis-b1180182 ; http://repository.ust.hk/ir/bitstream/1783.1-7579/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Han, Jiale. “Wire sweep study of package array mold during transfer molding process.” 2012. Web. 05 Apr 2020.

Vancouver:

Han J. Wire sweep study of package array mold during transfer molding process. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2012. [cited 2020 Apr 05]. Available from: http://repository.ust.hk/ir/Record/1783.1-7579 ; https://doi.org/10.14711/thesis-b1180182 ; http://repository.ust.hk/ir/bitstream/1783.1-7579/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Han J. Wire sweep study of package array mold during transfer molding process. [Thesis]. Hong Kong University of Science and Technology; 2012. Available from: http://repository.ust.hk/ir/Record/1783.1-7579 ; https://doi.org/10.14711/thesis-b1180182 ; http://repository.ust.hk/ir/bitstream/1783.1-7579/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

10. Chen, Kewei. Integration of phosphor printing and encapsulant dispensing processes for LED array wafer level packaging.

Degree: 2011, Hong Kong University of Science and Technology

 Solid-state lighting (SSL) using light-emitting diode (LED) as an alternative light source is an emerging technology. Compared with conventional light sources, LEDs have superior characteristics… (more)

Subjects/Keywords: Light emitting diodes ; Microelectronic packaging

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, K. (2011). Integration of phosphor printing and encapsulant dispensing processes for LED array wafer level packaging. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-7154 ; https://doi.org/10.14711/thesis-b1136689 ; http://repository.ust.hk/ir/bitstream/1783.1-7154/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Kewei. “Integration of phosphor printing and encapsulant dispensing processes for LED array wafer level packaging.” 2011. Thesis, Hong Kong University of Science and Technology. Accessed April 05, 2020. http://repository.ust.hk/ir/Record/1783.1-7154 ; https://doi.org/10.14711/thesis-b1136689 ; http://repository.ust.hk/ir/bitstream/1783.1-7154/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Kewei. “Integration of phosphor printing and encapsulant dispensing processes for LED array wafer level packaging.” 2011. Web. 05 Apr 2020.

Vancouver:

Chen K. Integration of phosphor printing and encapsulant dispensing processes for LED array wafer level packaging. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2011. [cited 2020 Apr 05]. Available from: http://repository.ust.hk/ir/Record/1783.1-7154 ; https://doi.org/10.14711/thesis-b1136689 ; http://repository.ust.hk/ir/bitstream/1783.1-7154/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen K. Integration of phosphor printing and encapsulant dispensing processes for LED array wafer level packaging. [Thesis]. Hong Kong University of Science and Technology; 2011. Available from: http://repository.ust.hk/ir/Record/1783.1-7154 ; https://doi.org/10.14711/thesis-b1136689 ; http://repository.ust.hk/ir/bitstream/1783.1-7154/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Haspil, Gabriel Solivan. Assembly of 3D Microelectronic Blocks by Folding.

Degree: 2014, Johns Hopkins University

 Integrated circuits are present in every electronic and computational device, and as such, efficient use of space is of major importance. Conventional technology relies on… (more)

Subjects/Keywords: 3D computing; microelectronic circuits; self-folding;

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APA (6th Edition):

Haspil, G. S. (2014). Assembly of 3D Microelectronic Blocks by Folding. (Thesis). Johns Hopkins University. Retrieved from http://jhir.library.jhu.edu/handle/1774.2/37089

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Haspil, Gabriel Solivan. “Assembly of 3D Microelectronic Blocks by Folding.” 2014. Thesis, Johns Hopkins University. Accessed April 05, 2020. http://jhir.library.jhu.edu/handle/1774.2/37089.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Haspil, Gabriel Solivan. “Assembly of 3D Microelectronic Blocks by Folding.” 2014. Web. 05 Apr 2020.

Vancouver:

Haspil GS. Assembly of 3D Microelectronic Blocks by Folding. [Internet] [Thesis]. Johns Hopkins University; 2014. [cited 2020 Apr 05]. Available from: http://jhir.library.jhu.edu/handle/1774.2/37089.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Haspil GS. Assembly of 3D Microelectronic Blocks by Folding. [Thesis]. Johns Hopkins University; 2014. Available from: http://jhir.library.jhu.edu/handle/1774.2/37089

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

12. Fakhry, Tayaz. Optimization of a compact thermal model for a Ball Grid Array (BGA) package using experimental data.

Degree: 2011, Ryerson University

 The goal of this research is to optimize a static and dynamic compact thermal model for a ball grid array (BGA) package using experimental data.… (more)

Subjects/Keywords: Ball grid array technology; Microelectronic packaging

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APA (6th Edition):

Fakhry, T. (2011). Optimization of a compact thermal model for a Ball Grid Array (BGA) package using experimental data. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fakhry, Tayaz. “Optimization of a compact thermal model for a Ball Grid Array (BGA) package using experimental data.” 2011. Thesis, Ryerson University. Accessed April 05, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fakhry, Tayaz. “Optimization of a compact thermal model for a Ball Grid Array (BGA) package using experimental data.” 2011. Web. 05 Apr 2020.

Vancouver:

Fakhry T. Optimization of a compact thermal model for a Ball Grid Array (BGA) package using experimental data. [Internet] [Thesis]. Ryerson University; 2011. [cited 2020 Apr 05]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fakhry T. Optimization of a compact thermal model for a Ball Grid Array (BGA) package using experimental data. [Thesis]. Ryerson University; 2011. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat de Valencia

13. Zuccarello, Pedro Diego. Development and implementation of a selective change-driven vision sensor for high speed movement analysis .

Degree: 2013, Universitat de Valencia

 Un sistema de vision artificial esta compuesto, en su forma más basica, por un sensor VLSI, habitualmente fabricado en tecnología CMOS o CCD, y una… (more)

Subjects/Keywords: microelectronic design; vision sensor; artificial vision system

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APA (6th Edition):

Zuccarello, P. D. (2013). Development and implementation of a selective change-driven vision sensor for high speed movement analysis . (Doctoral Dissertation). Universitat de Valencia. Retrieved from http://hdl.handle.net/10550/26742

Chicago Manual of Style (16th Edition):

Zuccarello, Pedro Diego. “Development and implementation of a selective change-driven vision sensor for high speed movement analysis .” 2013. Doctoral Dissertation, Universitat de Valencia. Accessed April 05, 2020. http://hdl.handle.net/10550/26742.

MLA Handbook (7th Edition):

Zuccarello, Pedro Diego. “Development and implementation of a selective change-driven vision sensor for high speed movement analysis .” 2013. Web. 05 Apr 2020.

Vancouver:

Zuccarello PD. Development and implementation of a selective change-driven vision sensor for high speed movement analysis . [Internet] [Doctoral dissertation]. Universitat de Valencia; 2013. [cited 2020 Apr 05]. Available from: http://hdl.handle.net/10550/26742.

Council of Science Editors:

Zuccarello PD. Development and implementation of a selective change-driven vision sensor for high speed movement analysis . [Doctoral Dissertation]. Universitat de Valencia; 2013. Available from: http://hdl.handle.net/10550/26742


Aston University

14. Randrianandrasana, Michel F. Finding structures in information networks using the affinity network.

Degree: PhD, 2011, Aston University

 This thesis proposes a novel graphical model for inference called the Affinity Network,which displays the closeness between pairs of variables and is an alternative to… (more)

Subjects/Keywords: 006.3; Microelectronic Engineering; Electromechanical Engineering; Information Modelling

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APA (6th Edition):

Randrianandrasana, M. F. (2011). Finding structures in information networks using the affinity network. (Doctoral Dissertation). Aston University. Retrieved from http://publications.aston.ac.uk/id/eprint/15684/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.545311

Chicago Manual of Style (16th Edition):

Randrianandrasana, Michel F. “Finding structures in information networks using the affinity network.” 2011. Doctoral Dissertation, Aston University. Accessed April 05, 2020. http://publications.aston.ac.uk/id/eprint/15684/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.545311.

MLA Handbook (7th Edition):

Randrianandrasana, Michel F. “Finding structures in information networks using the affinity network.” 2011. Web. 05 Apr 2020.

Vancouver:

Randrianandrasana MF. Finding structures in information networks using the affinity network. [Internet] [Doctoral dissertation]. Aston University; 2011. [cited 2020 Apr 05]. Available from: http://publications.aston.ac.uk/id/eprint/15684/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.545311.

Council of Science Editors:

Randrianandrasana MF. Finding structures in information networks using the affinity network. [Doctoral Dissertation]. Aston University; 2011. Available from: http://publications.aston.ac.uk/id/eprint/15684/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.545311


National University of Ireland – Maynooth

15. Collins, Diarmuid. A Fully Difffferential Phase-Locked Loop With Reduced Loop Bandwidth Variation.

Degree: Callan Institute, 2011, National University of Ireland – Maynooth

 Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order… (more)

Subjects/Keywords: Electronic Engineering; Institute of Microelectronic & Wireless Systems

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APA (6th Edition):

Collins, D. (2011). A Fully Difffferential Phase-Locked Loop With Reduced Loop Bandwidth Variation. (Masters Thesis). National University of Ireland – Maynooth. Retrieved from http://mural.maynoothuniversity.ie/3984/

Chicago Manual of Style (16th Edition):

Collins, Diarmuid. “A Fully Difffferential Phase-Locked Loop With Reduced Loop Bandwidth Variation.” 2011. Masters Thesis, National University of Ireland – Maynooth. Accessed April 05, 2020. http://mural.maynoothuniversity.ie/3984/.

MLA Handbook (7th Edition):

Collins, Diarmuid. “A Fully Difffferential Phase-Locked Loop With Reduced Loop Bandwidth Variation.” 2011. Web. 05 Apr 2020.

Vancouver:

Collins D. A Fully Difffferential Phase-Locked Loop With Reduced Loop Bandwidth Variation. [Internet] [Masters thesis]. National University of Ireland – Maynooth; 2011. [cited 2020 Apr 05]. Available from: http://mural.maynoothuniversity.ie/3984/.

Council of Science Editors:

Collins D. A Fully Difffferential Phase-Locked Loop With Reduced Loop Bandwidth Variation. [Masters Thesis]. National University of Ireland – Maynooth; 2011. Available from: http://mural.maynoothuniversity.ie/3984/

16. Ahmed, Nayera. MOS Capacitor Deep Trench Isolation (CDTI) for CMOS Image Sensors : Tranchée d'isolement profonde de type capacité MOS verticale pour les capteurs d'images CMOS.

Degree: Docteur es, Microélectronique, 2015, Université Claude Bernard – Lyon I

 The development of high-resolution image sensors with smaller pixel sizes is facing critical issues, such as optical and electrical crosstalk, dark current and dynamic range.… (more)

Subjects/Keywords: Microélectronique; Capteurs d'images; Microelectronic; Image sensors; 620

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APA (6th Edition):

Ahmed, N. (2015). MOS Capacitor Deep Trench Isolation (CDTI) for CMOS Image Sensors : Tranchée d'isolement profonde de type capacité MOS verticale pour les capteurs d'images CMOS. (Doctoral Dissertation). Université Claude Bernard – Lyon I. Retrieved from http://www.theses.fr/2015LYO10048

Chicago Manual of Style (16th Edition):

Ahmed, Nayera. “MOS Capacitor Deep Trench Isolation (CDTI) for CMOS Image Sensors : Tranchée d'isolement profonde de type capacité MOS verticale pour les capteurs d'images CMOS.” 2015. Doctoral Dissertation, Université Claude Bernard – Lyon I. Accessed April 05, 2020. http://www.theses.fr/2015LYO10048.

MLA Handbook (7th Edition):

Ahmed, Nayera. “MOS Capacitor Deep Trench Isolation (CDTI) for CMOS Image Sensors : Tranchée d'isolement profonde de type capacité MOS verticale pour les capteurs d'images CMOS.” 2015. Web. 05 Apr 2020.

Vancouver:

Ahmed N. MOS Capacitor Deep Trench Isolation (CDTI) for CMOS Image Sensors : Tranchée d'isolement profonde de type capacité MOS verticale pour les capteurs d'images CMOS. [Internet] [Doctoral dissertation]. Université Claude Bernard – Lyon I; 2015. [cited 2020 Apr 05]. Available from: http://www.theses.fr/2015LYO10048.

Council of Science Editors:

Ahmed N. MOS Capacitor Deep Trench Isolation (CDTI) for CMOS Image Sensors : Tranchée d'isolement profonde de type capacité MOS verticale pour les capteurs d'images CMOS. [Doctoral Dissertation]. Université Claude Bernard – Lyon I; 2015. Available from: http://www.theses.fr/2015LYO10048


Georgia Tech

17. Chen, Wei. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.

Degree: PhD, Mechanical Engineering, 2015, Georgia Tech

 Free-standing off-chip interconnects have high in-plane and out-of-plane compliance and are being pursued in academia and industry to reduce die stresses and to enhance interconnect… (more)

Subjects/Keywords: Compliant interconnect; Microelectronic packaging; Packaging reliability

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APA (6th Edition):

Chen, W. (2015). Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55550

Chicago Manual of Style (16th Edition):

Chen, Wei. “Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.” 2015. Doctoral Dissertation, Georgia Tech. Accessed April 05, 2020. http://hdl.handle.net/1853/55550.

MLA Handbook (7th Edition):

Chen, Wei. “Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.” 2015. Web. 05 Apr 2020.

Vancouver:

Chen W. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2020 Apr 05]. Available from: http://hdl.handle.net/1853/55550.

Council of Science Editors:

Chen W. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/55550


Hong Kong University of Science and Technology

18. Liu, Huihua. LED wafer level packaging with remote phosphor and correlated ray tracing optical simulation.

Degree: 2013, Hong Kong University of Science and Technology

 LEDs provide an environmental friendly light source for general lighting. They offer high efficiency, a long life span and do not contain hazardous substances. Wafer… (more)

Subjects/Keywords: Light emitting diodes ; Microelectronic packaging ; Phosphors

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APA (6th Edition):

Liu, H. (2013). LED wafer level packaging with remote phosphor and correlated ray tracing optical simulation. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-62371 ; https://doi.org/10.14711/thesis-b1255616 ; http://repository.ust.hk/ir/bitstream/1783.1-62371/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Huihua. “LED wafer level packaging with remote phosphor and correlated ray tracing optical simulation.” 2013. Thesis, Hong Kong University of Science and Technology. Accessed April 05, 2020. http://repository.ust.hk/ir/Record/1783.1-62371 ; https://doi.org/10.14711/thesis-b1255616 ; http://repository.ust.hk/ir/bitstream/1783.1-62371/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Huihua. “LED wafer level packaging with remote phosphor and correlated ray tracing optical simulation.” 2013. Web. 05 Apr 2020.

Vancouver:

Liu H. LED wafer level packaging with remote phosphor and correlated ray tracing optical simulation. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2020 Apr 05]. Available from: http://repository.ust.hk/ir/Record/1783.1-62371 ; https://doi.org/10.14711/thesis-b1255616 ; http://repository.ust.hk/ir/bitstream/1783.1-62371/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu H. LED wafer level packaging with remote phosphor and correlated ray tracing optical simulation. [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: http://repository.ust.hk/ir/Record/1783.1-62371 ; https://doi.org/10.14711/thesis-b1255616 ; http://repository.ust.hk/ir/bitstream/1783.1-62371/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

19. Wu, Hailong. Analytical characterization of electrolyte and additives for high quality copper plating of through silicon vias (TSVs).

Degree: 2013, Hong Kong University of Science and Technology

 The heart of three-dimensional (3D) Si integration is the copper filled Through Silicon Via (TSV), which allows the shortest chip-to-chip interconnections. The copper filling of… (more)

Subjects/Keywords: Microelectronic packaging ; Silicon ; Additives ; Copper plating ; Electroplating

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APA (6th Edition):

Wu, H. (2013). Analytical characterization of electrolyte and additives for high quality copper plating of through silicon vias (TSVs). (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-73430 ; https://doi.org/10.14711/thesis-b1251161 ; http://repository.ust.hk/ir/bitstream/1783.1-73430/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Hailong. “Analytical characterization of electrolyte and additives for high quality copper plating of through silicon vias (TSVs).” 2013. Thesis, Hong Kong University of Science and Technology. Accessed April 05, 2020. http://repository.ust.hk/ir/Record/1783.1-73430 ; https://doi.org/10.14711/thesis-b1251161 ; http://repository.ust.hk/ir/bitstream/1783.1-73430/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Hailong. “Analytical characterization of electrolyte and additives for high quality copper plating of through silicon vias (TSVs).” 2013. Web. 05 Apr 2020.

Vancouver:

Wu H. Analytical characterization of electrolyte and additives for high quality copper plating of through silicon vias (TSVs). [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2020 Apr 05]. Available from: http://repository.ust.hk/ir/Record/1783.1-73430 ; https://doi.org/10.14711/thesis-b1251161 ; http://repository.ust.hk/ir/bitstream/1783.1-73430/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu H. Analytical characterization of electrolyte and additives for high quality copper plating of through silicon vias (TSVs). [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: http://repository.ust.hk/ir/Record/1783.1-73430 ; https://doi.org/10.14711/thesis-b1251161 ; http://repository.ust.hk/ir/bitstream/1783.1-73430/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. Collins, Diarmuid. A Fully Differential Phase-Locked Loop With Reduced Loop Bandwidth Variation.

Degree: 2011, RIAN

 Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order… (more)

Subjects/Keywords: Electronic Engineering; Institute of Microelectronic & Wireless Systems

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APA (6th Edition):

Collins, D. (2011). A Fully Differential Phase-Locked Loop With Reduced Loop Bandwidth Variation. (Thesis). RIAN. Retrieved from http://mural.maynoothuniversity.ie/3984/1/A_Fully_Differential_Phase-Locked_Loop_with_Reduced_Loop_Bandwidth_Variation.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Collins, Diarmuid. “A Fully Differential Phase-Locked Loop With Reduced Loop Bandwidth Variation.” 2011. Thesis, RIAN. Accessed April 05, 2020. http://mural.maynoothuniversity.ie/3984/1/A_Fully_Differential_Phase-Locked_Loop_with_Reduced_Loop_Bandwidth_Variation.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Collins, Diarmuid. “A Fully Differential Phase-Locked Loop With Reduced Loop Bandwidth Variation.” 2011. Web. 05 Apr 2020.

Vancouver:

Collins D. A Fully Differential Phase-Locked Loop With Reduced Loop Bandwidth Variation. [Internet] [Thesis]. RIAN; 2011. [cited 2020 Apr 05]. Available from: http://mural.maynoothuniversity.ie/3984/1/A_Fully_Differential_Phase-Locked_Loop_with_Reduced_Loop_Bandwidth_Variation.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Collins D. A Fully Differential Phase-Locked Loop With Reduced Loop Bandwidth Variation. [Thesis]. RIAN; 2011. Available from: http://mural.maynoothuniversity.ie/3984/1/A_Fully_Differential_Phase-Locked_Loop_with_Reduced_Loop_Bandwidth_Variation.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Rocha, Otávio Filipe da. Caracterização de filmes finos de óxido de silício depositados em um reator HD-PECVD a partir de TEOS a ultra baixa temperatura.

Degree: Mestrado, Microeletrônica, 2007, University of São Paulo

Este trabalho reporta o estudo e desenvolvimento do processo de deposição química a vapor enriquecida por plasma de alta densidade de filmes finos de óxido… (more)

Subjects/Keywords: Filmes finos; Microelectronic processes; Plasma (microelectronic); Plasma (microeletrônica); Processos de microeletrônica; Thin films

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APA (6th Edition):

Rocha, O. F. d. (2007). Caracterização de filmes finos de óxido de silício depositados em um reator HD-PECVD a partir de TEOS a ultra baixa temperatura. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3140/tde-08012008-142809/ ;

Chicago Manual of Style (16th Edition):

Rocha, Otávio Filipe da. “Caracterização de filmes finos de óxido de silício depositados em um reator HD-PECVD a partir de TEOS a ultra baixa temperatura.” 2007. Masters Thesis, University of São Paulo. Accessed April 05, 2020. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-08012008-142809/ ;.

MLA Handbook (7th Edition):

Rocha, Otávio Filipe da. “Caracterização de filmes finos de óxido de silício depositados em um reator HD-PECVD a partir de TEOS a ultra baixa temperatura.” 2007. Web. 05 Apr 2020.

Vancouver:

Rocha OFd. Caracterização de filmes finos de óxido de silício depositados em um reator HD-PECVD a partir de TEOS a ultra baixa temperatura. [Internet] [Masters thesis]. University of São Paulo; 2007. [cited 2020 Apr 05]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-08012008-142809/ ;.

Council of Science Editors:

Rocha OFd. Caracterização de filmes finos de óxido de silício depositados em um reator HD-PECVD a partir de TEOS a ultra baixa temperatura. [Masters Thesis]. University of São Paulo; 2007. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-08012008-142809/ ;


University of Edinburgh

22. McGillivray, Ian Grant. The measurement of electrical parameters and trace impurity effects in MOS capacitors.

Degree: PhD, 1987, University of Edinburgh

Subjects/Keywords: 621.31042; Microelectronic component test

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APA (6th Edition):

McGillivray, I. G. (1987). The measurement of electrical parameters and trace impurity effects in MOS capacitors. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/15333

Chicago Manual of Style (16th Edition):

McGillivray, Ian Grant. “The measurement of electrical parameters and trace impurity effects in MOS capacitors.” 1987. Doctoral Dissertation, University of Edinburgh. Accessed April 05, 2020. http://hdl.handle.net/1842/15333.

MLA Handbook (7th Edition):

McGillivray, Ian Grant. “The measurement of electrical parameters and trace impurity effects in MOS capacitors.” 1987. Web. 05 Apr 2020.

Vancouver:

McGillivray IG. The measurement of electrical parameters and trace impurity effects in MOS capacitors. [Internet] [Doctoral dissertation]. University of Edinburgh; 1987. [cited 2020 Apr 05]. Available from: http://hdl.handle.net/1842/15333.

Council of Science Editors:

McGillivray IG. The measurement of electrical parameters and trace impurity effects in MOS capacitors. [Doctoral Dissertation]. University of Edinburgh; 1987. Available from: http://hdl.handle.net/1842/15333

23. Spitaleri, Fabiola. Synthesis, characterization and thermal properties of polymers based composites materials for High Power Electronic Packaging Applications.

Degree: 2015, Università degli Studi di Catania

 As devices evolve, it s necessary that also interconnections and all hardware circuits evolve, including packaging. Nowadays are required significant improvement in packaging properties: low… (more)

Subjects/Keywords: Area 03 - Scienze chimiche; microelectronic packaging,epoxy resin,composites,energy saving

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APA (6th Edition):

Spitaleri, F. (2015). Synthesis, characterization and thermal properties of polymers based composites materials for High Power Electronic Packaging Applications. (Thesis). Università degli Studi di Catania. Retrieved from http://hdl.handle.net/10761/1727

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Spitaleri, Fabiola. “Synthesis, characterization and thermal properties of polymers based composites materials for High Power Electronic Packaging Applications.” 2015. Thesis, Università degli Studi di Catania. Accessed April 05, 2020. http://hdl.handle.net/10761/1727.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Spitaleri, Fabiola. “Synthesis, characterization and thermal properties of polymers based composites materials for High Power Electronic Packaging Applications.” 2015. Web. 05 Apr 2020.

Vancouver:

Spitaleri F. Synthesis, characterization and thermal properties of polymers based composites materials for High Power Electronic Packaging Applications. [Internet] [Thesis]. Università degli Studi di Catania; 2015. [cited 2020 Apr 05]. Available from: http://hdl.handle.net/10761/1727.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Spitaleri F. Synthesis, characterization and thermal properties of polymers based composites materials for High Power Electronic Packaging Applications. [Thesis]. Università degli Studi di Catania; 2015. Available from: http://hdl.handle.net/10761/1727

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Cechelero, Gustavo Sampaio e Silva. Sensores eletroquímicos para detecção de íons e medida de pH baseados em filmes de silício poroso.

Degree: Mestrado, Microeletrônica, 2007, University of São Paulo

O presente trabalho foi realizado com o objetivo de contribuir para o desenvolvimento tecnológico de sensores eletroquímicos utilizados na detecção de íons, especificamente, de íons… (more)

Subjects/Keywords: Electrochemistry; Eletroquímica; Microelectronic processes; Processos de microeletrônica; Silício; Silicon

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APA (6th Edition):

Cechelero, G. S. e. S. (2007). Sensores eletroquímicos para detecção de íons e medida de pH baseados em filmes de silício poroso. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04072007-152612/ ;

Chicago Manual of Style (16th Edition):

Cechelero, Gustavo Sampaio e Silva. “Sensores eletroquímicos para detecção de íons e medida de pH baseados em filmes de silício poroso.” 2007. Masters Thesis, University of São Paulo. Accessed April 05, 2020. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04072007-152612/ ;.

MLA Handbook (7th Edition):

Cechelero, Gustavo Sampaio e Silva. “Sensores eletroquímicos para detecção de íons e medida de pH baseados em filmes de silício poroso.” 2007. Web. 05 Apr 2020.

Vancouver:

Cechelero GSeS. Sensores eletroquímicos para detecção de íons e medida de pH baseados em filmes de silício poroso. [Internet] [Masters thesis]. University of São Paulo; 2007. [cited 2020 Apr 05]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04072007-152612/ ;.

Council of Science Editors:

Cechelero GSeS. Sensores eletroquímicos para detecção de íons e medida de pH baseados em filmes de silício poroso. [Masters Thesis]. University of São Paulo; 2007. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04072007-152612/ ;


Rochester Institute of Technology

25. Fullerton, Daniel. Process development of a novel pseudo two-phase CCD pixel using transparent conduction oxide electrodes.

Degree: Microelectronic Engineering, 2003, Rochester Institute of Technology

 A microelectronic fabrication process for an all-transparent electrode, pseudo two-phase CCD image sensor pixel, resistant to DC shorting and compatible with a self-aligned barrier implant,… (more)

Subjects/Keywords: CCD imaging; Microelectronic engineering

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APA (6th Edition):

Fullerton, D. (2003). Process development of a novel pseudo two-phase CCD pixel using transparent conduction oxide electrodes. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/1207

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fullerton, Daniel. “Process development of a novel pseudo two-phase CCD pixel using transparent conduction oxide electrodes.” 2003. Thesis, Rochester Institute of Technology. Accessed April 05, 2020. https://scholarworks.rit.edu/theses/1207.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fullerton, Daniel. “Process development of a novel pseudo two-phase CCD pixel using transparent conduction oxide electrodes.” 2003. Web. 05 Apr 2020.

Vancouver:

Fullerton D. Process development of a novel pseudo two-phase CCD pixel using transparent conduction oxide electrodes. [Internet] [Thesis]. Rochester Institute of Technology; 2003. [cited 2020 Apr 05]. Available from: https://scholarworks.rit.edu/theses/1207.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fullerton D. Process development of a novel pseudo two-phase CCD pixel using transparent conduction oxide electrodes. [Thesis]. Rochester Institute of Technology; 2003. Available from: https://scholarworks.rit.edu/theses/1207

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

26. Munger, Kevin. Polycrystalline silicon thermal actuators integrated with photodiode.

Degree: Microelectronic Engineering, 2002, Rochester Institute of Technology

 A thermal actuator (TA) is the thermal compliment of electrostatic actuators. A TA has several advantages over other microactuation methods. They can provide relatively large… (more)

Subjects/Keywords: Hardware; Microelectronic engineering; Software

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APA (6th Edition):

Munger, K. (2002). Polycrystalline silicon thermal actuators integrated with photodiode. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/1208

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Munger, Kevin. “Polycrystalline silicon thermal actuators integrated with photodiode.” 2002. Thesis, Rochester Institute of Technology. Accessed April 05, 2020. https://scholarworks.rit.edu/theses/1208.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Munger, Kevin. “Polycrystalline silicon thermal actuators integrated with photodiode.” 2002. Web. 05 Apr 2020.

Vancouver:

Munger K. Polycrystalline silicon thermal actuators integrated with photodiode. [Internet] [Thesis]. Rochester Institute of Technology; 2002. [cited 2020 Apr 05]. Available from: https://scholarworks.rit.edu/theses/1208.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Munger K. Polycrystalline silicon thermal actuators integrated with photodiode. [Thesis]. Rochester Institute of Technology; 2002. Available from: https://scholarworks.rit.edu/theses/1208

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Ouhab, Djamila. Auto-assemblage dirigé de copolymères à blocs de forte incompatibilité comprenant un bloc carbohydrate pour des applications de nano-Lithographie : Directed self-assembly of high incompatibility of block copolymers comprising a carbohydrate block for nano-lithography applications.

Degree: Docteur es, Sciences des polymères, 2016, Grenoble Alpes

En combinant l’expertise du Cermav dans la conception de films minces de très haute résolution obtenus par auto-assemblage de glycopolymères biosourcés et le savoir-faire du… (more)

Subjects/Keywords: Polymères; Auto-Assemblage; Microélectronique; Carbohydrate; Polymers; Self-Assembly; Microelectronic; Carbohydrate

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APA (6th Edition):

Ouhab, D. (2016). Auto-assemblage dirigé de copolymères à blocs de forte incompatibilité comprenant un bloc carbohydrate pour des applications de nano-Lithographie : Directed self-assembly of high incompatibility of block copolymers comprising a carbohydrate block for nano-lithography applications. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2016GREAV006

Chicago Manual of Style (16th Edition):

Ouhab, Djamila. “Auto-assemblage dirigé de copolymères à blocs de forte incompatibilité comprenant un bloc carbohydrate pour des applications de nano-Lithographie : Directed self-assembly of high incompatibility of block copolymers comprising a carbohydrate block for nano-lithography applications.” 2016. Doctoral Dissertation, Grenoble Alpes. Accessed April 05, 2020. http://www.theses.fr/2016GREAV006.

MLA Handbook (7th Edition):

Ouhab, Djamila. “Auto-assemblage dirigé de copolymères à blocs de forte incompatibilité comprenant un bloc carbohydrate pour des applications de nano-Lithographie : Directed self-assembly of high incompatibility of block copolymers comprising a carbohydrate block for nano-lithography applications.” 2016. Web. 05 Apr 2020.

Vancouver:

Ouhab D. Auto-assemblage dirigé de copolymères à blocs de forte incompatibilité comprenant un bloc carbohydrate pour des applications de nano-Lithographie : Directed self-assembly of high incompatibility of block copolymers comprising a carbohydrate block for nano-lithography applications. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2016. [cited 2020 Apr 05]. Available from: http://www.theses.fr/2016GREAV006.

Council of Science Editors:

Ouhab D. Auto-assemblage dirigé de copolymères à blocs de forte incompatibilité comprenant un bloc carbohydrate pour des applications de nano-Lithographie : Directed self-assembly of high incompatibility of block copolymers comprising a carbohydrate block for nano-lithography applications. [Doctoral Dissertation]. Grenoble Alpes; 2016. Available from: http://www.theses.fr/2016GREAV006


Universidade do Rio Grande do Sul

28. Flach, Guilherme Augusto. Clock mesh optimization.

Degree: 2010, Universidade do Rio Grande do Sul

Malhas de relógio são arquiteturas de rede de relógio adequadas para distribuir confiavelmente o sinal de relógio na presença de variações de processo e ambientais.… (more)

Subjects/Keywords: Clock; Microeletrônica; Clock mesh; Microprocessadores; Skew; Performance; Microprocessor; Variability; Microelectronic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Flach, G. A. (2010). Clock mesh optimization. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/34773

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Flach, Guilherme Augusto. “Clock mesh optimization.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed April 05, 2020. http://hdl.handle.net/10183/34773.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Flach, Guilherme Augusto. “Clock mesh optimization.” 2010. Web. 05 Apr 2020.

Vancouver:

Flach GA. Clock mesh optimization. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2020 Apr 05]. Available from: http://hdl.handle.net/10183/34773.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Flach GA. Clock mesh optimization. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/34773

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Chambettaz, Florentin. Caractérisation et développement d'un procédé de gravure séquentiel contrôlé à l'échelle nanométrique : Characterization and development of a nanoscale controlled sequential etching process for SiN spacers.

Degree: Docteur es, Nano electronique et nano technologies, 2018, Grenoble Alpes

La miniaturisation des dispositifs de la microélectronique nécessite la mise au point de procédé de gravure toujours plus précis. Le sujet de cette thèse s’inscrit… (more)

Subjects/Keywords: Microelectronique; Gravure Plasma; Implantion Hydrogène; Microelectronic; Plasma etching; Hydrogen implantation; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chambettaz, F. (2018). Caractérisation et développement d'un procédé de gravure séquentiel contrôlé à l'échelle nanométrique : Characterization and development of a nanoscale controlled sequential etching process for SiN spacers. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2018GREAT023

Chicago Manual of Style (16th Edition):

Chambettaz, Florentin. “Caractérisation et développement d'un procédé de gravure séquentiel contrôlé à l'échelle nanométrique : Characterization and development of a nanoscale controlled sequential etching process for SiN spacers.” 2018. Doctoral Dissertation, Grenoble Alpes. Accessed April 05, 2020. http://www.theses.fr/2018GREAT023.

MLA Handbook (7th Edition):

Chambettaz, Florentin. “Caractérisation et développement d'un procédé de gravure séquentiel contrôlé à l'échelle nanométrique : Characterization and development of a nanoscale controlled sequential etching process for SiN spacers.” 2018. Web. 05 Apr 2020.

Vancouver:

Chambettaz F. Caractérisation et développement d'un procédé de gravure séquentiel contrôlé à l'échelle nanométrique : Characterization and development of a nanoscale controlled sequential etching process for SiN spacers. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2018. [cited 2020 Apr 05]. Available from: http://www.theses.fr/2018GREAT023.

Council of Science Editors:

Chambettaz F. Caractérisation et développement d'un procédé de gravure séquentiel contrôlé à l'échelle nanométrique : Characterization and development of a nanoscale controlled sequential etching process for SiN spacers. [Doctoral Dissertation]. Grenoble Alpes; 2018. Available from: http://www.theses.fr/2018GREAT023

30. Garcia barros, Maxime. Développement et caractérisation de procédés de gravure des espaceurs Si3N4 et SiCO pour la technologie FDSOI 14nm. : Development and characterization of spacers etching process for 14 nm FDSOI technology.

Degree: Docteur es, Nano electronique et nano technologies, 2018, Grenoble Alpes

Les gravures par plasma pour les technologies sub 14nm nécessitent de bien contrôler la gravure de couches très minces de l’ordre du nanomètre, tout en… (more)

Subjects/Keywords: Microélectronnique; Gravure par plasma; Espaceur; Microelectronic; Etching by plasma; Spacer; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Garcia barros, M. (2018). Développement et caractérisation de procédés de gravure des espaceurs Si3N4 et SiCO pour la technologie FDSOI 14nm. : Development and characterization of spacers etching process for 14 nm FDSOI technology. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2018GREAT028

Chicago Manual of Style (16th Edition):

Garcia barros, Maxime. “Développement et caractérisation de procédés de gravure des espaceurs Si3N4 et SiCO pour la technologie FDSOI 14nm. : Development and characterization of spacers etching process for 14 nm FDSOI technology.” 2018. Doctoral Dissertation, Grenoble Alpes. Accessed April 05, 2020. http://www.theses.fr/2018GREAT028.

MLA Handbook (7th Edition):

Garcia barros, Maxime. “Développement et caractérisation de procédés de gravure des espaceurs Si3N4 et SiCO pour la technologie FDSOI 14nm. : Development and characterization of spacers etching process for 14 nm FDSOI technology.” 2018. Web. 05 Apr 2020.

Vancouver:

Garcia barros M. Développement et caractérisation de procédés de gravure des espaceurs Si3N4 et SiCO pour la technologie FDSOI 14nm. : Development and characterization of spacers etching process for 14 nm FDSOI technology. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2018. [cited 2020 Apr 05]. Available from: http://www.theses.fr/2018GREAT028.

Council of Science Editors:

Garcia barros M. Développement et caractérisation de procédés de gravure des espaceurs Si3N4 et SiCO pour la technologie FDSOI 14nm. : Development and characterization of spacers etching process for 14 nm FDSOI technology. [Doctoral Dissertation]. Grenoble Alpes; 2018. Available from: http://www.theses.fr/2018GREAT028

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