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You searched for subject:(Microelectronic packaging). Showing records 1 – 30 of 74 total matches.

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Hong Kong University of Science and Technology

1. Guan, Chunhua. Characterization and selecting criteria of die attach film (DAF) for adhesive die bonding packages.

Degree: 2013, Hong Kong University of Science and Technology

 Nowadays, die attach glue is widely used in adhesive die bonding packages, for its high heat dissipation ability and good resistance against thermal fatigue. However,… (more)

Subjects/Keywords: Microelectronic packaging; Electronic packaging; Adhesives

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APA (6th Edition):

Guan, C. (2013). Characterization and selecting criteria of die attach film (DAF) for adhesive die bonding packages. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1213720 ; http://repository.ust.hk/ir/bitstream/1783.1-7883/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Guan, Chunhua. “Characterization and selecting criteria of die attach film (DAF) for adhesive die bonding packages.” 2013. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1213720 ; http://repository.ust.hk/ir/bitstream/1783.1-7883/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Guan, Chunhua. “Characterization and selecting criteria of die attach film (DAF) for adhesive die bonding packages.” 2013. Web. 19 Sep 2019.

Vancouver:

Guan C. Characterization and selecting criteria of die attach film (DAF) for adhesive die bonding packages. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1213720 ; http://repository.ust.hk/ir/bitstream/1783.1-7883/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guan C. Characterization and selecting criteria of die attach film (DAF) for adhesive die bonding packages. [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: https://doi.org/10.14711/thesis-b1213720 ; http://repository.ust.hk/ir/bitstream/1783.1-7883/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Hong Kong

2. 박용화; Park, Yonghua. Packaging designs for geometrical shaping light emitting diodes.

Degree: M. Phil., 2017, University of Hong Kong

 Over more than two decades, Gallium-nitride (GaN)-based light-emitting diodes (LEDs) have successfully penetrated many applications starting with point light sources, general indoor lightings, LED displays… (more)

Subjects/Keywords: Microelectronic packaging; Light emitting diodes

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APA (6th Edition):

박용화; Park, Y. (2017). Packaging designs for geometrical shaping light emitting diodes. (Masters Thesis). University of Hong Kong. Retrieved from http://hdl.handle.net/10722/249925

Chicago Manual of Style (16th Edition):

박용화; Park, Yonghua. “Packaging designs for geometrical shaping light emitting diodes.” 2017. Masters Thesis, University of Hong Kong. Accessed September 19, 2019. http://hdl.handle.net/10722/249925.

MLA Handbook (7th Edition):

박용화; Park, Yonghua. “Packaging designs for geometrical shaping light emitting diodes.” 2017. Web. 19 Sep 2019.

Vancouver:

박용화; Park Y. Packaging designs for geometrical shaping light emitting diodes. [Internet] [Masters thesis]. University of Hong Kong; 2017. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/10722/249925.

Council of Science Editors:

박용화; Park Y. Packaging designs for geometrical shaping light emitting diodes. [Masters Thesis]. University of Hong Kong; 2017. Available from: http://hdl.handle.net/10722/249925


Hong Kong University of Science and Technology

3. Han, Jiale. Wire sweep study of package array mold during transfer molding process.

Degree: 2012, Hong Kong University of Science and Technology

 In order to maximize production rate, an increasing number of electronic packages are manufactured in a package array mold, such as Small Outline Transistor (SOT)… (more)

Subjects/Keywords: Microelectronic packaging  – Mathematical models

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APA (6th Edition):

Han, J. (2012). Wire sweep study of package array mold during transfer molding process. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1180182 ; http://repository.ust.hk/ir/bitstream/1783.1-7579/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Han, Jiale. “Wire sweep study of package array mold during transfer molding process.” 2012. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1180182 ; http://repository.ust.hk/ir/bitstream/1783.1-7579/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Han, Jiale. “Wire sweep study of package array mold during transfer molding process.” 2012. Web. 19 Sep 2019.

Vancouver:

Han J. Wire sweep study of package array mold during transfer molding process. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2012. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1180182 ; http://repository.ust.hk/ir/bitstream/1783.1-7579/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Han J. Wire sweep study of package array mold during transfer molding process. [Thesis]. Hong Kong University of Science and Technology; 2012. Available from: https://doi.org/10.14711/thesis-b1180182 ; http://repository.ust.hk/ir/bitstream/1783.1-7579/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

4. Chen, Kewei. Integration of phosphor printing and encapsulant dispensing processes for LED array wafer level packaging.

Degree: 2011, Hong Kong University of Science and Technology

 Solid-state lighting (SSL) using light-emitting diode (LED) as an alternative light source is an emerging technology. Compared with conventional light sources, LEDs have superior characteristics… (more)

Subjects/Keywords: Light emitting diodes; Microelectronic packaging

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APA (6th Edition):

Chen, K. (2011). Integration of phosphor printing and encapsulant dispensing processes for LED array wafer level packaging. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1136689 ; http://repository.ust.hk/ir/bitstream/1783.1-7154/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Kewei. “Integration of phosphor printing and encapsulant dispensing processes for LED array wafer level packaging.” 2011. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1136689 ; http://repository.ust.hk/ir/bitstream/1783.1-7154/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Kewei. “Integration of phosphor printing and encapsulant dispensing processes for LED array wafer level packaging.” 2011. Web. 19 Sep 2019.

Vancouver:

Chen K. Integration of phosphor printing and encapsulant dispensing processes for LED array wafer level packaging. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2011. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1136689 ; http://repository.ust.hk/ir/bitstream/1783.1-7154/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen K. Integration of phosphor printing and encapsulant dispensing processes for LED array wafer level packaging. [Thesis]. Hong Kong University of Science and Technology; 2011. Available from: https://doi.org/10.14711/thesis-b1136689 ; http://repository.ust.hk/ir/bitstream/1783.1-7154/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

5. Wang, Su. Fast filling of through silicon vias (TSV) and related reliability studies.

Degree: 2013, Hong Kong University of Science and Technology

 There is an increasing demand for electronic devices with smaller sizes, higher performances and increased functionality. The formation of vertical interconnects or through silicon vias… (more)

Subjects/Keywords: Microelectronic packaging; Reliability; Electroplating

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APA (6th Edition):

Wang, S. (2013). Fast filling of through silicon vias (TSV) and related reliability studies. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1251530 ; http://repository.ust.hk/ir/bitstream/1783.1-62263/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Su. “Fast filling of through silicon vias (TSV) and related reliability studies.” 2013. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1251530 ; http://repository.ust.hk/ir/bitstream/1783.1-62263/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Su. “Fast filling of through silicon vias (TSV) and related reliability studies.” 2013. Web. 19 Sep 2019.

Vancouver:

Wang S. Fast filling of through silicon vias (TSV) and related reliability studies. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1251530 ; http://repository.ust.hk/ir/bitstream/1783.1-62263/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang S. Fast filling of through silicon vias (TSV) and related reliability studies. [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: https://doi.org/10.14711/thesis-b1251530 ; http://repository.ust.hk/ir/bitstream/1783.1-62263/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

6. Chen, Wei. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.

Degree: PhD, Mechanical Engineering, 2015, Georgia Tech

 Free-standing off-chip interconnects have high in-plane and out-of-plane compliance and are being pursued in academia and industry to reduce die stresses and to enhance interconnect… (more)

Subjects/Keywords: Compliant interconnect; Microelectronic packaging; Packaging reliability

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APA (6th Edition):

Chen, W. (2015). Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55550

Chicago Manual of Style (16th Edition):

Chen, Wei. “Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.” 2015. Doctoral Dissertation, Georgia Tech. Accessed September 19, 2019. http://hdl.handle.net/1853/55550.

MLA Handbook (7th Edition):

Chen, Wei. “Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.” 2015. Web. 19 Sep 2019.

Vancouver:

Chen W. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1853/55550.

Council of Science Editors:

Chen W. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/55550


Hong Kong University of Science and Technology

7. Liu, Huihua. LED wafer level packaging with remote phosphor and correlated ray tracing optical simulation.

Degree: 2013, Hong Kong University of Science and Technology

 LEDs provide an environmental friendly light source for general lighting. They offer high efficiency, a long life span and do not contain hazardous substances. Wafer… (more)

Subjects/Keywords: Light emitting diodes; Microelectronic packaging; Phosphors

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APA (6th Edition):

Liu, H. (2013). LED wafer level packaging with remote phosphor and correlated ray tracing optical simulation. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1255616 ; http://repository.ust.hk/ir/bitstream/1783.1-62371/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Huihua. “LED wafer level packaging with remote phosphor and correlated ray tracing optical simulation.” 2013. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1255616 ; http://repository.ust.hk/ir/bitstream/1783.1-62371/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Huihua. “LED wafer level packaging with remote phosphor and correlated ray tracing optical simulation.” 2013. Web. 19 Sep 2019.

Vancouver:

Liu H. LED wafer level packaging with remote phosphor and correlated ray tracing optical simulation. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1255616 ; http://repository.ust.hk/ir/bitstream/1783.1-62371/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu H. LED wafer level packaging with remote phosphor and correlated ray tracing optical simulation. [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: https://doi.org/10.14711/thesis-b1255616 ; http://repository.ust.hk/ir/bitstream/1783.1-62371/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

8. Wu, Hailong. Analytical characterization of electrolyte and additives for high quality copper plating of through silicon vias (TSVs).

Degree: 2013, Hong Kong University of Science and Technology

 The heart of three-dimensional (3D) Si integration is the copper filled Through Silicon Via (TSV), which allows the shortest chip-to-chip interconnections. The copper filling of… (more)

Subjects/Keywords: Microelectronic packaging; Silicon; Additives; Copper plating; Electroplating

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APA (6th Edition):

Wu, H. (2013). Analytical characterization of electrolyte and additives for high quality copper plating of through silicon vias (TSVs). (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1251161 ; http://repository.ust.hk/ir/bitstream/1783.1-73430/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Hailong. “Analytical characterization of electrolyte and additives for high quality copper plating of through silicon vias (TSVs).” 2013. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1251161 ; http://repository.ust.hk/ir/bitstream/1783.1-73430/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Hailong. “Analytical characterization of electrolyte and additives for high quality copper plating of through silicon vias (TSVs).” 2013. Web. 19 Sep 2019.

Vancouver:

Wu H. Analytical characterization of electrolyte and additives for high quality copper plating of through silicon vias (TSVs). [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1251161 ; http://repository.ust.hk/ir/bitstream/1783.1-73430/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu H. Analytical characterization of electrolyte and additives for high quality copper plating of through silicon vias (TSVs). [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: https://doi.org/10.14711/thesis-b1251161 ; http://repository.ust.hk/ir/bitstream/1783.1-73430/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

9. Xue, Ke. Simulation based design optimization for microelectronics packaging product.

Degree: 2010, Hong Kong University of Science and Technology

 Reduction in size of portable products such as cellular phones and camcorders has led to the miniaturization of integrated circuit packages. Fine-pitch BGA (fpBGA) packages… (more)

Subjects/Keywords: Microelectronic packaging  – Design and construction  – Simulation methods

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APA (6th Edition):

Xue, K. (2010). Simulation based design optimization for microelectronics packaging product. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1115043 ; http://repository.ust.hk/ir/bitstream/1783.1-7038/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xue, Ke. “Simulation based design optimization for microelectronics packaging product.” 2010. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1115043 ; http://repository.ust.hk/ir/bitstream/1783.1-7038/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xue, Ke. “Simulation based design optimization for microelectronics packaging product.” 2010. Web. 19 Sep 2019.

Vancouver:

Xue K. Simulation based design optimization for microelectronics packaging product. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2010. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1115043 ; http://repository.ust.hk/ir/bitstream/1783.1-7038/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xue K. Simulation based design optimization for microelectronics packaging product. [Thesis]. Hong Kong University of Science and Technology; 2010. Available from: https://doi.org/10.14711/thesis-b1115043 ; http://repository.ust.hk/ir/bitstream/1783.1-7038/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

10. Fakhry, Tayaz. Optimization of a compact thermal model for a Ball Grid Array (BGA) package using experimental data.

Degree: 2011, Ryerson University

 The goal of this research is to optimize a static and dynamic compact thermal model for a ball grid array (BGA) package using experimental data.… (more)

Subjects/Keywords: Ball grid array technology; Microelectronic packaging

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APA (6th Edition):

Fakhry, T. (2011). Optimization of a compact thermal model for a Ball Grid Array (BGA) package using experimental data. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fakhry, Tayaz. “Optimization of a compact thermal model for a Ball Grid Array (BGA) package using experimental data.” 2011. Thesis, Ryerson University. Accessed September 19, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fakhry, Tayaz. “Optimization of a compact thermal model for a Ball Grid Array (BGA) package using experimental data.” 2011. Web. 19 Sep 2019.

Vancouver:

Fakhry T. Optimization of a compact thermal model for a Ball Grid Array (BGA) package using experimental data. [Internet] [Thesis]. Ryerson University; 2011. [cited 2019 Sep 19]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fakhry T. Optimization of a compact thermal model for a Ball Grid Array (BGA) package using experimental data. [Thesis]. Ryerson University; 2011. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

11. Liu, Dong. A study on the relationship of processing conditions, microstructure and properties of copper wirebond in microelectronic connections.

Degree: 2014, Hong Kong University of Science and Technology

 Wire bonding is one of the dominant microelectronic connection technologies, which provides electrical connection between integrated circuits and external leads. A solid free air ball… (more)

Subjects/Keywords: Wire bonding (Electronic packaging); Microelectronic packaging; Interconnects (Integrated circuit technology)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, D. (2014). A study on the relationship of processing conditions, microstructure and properties of copper wirebond in microelectronic connections. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1333922 ; http://repository.ust.hk/ir/bitstream/1783.1-87490/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Dong. “A study on the relationship of processing conditions, microstructure and properties of copper wirebond in microelectronic connections.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1333922 ; http://repository.ust.hk/ir/bitstream/1783.1-87490/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Dong. “A study on the relationship of processing conditions, microstructure and properties of copper wirebond in microelectronic connections.” 2014. Web. 19 Sep 2019.

Vancouver:

Liu D. A study on the relationship of processing conditions, microstructure and properties of copper wirebond in microelectronic connections. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1333922 ; http://repository.ust.hk/ir/bitstream/1783.1-87490/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu D. A study on the relationship of processing conditions, microstructure and properties of copper wirebond in microelectronic connections. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: https://doi.org/10.14711/thesis-b1333922 ; http://repository.ust.hk/ir/bitstream/1783.1-87490/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

12. Sundaram, Venkatesh. Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics.

Degree: PhD, Materials Science and Engineering, 2009, Georgia Tech

 The fundamental motivation for this dissertation is to address the widening interconnect gap between integrated circuit (IC) demands and package substrates specifically for high frequency… (more)

Subjects/Keywords: Semiconductors; Electronics; Microsystems; Substrates; Packaging; System on a package; Microelectronic packaging; Interconnects (Integrated circuit technology)

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APA (6th Edition):

Sundaram, V. (2009). Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/28141

Chicago Manual of Style (16th Edition):

Sundaram, Venkatesh. “Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics.” 2009. Doctoral Dissertation, Georgia Tech. Accessed September 19, 2019. http://hdl.handle.net/1853/28141.

MLA Handbook (7th Edition):

Sundaram, Venkatesh. “Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics.” 2009. Web. 19 Sep 2019.

Vancouver:

Sundaram V. Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1853/28141.

Council of Science Editors:

Sundaram V. Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/28141


University of North Texas

13. Gaddam, Sneha Sen. The Effect of Plasma on Silicon Nitride, Oxynitride and Other Metals for Enhanced Epoxy Adhesion for Packaging Applications.

Degree: 2014, University of North Texas

 The effects of direct plasma chemistries on carbon removal from silicon nitride (SiNx) and oxynitride (SiOxNy ) surfaces and Cu have been studied by x-photoelectron… (more)

Subjects/Keywords: plasma; packaging; contact angle; Plasma chemistry.; Silicon nitride.; Epoxy coatings.; Adhesives.; Microelectronic packaging.

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APA (6th Edition):

Gaddam, S. S. (2014). The Effect of Plasma on Silicon Nitride, Oxynitride and Other Metals for Enhanced Epoxy Adhesion for Packaging Applications. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc700040/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gaddam, Sneha Sen. “The Effect of Plasma on Silicon Nitride, Oxynitride and Other Metals for Enhanced Epoxy Adhesion for Packaging Applications.” 2014. Thesis, University of North Texas. Accessed September 19, 2019. https://digital.library.unt.edu/ark:/67531/metadc700040/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gaddam, Sneha Sen. “The Effect of Plasma on Silicon Nitride, Oxynitride and Other Metals for Enhanced Epoxy Adhesion for Packaging Applications.” 2014. Web. 19 Sep 2019.

Vancouver:

Gaddam SS. The Effect of Plasma on Silicon Nitride, Oxynitride and Other Metals for Enhanced Epoxy Adhesion for Packaging Applications. [Internet] [Thesis]. University of North Texas; 2014. [cited 2019 Sep 19]. Available from: https://digital.library.unt.edu/ark:/67531/metadc700040/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gaddam SS. The Effect of Plasma on Silicon Nitride, Oxynitride and Other Metals for Enhanced Epoxy Adhesion for Packaging Applications. [Thesis]. University of North Texas; 2014. Available from: https://digital.library.unt.edu/ark:/67531/metadc700040/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

14. Spitaleri, Fabiola. Synthesis, characterization and thermal properties of polymers based composites materials for High Power Electronic Packaging Applications.

Degree: 2015, Università degli Studi di Catania

 As devices evolve, it s necessary that also interconnections and all hardware circuits evolve, including packaging. Nowadays are required significant improvement in packaging properties: low… (more)

Subjects/Keywords: Area 03 - Scienze chimiche; microelectronic packaging,epoxy resin,composites,energy saving

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APA (6th Edition):

Spitaleri, F. (2015). Synthesis, characterization and thermal properties of polymers based composites materials for High Power Electronic Packaging Applications. (Thesis). Università degli Studi di Catania. Retrieved from http://hdl.handle.net/10761/1727

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Spitaleri, Fabiola. “Synthesis, characterization and thermal properties of polymers based composites materials for High Power Electronic Packaging Applications.” 2015. Thesis, Università degli Studi di Catania. Accessed September 19, 2019. http://hdl.handle.net/10761/1727.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Spitaleri, Fabiola. “Synthesis, characterization and thermal properties of polymers based composites materials for High Power Electronic Packaging Applications.” 2015. Web. 19 Sep 2019.

Vancouver:

Spitaleri F. Synthesis, characterization and thermal properties of polymers based composites materials for High Power Electronic Packaging Applications. [Internet] [Thesis]. Università degli Studi di Catania; 2015. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/10761/1727.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Spitaleri F. Synthesis, characterization and thermal properties of polymers based composites materials for High Power Electronic Packaging Applications. [Thesis]. Università degli Studi di Catania; 2015. Available from: http://hdl.handle.net/10761/1727

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

15. Ding, Hua. Thermal modeling of three-dimensional integrated circuits considering the thermal removal capability of different TSVs.

Degree: 2011, Hong Kong University of Science and Technology

 Three-dimensional integrated circuit (3D ICs) technology has become a popular research topic to further enhance integration scale as well as reduce the interconnection cost. However,… (more)

Subjects/Keywords: Integrated circuits; Design and construction; Thermal properties; Microelectronic packaging

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APA (6th Edition):

Ding, H. (2011). Thermal modeling of three-dimensional integrated circuits considering the thermal removal capability of different TSVs. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1155582 ; http://repository.ust.hk/ir/bitstream/1783.1-62483/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ding, Hua. “Thermal modeling of three-dimensional integrated circuits considering the thermal removal capability of different TSVs.” 2011. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1155582 ; http://repository.ust.hk/ir/bitstream/1783.1-62483/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ding, Hua. “Thermal modeling of three-dimensional integrated circuits considering the thermal removal capability of different TSVs.” 2011. Web. 19 Sep 2019.

Vancouver:

Ding H. Thermal modeling of three-dimensional integrated circuits considering the thermal removal capability of different TSVs. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2011. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1155582 ; http://repository.ust.hk/ir/bitstream/1783.1-62483/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ding H. Thermal modeling of three-dimensional integrated circuits considering the thermal removal capability of different TSVs. [Thesis]. Hong Kong University of Science and Technology; 2011. Available from: https://doi.org/10.14711/thesis-b1155582 ; http://repository.ust.hk/ir/bitstream/1783.1-62483/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

16. Yang, Chaoran. Comparison of thermal fatigue reliability between SAC and SnPb solders under various stress range conditions.

Degree: 2009, Hong Kong University of Science and Technology

 A general idea of thermal reliability of the tin-lead (SnPb) solder and the tin-silver-copper (SAC) solder family is that the SAC solders give a better… (more)

Subjects/Keywords: Solder and soldering  – Thermal properties  – Testing; Microelectronic packaging

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APA (6th Edition):

Yang, C. (2009). Comparison of thermal fatigue reliability between SAC and SnPb solders under various stress range conditions. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1097574 ; http://repository.ust.hk/ir/bitstream/1783.1-6493/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Chaoran. “Comparison of thermal fatigue reliability between SAC and SnPb solders under various stress range conditions.” 2009. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1097574 ; http://repository.ust.hk/ir/bitstream/1783.1-6493/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Chaoran. “Comparison of thermal fatigue reliability between SAC and SnPb solders under various stress range conditions.” 2009. Web. 19 Sep 2019.

Vancouver:

Yang C. Comparison of thermal fatigue reliability between SAC and SnPb solders under various stress range conditions. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2009. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1097574 ; http://repository.ust.hk/ir/bitstream/1783.1-6493/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang C. Comparison of thermal fatigue reliability between SAC and SnPb solders under various stress range conditions. [Thesis]. Hong Kong University of Science and Technology; 2009. Available from: https://doi.org/10.14711/thesis-b1097574 ; http://repository.ust.hk/ir/bitstream/1783.1-6493/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

17. Hung, Chung Yan. Solder bumping for flip-chip applications.

Degree: 1999, Hong Kong University of Science and Technology

 An advanced packaging technology (developed over 40 years ago) which has begun to generate renewed interest is the solder-bumped flip chip technology. This interconnection method… (more)

Subjects/Keywords: Microelectronic packaging; Solder and soldering

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APA (6th Edition):

Hung, C. Y. (1999). Solder bumping for flip-chip applications. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b622465 ; http://repository.ust.hk/ir/bitstream/1783.1-4500/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hung, Chung Yan. “Solder bumping for flip-chip applications.” 1999. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b622465 ; http://repository.ust.hk/ir/bitstream/1783.1-4500/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hung, Chung Yan. “Solder bumping for flip-chip applications.” 1999. Web. 19 Sep 2019.

Vancouver:

Hung CY. Solder bumping for flip-chip applications. [Internet] [Thesis]. Hong Kong University of Science and Technology; 1999. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b622465 ; http://repository.ust.hk/ir/bitstream/1783.1-4500/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hung CY. Solder bumping for flip-chip applications. [Thesis]. Hong Kong University of Science and Technology; 1999. Available from: https://doi.org/10.14711/thesis-b622465 ; http://repository.ust.hk/ir/bitstream/1783.1-4500/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

18. Hon, Chi Kwong. 3D packaging of multi-stacked flip chips with plugged through silicon vias for vertical interconnection.

Degree: 2006, Hong Kong University of Science and Technology

 Three-dimensional packaging (3DP) is an emerging trend in microelectronics development toward system in package (SiP). 3D flip chip stacking structures with through silicon vias (TSVs)… (more)

Subjects/Keywords: Microelectronic packaging; Multichip modules (Microelectronics)

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APA (6th Edition):

Hon, C. K. (2006). 3D packaging of multi-stacked flip chips with plugged through silicon vias for vertical interconnection. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b931619 ; http://repository.ust.hk/ir/bitstream/1783.1-5286/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hon, Chi Kwong. “3D packaging of multi-stacked flip chips with plugged through silicon vias for vertical interconnection.” 2006. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b931619 ; http://repository.ust.hk/ir/bitstream/1783.1-5286/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hon, Chi Kwong. “3D packaging of multi-stacked flip chips with plugged through silicon vias for vertical interconnection.” 2006. Web. 19 Sep 2019.

Vancouver:

Hon CK. 3D packaging of multi-stacked flip chips with plugged through silicon vias for vertical interconnection. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2006. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b931619 ; http://repository.ust.hk/ir/bitstream/1783.1-5286/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hon CK. 3D packaging of multi-stacked flip chips with plugged through silicon vias for vertical interconnection. [Thesis]. Hong Kong University of Science and Technology; 2006. Available from: https://doi.org/10.14711/thesis-b931619 ; http://repository.ust.hk/ir/bitstream/1783.1-5286/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

19. Kwatra, Abhishek. Effect of temperature and humidity conditioning on mold compound/copper interfacial fracture and the associated cohesive zone models.

Degree: MS, Mechanical Engineering, 2016, Georgia Tech

Microelectronic packages consist of multilayered structures made of dissimilar materials. Interfacial delamination is a common failure mechanism present in microelectronic packages due to the mismatch… (more)

Subjects/Keywords: Mechanical reliability; Interfacial fracture mechanics; Microelectronic packaging; Finite element modeling

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APA (6th Edition):

Kwatra, A. (2016). Effect of temperature and humidity conditioning on mold compound/copper interfacial fracture and the associated cohesive zone models. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59166

Chicago Manual of Style (16th Edition):

Kwatra, Abhishek. “Effect of temperature and humidity conditioning on mold compound/copper interfacial fracture and the associated cohesive zone models.” 2016. Masters Thesis, Georgia Tech. Accessed September 19, 2019. http://hdl.handle.net/1853/59166.

MLA Handbook (7th Edition):

Kwatra, Abhishek. “Effect of temperature and humidity conditioning on mold compound/copper interfacial fracture and the associated cohesive zone models.” 2016. Web. 19 Sep 2019.

Vancouver:

Kwatra A. Effect of temperature and humidity conditioning on mold compound/copper interfacial fracture and the associated cohesive zone models. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1853/59166.

Council of Science Editors:

Kwatra A. Effect of temperature and humidity conditioning on mold compound/copper interfacial fracture and the associated cohesive zone models. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/59166


Hong Kong University of Science and Technology

20. Li, Lin. Phase-change memory on thin-film-transistor technology for system-on-panel applications.

Degree: 2012, Hong Kong University of Science and Technology

 At the mobile multi-media age, high resolution flat-panel displays are becoming the central feature of many consumer products. Functional circuit blocks monolithically integrated with the… (more)

Subjects/Keywords: Thin film transistors; Phase change memory; Microelectronic packaging

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APA (6th Edition):

Li, L. (2012). Phase-change memory on thin-film-transistor technology for system-on-panel applications. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1165777 ; http://repository.ust.hk/ir/bitstream/1783.1-92023/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Lin. “Phase-change memory on thin-film-transistor technology for system-on-panel applications.” 2012. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1165777 ; http://repository.ust.hk/ir/bitstream/1783.1-92023/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Lin. “Phase-change memory on thin-film-transistor technology for system-on-panel applications.” 2012. Web. 19 Sep 2019.

Vancouver:

Li L. Phase-change memory on thin-film-transistor technology for system-on-panel applications. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2012. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1165777 ; http://repository.ust.hk/ir/bitstream/1783.1-92023/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li L. Phase-change memory on thin-film-transistor technology for system-on-panel applications. [Thesis]. Hong Kong University of Science and Technology; 2012. Available from: https://doi.org/10.14711/thesis-b1165777 ; http://repository.ust.hk/ir/bitstream/1783.1-92023/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

21. Lightsey, Charles Hunter. All-copper chip-to-substrate interconnections for flip-chip packages.

Degree: MS, Chemical Engineering, 2010, Georgia Tech

 Avatrel 8000P's excellent photo-definition properties and mechanical strength make it an ideal polymer collar material. Avatrel 8000P is a high contrast, I-line sensitive mixture that… (more)

Subjects/Keywords: Bonding; Flip-chip; Pillar; Electroless deposition; Copper; Flip chip technology; Microelectronic packaging; Microelectronics; Electroless plating

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APA (6th Edition):

Lightsey, C. H. (2010). All-copper chip-to-substrate interconnections for flip-chip packages. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/34729

Chicago Manual of Style (16th Edition):

Lightsey, Charles Hunter. “All-copper chip-to-substrate interconnections for flip-chip packages.” 2010. Masters Thesis, Georgia Tech. Accessed September 19, 2019. http://hdl.handle.net/1853/34729.

MLA Handbook (7th Edition):

Lightsey, Charles Hunter. “All-copper chip-to-substrate interconnections for flip-chip packages.” 2010. Web. 19 Sep 2019.

Vancouver:

Lightsey CH. All-copper chip-to-substrate interconnections for flip-chip packages. [Internet] [Masters thesis]. Georgia Tech; 2010. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1853/34729.

Council of Science Editors:

Lightsey CH. All-copper chip-to-substrate interconnections for flip-chip packages. [Masters Thesis]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/34729


Georgia Tech

22. Lee, Sangil. Fundamental study of underfill void formation in flip chip assembly.

Degree: PhD, Mechanical Engineering, 2009, Georgia Tech

 Flip Chip in Package (FCIP) has been developed to achieve the assembly process with area array interconnects. Particularly, a high I/O count coupled with finer… (more)

Subjects/Keywords: Nano; Nucleation; Void; No-flow; Flip chip; Flip chip technology; Microelectronic packaging; Solder and soldering

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APA (6th Edition):

Lee, S. (2009). Fundamental study of underfill void formation in flip chip assembly. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/29755

Chicago Manual of Style (16th Edition):

Lee, Sangil. “Fundamental study of underfill void formation in flip chip assembly.” 2009. Doctoral Dissertation, Georgia Tech. Accessed September 19, 2019. http://hdl.handle.net/1853/29755.

MLA Handbook (7th Edition):

Lee, Sangil. “Fundamental study of underfill void formation in flip chip assembly.” 2009. Web. 19 Sep 2019.

Vancouver:

Lee S. Fundamental study of underfill void formation in flip chip assembly. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1853/29755.

Council of Science Editors:

Lee S. Fundamental study of underfill void formation in flip chip assembly. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/29755


Hong Kong University of Science and Technology

23. Le, Fuliang. Through-silicon-via underfill dispensing for 3D die/interposer stacking.

Degree: 2014, Hong Kong University of Science and Technology

 The next generation packaging keeps up with the increased demands of functionality by using the third dimension. 3D chip stacking with TSVs has been identified… (more)

Subjects/Keywords: Microelectronic packaging; Electronic apparatus and appliances; Plastic embedment; Three-dimensional integrated circuits; Multichip modules (Microelectronics)

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APA (6th Edition):

Le, F. (2014). Through-silicon-via underfill dispensing for 3D die/interposer stacking. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1333928 ; http://repository.ust.hk/ir/bitstream/1783.1-71616/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Le, Fuliang. “Through-silicon-via underfill dispensing for 3D die/interposer stacking.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1333928 ; http://repository.ust.hk/ir/bitstream/1783.1-71616/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Le, Fuliang. “Through-silicon-via underfill dispensing for 3D die/interposer stacking.” 2014. Web. 19 Sep 2019.

Vancouver:

Le F. Through-silicon-via underfill dispensing for 3D die/interposer stacking. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1333928 ; http://repository.ust.hk/ir/bitstream/1783.1-71616/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Le F. Through-silicon-via underfill dispensing for 3D die/interposer stacking. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: https://doi.org/10.14711/thesis-b1333928 ; http://repository.ust.hk/ir/bitstream/1783.1-71616/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

24. Bi, Xianghong. Evaluation of graphene oxide - silicone die attach adhesive in LED packaging.

Degree: 2014, Hong Kong University of Science and Technology

 The successful wide application of LED lighting in general lighting market requires reduction in product cost, among which, LED packaging cost is proved to be… (more)

Subjects/Keywords: Light emitting diodes; Graphene; Oxidation; Solid state electronics; Synthesis; Microelectronic packaging; Materials

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APA (6th Edition):

Bi, X. (2014). Evaluation of graphene oxide - silicone die attach adhesive in LED packaging. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1333627 ; http://repository.ust.hk/ir/bitstream/1783.1-70835/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bi, Xianghong. “Evaluation of graphene oxide - silicone die attach adhesive in LED packaging.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b1333627 ; http://repository.ust.hk/ir/bitstream/1783.1-70835/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bi, Xianghong. “Evaluation of graphene oxide - silicone die attach adhesive in LED packaging.” 2014. Web. 19 Sep 2019.

Vancouver:

Bi X. Evaluation of graphene oxide - silicone die attach adhesive in LED packaging. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b1333627 ; http://repository.ust.hk/ir/bitstream/1783.1-70835/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bi X. Evaluation of graphene oxide - silicone die attach adhesive in LED packaging. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: https://doi.org/10.14711/thesis-b1333627 ; http://repository.ust.hk/ir/bitstream/1783.1-70835/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

25. Creel, Kenneth E. A thermal analysis tool for three-dimensional models of multilayer microelectronics.

Degree: MS, Mechanical Engineering, 1994, Virginia Tech

see document Advisors/Committee Members: Nelson, Douglas J. (committeechair), Vick, Brian L. (committee member), Elshabini-Riad, Aicha A. (committee member).

Subjects/Keywords: Microelectronic packaging; LD5655.V855 1994.C744

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APA (6th Edition):

Creel, K. E. (1994). A thermal analysis tool for three-dimensional models of multilayer microelectronics. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/42489

Chicago Manual of Style (16th Edition):

Creel, Kenneth E. “A thermal analysis tool for three-dimensional models of multilayer microelectronics.” 1994. Masters Thesis, Virginia Tech. Accessed September 19, 2019. http://hdl.handle.net/10919/42489.

MLA Handbook (7th Edition):

Creel, Kenneth E. “A thermal analysis tool for three-dimensional models of multilayer microelectronics.” 1994. Web. 19 Sep 2019.

Vancouver:

Creel KE. A thermal analysis tool for three-dimensional models of multilayer microelectronics. [Internet] [Masters thesis]. Virginia Tech; 1994. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/10919/42489.

Council of Science Editors:

Creel KE. A thermal analysis tool for three-dimensional models of multilayer microelectronics. [Masters Thesis]. Virginia Tech; 1994. Available from: http://hdl.handle.net/10919/42489


University of Arizona

26. Mustapha, Lateef Abimbola. Thermo-Mechanical Characterization and Interfacial Thermal Resistance Studies of Chemically Modified Carbon Nanotube Thermal Interface Material - Experimental and Mechanistic Approaches .

Degree: 2017, University of Arizona

 Effective application of thermal interface materials (TIM) sandwiched between silicon and a heat spreader in a microelectronic package for improved heat dissipation is studied through… (more)

Subjects/Keywords: Integrated Circuits; Microelectronic Packaging; Thermal Conductivity; Thermal Design power; Thermal Interface Material; Thermal Interface resistance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mustapha, L. A. (2017). Thermo-Mechanical Characterization and Interfacial Thermal Resistance Studies of Chemically Modified Carbon Nanotube Thermal Interface Material - Experimental and Mechanistic Approaches . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/625379

Chicago Manual of Style (16th Edition):

Mustapha, Lateef Abimbola. “Thermo-Mechanical Characterization and Interfacial Thermal Resistance Studies of Chemically Modified Carbon Nanotube Thermal Interface Material - Experimental and Mechanistic Approaches .” 2017. Doctoral Dissertation, University of Arizona. Accessed September 19, 2019. http://hdl.handle.net/10150/625379.

MLA Handbook (7th Edition):

Mustapha, Lateef Abimbola. “Thermo-Mechanical Characterization and Interfacial Thermal Resistance Studies of Chemically Modified Carbon Nanotube Thermal Interface Material - Experimental and Mechanistic Approaches .” 2017. Web. 19 Sep 2019.

Vancouver:

Mustapha LA. Thermo-Mechanical Characterization and Interfacial Thermal Resistance Studies of Chemically Modified Carbon Nanotube Thermal Interface Material - Experimental and Mechanistic Approaches . [Internet] [Doctoral dissertation]. University of Arizona; 2017. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/10150/625379.

Council of Science Editors:

Mustapha LA. Thermo-Mechanical Characterization and Interfacial Thermal Resistance Studies of Chemically Modified Carbon Nanotube Thermal Interface Material - Experimental and Mechanistic Approaches . [Doctoral Dissertation]. University of Arizona; 2017. Available from: http://hdl.handle.net/10150/625379


Hong Kong University of Science and Technology

27. Zhang, Xiaowu. Solder joint reliability of plastic ball grid array (PBGA) and bottom-leaded plastic (BLP) assemblies.

Degree: 1998, Hong Kong University of Science and Technology

 The plastic ball grid array (PBGA) and the bottom-leaded plastic (BLP) packages have attracted substantial attention since their appearance in the electronics industry. Since the… (more)

Subjects/Keywords: Ball grid array technology; Electronic packaging; Microelectronic packaging

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, X. (1998). Solder joint reliability of plastic ball grid array (PBGA) and bottom-leaded plastic (BLP) assemblies. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b622420 ; http://repository.ust.hk/ir/bitstream/1783.1-1576/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Xiaowu. “Solder joint reliability of plastic ball grid array (PBGA) and bottom-leaded plastic (BLP) assemblies.” 1998. Thesis, Hong Kong University of Science and Technology. Accessed September 19, 2019. https://doi.org/10.14711/thesis-b622420 ; http://repository.ust.hk/ir/bitstream/1783.1-1576/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Xiaowu. “Solder joint reliability of plastic ball grid array (PBGA) and bottom-leaded plastic (BLP) assemblies.” 1998. Web. 19 Sep 2019.

Vancouver:

Zhang X. Solder joint reliability of plastic ball grid array (PBGA) and bottom-leaded plastic (BLP) assemblies. [Internet] [Thesis]. Hong Kong University of Science and Technology; 1998. [cited 2019 Sep 19]. Available from: https://doi.org/10.14711/thesis-b622420 ; http://repository.ust.hk/ir/bitstream/1783.1-1576/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang X. Solder joint reliability of plastic ball grid array (PBGA) and bottom-leaded plastic (BLP) assemblies. [Thesis]. Hong Kong University of Science and Technology; 1998. Available from: https://doi.org/10.14711/thesis-b622420 ; http://repository.ust.hk/ir/bitstream/1783.1-1576/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

28. Monadgemi, Pezhman. Polymer-Based Wafer-Level Packaging of Micromachined HARPSS Devices.

Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech

 This thesis reports on a new low-cost wafer-level packaging technology for microelectromechanical systems (MEMS). The MEMS process is based on a revised version of High… (more)

Subjects/Keywords: Wafer-level metal-organic packaging; Sacrificial polymer; Polymer overcoat; HARPSS; Microelectronic packaging Materials; Microelectronic packaging Design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Monadgemi, P. (2006). Polymer-Based Wafer-Level Packaging of Micromachined HARPSS Devices. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/11473

Chicago Manual of Style (16th Edition):

Monadgemi, Pezhman. “Polymer-Based Wafer-Level Packaging of Micromachined HARPSS Devices.” 2006. Doctoral Dissertation, Georgia Tech. Accessed September 19, 2019. http://hdl.handle.net/1853/11473.

MLA Handbook (7th Edition):

Monadgemi, Pezhman. “Polymer-Based Wafer-Level Packaging of Micromachined HARPSS Devices.” 2006. Web. 19 Sep 2019.

Vancouver:

Monadgemi P. Polymer-Based Wafer-Level Packaging of Micromachined HARPSS Devices. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1853/11473.

Council of Science Editors:

Monadgemi P. Polymer-Based Wafer-Level Packaging of Micromachined HARPSS Devices. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/11473


Georgia Tech

29. Krieger, William E. R. Cohesive zone modeling for predicting interfacial delamination in microelectronic packaging.

Degree: MS, Mechanical Engineering, 2014, Georgia Tech

 Multi-layered electronic packages increase in complexity with demands for functionality. Interfacial delamination remains a prominent failure mechanism due to mismatch of coefficient of thermal expansion… (more)

Subjects/Keywords: Interfacial delamination; Cohesive zone modeling; Finite element modeling; Critical strain energy release rate; Microelectronic packaging; Composite materials Delamination; Microelectronics Research; Microelectronics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Krieger, W. E. R. (2014). Cohesive zone modeling for predicting interfacial delamination in microelectronic packaging. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51888

Chicago Manual of Style (16th Edition):

Krieger, William E R. “Cohesive zone modeling for predicting interfacial delamination in microelectronic packaging.” 2014. Masters Thesis, Georgia Tech. Accessed September 19, 2019. http://hdl.handle.net/1853/51888.

MLA Handbook (7th Edition):

Krieger, William E R. “Cohesive zone modeling for predicting interfacial delamination in microelectronic packaging.” 2014. Web. 19 Sep 2019.

Vancouver:

Krieger WER. Cohesive zone modeling for predicting interfacial delamination in microelectronic packaging. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1853/51888.

Council of Science Editors:

Krieger WER. Cohesive zone modeling for predicting interfacial delamination in microelectronic packaging. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51888


Georgia Tech

30. Kohl, Michael. An experimental investigation of microchannel flow with internal pressure measurements.

Degree: PhD, Mechanical Engineering, 2004, Georgia Tech

Subjects/Keywords: Fluidic devices; Microelectromechanical systems; Micromechanics; Microelectronic packaging

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kohl, M. (2004). An experimental investigation of microchannel flow with internal pressure measurements. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/36609

Chicago Manual of Style (16th Edition):

Kohl, Michael. “An experimental investigation of microchannel flow with internal pressure measurements.” 2004. Doctoral Dissertation, Georgia Tech. Accessed September 19, 2019. http://hdl.handle.net/1853/36609.

MLA Handbook (7th Edition):

Kohl, Michael. “An experimental investigation of microchannel flow with internal pressure measurements.” 2004. Web. 19 Sep 2019.

Vancouver:

Kohl M. An experimental investigation of microchannel flow with internal pressure measurements. [Internet] [Doctoral dissertation]. Georgia Tech; 2004. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1853/36609.

Council of Science Editors:

Kohl M. An experimental investigation of microchannel flow with internal pressure measurements. [Doctoral Dissertation]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/36609

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