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You searched for subject:(Metal oxide semiconductors Complementary). Showing records 1 – 30 of 20145 total matches.

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University of New Mexico

1. Mallajosyula, Aahlad. Single event upset hardened CMOS combinational logic and clock buffer design.

Degree: Electrical and Computer Engineering, 2009, University of New Mexico

 A radiation strike on semiconductor device may lead to charge collection, which may manifest as a wrong logic level causing failure. Soft errors or Single… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Mallajosyula, A. (2009). Single event upset hardened CMOS combinational logic and clock buffer design. (Masters Thesis). University of New Mexico. Retrieved from http://hdl.handle.net/1928/7631

Chicago Manual of Style (16th Edition):

Mallajosyula, Aahlad. “Single event upset hardened CMOS combinational logic and clock buffer design.” 2009. Masters Thesis, University of New Mexico. Accessed February 19, 2020. http://hdl.handle.net/1928/7631.

MLA Handbook (7th Edition):

Mallajosyula, Aahlad. “Single event upset hardened CMOS combinational logic and clock buffer design.” 2009. Web. 19 Feb 2020.

Vancouver:

Mallajosyula A. Single event upset hardened CMOS combinational logic and clock buffer design. [Internet] [Masters thesis]. University of New Mexico; 2009. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1928/7631.

Council of Science Editors:

Mallajosyula A. Single event upset hardened CMOS combinational logic and clock buffer design. [Masters Thesis]. University of New Mexico; 2009. Available from: http://hdl.handle.net/1928/7631


Dalhousie University

2. Yu, Haoran. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.

Degree: PhD, Department of Electrical & Computer Engineering, 2014, Dalhousie University

 Bulk-driven (BD) technique has been proposed to remedy the voltage swing limitation problem in modern CMOS technology. However, challenges exist when the CMOS technologies move… (more)

Subjects/Keywords: CMOS; bulk-driven; Metal oxide semiconductors, Complementary; Metal oxide semiconductors, Complementary

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APA (6th Edition):

Yu, H. (2014). Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. (Doctoral Dissertation). Dalhousie University. Retrieved from http://hdl.handle.net/10222/55992

Chicago Manual of Style (16th Edition):

Yu, Haoran. “Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.” 2014. Doctoral Dissertation, Dalhousie University. Accessed February 19, 2020. http://hdl.handle.net/10222/55992.

MLA Handbook (7th Edition):

Yu, Haoran. “Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.” 2014. Web. 19 Feb 2020.

Vancouver:

Yu H. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. [Internet] [Doctoral dissertation]. Dalhousie University; 2014. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/10222/55992.

Council of Science Editors:

Yu H. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. [Doctoral Dissertation]. Dalhousie University; 2014. Available from: http://hdl.handle.net/10222/55992


University of Hong Kong

3. Li, Chunxia. A study on gate dielectrics for Ge MOS devices.

Degree: PhD, 2010, University of Hong Kong

published_or_final_version

Electrical and Electronic Engineering

Doctoral

Doctor of Philosophy

Advisors/Committee Members: Lai, PT.

Subjects/Keywords: Germanium.; Dielectrics.; Metal oxide semiconductors, Complementary.

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APA (6th Edition):

Li, C. (2010). A study on gate dielectrics for Ge MOS devices. (Doctoral Dissertation). University of Hong Kong. Retrieved from Li, C. [李春霞]. (2010). A study on gate dielectrics for Ge MOS devices. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4370387 ; http://dx.doi.org/10.5353/th_b4370387 ; http://hdl.handle.net/10722/57560

Chicago Manual of Style (16th Edition):

Li, Chunxia. “A study on gate dielectrics for Ge MOS devices.” 2010. Doctoral Dissertation, University of Hong Kong. Accessed February 19, 2020. Li, C. [李春霞]. (2010). A study on gate dielectrics for Ge MOS devices. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4370387 ; http://dx.doi.org/10.5353/th_b4370387 ; http://hdl.handle.net/10722/57560.

MLA Handbook (7th Edition):

Li, Chunxia. “A study on gate dielectrics for Ge MOS devices.” 2010. Web. 19 Feb 2020.

Vancouver:

Li C. A study on gate dielectrics for Ge MOS devices. [Internet] [Doctoral dissertation]. University of Hong Kong; 2010. [cited 2020 Feb 19]. Available from: Li, C. [李春霞]. (2010). A study on gate dielectrics for Ge MOS devices. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4370387 ; http://dx.doi.org/10.5353/th_b4370387 ; http://hdl.handle.net/10722/57560.

Council of Science Editors:

Li C. A study on gate dielectrics for Ge MOS devices. [Doctoral Dissertation]. University of Hong Kong; 2010. Available from: Li, C. [李春霞]. (2010). A study on gate dielectrics for Ge MOS devices. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4370387 ; http://dx.doi.org/10.5353/th_b4370387 ; http://hdl.handle.net/10722/57560


Hong Kong University of Science and Technology

4. Zeng, Fan. Silicon-migration technology and its applications to micro-electro-mechanical systems.

Degree: 2014, Hong Kong University of Science and Technology

 It is difficult for traditional micro-engineering methods to generate a suspended structural layer for micro-electro-mechanical systems (MEMS) applications without a releasing step. The limitation becomes… (more)

Subjects/Keywords: Microelectromechanical systems ; Metal oxide semiconductors, Complementary ; Silicon

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APA (6th Edition):

Zeng, F. (2014). Silicon-migration technology and its applications to micro-electro-mechanical systems. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-72513 ; https://doi.org/10.14711/thesis-b1432232 ; http://repository.ust.hk/ir/bitstream/1783.1-72513/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zeng, Fan. “Silicon-migration technology and its applications to micro-electro-mechanical systems.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed February 19, 2020. http://repository.ust.hk/ir/Record/1783.1-72513 ; https://doi.org/10.14711/thesis-b1432232 ; http://repository.ust.hk/ir/bitstream/1783.1-72513/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zeng, Fan. “Silicon-migration technology and its applications to micro-electro-mechanical systems.” 2014. Web. 19 Feb 2020.

Vancouver:

Zeng F. Silicon-migration technology and its applications to micro-electro-mechanical systems. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2020 Feb 19]. Available from: http://repository.ust.hk/ir/Record/1783.1-72513 ; https://doi.org/10.14711/thesis-b1432232 ; http://repository.ust.hk/ir/bitstream/1783.1-72513/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zeng F. Silicon-migration technology and its applications to micro-electro-mechanical systems. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: http://repository.ust.hk/ir/Record/1783.1-72513 ; https://doi.org/10.14711/thesis-b1432232 ; http://repository.ust.hk/ir/bitstream/1783.1-72513/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

5. Liu, Bing. CMOS image sensor for computed tomography applications.

Degree: 2011, Hong Kong University of Science and Technology

 Computed tomography (CT) is a primary non-invasive medical diagnostic modality. In a CT system, X-ray radiation is normally converted into visible light by a scintillator… (more)

Subjects/Keywords: Metal oxide semiconductors, Complementary ; Image converters ; Tomography

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APA (6th Edition):

Liu, B. (2011). CMOS image sensor for computed tomography applications. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-7612 ; https://doi.org/10.14711/thesis-b1155553 ; http://repository.ust.hk/ir/bitstream/1783.1-7612/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Bing. “CMOS image sensor for computed tomography applications.” 2011. Thesis, Hong Kong University of Science and Technology. Accessed February 19, 2020. http://repository.ust.hk/ir/Record/1783.1-7612 ; https://doi.org/10.14711/thesis-b1155553 ; http://repository.ust.hk/ir/bitstream/1783.1-7612/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Bing. “CMOS image sensor for computed tomography applications.” 2011. Web. 19 Feb 2020.

Vancouver:

Liu B. CMOS image sensor for computed tomography applications. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2011. [cited 2020 Feb 19]. Available from: http://repository.ust.hk/ir/Record/1783.1-7612 ; https://doi.org/10.14711/thesis-b1155553 ; http://repository.ust.hk/ir/bitstream/1783.1-7612/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu B. CMOS image sensor for computed tomography applications. [Thesis]. Hong Kong University of Science and Technology; 2011. Available from: http://repository.ust.hk/ir/Record/1783.1-7612 ; https://doi.org/10.14711/thesis-b1155553 ; http://repository.ust.hk/ir/bitstream/1783.1-7612/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

6. Zheng, Shiyuan. A CMOS digital polar transmitter with low noise ADPLL and high linear PA.

Degree: 2013, Hong Kong University of Science and Technology

 Digitally-intensive RF design has attracted a lot of attention recently because it is highly programmable for multi-standard operation and enables high system integration with digital… (more)

Subjects/Keywords: Radio ; Transmitter-receivers ; Metal oxide semiconductors, Complementary

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APA (6th Edition):

Zheng, S. (2013). A CMOS digital polar transmitter with low noise ADPLL and high linear PA. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-76066 ; https://doi.org/10.14711/thesis-b1214710 ; http://repository.ust.hk/ir/bitstream/1783.1-76066/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zheng, Shiyuan. “A CMOS digital polar transmitter with low noise ADPLL and high linear PA.” 2013. Thesis, Hong Kong University of Science and Technology. Accessed February 19, 2020. http://repository.ust.hk/ir/Record/1783.1-76066 ; https://doi.org/10.14711/thesis-b1214710 ; http://repository.ust.hk/ir/bitstream/1783.1-76066/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zheng, Shiyuan. “A CMOS digital polar transmitter with low noise ADPLL and high linear PA.” 2013. Web. 19 Feb 2020.

Vancouver:

Zheng S. A CMOS digital polar transmitter with low noise ADPLL and high linear PA. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2020 Feb 19]. Available from: http://repository.ust.hk/ir/Record/1783.1-76066 ; https://doi.org/10.14711/thesis-b1214710 ; http://repository.ust.hk/ir/bitstream/1783.1-76066/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zheng S. A CMOS digital polar transmitter with low noise ADPLL and high linear PA. [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: http://repository.ust.hk/ir/Record/1783.1-76066 ; https://doi.org/10.14711/thesis-b1214710 ; http://repository.ust.hk/ir/bitstream/1783.1-76066/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Joplin, Matt. A method for characterization of single-event latchup technologies as a function of geometric variation.

Degree: 2018, University of Tennessee – Chattanooga

Complementary metal-oxide-semiconductor (CMOS) technology is the dominant integrated circuit (IC) technology in modern electronics systems. As CMOS comprises of p-channel and n-channel transistors, there are… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary  – Design and construction

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APA (6th Edition):

Joplin, M. (2018). A method for characterization of single-event latchup technologies as a function of geometric variation. (Thesis). University of Tennessee – Chattanooga. Retrieved from https://scholar.utc.edu/theses/567

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Joplin, Matt. “A method for characterization of single-event latchup technologies as a function of geometric variation.” 2018. Thesis, University of Tennessee – Chattanooga. Accessed February 19, 2020. https://scholar.utc.edu/theses/567.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Joplin, Matt. “A method for characterization of single-event latchup technologies as a function of geometric variation.” 2018. Web. 19 Feb 2020.

Vancouver:

Joplin M. A method for characterization of single-event latchup technologies as a function of geometric variation. [Internet] [Thesis]. University of Tennessee – Chattanooga; 2018. [cited 2020 Feb 19]. Available from: https://scholar.utc.edu/theses/567.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Joplin M. A method for characterization of single-event latchup technologies as a function of geometric variation. [Thesis]. University of Tennessee – Chattanooga; 2018. Available from: https://scholar.utc.edu/theses/567

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Columbia University

8. Irez, Kagan. Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies.

Degree: 2015, Columbia University

 This dissertation explores the characteristics of Monotonic-Static CMOS and its potential applications in leakage reduction in ultra scaled Bulk-Si technology with significant gate leakage currents.… (more)

Subjects/Keywords: Metal oxide semiconductors, Complementary – Testing; Electric circuits; Electric leakage; Metal oxide semiconductors, Complementary; Electrical engineering

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APA (6th Edition):

Irez, K. (2015). Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D86D5S5P

Chicago Manual of Style (16th Edition):

Irez, Kagan. “Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies.” 2015. Doctoral Dissertation, Columbia University. Accessed February 19, 2020. https://doi.org/10.7916/D86D5S5P.

MLA Handbook (7th Edition):

Irez, Kagan. “Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies.” 2015. Web. 19 Feb 2020.

Vancouver:

Irez K. Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies. [Internet] [Doctoral dissertation]. Columbia University; 2015. [cited 2020 Feb 19]. Available from: https://doi.org/10.7916/D86D5S5P.

Council of Science Editors:

Irez K. Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies. [Doctoral Dissertation]. Columbia University; 2015. Available from: https://doi.org/10.7916/D86D5S5P


Oregon State University

9. Sadate, Aline C. A substrate noise coupling model for lightly doped CMOS processes.

Degree: MS, Electrical and Computer Engineering, 2000, Oregon State University

 This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Sadate, A. C. (2000). A substrate noise coupling model for lightly doped CMOS processes. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/8280

Chicago Manual of Style (16th Edition):

Sadate, Aline C. “A substrate noise coupling model for lightly doped CMOS processes.” 2000. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/8280.

MLA Handbook (7th Edition):

Sadate, Aline C. “A substrate noise coupling model for lightly doped CMOS processes.” 2000. Web. 19 Feb 2020.

Vancouver:

Sadate AC. A substrate noise coupling model for lightly doped CMOS processes. [Internet] [Masters thesis]. Oregon State University; 2000. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/8280.

Council of Science Editors:

Sadate AC. A substrate noise coupling model for lightly doped CMOS processes. [Masters Thesis]. Oregon State University; 2000. Available from: http://hdl.handle.net/1957/8280


Oregon State University

10. Sharma, Ajit. Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates.

Degree: MS, Electrical and Computer Engineering, 2003, Oregon State University

 This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Sharma, A. (2003). Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/31842

Chicago Manual of Style (16th Edition):

Sharma, Ajit. “Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates.” 2003. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/31842.

MLA Handbook (7th Edition):

Sharma, Ajit. “Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates.” 2003. Web. 19 Feb 2020.

Vancouver:

Sharma A. Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates. [Internet] [Masters thesis]. Oregon State University; 2003. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/31842.

Council of Science Editors:

Sharma A. Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates. [Masters Thesis]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/31842


Oregon State University

11. Maskai, Sailesh R. Design of complex digital blocks using folded source-coupled logic for mixed-mode applications.

Degree: MS, Electrical and Computer Engineering, 1991, Oregon State University

 A series of complex digital blocks have been designed and fabricated using the newly developed current-mode differential CMOS logic family viz. the Folded Source-Coupled Logic… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Maskai, S. R. (1991). Design of complex digital blocks using folded source-coupled logic for mixed-mode applications. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37131

Chicago Manual of Style (16th Edition):

Maskai, Sailesh R. “Design of complex digital blocks using folded source-coupled logic for mixed-mode applications.” 1991. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/37131.

MLA Handbook (7th Edition):

Maskai, Sailesh R. “Design of complex digital blocks using folded source-coupled logic for mixed-mode applications.” 1991. Web. 19 Feb 2020.

Vancouver:

Maskai SR. Design of complex digital blocks using folded source-coupled logic for mixed-mode applications. [Internet] [Masters thesis]. Oregon State University; 1991. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/37131.

Council of Science Editors:

Maskai SR. Design of complex digital blocks using folded source-coupled logic for mixed-mode applications. [Masters Thesis]. Oregon State University; 1991. Available from: http://hdl.handle.net/1957/37131


Oregon State University

12. Fiez, Theresa S. Design of CMOS switched-current filters.

Degree: PhD, Electrical and Computer Engineering, 1990, Oregon State University

 The design and implementation of Switched-Current (SI) ladder filters is described. SI filters require only a standard digital CMOS process and the power supply voltage… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Fiez, T. S. (1990). Design of CMOS switched-current filters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/37183

Chicago Manual of Style (16th Edition):

Fiez, Theresa S. “Design of CMOS switched-current filters.” 1990. Doctoral Dissertation, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/37183.

MLA Handbook (7th Edition):

Fiez, Theresa S. “Design of CMOS switched-current filters.” 1990. Web. 19 Feb 2020.

Vancouver:

Fiez TS. Design of CMOS switched-current filters. [Internet] [Doctoral dissertation]. Oregon State University; 1990. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/37183.

Council of Science Editors:

Fiez TS. Design of CMOS switched-current filters. [Doctoral Dissertation]. Oregon State University; 1990. Available from: http://hdl.handle.net/1957/37183


University of Hong Kong

13. Ng, Chik-wai. Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits.

Degree: PhD, 2011, University of Hong Kong

published_or_final_version

Electrical and Electronic Engineering

Doctoral

Doctor of Philosophy

Advisors/Committee Members: Wong, N.

Subjects/Keywords: Metal oxide semiconductors, Complementary - Design and construction.; Integrated circuits - Power supply.

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APA (6th Edition):

Ng, C. (2011). Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. (Doctoral Dissertation). University of Hong Kong. Retrieved from Ng, C. [吳植偉]. (2011). Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4589692 ; http://dx.doi.org/10.5353/th_b4589692 ; http://hdl.handle.net/10722/163587

Chicago Manual of Style (16th Edition):

Ng, Chik-wai. “Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits.” 2011. Doctoral Dissertation, University of Hong Kong. Accessed February 19, 2020. Ng, C. [吳植偉]. (2011). Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4589692 ; http://dx.doi.org/10.5353/th_b4589692 ; http://hdl.handle.net/10722/163587.

MLA Handbook (7th Edition):

Ng, Chik-wai. “Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits.” 2011. Web. 19 Feb 2020.

Vancouver:

Ng C. Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. [Internet] [Doctoral dissertation]. University of Hong Kong; 2011. [cited 2020 Feb 19]. Available from: Ng, C. [吳植偉]. (2011). Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4589692 ; http://dx.doi.org/10.5353/th_b4589692 ; http://hdl.handle.net/10722/163587.

Council of Science Editors:

Ng C. Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. [Doctoral Dissertation]. University of Hong Kong; 2011. Available from: Ng, C. [吳植偉]. (2011). Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4589692 ; http://dx.doi.org/10.5353/th_b4589692 ; http://hdl.handle.net/10722/163587


Oregon State University

14. Desikachari, Ranganathan. High-speed CMOS dual-modulus presalers for frequency synthesis.

Degree: MS, Electrical and Computer Engineering, 2003, Oregon State University

 Phase-locked loop (PLL) frequency synthesizers lie at the heart of most radio transceivers. An important objective of the electronics and communications industry is to design… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Desikachari, R. (2003). High-speed CMOS dual-modulus presalers for frequency synthesis. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/11724

Chicago Manual of Style (16th Edition):

Desikachari, Ranganathan. “High-speed CMOS dual-modulus presalers for frequency synthesis.” 2003. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/11724.

MLA Handbook (7th Edition):

Desikachari, Ranganathan. “High-speed CMOS dual-modulus presalers for frequency synthesis.” 2003. Web. 19 Feb 2020.

Vancouver:

Desikachari R. High-speed CMOS dual-modulus presalers for frequency synthesis. [Internet] [Masters thesis]. Oregon State University; 2003. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/11724.

Council of Science Editors:

Desikachari R. High-speed CMOS dual-modulus presalers for frequency synthesis. [Masters Thesis]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/11724


Oregon State University

15. Natesan, Peroly. Comparison and analysis of jitter in CMOS ring oscillators.

Degree: MS, Electrical and Computer Engineering, 2003, Oregon State University

 A comparison and analysis of jitter for five different architectures of ring oscillators using a novel simulation technique developed by Professor Forbes' group is presented.… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Natesan, P. (2003). Comparison and analysis of jitter in CMOS ring oscillators. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/11795

Chicago Manual of Style (16th Edition):

Natesan, Peroly. “Comparison and analysis of jitter in CMOS ring oscillators.” 2003. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/11795.

MLA Handbook (7th Edition):

Natesan, Peroly. “Comparison and analysis of jitter in CMOS ring oscillators.” 2003. Web. 19 Feb 2020.

Vancouver:

Natesan P. Comparison and analysis of jitter in CMOS ring oscillators. [Internet] [Masters thesis]. Oregon State University; 2003. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/11795.

Council of Science Editors:

Natesan P. Comparison and analysis of jitter in CMOS ring oscillators. [Masters Thesis]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/11795


Montana State University

16. Hollender, Reinhold Frederick William III. Improved control system for process, voltage, and temperature compensation of CMOS active inductors.

Degree: College of Engineering, 2011, Montana State University

 Wireless communications play an increasingly large role in today's society. Today, many wireless functions are necessarily integrated into chips and other small packages to support… (more)

Subjects/Keywords: Wireless communication systems.; Radio frequency integrated circuits.; Metal oxide semiconductors, Complementary.

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APA (6th Edition):

Hollender, R. F. W. I. (2011). Improved control system for process, voltage, and temperature compensation of CMOS active inductors. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/1491

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hollender, Reinhold Frederick William III. “Improved control system for process, voltage, and temperature compensation of CMOS active inductors.” 2011. Thesis, Montana State University. Accessed February 19, 2020. https://scholarworks.montana.edu/xmlui/handle/1/1491.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hollender, Reinhold Frederick William III. “Improved control system for process, voltage, and temperature compensation of CMOS active inductors.” 2011. Web. 19 Feb 2020.

Vancouver:

Hollender RFWI. Improved control system for process, voltage, and temperature compensation of CMOS active inductors. [Internet] [Thesis]. Montana State University; 2011. [cited 2020 Feb 19]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1491.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hollender RFWI. Improved control system for process, voltage, and temperature compensation of CMOS active inductors. [Thesis]. Montana State University; 2011. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1491

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

17. Chandrasekhar, Vinay. Analysis and design of CMOS RF LNAs with ESD protection.

Degree: MS, Electrical and Computer Engineering, 2002, Oregon State University

 An analysis that accounts for the effect of standard electrostatic discharge (ESD) structures on critical LNA specifications of noise figure, input matching and gain is… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary  – Design

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APA (6th Edition):

Chandrasekhar, V. (2002). Analysis and design of CMOS RF LNAs with ESD protection. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/32159

Chicago Manual of Style (16th Edition):

Chandrasekhar, Vinay. “Analysis and design of CMOS RF LNAs with ESD protection.” 2002. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/32159.

MLA Handbook (7th Edition):

Chandrasekhar, Vinay. “Analysis and design of CMOS RF LNAs with ESD protection.” 2002. Web. 19 Feb 2020.

Vancouver:

Chandrasekhar V. Analysis and design of CMOS RF LNAs with ESD protection. [Internet] [Masters thesis]. Oregon State University; 2002. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/32159.

Council of Science Editors:

Chandrasekhar V. Analysis and design of CMOS RF LNAs with ESD protection. [Masters Thesis]. Oregon State University; 2002. Available from: http://hdl.handle.net/1957/32159


Oregon State University

18. Perigny, Ryan. Area efficiency improvement of CMOS charge pump circuits.

Degree: MS, Electrical and Computer Engineering, 2000, Oregon State University

 In this thesis, the literature relating to charge pump dc-dc converters and their uses is reviewed. Charge pumps are useful in many circuits, including low-voltage… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Perigny, R. (2000). Area efficiency improvement of CMOS charge pump circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/32932

Chicago Manual of Style (16th Edition):

Perigny, Ryan. “Area efficiency improvement of CMOS charge pump circuits.” 2000. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/32932.

MLA Handbook (7th Edition):

Perigny, Ryan. “Area efficiency improvement of CMOS charge pump circuits.” 2000. Web. 19 Feb 2020.

Vancouver:

Perigny R. Area efficiency improvement of CMOS charge pump circuits. [Internet] [Masters thesis]. Oregon State University; 2000. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/32932.

Council of Science Editors:

Perigny R. Area efficiency improvement of CMOS charge pump circuits. [Masters Thesis]. Oregon State University; 2000. Available from: http://hdl.handle.net/1957/32932


Oregon State University

19. Zhou, Jianjun J. CMOS low noise amplifier design utilizing monolithic transformers.

Degree: PhD, Electrical and Computer Engineering, 1998, Oregon State University

 Full integration of CMOS low noise amplifiers (LNA) presents a challenge for low cost CMOS receiver systems. A critical problem faced in the design of… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Zhou, J. J. (1998). CMOS low noise amplifier design utilizing monolithic transformers. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/33529

Chicago Manual of Style (16th Edition):

Zhou, Jianjun J. “CMOS low noise amplifier design utilizing monolithic transformers.” 1998. Doctoral Dissertation, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/33529.

MLA Handbook (7th Edition):

Zhou, Jianjun J. “CMOS low noise amplifier design utilizing monolithic transformers.” 1998. Web. 19 Feb 2020.

Vancouver:

Zhou JJ. CMOS low noise amplifier design utilizing monolithic transformers. [Internet] [Doctoral dissertation]. Oregon State University; 1998. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/33529.

Council of Science Editors:

Zhou JJ. CMOS low noise amplifier design utilizing monolithic transformers. [Doctoral Dissertation]. Oregon State University; 1998. Available from: http://hdl.handle.net/1957/33529


Oregon State University

20. Ballweber, Brian M. Design and computer aided optimization of a fully integrated CMOS RF distributed amplifier.

Degree: MS, Electrical and Computer Engineering, 1998, Oregon State University

 Advancements in the sophistication and complexity of modern electronic systems are creating a need for highly integrated systems with ever higher operational frequencies. The economical… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Ballweber, B. M. (1998). Design and computer aided optimization of a fully integrated CMOS RF distributed amplifier. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/33554

Chicago Manual of Style (16th Edition):

Ballweber, Brian M. “Design and computer aided optimization of a fully integrated CMOS RF distributed amplifier.” 1998. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/33554.

MLA Handbook (7th Edition):

Ballweber, Brian M. “Design and computer aided optimization of a fully integrated CMOS RF distributed amplifier.” 1998. Web. 19 Feb 2020.

Vancouver:

Ballweber BM. Design and computer aided optimization of a fully integrated CMOS RF distributed amplifier. [Internet] [Masters thesis]. Oregon State University; 1998. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/33554.

Council of Science Editors:

Ballweber BM. Design and computer aided optimization of a fully integrated CMOS RF distributed amplifier. [Masters Thesis]. Oregon State University; 1998. Available from: http://hdl.handle.net/1957/33554


Oregon State University

21. Shah, Parag Shantu. Low-power high-performance 32-bit 0.5[u]m CMOS adder.

Degree: MS, Electrical and Computer Engineering, 1998, Oregon State University

 Currently, the two most critical factors of microprocessor design are performance and power. The optimum balance of these two factors is reflected in the speed-power… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Shah, P. S. (1998). Low-power high-performance 32-bit 0.5[u]m CMOS adder. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/33605

Chicago Manual of Style (16th Edition):

Shah, Parag Shantu. “Low-power high-performance 32-bit 0.5[u]m CMOS adder.” 1998. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/33605.

MLA Handbook (7th Edition):

Shah, Parag Shantu. “Low-power high-performance 32-bit 0.5[u]m CMOS adder.” 1998. Web. 19 Feb 2020.

Vancouver:

Shah PS. Low-power high-performance 32-bit 0.5[u]m CMOS adder. [Internet] [Masters thesis]. Oregon State University; 1998. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/33605.

Council of Science Editors:

Shah PS. Low-power high-performance 32-bit 0.5[u]m CMOS adder. [Masters Thesis]. Oregon State University; 1998. Available from: http://hdl.handle.net/1957/33605


Oregon State University

22. Lim, Wei Tjan (Richard). Suppression of substrate noise in a mixed-signal CMOS intergrated circuit.

Degree: MS, Electrical and Computer Engineering, 1996, Oregon State University

 Substrate switching noise is becoming a concern as integrated circuits get larger and speeds get faster. Mixed-mode integrated circuits are especially affected as the substrate… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Lim, W. T. (. (1996). Suppression of substrate noise in a mixed-signal CMOS intergrated circuit. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/34197

Chicago Manual of Style (16th Edition):

Lim, Wei Tjan (Richard). “Suppression of substrate noise in a mixed-signal CMOS intergrated circuit.” 1996. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/34197.

MLA Handbook (7th Edition):

Lim, Wei Tjan (Richard). “Suppression of substrate noise in a mixed-signal CMOS intergrated circuit.” 1996. Web. 19 Feb 2020.

Vancouver:

Lim WT(. Suppression of substrate noise in a mixed-signal CMOS intergrated circuit. [Internet] [Masters thesis]. Oregon State University; 1996. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/34197.

Council of Science Editors:

Lim WT(. Suppression of substrate noise in a mixed-signal CMOS intergrated circuit. [Masters Thesis]. Oregon State University; 1996. Available from: http://hdl.handle.net/1957/34197


Oregon State University

23. Zhang, Jing, 1962-. Generation of substrate bias and current sources in CMOS technology.

Degree: MS, Electrical and Computer Engineering, 1995, Oregon State University

 A negatively biased substrate has several advantages over a grounded substrate in CMOS technology. The on-chip generation of this negative substrate bias has made chips… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Zhang, Jing, 1. (1995). Generation of substrate bias and current sources in CMOS technology. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/34653

Chicago Manual of Style (16th Edition):

Zhang, Jing, 1962-. “Generation of substrate bias and current sources in CMOS technology.” 1995. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/34653.

MLA Handbook (7th Edition):

Zhang, Jing, 1962-. “Generation of substrate bias and current sources in CMOS technology.” 1995. Web. 19 Feb 2020.

Vancouver:

Zhang, Jing 1. Generation of substrate bias and current sources in CMOS technology. [Internet] [Masters thesis]. Oregon State University; 1995. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/34653.

Council of Science Editors:

Zhang, Jing 1. Generation of substrate bias and current sources in CMOS technology. [Masters Thesis]. Oregon State University; 1995. Available from: http://hdl.handle.net/1957/34653


Oregon State University

24. Hwang, Nam. Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors.

Degree: PhD, Electrical and Computer Engineering, 1993, Oregon State University

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Hwang, N. (1993). Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/35625

Chicago Manual of Style (16th Edition):

Hwang, Nam. “Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors.” 1993. Doctoral Dissertation, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/35625.

MLA Handbook (7th Edition):

Hwang, Nam. “Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors.” 1993. Web. 19 Feb 2020.

Vancouver:

Hwang N. Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors. [Internet] [Doctoral dissertation]. Oregon State University; 1993. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/35625.

Council of Science Editors:

Hwang N. Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors. [Doctoral Dissertation]. Oregon State University; 1993. Available from: http://hdl.handle.net/1957/35625


Oregon State University

25. Lao, Paul A. Current-feedthrough cancellation techniques in switched-current circuits.

Degree: MS, Electrical and Computer Engineering, 1990, Oregon State University

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Lao, P. A. (1990). Current-feedthrough cancellation techniques in switched-current circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37719

Chicago Manual of Style (16th Edition):

Lao, Paul A. “Current-feedthrough cancellation techniques in switched-current circuits.” 1990. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/37719.

MLA Handbook (7th Edition):

Lao, Paul A. “Current-feedthrough cancellation techniques in switched-current circuits.” 1990. Web. 19 Feb 2020.

Vancouver:

Lao PA. Current-feedthrough cancellation techniques in switched-current circuits. [Internet] [Masters thesis]. Oregon State University; 1990. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/37719.

Council of Science Editors:

Lao PA. Current-feedthrough cancellation techniques in switched-current circuits. [Masters Thesis]. Oregon State University; 1990. Available from: http://hdl.handle.net/1957/37719


Oregon State University

26. Zele, Rajesh H. Fully-differential current-mode CMOS circuits and applications.

Degree: MS, Electrical and Computer Engineering, 1990, Oregon State University

 With increasing interest in current-mode analogue processing due to its high performance properties such as speed, bandwidth and accuracy compared to voltage-mode processing, new current-mode… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Zele, R. H. (1990). Fully-differential current-mode CMOS circuits and applications. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37934

Chicago Manual of Style (16th Edition):

Zele, Rajesh H. “Fully-differential current-mode CMOS circuits and applications.” 1990. Masters Thesis, Oregon State University. Accessed February 19, 2020. http://hdl.handle.net/1957/37934.

MLA Handbook (7th Edition):

Zele, Rajesh H. “Fully-differential current-mode CMOS circuits and applications.” 1990. Web. 19 Feb 2020.

Vancouver:

Zele RH. Fully-differential current-mode CMOS circuits and applications. [Internet] [Masters thesis]. Oregon State University; 1990. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/1957/37934.

Council of Science Editors:

Zele RH. Fully-differential current-mode CMOS circuits and applications. [Masters Thesis]. Oregon State University; 1990. Available from: http://hdl.handle.net/1957/37934


Columbia University

27. Shekar, Siddharth. Design of custom CMOS amplifiers for nanoscale bio-interfaces.

Degree: 2019, Columbia University

 The miniaturization of electronics is a technique that holds a lot of potential in improving system performance in a variety of applications. The simultaneous miniaturization… (more)

Subjects/Keywords: Electrical engineering; Nanotechnology; Metal oxide semiconductors, Complementary; Amplifiers (Electronics); Biological interfaces

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APA (6th Edition):

Shekar, S. (2019). Design of custom CMOS amplifiers for nanoscale bio-interfaces. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/d8-kb2p-zm21

Chicago Manual of Style (16th Edition):

Shekar, Siddharth. “Design of custom CMOS amplifiers for nanoscale bio-interfaces.” 2019. Doctoral Dissertation, Columbia University. Accessed February 19, 2020. https://doi.org/10.7916/d8-kb2p-zm21.

MLA Handbook (7th Edition):

Shekar, Siddharth. “Design of custom CMOS amplifiers for nanoscale bio-interfaces.” 2019. Web. 19 Feb 2020.

Vancouver:

Shekar S. Design of custom CMOS amplifiers for nanoscale bio-interfaces. [Internet] [Doctoral dissertation]. Columbia University; 2019. [cited 2020 Feb 19]. Available from: https://doi.org/10.7916/d8-kb2p-zm21.

Council of Science Editors:

Shekar S. Design of custom CMOS amplifiers for nanoscale bio-interfaces. [Doctoral Dissertation]. Columbia University; 2019. Available from: https://doi.org/10.7916/d8-kb2p-zm21


Columbia University

28. Zhu, Jianxun. Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios.

Degree: 2017, Columbia University

 Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the… (more)

Subjects/Keywords: Electrical engineering; Metal oxide semiconductors, Complementary; Electric circuits; Electronics

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APA (6th Edition):

Zhu, J. (2017). Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D8TX3SNZ

Chicago Manual of Style (16th Edition):

Zhu, Jianxun. “Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios.” 2017. Doctoral Dissertation, Columbia University. Accessed February 19, 2020. https://doi.org/10.7916/D8TX3SNZ.

MLA Handbook (7th Edition):

Zhu, Jianxun. “Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios.” 2017. Web. 19 Feb 2020.

Vancouver:

Zhu J. Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios. [Internet] [Doctoral dissertation]. Columbia University; 2017. [cited 2020 Feb 19]. Available from: https://doi.org/10.7916/D8TX3SNZ.

Council of Science Editors:

Zhu J. Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios. [Doctoral Dissertation]. Columbia University; 2017. Available from: https://doi.org/10.7916/D8TX3SNZ


Massey University

29. Abbas, Ibtisam. Biomedical integrated circuit design for an electro-therapy device : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering (Bioelectronics) at School of Engineering and Advanced Technology, Massey University, Albany Campus, New Zealand .

Degree: 2017, Massey University

 A biomedical integrated circuit design (IC) is utilized for the development of a novel non-invasive electro-therapy device, for low frequency multi-channel biomedical stimulation to transform… (more)

Subjects/Keywords: Integrated circuits  – Design and construction; Metal oxide semiconductors, Complementary; Electrotherapeutics  – Instruments

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APA (6th Edition):

Abbas, I. (2017). Biomedical integrated circuit design for an electro-therapy device : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering (Bioelectronics) at School of Engineering and Advanced Technology, Massey University, Albany Campus, New Zealand . (Thesis). Massey University. Retrieved from http://hdl.handle.net/10179/14415

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Abbas, Ibtisam. “Biomedical integrated circuit design for an electro-therapy device : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering (Bioelectronics) at School of Engineering and Advanced Technology, Massey University, Albany Campus, New Zealand .” 2017. Thesis, Massey University. Accessed February 19, 2020. http://hdl.handle.net/10179/14415.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Abbas, Ibtisam. “Biomedical integrated circuit design for an electro-therapy device : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering (Bioelectronics) at School of Engineering and Advanced Technology, Massey University, Albany Campus, New Zealand .” 2017. Web. 19 Feb 2020.

Vancouver:

Abbas I. Biomedical integrated circuit design for an electro-therapy device : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering (Bioelectronics) at School of Engineering and Advanced Technology, Massey University, Albany Campus, New Zealand . [Internet] [Thesis]. Massey University; 2017. [cited 2020 Feb 19]. Available from: http://hdl.handle.net/10179/14415.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Abbas I. Biomedical integrated circuit design for an electro-therapy device : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering (Bioelectronics) at School of Engineering and Advanced Technology, Massey University, Albany Campus, New Zealand . [Thesis]. Massey University; 2017. Available from: http://hdl.handle.net/10179/14415

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

30. Liu, Rui. CMOS class-C VCO and QVCO for WLAN applications.

Degree: 2013, Hong Kong University of Science and Technology

 WLAN (Wireless Local Area Network) applications based on 802.11 protocol family have enjoyed a tremendous growth in both home and enterprise market since it was… (more)

Subjects/Keywords: Voltage-controlled oscillators ; Wireless LANs ; Metal oxide semiconductors, Complementary

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APA (6th Edition):

Liu, R. (2013). CMOS class-C VCO and QVCO for WLAN applications. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-62320 ; https://doi.org/10.14711/thesis-b1255633 ; http://repository.ust.hk/ir/bitstream/1783.1-62320/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Rui. “CMOS class-C VCO and QVCO for WLAN applications.” 2013. Thesis, Hong Kong University of Science and Technology. Accessed February 19, 2020. http://repository.ust.hk/ir/Record/1783.1-62320 ; https://doi.org/10.14711/thesis-b1255633 ; http://repository.ust.hk/ir/bitstream/1783.1-62320/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Rui. “CMOS class-C VCO and QVCO for WLAN applications.” 2013. Web. 19 Feb 2020.

Vancouver:

Liu R. CMOS class-C VCO and QVCO for WLAN applications. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2020 Feb 19]. Available from: http://repository.ust.hk/ir/Record/1783.1-62320 ; https://doi.org/10.14711/thesis-b1255633 ; http://repository.ust.hk/ir/bitstream/1783.1-62320/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu R. CMOS class-C VCO and QVCO for WLAN applications. [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: http://repository.ust.hk/ir/Record/1783.1-62320 ; https://doi.org/10.14711/thesis-b1255633 ; http://repository.ust.hk/ir/bitstream/1783.1-62320/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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