subject:(Metal oxide semiconductors Complementary )

Dalhousie University

1. Yu, Haoran. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.

Degree: PhD, Department of Electrical & Computer Engineering, 2014, Dalhousie University

► Bulk-driven (BD) technique has been proposed to remedy the voltage swing limitation problem in modern CMOS technology. However, challenges exist when the CMOS technologies move… (more)

▼ Bulk-driven (BD) technique has been proposed to remedy the voltage swing limitation problem in modern CMOS technology. However, challenges exist when the CMOS technologies move to the nanometer-scale. The goal of this research work is to develop techniques to overcome certain challenges resulting from the scaling down of the CMOS technologies. Furthermore, the results are applied to analyze nano-scale BD CMOS circuits and develop novel high performance circuits. The mixing mechanism of BD mixers is analyzed comprehensively for the first time, using two different models to demonstrate the importance of model selection, which is one of the challenging tasks in scaling CMOS technology. The mixing mechanism is developed for different BD mixer structures and different local oscillator (LO) waveforms using the square-law model, and a compound mixing product is found. Based on this analysis, including the short-channel effects in nano-scale CMOS technology, a more advanced model is used to study the optimal bias condition for harmonic rejection (HR). A novel design method to suppress HR is proposed for wideband applications. Two BD mixers are fabricated in 65 nm CMOS technology; and this design methodology is verified by measurement results. Nonlinearity analysis is another challenging subject in nano-scale CMOS circuits. A detailed distortion analysis of nano-scale (65 nm) BD and gate-driven (GD) CMOS RF amplifier is completed using Volterra series. In this work, it is found that the effect of the nonlinear output conductance and the cross-terms among v_gs,v_ds,and v_bs must be included in the analysis of the MOSFET at nano-scales. The first three-order Volterra kernels are computed; and the closed-form expressions of the second-order and third-order harmonic distortion (HD) are derived, which can provide more insight into the nonlinearity of nano-scale amplifier. Distortion-aware design guidelines for nano-scale CMOS amplifier are provided. An ultra-compact current model is chosen for this quantitative analysis; and it is modified in this research to be adapted to nano-scale BD MOSFET. Further, to suppress the third-order intermodulation (IM3) product of differential BD RF amplifier, a modified second-order intermodulation (IM2) injection technique is proposed based on a system-level nonlinearity analysis using Volterra series. Advisors/Committee Members: Dr. Jamal Deen (external-examiner), Dr. Sergey Ponomarenko (graduate-coordinator), Dr. Jason Gu (thesis-reader), Dr. William Phillips (thesis-reader), Dr. Ezz El-Masry (thesis-supervisor), Dr. Kamal El-Sankary (thesis-supervisor), Not Applicable (ethics-approval), Not Applicable (manuscripts), Yes (copyright-release).

Subjects/Keywords: CMOS; bulk-driven; Metal oxide semiconductors, Complementary; Metal oxide semiconductors, Complementary

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APA (6^th Edition):

Yu, H. (2014). Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. (Doctoral Dissertation). Dalhousie University. Retrieved from http://hdl.handle.net/10222/55992

Chicago Manual of Style (16^th Edition):

Yu, Haoran. “Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.” 2014. Doctoral Dissertation, Dalhousie University. Accessed March 01, 2021. http://hdl.handle.net/10222/55992.

MLA Handbook (7^th Edition):

Yu, Haoran. “Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.” 2014. Web. 01 Mar 2021.

Vancouver:

Yu H. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. [Internet] [Doctoral dissertation]. Dalhousie University; 2014. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/10222/55992.

Council of Science Editors:

Yu H. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. [Doctoral Dissertation]. Dalhousie University; 2014. Available from: http://hdl.handle.net/10222/55992

Hong Kong University of Science and Technology

2. Zeng, Fan. Silicon-migration technology and its applications to micro-electro-mechanical systems.

Degree: 2014, Hong Kong University of Science and Technology

URL: http://repository.ust.hk/ir/Record/1783.1-72513 ; https://doi.org/10.14711/thesis-b1432232 ; http://repository.ust.hk/ir/bitstream/1783.1-72513/1/th_redirect.html

► It is difficult for traditional micro-engineering methods to generate a suspended structural layer for micro-electro-mechanical systems (MEMS) applications without a releasing step. The limitation becomes… (more)

▼ It is difficult for traditional micro-engineering methods to generate a suspended structural layer for micro-electro-mechanical systems (MEMS) applications without a releasing step. The limitation becomes more serious when it comes to integration with electronic circuits. Various schemes proposed for MEMS-CMOS integration have issues that either hamper design flexibility or require special care. Silicon-Migration Technology (SiMiT) starts with the formation of an array of “wells” using a deep reactive-ion etcher (DRIE). During a subsequent heat-treatment, surface-diffusion of silicon leads to the coalescence of the voids at the bases of adjacent wells and the closing of the space at the top of a well. In the end a continuous cavity buried under a cover-diaphragm can be obtained without a releasing step. Following a brief summary of the physics, simulations and experimental results of the initial works on SiMiT, the SiMiT process was further understood via a self-developed front-tracking simulator. SiMiT thermal treatment was carried out using rapid thermal annealing at 1150 °C in atmospheric pressure argon. Various structures useful for MEMS applications including oxide micro-channels, suspended cantilevers and diaphragms were realized using SiMiT. Potential application issues with SiMiT were discussed, with solutions provided. The application of SiMiT to the realization of a CMOS integrated 16×16 self-scanned active-matrix tactile sensor was subsequently described. A sensitivity of ~0.03 μV/V/Pa and spatial resolution of ~145 “pixels per inch”, suitable for applications such as dexterous robotic manipulation, was achieved. With the elimination of the conventional sacrificial layer etch, the issues of material- and process-incompatibility inherently present in many integration schemes are largely avoided. Finally, SiMiT is applied to the realization of a differential capacitive pressure sensor with innovative diaphragm shape and reference capacitor designs, achieving a sensitivity of ~40 aF/Pa in a ~100 kPa pressure range.

Subjects/Keywords: Microelectromechanical systems ; Metal oxide semiconductors, Complementary ; Silicon

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APA (6^th Edition):

Zeng, F. (2014). Silicon-migration technology and its applications to micro-electro-mechanical systems. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-72513 ; https://doi.org/10.14711/thesis-b1432232 ; http://repository.ust.hk/ir/bitstream/1783.1-72513/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zeng, Fan. “Silicon-migration technology and its applications to micro-electro-mechanical systems.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed March 01, 2021. http://repository.ust.hk/ir/Record/1783.1-72513 ; https://doi.org/10.14711/thesis-b1432232 ; http://repository.ust.hk/ir/bitstream/1783.1-72513/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zeng, Fan. “Silicon-migration technology and its applications to micro-electro-mechanical systems.” 2014. Web. 01 Mar 2021.

Vancouver:

Zeng F. Silicon-migration technology and its applications to micro-electro-mechanical systems. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2021 Mar 01]. Available from: http://repository.ust.hk/ir/Record/1783.1-72513 ; https://doi.org/10.14711/thesis-b1432232 ; http://repository.ust.hk/ir/bitstream/1783.1-72513/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zeng F. Silicon-migration technology and its applications to micro-electro-mechanical systems. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: http://repository.ust.hk/ir/Record/1783.1-72513 ; https://doi.org/10.14711/thesis-b1432232 ; http://repository.ust.hk/ir/bitstream/1783.1-72513/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Hong Kong University of Science and Technology

3. Liu, Bing. CMOS image sensor for computed tomography applications.

Degree: 2011, Hong Kong University of Science and Technology

URL: http://repository.ust.hk/ir/Record/1783.1-7612 ; https://doi.org/10.14711/thesis-b1155553 ; http://repository.ust.hk/ir/bitstream/1783.1-7612/1/th_redirect.html

► Computed tomography (CT) is a primary non-invasive medical diagnostic modality. In a CT system, X-ray radiation is normally converted into visible light by a scintillator… (more)

▼ Computed tomography (CT) is a primary non-invasive medical diagnostic modality. In a CT system, X-ray radiation is normally converted into visible light by a scintillator screen, which is further sensed by a solid-state imaging sensor. It requires a detecting sensor with wide dynamic range (WDR) and high speed. The existing industry is dominated by hybrid detector designs with amorphous silicon (α-Si) or charge-coupled device (CCD) photodiode array and CMOS acquisition circuits. Monolithic CMOS imaging sensor (CIS) has great potentials for CT detectors. This thesis focuses on exploring novel CMOS imaging sensor technologies for CT applications. The thesis first introduces the application of CT and various types of solid-state imaging sensors. Then, it analyzes existing wide dynamic range CIS techniques and introduces our design of a WDR CIS with good linearity. The most important contribution of this thesis is that it continues to introduce our designs of CMOS imaging sensors for clinical CT and for micro-CT applications respectively. Existing CMOS detectors for clinical CT are limited by their low linearity. They also need high-resolution external analog-to-digital converters (ADC) to quantize the WDR. In this thesis, a novel synchronous partial quantization technique is developed to enable monolithic digital CMOS CT detector. Improved from previous current quantization designs, the new detector quantizes the photocurrent in the charge domain with constant charge packet size. As the result, the detector can quantize the WDR photocurrent with improved linearity. The two-step charge-domain ADC scheme also allows low resolution single-slope ADCs for residual voltage quantization, which enables in-pixel integration. A prototype pixel detector is fabricated in a 0.35um CMOS process. Silicon measurements show the detector can quantize signal currents from 6 pA to 63.4 nA with relative gain deviation lower than 0.06% at 1.1k Hz frame rate, which does not generate detector-induced artifact after the image reconstruction. The detector noise is smaller than the X-ray Poisson noise in the whole signal range. The minimum detector noise is 0.8 pArms. Hence, the detector achieves 16.6 bits dynamic range. The geometrical detective efficiency (GDE) of the detector is 75.5% including the band-gap voltage reference and ADC. The digital pixel detector can be easily tiled into a 2D CT detection panel. A high-speed CMOS imaging sensor is designed for a micro-CT scanner. The high-speed CIS normally has low optical sensitivity due to the short integration time. For applications, such as micro-CT, this is a major limitation. In this thesis, we developed a novel high-speed CIS with very high optical sensitivity. To maximize the sensitivity, we developed a capacitive trans-impedance amplifier (CTIA) pixel with a tiny metal-oxide-metal (MOM) capacitor. As a result, the noise is greatly reduced, while the optical sensitivity improves dramatically. We developed an on-chip calibration scheme with in-pixel circuits to compensate the mismatch…

Subjects/Keywords: Metal oxide semiconductors, Complementary ; Image converters ; Tomography

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APA (6^th Edition):

Liu, B. (2011). CMOS image sensor for computed tomography applications. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-7612 ; https://doi.org/10.14711/thesis-b1155553 ; http://repository.ust.hk/ir/bitstream/1783.1-7612/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liu, Bing. “CMOS image sensor for computed tomography applications.” 2011. Thesis, Hong Kong University of Science and Technology. Accessed March 01, 2021. http://repository.ust.hk/ir/Record/1783.1-7612 ; https://doi.org/10.14711/thesis-b1155553 ; http://repository.ust.hk/ir/bitstream/1783.1-7612/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liu, Bing. “CMOS image sensor for computed tomography applications.” 2011. Web. 01 Mar 2021.

Vancouver:

Liu B. CMOS image sensor for computed tomography applications. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2011. [cited 2021 Mar 01]. Available from: http://repository.ust.hk/ir/Record/1783.1-7612 ; https://doi.org/10.14711/thesis-b1155553 ; http://repository.ust.hk/ir/bitstream/1783.1-7612/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu B. CMOS image sensor for computed tomography applications. [Thesis]. Hong Kong University of Science and Technology; 2011. Available from: http://repository.ust.hk/ir/Record/1783.1-7612 ; https://doi.org/10.14711/thesis-b1155553 ; http://repository.ust.hk/ir/bitstream/1783.1-7612/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Hong Kong University of Science and Technology

4. Zheng, Shiyuan. A CMOS digital polar transmitter with low noise ADPLL and high linear PA.

Degree: 2013, Hong Kong University of Science and Technology

URL: http://repository.ust.hk/ir/Record/1783.1-76066 ; https://doi.org/10.14711/thesis-b1214710 ; http://repository.ust.hk/ir/bitstream/1783.1-76066/1/th_redirect.html

► Digitally-intensive RF design has attracted a lot of attention recently because it is highly programmable for multi-standard operation and enables high system integration with digital… (more)

Subjects/Keywords: Radio ; Transmitter-receivers ; Metal oxide semiconductors, Complementary

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APA (6^th Edition):

Zheng, S. (2013). A CMOS digital polar transmitter with low noise ADPLL and high linear PA. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-76066 ; https://doi.org/10.14711/thesis-b1214710 ; http://repository.ust.hk/ir/bitstream/1783.1-76066/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zheng, Shiyuan. “A CMOS digital polar transmitter with low noise ADPLL and high linear PA.” 2013. Thesis, Hong Kong University of Science and Technology. Accessed March 01, 2021. http://repository.ust.hk/ir/Record/1783.1-76066 ; https://doi.org/10.14711/thesis-b1214710 ; http://repository.ust.hk/ir/bitstream/1783.1-76066/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zheng, Shiyuan. “A CMOS digital polar transmitter with low noise ADPLL and high linear PA.” 2013. Web. 01 Mar 2021.

Vancouver:

Zheng S. A CMOS digital polar transmitter with low noise ADPLL and high linear PA. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2021 Mar 01]. Available from: http://repository.ust.hk/ir/Record/1783.1-76066 ; https://doi.org/10.14711/thesis-b1214710 ; http://repository.ust.hk/ir/bitstream/1783.1-76066/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zheng S. A CMOS digital polar transmitter with low noise ADPLL and high linear PA. [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: http://repository.ust.hk/ir/Record/1783.1-76066 ; https://doi.org/10.14711/thesis-b1214710 ; http://repository.ust.hk/ir/bitstream/1783.1-76066/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

5. Joplin, Matt. A method for characterization of single-event latchup technologies as a function of geometric variation.

Degree: 2018, University of Tennessee – Chattanooga

URL: https://scholar.utc.edu/theses/567

► Complementary metal-oxide-semiconductor (CMOS) technology is the dominant integrated circuit (IC) technology in modern electronics systems. As CMOS comprises of p-channel and n-channel transistors, there are… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary – Design and construction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Joplin, M. (2018). A method for characterization of single-event latchup technologies as a function of geometric variation. (Masters Thesis). University of Tennessee – Chattanooga. Retrieved from https://scholar.utc.edu/theses/567

Chicago Manual of Style (16^th Edition):

Joplin, Matt. “A method for characterization of single-event latchup technologies as a function of geometric variation.” 2018. Masters Thesis, University of Tennessee – Chattanooga. Accessed March 01, 2021. https://scholar.utc.edu/theses/567.

MLA Handbook (7^th Edition):

Joplin, Matt. “A method for characterization of single-event latchup technologies as a function of geometric variation.” 2018. Web. 01 Mar 2021.

Vancouver:

Joplin M. A method for characterization of single-event latchup technologies as a function of geometric variation. [Internet] [Masters thesis]. University of Tennessee – Chattanooga; 2018. [cited 2021 Mar 01]. Available from: https://scholar.utc.edu/theses/567.

Council of Science Editors:

Joplin M. A method for characterization of single-event latchup technologies as a function of geometric variation. [Masters Thesis]. University of Tennessee – Chattanooga; 2018. Available from: https://scholar.utc.edu/theses/567

Columbia University

6. Irez, Kagan. Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies.

Degree: 2015, Columbia University

URL: https://doi.org/10.7916/D86D5S5P

► This dissertation explores the characteristics of Monotonic-Static CMOS and its potential applications in leakage reduction in ultra scaled Bulk-Si technology with significant gate leakage currents.… (more)

Subjects/Keywords: Metal oxide semiconductors, Complementary – Testing; Electric circuits; Electric leakage; Metal oxide semiconductors, Complementary; Electrical engineering

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APA (6^th Edition):

Irez, K. (2015). Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D86D5S5P

Chicago Manual of Style (16^th Edition):

Irez, Kagan. “Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies.” 2015. Doctoral Dissertation, Columbia University. Accessed March 01, 2021. https://doi.org/10.7916/D86D5S5P.

MLA Handbook (7^th Edition):

Irez, Kagan. “Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies.” 2015. Web. 01 Mar 2021.

Vancouver:

Irez K. Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies. [Internet] [Doctoral dissertation]. Columbia University; 2015. [cited 2021 Mar 01]. Available from: https://doi.org/10.7916/D86D5S5P.

Council of Science Editors:

Irez K. Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies. [Doctoral Dissertation]. Columbia University; 2015. Available from: https://doi.org/10.7916/D86D5S5P

Michigan State University

7. Li, Lin (Electrical engineer). Development of epoxy chip-in-carrier integration for lab-on-CMOS electrochemical microsystem.

Degree: 2017, Michigan State University

URL: http://etd.lib.msu.edu/islandora/object/etd:4572

►

Thesis Ph. D. Michigan State University. Electrical Engineering 2017

"Miniaturized biosensor arrays are attractive for parallel analysis of multiple parameters and targets. Overcoming the need… (more)

Subjects/Keywords: Metal oxide semiconductors, Complementary; Interconnects (Integrated circuit technology); Metal oxide semiconductors, Complementary – Design and construction; Biosensors; Electrical engineering

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APA (6^th Edition):

Li, L. (. e. (2017). Development of epoxy chip-in-carrier integration for lab-on-CMOS electrochemical microsystem. (Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:4572

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Li, Lin (Electrical engineer). “Development of epoxy chip-in-carrier integration for lab-on-CMOS electrochemical microsystem.” 2017. Thesis, Michigan State University. Accessed March 01, 2021. http://etd.lib.msu.edu/islandora/object/etd:4572.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Li, Lin (Electrical engineer). “Development of epoxy chip-in-carrier integration for lab-on-CMOS electrochemical microsystem.” 2017. Web. 01 Mar 2021.

Vancouver:

Li L(e. Development of epoxy chip-in-carrier integration for lab-on-CMOS electrochemical microsystem. [Internet] [Thesis]. Michigan State University; 2017. [cited 2021 Mar 01]. Available from: http://etd.lib.msu.edu/islandora/object/etd:4572.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li L(e. Development of epoxy chip-in-carrier integration for lab-on-CMOS electrochemical microsystem. [Thesis]. Michigan State University; 2017. Available from: http://etd.lib.msu.edu/islandora/object/etd:4572

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Hong Kong University of Science and Technology

8. Ahmed, Moaaz ECE. Design methodology and circuit techniques for CMOS readout of MEMS flow sensors.

Degree: 2017, Hong Kong University of Science and Technology

URL: http://repository.ust.hk/ir/Record/1783.1-104963 ; https://doi.org/10.14711/thesis-991012552668203412 ; http://repository.ust.hk/ir/bitstream/1783.1-104963/1/th_redirect.html

► Sensing anything (sense-worthy), anywhere and anytime is one of the future goals of Semiconductor industry. Combine it with Internet of Things (IOT) and there we… (more)

▼ Sensing anything (sense-worthy), anywhere and anytime is one of the future goals of Semiconductor industry. Combine it with Internet of Things (IOT) and there we go - ubiquitous deployment of smart sensors, preferably operating with passive energy sources like energy harvesting. Minimizing the power consumption of such systems is critical to ensure longer lifetime which leads to lower deployment costs and broad applications spectrum. Arguably, the most power hungry block in the sensing chain is the front end (instrumentation) amplifier which usually has to meet stringent noise and linearity constraints. This inevitably leads to high power consumption which is usually benchmarked with noise -efficiency factor (NEF). In this work, we present a systematic design methodology which explores the design space (for ultra-low noise chopper instrumentation amplifiers) in all regions of MOSFET operation. Our work is the first of its kind to extend the g_m/I_D based design methodology for precision instrumentation amplifiers by taking into account a comprehensive set of parameters and validate the same through experimental demonstration. Various design tradeoffs, including the choice of chopping frequency for minimum residue offset and chopping ripple, gain-precision, bandwidth and area constraints are considered to meet the stringent specifications of a high-performance instrumentation amplifier with minimum power consumption and achieve state-of-the-art NEF. We also design several readout interfaces for the MEMS-CMOS flow sensing platform. First, an integrated MEMS-CMOS flow sensor is presented which demonstrates a very compact system on chip (SoC) that can sense N₂ gas flow ranging from 0 to 26m/s (0-50sccm). The measured sensitivity of our MEMS-CMOS flow sensor is 35mV/sccm. Second, we design a nested-chopped CFIA by employing two sets of choppers; the outer chopper is clocked at a high frequency to mitigate the flicker noise whereas the inner chopper is clocked at the slower frequency to suppress the residue offset. Thus a CFIA with extremely-low offset (250nV) is obtained, which is interfaced with a pulse width modulation (PWM) based ADC to convert the flow-rate in digital bits. Third, a fully-differential version of this CFIA (with improved noise performance), that serves as a front-end IA to a 12-bit incremental ADC is also reported. To conclude, several readout interfaces for fully-integrated CMOS-MEMS flow sensing platform have been implemented which enable a compact low-power flow sensor with enhanced dynamic range and minimum detectable flow value. The power consumption and design complexity of the high-performance readout interface are reduced by adopting mixed-signal integrated circuit techniques and a systematic design methodology.

Subjects/Keywords: Microelectromechanical systems ; Metal oxide semiconductors, Complementary ; Detectors ; Flow meters ; Metal oxide semiconductor field-effect transistors

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APA (6^th Edition):

Ahmed, M. E. (2017). Design methodology and circuit techniques for CMOS readout of MEMS flow sensors. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-104963 ; https://doi.org/10.14711/thesis-991012552668203412 ; http://repository.ust.hk/ir/bitstream/1783.1-104963/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ahmed, Moaaz ECE. “Design methodology and circuit techniques for CMOS readout of MEMS flow sensors.” 2017. Thesis, Hong Kong University of Science and Technology. Accessed March 01, 2021. http://repository.ust.hk/ir/Record/1783.1-104963 ; https://doi.org/10.14711/thesis-991012552668203412 ; http://repository.ust.hk/ir/bitstream/1783.1-104963/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ahmed, Moaaz ECE. “Design methodology and circuit techniques for CMOS readout of MEMS flow sensors.” 2017. Web. 01 Mar 2021.

Vancouver:

Ahmed ME. Design methodology and circuit techniques for CMOS readout of MEMS flow sensors. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2017. [cited 2021 Mar 01]. Available from: http://repository.ust.hk/ir/Record/1783.1-104963 ; https://doi.org/10.14711/thesis-991012552668203412 ; http://repository.ust.hk/ir/bitstream/1783.1-104963/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ahmed ME. Design methodology and circuit techniques for CMOS readout of MEMS flow sensors. [Thesis]. Hong Kong University of Science and Technology; 2017. Available from: http://repository.ust.hk/ir/Record/1783.1-104963 ; https://doi.org/10.14711/thesis-991012552668203412 ; http://repository.ust.hk/ir/bitstream/1783.1-104963/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Oregon State University

9. Desikachari, Ranganathan. High-speed CMOS dual-modulus presalers for frequency synthesis.

Degree: MS, Electrical and Computer Engineering, 2003, Oregon State University

URL: http://hdl.handle.net/1957/11724

► Phase-locked loop (PLL) frequency synthesizers lie at the heart of most radio transceivers. An important objective of the electronics and communications industry is to design… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Desikachari, R. (2003). High-speed CMOS dual-modulus presalers for frequency synthesis. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/11724

Chicago Manual of Style (16^th Edition):

Desikachari, Ranganathan. “High-speed CMOS dual-modulus presalers for frequency synthesis.” 2003. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/11724.

MLA Handbook (7^th Edition):

Desikachari, Ranganathan. “High-speed CMOS dual-modulus presalers for frequency synthesis.” 2003. Web. 01 Mar 2021.

Vancouver:

Desikachari R. High-speed CMOS dual-modulus presalers for frequency synthesis. [Internet] [Masters thesis]. Oregon State University; 2003. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/11724.

Council of Science Editors:

Desikachari R. High-speed CMOS dual-modulus presalers for frequency synthesis. [Masters Thesis]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/11724

Oregon State University

10. Natesan, Peroly. Comparison and analysis of jitter in CMOS ring oscillators.

Degree: MS, Electrical and Computer Engineering, 2003, Oregon State University

URL: http://hdl.handle.net/1957/11795

► A comparison and analysis of jitter for five different architectures of ring oscillators using a novel simulation technique developed by Professor Forbes' group is presented.… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Natesan, P. (2003). Comparison and analysis of jitter in CMOS ring oscillators. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/11795

Chicago Manual of Style (16^th Edition):

Natesan, Peroly. “Comparison and analysis of jitter in CMOS ring oscillators.” 2003. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/11795.

MLA Handbook (7^th Edition):

Natesan, Peroly. “Comparison and analysis of jitter in CMOS ring oscillators.” 2003. Web. 01 Mar 2021.

Vancouver:

Natesan P. Comparison and analysis of jitter in CMOS ring oscillators. [Internet] [Masters thesis]. Oregon State University; 2003. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/11795.

Council of Science Editors:

Natesan P. Comparison and analysis of jitter in CMOS ring oscillators. [Masters Thesis]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/11795

Oregon State University

11. Sadate, Aline C. A substrate noise coupling model for lightly doped CMOS processes.

Degree: MS, Electrical and Computer Engineering, 2000, Oregon State University

URL: http://hdl.handle.net/1957/8280

► This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Sadate, A. C. (2000). A substrate noise coupling model for lightly doped CMOS processes. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/8280

Chicago Manual of Style (16^th Edition):

Sadate, Aline C. “A substrate noise coupling model for lightly doped CMOS processes.” 2000. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/8280.

MLA Handbook (7^th Edition):

Sadate, Aline C. “A substrate noise coupling model for lightly doped CMOS processes.” 2000. Web. 01 Mar 2021.

Vancouver:

Sadate AC. A substrate noise coupling model for lightly doped CMOS processes. [Internet] [Masters thesis]. Oregon State University; 2000. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/8280.

Council of Science Editors:

Sadate AC. A substrate noise coupling model for lightly doped CMOS processes. [Masters Thesis]. Oregon State University; 2000. Available from: http://hdl.handle.net/1957/8280

Oregon State University

12. Sharma, Ajit. Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates.

Degree: MS, Electrical and Computer Engineering, 2003, Oregon State University

URL: http://hdl.handle.net/1957/31842

► This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Sharma, A. (2003). Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/31842

Chicago Manual of Style (16^th Edition):

Sharma, Ajit. “Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates.” 2003. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/31842.

MLA Handbook (7^th Edition):

Sharma, Ajit. “Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates.” 2003. Web. 01 Mar 2021.

Vancouver:

Sharma A. Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates. [Internet] [Masters thesis]. Oregon State University; 2003. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/31842.

Council of Science Editors:

Sharma A. Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates. [Masters Thesis]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/31842

Oregon State University

13. Maskai, Sailesh R. Design of complex digital blocks using folded source-coupled logic for mixed-mode applications.

Degree: MS, Electrical and Computer Engineering, 1991, Oregon State University

URL: http://hdl.handle.net/1957/37131

► A series of complex digital blocks have been designed and fabricated using the newly developed current-mode differential CMOS logic family viz. the Folded Source-Coupled Logic… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Maskai, S. R. (1991). Design of complex digital blocks using folded source-coupled logic for mixed-mode applications. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37131

Chicago Manual of Style (16^th Edition):

Maskai, Sailesh R. “Design of complex digital blocks using folded source-coupled logic for mixed-mode applications.” 1991. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/37131.

MLA Handbook (7^th Edition):

Maskai, Sailesh R. “Design of complex digital blocks using folded source-coupled logic for mixed-mode applications.” 1991. Web. 01 Mar 2021.

Vancouver:

Maskai SR. Design of complex digital blocks using folded source-coupled logic for mixed-mode applications. [Internet] [Masters thesis]. Oregon State University; 1991. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/37131.

Council of Science Editors:

Maskai SR. Design of complex digital blocks using folded source-coupled logic for mixed-mode applications. [Masters Thesis]. Oregon State University; 1991. Available from: http://hdl.handle.net/1957/37131

Oregon State University

14. Fiez, Theresa S. Design of CMOS switched-current filters.

Degree: PhD, Electrical and Computer Engineering, 1990, Oregon State University

URL: http://hdl.handle.net/1957/37183

► The design and implementation of Switched-Current (SI) ladder filters is described. SI filters require only a standard digital CMOS process and the power supply voltage… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Fiez, T. S. (1990). Design of CMOS switched-current filters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/37183

Chicago Manual of Style (16^th Edition):

Fiez, Theresa S. “Design of CMOS switched-current filters.” 1990. Doctoral Dissertation, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/37183.

MLA Handbook (7^th Edition):

Fiez, Theresa S. “Design of CMOS switched-current filters.” 1990. Web. 01 Mar 2021.

Vancouver:

Fiez TS. Design of CMOS switched-current filters. [Internet] [Doctoral dissertation]. Oregon State University; 1990. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/37183.

Council of Science Editors:

Fiez TS. Design of CMOS switched-current filters. [Doctoral Dissertation]. Oregon State University; 1990. Available from: http://hdl.handle.net/1957/37183

Washington State University

15. [No author]. High IIP2 CMOS doubly balanced quadrature sub-harmonic mixer for 5 GHz direct conversion receiver .

Degree: 2005, Washington State University

URL: http://hdl.handle.net/2376/312

Subjects/Keywords: Metal oxide semiconductors; Complementary.

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APA (6^th Edition):

author], [. (2005). High IIP2 CMOS doubly balanced quadrature sub-harmonic mixer for 5 GHz direct conversion receiver . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

author], [No. “High IIP2 CMOS doubly balanced quadrature sub-harmonic mixer for 5 GHz direct conversion receiver .” 2005. Thesis, Washington State University. Accessed March 01, 2021. http://hdl.handle.net/2376/312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

author], [No. “High IIP2 CMOS doubly balanced quadrature sub-harmonic mixer for 5 GHz direct conversion receiver .” 2005. Web. 01 Mar 2021.

Vancouver:

author] [. High IIP2 CMOS doubly balanced quadrature sub-harmonic mixer for 5 GHz direct conversion receiver . [Internet] [Thesis]. Washington State University; 2005. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/2376/312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. High IIP2 CMOS doubly balanced quadrature sub-harmonic mixer for 5 GHz direct conversion receiver . [Thesis]. Washington State University; 2005. Available from: http://hdl.handle.net/2376/312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Oregon State University

16. Chandrasekhar, Vinay. Analysis and design of CMOS RF LNAs with ESD protection.

Degree: MS, Electrical and Computer Engineering, 2002, Oregon State University

URL: http://hdl.handle.net/1957/32159

► An analysis that accounts for the effect of standard electrostatic discharge (ESD) structures on critical LNA specifications of noise figure, input matching and gain is… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary – Design

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APA (6^th Edition):

Chandrasekhar, V. (2002). Analysis and design of CMOS RF LNAs with ESD protection. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/32159

Chicago Manual of Style (16^th Edition):

Chandrasekhar, Vinay. “Analysis and design of CMOS RF LNAs with ESD protection.” 2002. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/32159.

MLA Handbook (7^th Edition):

Chandrasekhar, Vinay. “Analysis and design of CMOS RF LNAs with ESD protection.” 2002. Web. 01 Mar 2021.

Vancouver:

Chandrasekhar V. Analysis and design of CMOS RF LNAs with ESD protection. [Internet] [Masters thesis]. Oregon State University; 2002. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/32159.

Council of Science Editors:

Chandrasekhar V. Analysis and design of CMOS RF LNAs with ESD protection. [Masters Thesis]. Oregon State University; 2002. Available from: http://hdl.handle.net/1957/32159

Oregon State University

17. Perigny, Ryan. Area efficiency improvement of CMOS charge pump circuits.

Degree: MS, Electrical and Computer Engineering, 2000, Oregon State University

URL: http://hdl.handle.net/1957/32932

► In this thesis, the literature relating to charge pump dc-dc converters and their uses is reviewed. Charge pumps are useful in many circuits, including low-voltage… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Perigny, R. (2000). Area efficiency improvement of CMOS charge pump circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/32932

Chicago Manual of Style (16^th Edition):

Perigny, Ryan. “Area efficiency improvement of CMOS charge pump circuits.” 2000. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/32932.

MLA Handbook (7^th Edition):

Perigny, Ryan. “Area efficiency improvement of CMOS charge pump circuits.” 2000. Web. 01 Mar 2021.

Vancouver:

Perigny R. Area efficiency improvement of CMOS charge pump circuits. [Internet] [Masters thesis]. Oregon State University; 2000. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/32932.

Council of Science Editors:

Perigny R. Area efficiency improvement of CMOS charge pump circuits. [Masters Thesis]. Oregon State University; 2000. Available from: http://hdl.handle.net/1957/32932

Oregon State University

18. Zhou, Jianjun J. CMOS low noise amplifier design utilizing monolithic transformers.

Degree: PhD, Electrical and Computer Engineering, 1998, Oregon State University

URL: http://hdl.handle.net/1957/33529

► Full integration of CMOS low noise amplifiers (LNA) presents a challenge for low cost CMOS receiver systems. A critical problem faced in the design of… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Zhou, J. J. (1998). CMOS low noise amplifier design utilizing monolithic transformers. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/33529

Chicago Manual of Style (16^th Edition):

Zhou, Jianjun J. “CMOS low noise amplifier design utilizing monolithic transformers.” 1998. Doctoral Dissertation, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/33529.

MLA Handbook (7^th Edition):

Zhou, Jianjun J. “CMOS low noise amplifier design utilizing monolithic transformers.” 1998. Web. 01 Mar 2021.

Vancouver:

Zhou JJ. CMOS low noise amplifier design utilizing monolithic transformers. [Internet] [Doctoral dissertation]. Oregon State University; 1998. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/33529.

Council of Science Editors:

Zhou JJ. CMOS low noise amplifier design utilizing monolithic transformers. [Doctoral Dissertation]. Oregon State University; 1998. Available from: http://hdl.handle.net/1957/33529

Oregon State University

19. Ballweber, Brian M. Design and computer aided optimization of a fully integrated CMOS RF distributed amplifier.

Degree: MS, Electrical and Computer Engineering, 1998, Oregon State University

URL: http://hdl.handle.net/1957/33554

► Advancements in the sophistication and complexity of modern electronic systems are creating a need for highly integrated systems with ever higher operational frequencies. The economical… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Ballweber, B. M. (1998). Design and computer aided optimization of a fully integrated CMOS RF distributed amplifier. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/33554

Chicago Manual of Style (16^th Edition):

Ballweber, Brian M. “Design and computer aided optimization of a fully integrated CMOS RF distributed amplifier.” 1998. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/33554.

MLA Handbook (7^th Edition):

Ballweber, Brian M. “Design and computer aided optimization of a fully integrated CMOS RF distributed amplifier.” 1998. Web. 01 Mar 2021.

Vancouver:

Ballweber BM. Design and computer aided optimization of a fully integrated CMOS RF distributed amplifier. [Internet] [Masters thesis]. Oregon State University; 1998. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/33554.

Council of Science Editors:

Ballweber BM. Design and computer aided optimization of a fully integrated CMOS RF distributed amplifier. [Masters Thesis]. Oregon State University; 1998. Available from: http://hdl.handle.net/1957/33554

Oregon State University

20. Shah, Parag Shantu. Low-power high-performance 32-bit 0.5[u]m CMOS adder.

Degree: MS, Electrical and Computer Engineering, 1998, Oregon State University

URL: http://hdl.handle.net/1957/33605

► Currently, the two most critical factors of microprocessor design are performance and power. The optimum balance of these two factors is reflected in the speed-power… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Shah, P. S. (1998). Low-power high-performance 32-bit 0.5[u]m CMOS adder. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/33605

Chicago Manual of Style (16^th Edition):

Shah, Parag Shantu. “Low-power high-performance 32-bit 0.5[u]m CMOS adder.” 1998. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/33605.

MLA Handbook (7^th Edition):

Shah, Parag Shantu. “Low-power high-performance 32-bit 0.5[u]m CMOS adder.” 1998. Web. 01 Mar 2021.

Vancouver:

Shah PS. Low-power high-performance 32-bit 0.5[u]m CMOS adder. [Internet] [Masters thesis]. Oregon State University; 1998. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/33605.

Council of Science Editors:

Shah PS. Low-power high-performance 32-bit 0.5[u]m CMOS adder. [Masters Thesis]. Oregon State University; 1998. Available from: http://hdl.handle.net/1957/33605

Oregon State University

21. Lim, Wei Tjan (Richard). Suppression of substrate noise in a mixed-signal CMOS intergrated circuit.

Degree: MS, Electrical and Computer Engineering, 1996, Oregon State University

URL: http://hdl.handle.net/1957/34197

► Substrate switching noise is becoming a concern as integrated circuits get larger and speeds get faster. Mixed-mode integrated circuits are especially affected as the substrate… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Lim, W. T. (. (1996). Suppression of substrate noise in a mixed-signal CMOS intergrated circuit. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/34197

Chicago Manual of Style (16^th Edition):

Lim, Wei Tjan (Richard). “Suppression of substrate noise in a mixed-signal CMOS intergrated circuit.” 1996. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/34197.

MLA Handbook (7^th Edition):

Lim, Wei Tjan (Richard). “Suppression of substrate noise in a mixed-signal CMOS intergrated circuit.” 1996. Web. 01 Mar 2021.

Vancouver:

Lim WT(. Suppression of substrate noise in a mixed-signal CMOS intergrated circuit. [Internet] [Masters thesis]. Oregon State University; 1996. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/34197.

Council of Science Editors:

Lim WT(. Suppression of substrate noise in a mixed-signal CMOS intergrated circuit. [Masters Thesis]. Oregon State University; 1996. Available from: http://hdl.handle.net/1957/34197

Oregon State University

22. Zhang, Jing, 1962-. Generation of substrate bias and current sources in CMOS technology.

Degree: MS, Electrical and Computer Engineering, 1995, Oregon State University

URL: http://hdl.handle.net/1957/34653

► A negatively biased substrate has several advantages over a grounded substrate in CMOS technology. The on-chip generation of this negative substrate bias has made chips… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Zhang, Jing, 1. (1995). Generation of substrate bias and current sources in CMOS technology. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/34653

Chicago Manual of Style (16^th Edition):

Zhang, Jing, 1962-. “Generation of substrate bias and current sources in CMOS technology.” 1995. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/34653.

MLA Handbook (7^th Edition):

Zhang, Jing, 1962-. “Generation of substrate bias and current sources in CMOS technology.” 1995. Web. 01 Mar 2021.

Vancouver:

Zhang, Jing 1. Generation of substrate bias and current sources in CMOS technology. [Internet] [Masters thesis]. Oregon State University; 1995. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/34653.

Council of Science Editors:

Zhang, Jing 1. Generation of substrate bias and current sources in CMOS technology. [Masters Thesis]. Oregon State University; 1995. Available from: http://hdl.handle.net/1957/34653

Oregon State University

23. Hwang, Nam. Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors.

Degree: PhD, Electrical and Computer Engineering, 1993, Oregon State University

URL: http://hdl.handle.net/1957/35625

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Hwang, N. (1993). Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/35625

Chicago Manual of Style (16^th Edition):

Hwang, Nam. “Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors.” 1993. Doctoral Dissertation, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/35625.

MLA Handbook (7^th Edition):

Hwang, Nam. “Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors.” 1993. Web. 01 Mar 2021.

Vancouver:

Hwang N. Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors. [Internet] [Doctoral dissertation]. Oregon State University; 1993. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/35625.

Council of Science Editors:

Hwang N. Physical mechanisms, device models, and lifetime projections of hot-carrier effects in CMOS transistors. [Doctoral Dissertation]. Oregon State University; 1993. Available from: http://hdl.handle.net/1957/35625

Oregon State University

24. Lao, Paul A. Current-feedthrough cancellation techniques in switched-current circuits.

Degree: MS, Electrical and Computer Engineering, 1990, Oregon State University

URL: http://hdl.handle.net/1957/37719

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Lao, P. A. (1990). Current-feedthrough cancellation techniques in switched-current circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37719

Chicago Manual of Style (16^th Edition):

Lao, Paul A. “Current-feedthrough cancellation techniques in switched-current circuits.” 1990. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/37719.

MLA Handbook (7^th Edition):

Lao, Paul A. “Current-feedthrough cancellation techniques in switched-current circuits.” 1990. Web. 01 Mar 2021.

Vancouver:

Lao PA. Current-feedthrough cancellation techniques in switched-current circuits. [Internet] [Masters thesis]. Oregon State University; 1990. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/37719.

Council of Science Editors:

Lao PA. Current-feedthrough cancellation techniques in switched-current circuits. [Masters Thesis]. Oregon State University; 1990. Available from: http://hdl.handle.net/1957/37719

Oregon State University

25. Zele, Rajesh H. Fully-differential current-mode CMOS circuits and applications.

Degree: MS, Electrical and Computer Engineering, 1990, Oregon State University

URL: http://hdl.handle.net/1957/37934

► With increasing interest in current-mode analogue processing due to its high performance properties such as speed, bandwidth and accuracy compared to voltage-mode processing, new current-mode… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6^th Edition):

Zele, R. H. (1990). Fully-differential current-mode CMOS circuits and applications. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37934

Chicago Manual of Style (16^th Edition):

Zele, Rajesh H. “Fully-differential current-mode CMOS circuits and applications.” 1990. Masters Thesis, Oregon State University. Accessed March 01, 2021. http://hdl.handle.net/1957/37934.

MLA Handbook (7^th Edition):

Zele, Rajesh H. “Fully-differential current-mode CMOS circuits and applications.” 1990. Web. 01 Mar 2021.

Vancouver:

Zele RH. Fully-differential current-mode CMOS circuits and applications. [Internet] [Masters thesis]. Oregon State University; 1990. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1957/37934.

Council of Science Editors:

Zele RH. Fully-differential current-mode CMOS circuits and applications. [Masters Thesis]. Oregon State University; 1990. Available from: http://hdl.handle.net/1957/37934

Columbia University

26. Shekar, Siddharth. Design of custom CMOS amplifiers for nanoscale bio-interfaces.

Degree: 2019, Columbia University

URL: https://doi.org/10.7916/d8-kb2p-zm21

► The miniaturization of electronics is a technique that holds a lot of potential in improving system performance in a variety of applications. The simultaneous miniaturization… (more)

Subjects/Keywords: Electrical engineering; Nanotechnology; Metal oxide semiconductors, Complementary; Amplifiers (Electronics); Biological interfaces

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APA (6^th Edition):

Shekar, S. (2019). Design of custom CMOS amplifiers for nanoscale bio-interfaces. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/d8-kb2p-zm21

Chicago Manual of Style (16^th Edition):

Shekar, Siddharth. “Design of custom CMOS amplifiers for nanoscale bio-interfaces.” 2019. Doctoral Dissertation, Columbia University. Accessed March 01, 2021. https://doi.org/10.7916/d8-kb2p-zm21.

MLA Handbook (7^th Edition):

Shekar, Siddharth. “Design of custom CMOS amplifiers for nanoscale bio-interfaces.” 2019. Web. 01 Mar 2021.

Vancouver:

Shekar S. Design of custom CMOS amplifiers for nanoscale bio-interfaces. [Internet] [Doctoral dissertation]. Columbia University; 2019. [cited 2021 Mar 01]. Available from: https://doi.org/10.7916/d8-kb2p-zm21.

Council of Science Editors:

Shekar S. Design of custom CMOS amplifiers for nanoscale bio-interfaces. [Doctoral Dissertation]. Columbia University; 2019. Available from: https://doi.org/10.7916/d8-kb2p-zm21

Columbia University

27. Zhu, Jianxun. Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios.

Degree: 2017, Columbia University

URL: https://doi.org/10.7916/D8TX3SNZ

► Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the… (more)

▼ Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and…

Subjects/Keywords: Electrical engineering; Metal oxide semiconductors, Complementary; Electric circuits; Electronics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhu, J. (2017). Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D8TX3SNZ

Chicago Manual of Style (16^th Edition):

Zhu, Jianxun. “Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios.” 2017. Doctoral Dissertation, Columbia University. Accessed March 01, 2021. https://doi.org/10.7916/D8TX3SNZ.

MLA Handbook (7^th Edition):

Zhu, Jianxun. “Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios.” 2017. Web. 01 Mar 2021.

Vancouver:

Zhu J. Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios. [Internet] [Doctoral dissertation]. Columbia University; 2017. [cited 2021 Mar 01]. Available from: https://doi.org/10.7916/D8TX3SNZ.

Council of Science Editors:

Zhu J. Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios. [Doctoral Dissertation]. Columbia University; 2017. Available from: https://doi.org/10.7916/D8TX3SNZ

Hong Kong University of Science and Technology

28. Zhong, Xiaopeng ECE. Low-power smart CMOS image sensors with embedded mixed-signal image processing.

Degree: 2019, Hong Kong University of Science and Technology

URL: http://repository.ust.hk/ir/Record/1783.1-102120 ; https://doi.org/10.14711/thesis-991012717867903412 ; http://repository.ust.hk/ir/bitstream/1783.1-102120/1/th_redirect.html

► Smart and low-power CMOS image sensor (CIS) has seen an increased attention over the last decade, specially targeting wireless sensor network applications. To further push… (more)

▼ Smart and low-power CMOS image sensor (CIS) has seen an increased attention over the last decade, specially targeting wireless sensor network applications. To further push the power limit, mixed-signal image processing has been embedded within CIS to reduce efforts on signal quantization, data movement and processing. In this thesis, four types of smart CISs with embedded mixed-signal image processing are presented, with focus on image compression, spatial and temporal feature extraction, and a combination of these functions, respectively. The aim is to build a smart image sensor featuring low power with high energy efficiency, improved processing capability and accuracy as well as low area overhead. The first CIS employs a planned-sensor-distortion (PSD) algorithm to compress image data before transmission or storage. 3-bit PSD imaging is enabled by a column-parallel microshift-guided SAR ADC based on a 3x3 predefined pattern. The data bandwidth is further compressed by a customized lossless encoder using predictive coding and run length coding. High reconstruction image quality with low data rate and low power consumption has been successfully demonstrated by the prototype chip. The second CIS focuses on local binary pattern (LBP) extraction and edge detection for object analysis applications. A 4-pixel group computation (GC) scheme is developed to efficiently extract 8-direction LBP and edge information. High-speed and energy-efficient column-parallel GC is realized through an innovative group-switchable multi-input-multi-output (MIMO) comparator. The proposed reconfigurable mixed-signal processing circuits have been successfully demonstrated featuring accurate feature extraction with state-of-the-art energy efficiency. The third proposed CIS embeds motion sensing for event-triggered applications. The sensor is reconfigurable for motion sensing, object segmentation and snapshot. High-frame-rate frame differencing (FD) and low-frame-rate background subtraction (BS) are combined as a cooperative sensing scheme to improve motion detection performance with minimum power overhead. Object segmentation is realized through BS-based region-of-interest imaging, which efficiently reduces both imaging and object localization efforts. Snapshot is performed through full-resolution imaging. Both high area and energy efficiencies have been validated by the prototype multi-mode CIS. Last but not least, a fourth CIS is demonstrated combining motion sensing, feature extraction and image compression as a System-on-Chip (SoC). This versatile CIS design provides scene-adaptive sensing with optimized power and bandwidth utilization. The proposed design has successfully combined the versatile smart functionalities from above designs with high energy efficiency and compact area, making the prospect of deploying such a sensor for a wide range of wireless camera network applications a reality.

Subjects/Keywords: Image converters ; Data processing ; Metal oxide semiconductors, Complementary ; Motion detectors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhong, X. E. (2019). Low-power smart CMOS image sensors with embedded mixed-signal image processing. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-102120 ; https://doi.org/10.14711/thesis-991012717867903412 ; http://repository.ust.hk/ir/bitstream/1783.1-102120/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zhong, Xiaopeng ECE. “Low-power smart CMOS image sensors with embedded mixed-signal image processing.” 2019. Thesis, Hong Kong University of Science and Technology. Accessed March 01, 2021. http://repository.ust.hk/ir/Record/1783.1-102120 ; https://doi.org/10.14711/thesis-991012717867903412 ; http://repository.ust.hk/ir/bitstream/1783.1-102120/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zhong, Xiaopeng ECE. “Low-power smart CMOS image sensors with embedded mixed-signal image processing.” 2019. Web. 01 Mar 2021.

Vancouver:

Zhong XE. Low-power smart CMOS image sensors with embedded mixed-signal image processing. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2019. [cited 2021 Mar 01]. Available from: http://repository.ust.hk/ir/Record/1783.1-102120 ; https://doi.org/10.14711/thesis-991012717867903412 ; http://repository.ust.hk/ir/bitstream/1783.1-102120/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhong XE. Low-power smart CMOS image sensors with embedded mixed-signal image processing. [Thesis]. Hong Kong University of Science and Technology; 2019. Available from: http://repository.ust.hk/ir/Record/1783.1-102120 ; https://doi.org/10.14711/thesis-991012717867903412 ; http://repository.ust.hk/ir/bitstream/1783.1-102120/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Hong Kong University of Science and Technology

29. Liu, Rui. CMOS class-C VCO and QVCO for WLAN applications.

Degree: 2013, Hong Kong University of Science and Technology

URL: http://repository.ust.hk/ir/Record/1783.1-62320 ; https://doi.org/10.14711/thesis-b1255633 ; http://repository.ust.hk/ir/bitstream/1783.1-62320/1/th_redirect.html

► WLAN (Wireless Local Area Network) applications based on 802.11 protocol family have enjoyed a tremendous growth in both home and enterprise market since it was… (more)

Subjects/Keywords: Voltage-controlled oscillators ; Wireless LANs ; Metal oxide semiconductors, Complementary

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liu, R. (2013). CMOS class-C VCO and QVCO for WLAN applications. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-62320 ; https://doi.org/10.14711/thesis-b1255633 ; http://repository.ust.hk/ir/bitstream/1783.1-62320/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liu, Rui. “CMOS class-C VCO and QVCO for WLAN applications.” 2013. Thesis, Hong Kong University of Science and Technology. Accessed March 01, 2021. http://repository.ust.hk/ir/Record/1783.1-62320 ; https://doi.org/10.14711/thesis-b1255633 ; http://repository.ust.hk/ir/bitstream/1783.1-62320/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liu, Rui. “CMOS class-C VCO and QVCO for WLAN applications.” 2013. Web. 01 Mar 2021.

Vancouver:

Liu R. CMOS class-C VCO and QVCO for WLAN applications. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2013. [cited 2021 Mar 01]. Available from: http://repository.ust.hk/ir/Record/1783.1-62320 ; https://doi.org/10.14711/thesis-b1255633 ; http://repository.ust.hk/ir/bitstream/1783.1-62320/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu R. CMOS class-C VCO and QVCO for WLAN applications. [Thesis]. Hong Kong University of Science and Technology; 2013. Available from: http://repository.ust.hk/ir/Record/1783.1-62320 ; https://doi.org/10.14711/thesis-b1255633 ; http://repository.ust.hk/ir/bitstream/1783.1-62320/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Hong Kong University of Science and Technology

30. Hou, Zhengxiong. CMOS photodetector and limiting amplifier for high speed optical communication.

Degree: 2014, Hong Kong University of Science and Technology

URL: http://repository.ust.hk/ir/Record/1783.1-71020 ; https://doi.org/10.14711/thesis-b1333704 ; http://repository.ust.hk/ir/bitstream/1783.1-71020/1/th_redirect.html

► Optical communication is essential in industrial applications and the consumer market. Active optical fiber has great potential to replace copper in short-distance wire line communication.… (more)

▼ Optical communication is essential in industrial applications and the consumer market. Active optical fiber has great potential to replace copper in short-distance wire line communication. Current products and some research focus on 100-Gb/s Ethernet. This is achieved by 10 channels, with each operating at 10-Gb/s. In our group, we have started building each block of a 25-Gb/s optical receiver for next generation Ethernet. In this thesis, two major areas are covered. Firstly, CMOS photodetectors, including the n+/p-substrate, n-well/p-substrate, and n-well/Deep n-well/p-substrate photodiode and PNP phototransistors and the Darlington pair, are presented. Currently, the common photodetector is made of Ge, InGaAs or GaAs. Although Ge p-i-n photodiodes are proved CMOS process compatible, the standard CMOS process still cannot build these photodetectors integrated with the circuits. The measured responsivity of the CMOS photodetectors is extracted and built into a model for our circuit simulation. Secondly, a limiting amplifier with high gain and large bandwidth is presented. Bipolar transistors in III-V compound technology used to be employed in high speed front ends due to their high mobility and low noise, but they cost much power and area. Currently, advanced CMOS technology is more attractive in terms of integration and power consumption. In this thesis, a CMOS limiting amplifier based on the structure of the modified Cherry-Hooper amplifier design is presented in detail. The CMOS photodetector and the limiting amplifier are fabricated in TSMC 65 nm CMOS technology with f_T=185 GHz. The n-well/p-substrate has the largest bandwidth, 120 MHz, and the Darlington pair has the highest responsivity, 1176 mA/W. Simulation results show that the CMOS photodiode is capable of achieving a 14Gb/s optical receiver. The measured results of the 25-Gb/s optical receiver with off-chip photodiode indicate that the limiting amplifier achieves a high gain and large bandwidth with low power consumption 23 mW.

Subjects/Keywords: Optical detectors ; Metal oxide semiconductors, Complementary ; Light amplifiers ; Optical communications

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hou, Z. (2014). CMOS photodetector and limiting amplifier for high speed optical communication. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-71020 ; https://doi.org/10.14711/thesis-b1333704 ; http://repository.ust.hk/ir/bitstream/1783.1-71020/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hou, Zhengxiong. “CMOS photodetector and limiting amplifier for high speed optical communication.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed March 01, 2021. http://repository.ust.hk/ir/Record/1783.1-71020 ; https://doi.org/10.14711/thesis-b1333704 ; http://repository.ust.hk/ir/bitstream/1783.1-71020/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hou, Zhengxiong. “CMOS photodetector and limiting amplifier for high speed optical communication.” 2014. Web. 01 Mar 2021.

Vancouver:

Hou Z. CMOS photodetector and limiting amplifier for high speed optical communication. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2021 Mar 01]. Available from: http://repository.ust.hk/ir/Record/1783.1-71020 ; https://doi.org/10.14711/thesis-b1333704 ; http://repository.ust.hk/ir/bitstream/1783.1-71020/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hou Z. CMOS photodetector and limiting amplifier for high speed optical communication. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: http://repository.ust.hk/ir/Record/1783.1-71020 ; https://doi.org/10.14711/thesis-b1333704 ; http://repository.ust.hk/ir/bitstream/1783.1-71020/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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Open Access Theses and Dissertations