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You searched for subject:(Memory system). Showing records 1 – 30 of 337 total matches.

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Penn State University

1. Niu, Dimin. Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System.

Degree: 2013, Penn State University

 As leakage power and fabrication difficulty have become major obstacles of DRAM scaling, the search for new technologies as DRAM alternative has gained increased attention.… (more)

Subjects/Keywords: Memory System; Non-Volatile Memory; Resistive Memory

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APA (6th Edition):

Niu, D. (2013). Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/19113

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Niu, Dimin. “Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System.” 2013. Thesis, Penn State University. Accessed March 02, 2021. https://submit-etda.libraries.psu.edu/catalog/19113.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Niu, Dimin. “Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System.” 2013. Web. 02 Mar 2021.

Vancouver:

Niu D. Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System. [Internet] [Thesis]. Penn State University; 2013. [cited 2021 Mar 02]. Available from: https://submit-etda.libraries.psu.edu/catalog/19113.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Niu D. Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System. [Thesis]. Penn State University; 2013. Available from: https://submit-etda.libraries.psu.edu/catalog/19113

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

2. Kwon, Youngjin, Ph. D. Designing systems for emerging memory technologies.

Degree: PhD, Computer Science, 2018, University of Texas – Austin

 Emerging memory technologies open new challenges in system software: diversity and large capacity. Non-volatile memory (NVM) technologies will have excellent performance, byte- addressability, and large… (more)

Subjects/Keywords: Non-volatile memory; File system; Memory system

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APA (6th Edition):

Kwon, Youngjin, P. D. (2018). Designing systems for emerging memory technologies. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/68486

Chicago Manual of Style (16th Edition):

Kwon, Youngjin, Ph D. “Designing systems for emerging memory technologies.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed March 02, 2021. http://hdl.handle.net/2152/68486.

MLA Handbook (7th Edition):

Kwon, Youngjin, Ph D. “Designing systems for emerging memory technologies.” 2018. Web. 02 Mar 2021.

Vancouver:

Kwon, Youngjin PD. Designing systems for emerging memory technologies. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2152/68486.

Council of Science Editors:

Kwon, Youngjin PD. Designing systems for emerging memory technologies. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/68486


University of Waikato

3. Chang, Su-Ping Carole. A Mobile Augmented Memory Aid for people with Traumatic Brain Injury .

Degree: 2017, University of Waikato

 Traumatic Brain Injury (TBI) occurs when an external mechanical force traumatically injures the brain. The 2010/2011 population-based study shows that the total incidence of TBI… (more)

Subjects/Keywords: Brain Injury; Memory Impairments; Augmented Memory System; Mobile Memory System; Autobiographical Memory System

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APA (6th Edition):

Chang, S. C. (2017). A Mobile Augmented Memory Aid for people with Traumatic Brain Injury . (Doctoral Dissertation). University of Waikato. Retrieved from http://hdl.handle.net/10289/10850

Chicago Manual of Style (16th Edition):

Chang, Su-Ping Carole. “A Mobile Augmented Memory Aid for people with Traumatic Brain Injury .” 2017. Doctoral Dissertation, University of Waikato. Accessed March 02, 2021. http://hdl.handle.net/10289/10850.

MLA Handbook (7th Edition):

Chang, Su-Ping Carole. “A Mobile Augmented Memory Aid for people with Traumatic Brain Injury .” 2017. Web. 02 Mar 2021.

Vancouver:

Chang SC. A Mobile Augmented Memory Aid for people with Traumatic Brain Injury . [Internet] [Doctoral dissertation]. University of Waikato; 2017. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10289/10850.

Council of Science Editors:

Chang SC. A Mobile Augmented Memory Aid for people with Traumatic Brain Injury . [Doctoral Dissertation]. University of Waikato; 2017. Available from: http://hdl.handle.net/10289/10850


Texas A&M University

4. Kim, Jinchun. Reference Speculation-driven Memory Management.

Degree: PhD, Computer Engineering, 2017, Texas A&M University

 The “Memory Wall”, the vast gulf between processor execution speed and memory latency, has led to the development of large and deep cache hierarchies over… (more)

Subjects/Keywords: Memory System; Microarchitecture; Virtual Memory; Speculation

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APA (6th Edition):

Kim, J. (2017). Reference Speculation-driven Memory Management. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/161573

Chicago Manual of Style (16th Edition):

Kim, Jinchun. “Reference Speculation-driven Memory Management.” 2017. Doctoral Dissertation, Texas A&M University. Accessed March 02, 2021. http://hdl.handle.net/1969.1/161573.

MLA Handbook (7th Edition):

Kim, Jinchun. “Reference Speculation-driven Memory Management.” 2017. Web. 02 Mar 2021.

Vancouver:

Kim J. Reference Speculation-driven Memory Management. [Internet] [Doctoral dissertation]. Texas A&M University; 2017. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/1969.1/161573.

Council of Science Editors:

Kim J. Reference Speculation-driven Memory Management. [Doctoral Dissertation]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/161573


University of Utah

5. Chatterjee, Niladrish. Designing efficient memory schedulers for future systems.

Degree: PhD, Computing (School of), 2013, University of Utah

 The internet-based information infrastructure that has powered the growth of modern personal/mobile computing is composed of powerful, warehouse-scale computers or datacenters. These heavily subscribed datacenters… (more)

Subjects/Keywords: DRAM; Memory system; Scheduling

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APA (6th Edition):

Chatterjee, N. (2013). Designing efficient memory schedulers for future systems. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/2678/rec/658

Chicago Manual of Style (16th Edition):

Chatterjee, Niladrish. “Designing efficient memory schedulers for future systems.” 2013. Doctoral Dissertation, University of Utah. Accessed March 02, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/2678/rec/658.

MLA Handbook (7th Edition):

Chatterjee, Niladrish. “Designing efficient memory schedulers for future systems.” 2013. Web. 02 Mar 2021.

Vancouver:

Chatterjee N. Designing efficient memory schedulers for future systems. [Internet] [Doctoral dissertation]. University of Utah; 2013. [cited 2021 Mar 02]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/2678/rec/658.

Council of Science Editors:

Chatterjee N. Designing efficient memory schedulers for future systems. [Doctoral Dissertation]. University of Utah; 2013. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/2678/rec/658


NSYSU

6. Yang, Shang-da. Implementation of Hierarchical Architecture of Basic Memory Modules.

Degree: Master, Electrical Engineering, 2008, NSYSU

 In system-on-chip designs, memory designs store data to be accessed by processing modules. Memory access time can affect overall system performance significantly. In this research,… (more)

Subjects/Keywords: system-on-chip; memory; memory interface; memory controller

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APA (6th Edition):

Yang, S. (2008). Implementation of Hierarchical Architecture of Basic Memory Modules. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911108-201039

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Shang-da. “Implementation of Hierarchical Architecture of Basic Memory Modules.” 2008. Thesis, NSYSU. Accessed March 02, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911108-201039.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Shang-da. “Implementation of Hierarchical Architecture of Basic Memory Modules.” 2008. Web. 02 Mar 2021.

Vancouver:

Yang S. Implementation of Hierarchical Architecture of Basic Memory Modules. [Internet] [Thesis]. NSYSU; 2008. [cited 2021 Mar 02]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911108-201039.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang S. Implementation of Hierarchical Architecture of Basic Memory Modules. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911108-201039

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Rochester

7. Nazm Bojnordi, Mahdi. Memory system optimizations for energy and bandwidth efficient data movement.

Degree: PhD, 2016, University of Rochester

 Since the early 2000s, power dissipation and memory bandwidth have been two of the most critical challenges that limit the performance of computer systems, from… (more)

Subjects/Keywords: Computer architecture; Data movement; Memory system

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APA (6th Edition):

Nazm Bojnordi, M. (2016). Memory system optimizations for energy and bandwidth efficient data movement. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/31311

Chicago Manual of Style (16th Edition):

Nazm Bojnordi, Mahdi. “Memory system optimizations for energy and bandwidth efficient data movement.” 2016. Doctoral Dissertation, University of Rochester. Accessed March 02, 2021. http://hdl.handle.net/1802/31311.

MLA Handbook (7th Edition):

Nazm Bojnordi, Mahdi. “Memory system optimizations for energy and bandwidth efficient data movement.” 2016. Web. 02 Mar 2021.

Vancouver:

Nazm Bojnordi M. Memory system optimizations for energy and bandwidth efficient data movement. [Internet] [Doctoral dissertation]. University of Rochester; 2016. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/1802/31311.

Council of Science Editors:

Nazm Bojnordi M. Memory system optimizations for energy and bandwidth efficient data movement. [Doctoral Dissertation]. University of Rochester; 2016. Available from: http://hdl.handle.net/1802/31311


Université de Neuchâtel

8. Facchin, Stéphanie. Faut-il réfléchir pour être performant en groupe ?: les conditions de l’efficacité de la réflexivité.

Degree: 2008, Université de Neuchâtel

 In this dissertation I concentrate on some of the boundary conditions of reflexivity in teams. Research has shown that reflexivity (collectively reflecting on the teams’… (more)

Subjects/Keywords: transactive memory system

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APA (6th Edition):

Facchin, S. (2008). Faut-il réfléchir pour être performant en groupe ?: les conditions de l’efficacité de la réflexivité. (Thesis). Université de Neuchâtel. Retrieved from http://doc.rero.ch/record/11746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Facchin, Stéphanie. “Faut-il réfléchir pour être performant en groupe ?: les conditions de l’efficacité de la réflexivité.” 2008. Thesis, Université de Neuchâtel. Accessed March 02, 2021. http://doc.rero.ch/record/11746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Facchin, Stéphanie. “Faut-il réfléchir pour être performant en groupe ?: les conditions de l’efficacité de la réflexivité.” 2008. Web. 02 Mar 2021.

Vancouver:

Facchin S. Faut-il réfléchir pour être performant en groupe ?: les conditions de l’efficacité de la réflexivité. [Internet] [Thesis]. Université de Neuchâtel; 2008. [cited 2021 Mar 02]. Available from: http://doc.rero.ch/record/11746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Facchin S. Faut-il réfléchir pour être performant en groupe ?: les conditions de l’efficacité de la réflexivité. [Thesis]. Université de Neuchâtel; 2008. Available from: http://doc.rero.ch/record/11746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


California State University – Sacramento

9. Bandri Anand, Kiran. Design and implementation of a sensor hub interface using an ARM cortex m0 processor.

Degree: MS, Electrical and Electronic Engineering, 2019, California State University – Sacramento

 Smart Devices and the need for intelligent systems has brought about a revolution in Technology. With devices getting smaller, yet more effective, there is a… (more)

Subjects/Keywords: Sensor applications; Computer architecture; Cache memory system

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APA (6th Edition):

Bandri Anand, K. (2019). Design and implementation of a sensor hub interface using an ARM cortex m0 processor. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/207768

Chicago Manual of Style (16th Edition):

Bandri Anand, Kiran. “Design and implementation of a sensor hub interface using an ARM cortex m0 processor.” 2019. Masters Thesis, California State University – Sacramento. Accessed March 02, 2021. http://hdl.handle.net/10211.3/207768.

MLA Handbook (7th Edition):

Bandri Anand, Kiran. “Design and implementation of a sensor hub interface using an ARM cortex m0 processor.” 2019. Web. 02 Mar 2021.

Vancouver:

Bandri Anand K. Design and implementation of a sensor hub interface using an ARM cortex m0 processor. [Internet] [Masters thesis]. California State University – Sacramento; 2019. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10211.3/207768.

Council of Science Editors:

Bandri Anand K. Design and implementation of a sensor hub interface using an ARM cortex m0 processor. [Masters Thesis]. California State University – Sacramento; 2019. Available from: http://hdl.handle.net/10211.3/207768


University of Maryland

10. DONG, YUNTAO. A MULTILEVEL INVESTIGATION OF LEADER EMPOWERING BEHAVIORS: INTEGRATING THE JOB DEMANDS-CONTROL MODEL AND TRANSACTIVE MEMORY SYSTEM THEORY.

Degree: Business and Management: Management & Organization, 2013, University of Maryland

 Empowering leader behaviors have been generally suggested to motivate employees and facilitate their goal achievement, but they can also be challenging and demanding. Yet questions… (more)

Subjects/Keywords: Management; Empowering leadership; Engagement; Transactive memory system

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APA (6th Edition):

DONG, Y. (2013). A MULTILEVEL INVESTIGATION OF LEADER EMPOWERING BEHAVIORS: INTEGRATING THE JOB DEMANDS-CONTROL MODEL AND TRANSACTIVE MEMORY SYSTEM THEORY. (Thesis). University of Maryland. Retrieved from http://hdl.handle.net/1903/14577

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

DONG, YUNTAO. “A MULTILEVEL INVESTIGATION OF LEADER EMPOWERING BEHAVIORS: INTEGRATING THE JOB DEMANDS-CONTROL MODEL AND TRANSACTIVE MEMORY SYSTEM THEORY.” 2013. Thesis, University of Maryland. Accessed March 02, 2021. http://hdl.handle.net/1903/14577.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

DONG, YUNTAO. “A MULTILEVEL INVESTIGATION OF LEADER EMPOWERING BEHAVIORS: INTEGRATING THE JOB DEMANDS-CONTROL MODEL AND TRANSACTIVE MEMORY SYSTEM THEORY.” 2013. Web. 02 Mar 2021.

Vancouver:

DONG Y. A MULTILEVEL INVESTIGATION OF LEADER EMPOWERING BEHAVIORS: INTEGRATING THE JOB DEMANDS-CONTROL MODEL AND TRANSACTIVE MEMORY SYSTEM THEORY. [Internet] [Thesis]. University of Maryland; 2013. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/1903/14577.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

DONG Y. A MULTILEVEL INVESTIGATION OF LEADER EMPOWERING BEHAVIORS: INTEGRATING THE JOB DEMANDS-CONTROL MODEL AND TRANSACTIVE MEMORY SYSTEM THEORY. [Thesis]. University of Maryland; 2013. Available from: http://hdl.handle.net/1903/14577

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

11. -9048-1017. Exploiting long-term behavior for improved memory system performance.

Degree: PhD, Computer science, 2016, University of Texas – Austin

Memory latency is a key bottleneck for many programs. Caching and prefetching are two popular hardware mechanisms to alleviate the impact of long memory latencies,… (more)

Subjects/Keywords: Caches; Replacement policy; Prefetching; Memory system

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APA (6th Edition):

-9048-1017. (2016). Exploiting long-term behavior for improved memory system performance. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/42015

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-9048-1017. “Exploiting long-term behavior for improved memory system performance.” 2016. Doctoral Dissertation, University of Texas – Austin. Accessed March 02, 2021. http://hdl.handle.net/2152/42015.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-9048-1017. “Exploiting long-term behavior for improved memory system performance.” 2016. Web. 02 Mar 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-9048-1017. Exploiting long-term behavior for improved memory system performance. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2016. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2152/42015.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-9048-1017. Exploiting long-term behavior for improved memory system performance. [Doctoral Dissertation]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/42015

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

12. Chi, Ping. Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives.

Degree: 2016, University of California – eScholarship, University of California

 This dissertation focuses on three types of emerging NVMs, spin-transfer torque RAM (STT-RAM), phase change memory (PCM), and metal-oxide resistive RAM (ReRAM). STT-RAM has been… (more)

Subjects/Keywords: Computer engineering; memory system design; non-volatile memory; phase change memory; ReRAM; STT-RAM

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APA (6th Edition):

Chi, P. (2016). Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives. (Thesis). University of California – eScholarship, University of California. Retrieved from http://www.escholarship.org/uc/item/2g6962cg

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chi, Ping. “Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives.” 2016. Thesis, University of California – eScholarship, University of California. Accessed March 02, 2021. http://www.escholarship.org/uc/item/2g6962cg.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chi, Ping. “Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives.” 2016. Web. 02 Mar 2021.

Vancouver:

Chi P. Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives. [Internet] [Thesis]. University of California – eScholarship, University of California; 2016. [cited 2021 Mar 02]. Available from: http://www.escholarship.org/uc/item/2g6962cg.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chi P. Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives. [Thesis]. University of California – eScholarship, University of California; 2016. Available from: http://www.escholarship.org/uc/item/2g6962cg

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

13. Xu, Cong. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory.

Degree: 2014, Penn State University

 Conventional memories technologies such as SRAM, DRAM, and NAND flash are facing formidable device scaling challenges. Various new non-volatile memory (NVM) technologies have emerged recently,… (more)

Subjects/Keywords: Non-Volatile Memory; ReRAM; Computer Architecture; Memory System

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xu, C. (2014). Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/23577

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xu, Cong. “Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory.” 2014. Thesis, Penn State University. Accessed March 02, 2021. https://submit-etda.libraries.psu.edu/catalog/23577.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xu, Cong. “Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory.” 2014. Web. 02 Mar 2021.

Vancouver:

Xu C. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory. [Internet] [Thesis]. Penn State University; 2014. [cited 2021 Mar 02]. Available from: https://submit-etda.libraries.psu.edu/catalog/23577.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu C. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory. [Thesis]. Penn State University; 2014. Available from: https://submit-etda.libraries.psu.edu/catalog/23577

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

14. Kang, Suk Chan. Optimizing high locality memory references in cache coherent shared memory multi-core processors.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 Optimizing memory references has been a primary research area of computer systems ever since the advent of the stored program computers. The objective of this… (more)

Subjects/Keywords: Shared memory system; Cache coherence; Memory consistency; Synchronization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kang, S. C. (2019). Optimizing high locality memory references in cache coherent shared memory multi-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62641

Chicago Manual of Style (16th Edition):

Kang, Suk Chan. “Optimizing high locality memory references in cache coherent shared memory multi-core processors.” 2019. Doctoral Dissertation, Georgia Tech. Accessed March 02, 2021. http://hdl.handle.net/1853/62641.

MLA Handbook (7th Edition):

Kang, Suk Chan. “Optimizing high locality memory references in cache coherent shared memory multi-core processors.” 2019. Web. 02 Mar 2021.

Vancouver:

Kang SC. Optimizing high locality memory references in cache coherent shared memory multi-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/1853/62641.

Council of Science Editors:

Kang SC. Optimizing high locality memory references in cache coherent shared memory multi-core processors. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62641


University of Minnesota

15. Natarajan, Ragavendra. Leveraging Hardware Support for Transactional Execution To Address Correctness and Performance Challenges in Software.

Degree: PhD, Computer Science, 2015, University of Minnesota

 Improvements in semiconductor technology and computer architecture have led to the proliferation of multicore and many-core processors. In order to improve the performance of multithreaded… (more)

Subjects/Keywords: Hardware Transactional Memory; Memory Consistency Model; System Emulation; Thread Level Speculation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Natarajan, R. (2015). Leveraging Hardware Support for Transactional Execution To Address Correctness and Performance Challenges in Software. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/175274

Chicago Manual of Style (16th Edition):

Natarajan, Ragavendra. “Leveraging Hardware Support for Transactional Execution To Address Correctness and Performance Challenges in Software.” 2015. Doctoral Dissertation, University of Minnesota. Accessed March 02, 2021. http://hdl.handle.net/11299/175274.

MLA Handbook (7th Edition):

Natarajan, Ragavendra. “Leveraging Hardware Support for Transactional Execution To Address Correctness and Performance Challenges in Software.” 2015. Web. 02 Mar 2021.

Vancouver:

Natarajan R. Leveraging Hardware Support for Transactional Execution To Address Correctness and Performance Challenges in Software. [Internet] [Doctoral dissertation]. University of Minnesota; 2015. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/11299/175274.

Council of Science Editors:

Natarajan R. Leveraging Hardware Support for Transactional Execution To Address Correctness and Performance Challenges in Software. [Doctoral Dissertation]. University of Minnesota; 2015. Available from: http://hdl.handle.net/11299/175274

16. Kumar, Pankaj. Analysis of memory architecture of parallel processing computer.

Degree: Computer Science, 2010, Integral University

In modern time the focus of parallel computer development is being shifted from the processor perspective to the memory system perspective. If we will go… (more)

Subjects/Keywords: Parallel Processing System; Computer applications; DSM System; DSM Architecture; Uniform Memory Model; Hybrid Memory Models

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kumar, P. (2010). Analysis of memory architecture of parallel processing computer. (Thesis). Integral University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/3398

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kumar, Pankaj. “Analysis of memory architecture of parallel processing computer.” 2010. Thesis, Integral University. Accessed March 02, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/3398.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kumar, Pankaj. “Analysis of memory architecture of parallel processing computer.” 2010. Web. 02 Mar 2021.

Vancouver:

Kumar P. Analysis of memory architecture of parallel processing computer. [Internet] [Thesis]. Integral University; 2010. [cited 2021 Mar 02]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/3398.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kumar P. Analysis of memory architecture of parallel processing computer. [Thesis]. Integral University; 2010. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/3398

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Nova

17. Martins, Artur Miguel Adriano. Transactional filesystems.

Degree: 2008, Universidade Nova

Dissertação de Mestrado em Engenharia Informática

The task of implementing correct software is not trivial; mainly when facing the need for supporting concurrency. To overcome… (more)

Subjects/Keywords: Transactional file system; File system; Transactional memory; Software transactional memory; Linux; Transactional locking II

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Martins, A. M. A. (2008). Transactional filesystems. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/4193

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Martins, Artur Miguel Adriano. “Transactional filesystems.” 2008. Thesis, Universidade Nova. Accessed March 02, 2021. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/4193.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Martins, Artur Miguel Adriano. “Transactional filesystems.” 2008. Web. 02 Mar 2021.

Vancouver:

Martins AMA. Transactional filesystems. [Internet] [Thesis]. Universidade Nova; 2008. [cited 2021 Mar 02]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/4193.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Martins AMA. Transactional filesystems. [Thesis]. Universidade Nova; 2008. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/4193

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

18. Tseng, Guo-Fu. CDPthread: A POSIX-Thread Based Distributed Computing Environment.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 Due to the limitation of single machineâs computing power, and the aspect of cost, distributed design is getting more and more popular nowadays. The Distributed… (more)

Subjects/Keywords: operating system; distributed system; POSIX; distributed shared memory; thread; multi-thread

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tseng, G. (2009). CDPthread: A POSIX-Thread Based Distributed Computing Environment. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tseng, Guo-Fu. “CDPthread: A POSIX-Thread Based Distributed Computing Environment.” 2009. Thesis, NSYSU. Accessed March 02, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tseng, Guo-Fu. “CDPthread: A POSIX-Thread Based Distributed Computing Environment.” 2009. Web. 02 Mar 2021.

Vancouver:

Tseng G. CDPthread: A POSIX-Thread Based Distributed Computing Environment. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Mar 02]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tseng G. CDPthread: A POSIX-Thread Based Distributed Computing Environment. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728109-115706

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

19. Bonatto, Alexsandro Cristóvão. Controle adaptativo para acesso à memória compartilhada em sistemas em chip.

Degree: 2014, Universidade do Rio Grande do Sul

Acessos simultâneos gerados por Elementos de Processamento (EP) contidos nos Sistemas em Chip (SoC) para um único canal de memória externa coloca desafios que requerem… (more)

Subjects/Keywords: Microeletrônica; Memory subsystem; Circuitos integrados; Integrated circuits; Memory hierarchy; System-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bonatto, A. C. (2014). Controle adaptativo para acesso à memória compartilhada em sistemas em chip. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/109193

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bonatto, Alexsandro Cristóvão. “Controle adaptativo para acesso à memória compartilhada em sistemas em chip.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed March 02, 2021. http://hdl.handle.net/10183/109193.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bonatto, Alexsandro Cristóvão. “Controle adaptativo para acesso à memória compartilhada em sistemas em chip.” 2014. Web. 02 Mar 2021.

Vancouver:

Bonatto AC. Controle adaptativo para acesso à memória compartilhada em sistemas em chip. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10183/109193.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bonatto AC. Controle adaptativo para acesso à memória compartilhada em sistemas em chip. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/109193

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

20. Yang, Jyun-sheng. Design and Implementation of Multi-Port Shared Cache in Multi-core Systems.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Multi-port shared cache memory plays an important role in multi-core systems. Although single/dual-port SRAM can be realized using commercial standard cell library, multi-port shared cache… (more)

Subjects/Keywords: multi-port shared cache memory; multi-port shared cache memory generator; multi-core system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, J. (2016). Design and Implementation of Multi-Port Shared Cache in Multi-core Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Jyun-sheng. “Design and Implementation of Multi-Port Shared Cache in Multi-core Systems.” 2016. Thesis, NSYSU. Accessed March 02, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Jyun-sheng. “Design and Implementation of Multi-Port Shared Cache in Multi-core Systems.” 2016. Web. 02 Mar 2021.

Vancouver:

Yang J. Design and Implementation of Multi-Port Shared Cache in Multi-core Systems. [Internet] [Thesis]. NSYSU; 2016. [cited 2021 Mar 02]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang J. Design and Implementation of Multi-Port Shared Cache in Multi-core Systems. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

21. Papadopoulos, Ioannis. STAPL-RTS: A Runtime System for Massive Parallelism.

Degree: PhD, Computer Science, 2016, Texas A&M University

 Modern High Performance Computing (HPC) systems are complex, with deep memory hierarchies and increasing use of computational heterogeneity via accelerators. When developing applications for these… (more)

Subjects/Keywords: parallel; runtime system; high performance; nested parallelism; asynchronous; shared memory; distributed memory

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Papadopoulos, I. (2016). STAPL-RTS: A Runtime System for Massive Parallelism. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156985

Chicago Manual of Style (16th Edition):

Papadopoulos, Ioannis. “STAPL-RTS: A Runtime System for Massive Parallelism.” 2016. Doctoral Dissertation, Texas A&M University. Accessed March 02, 2021. http://hdl.handle.net/1969.1/156985.

MLA Handbook (7th Edition):

Papadopoulos, Ioannis. “STAPL-RTS: A Runtime System for Massive Parallelism.” 2016. Web. 02 Mar 2021.

Vancouver:

Papadopoulos I. STAPL-RTS: A Runtime System for Massive Parallelism. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/1969.1/156985.

Council of Science Editors:

Papadopoulos I. STAPL-RTS: A Runtime System for Massive Parallelism. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/156985


Georgia Tech

22. Hassan, Syed Minhaj. Exploiting on-chip memory concurrency in 3d manycore architectures.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases… (more)

Subjects/Keywords: 3D memory systems; Network-on-chip; 3D system thermal analysis; Memory-level parallelism; DRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hassan, S. M. (2016). Exploiting on-chip memory concurrency in 3d manycore architectures. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56251

Chicago Manual of Style (16th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Doctoral Dissertation, Georgia Tech. Accessed March 02, 2021. http://hdl.handle.net/1853/56251.

MLA Handbook (7th Edition):

Hassan, Syed Minhaj. “Exploiting on-chip memory concurrency in 3d manycore architectures.” 2016. Web. 02 Mar 2021.

Vancouver:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/1853/56251.

Council of Science Editors:

Hassan SM. Exploiting on-chip memory concurrency in 3d manycore architectures. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56251


Indian Institute of Science

23. Shastry, Vyasa Vikasa. Some Processing and Mechanical Behavior Related Issues in Ti-Ni Based Shape Memory Alloys.

Degree: PhD, Faculty of Engineering, 2017, Indian Institute of Science

 Shape memory alloys (SMAs) exhibit unique combination of structural and functional properties and hence have a variety of current and potential applications. The mechanical behaviour… (more)

Subjects/Keywords: Nickel-Titanium Shape Memory Alloys; Shape Memory Alloys; Nickel-Titanium-Copper Shape Memory Alloys; TiNi Shape Memory Alloys; High Temperature Shape Memory Alloys; Shape Memory Alloys - Mechanical Behavior; Shape Memory Alloys (SMAs); TiNiCu Shape Memory Alloy; TiNi Alloy System; NiTi Shape Memory Alloys; Materials Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shastry, V. V. (2017). Some Processing and Mechanical Behavior Related Issues in Ti-Ni Based Shape Memory Alloys. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/2839

Chicago Manual of Style (16th Edition):

Shastry, Vyasa Vikasa. “Some Processing and Mechanical Behavior Related Issues in Ti-Ni Based Shape Memory Alloys.” 2017. Doctoral Dissertation, Indian Institute of Science. Accessed March 02, 2021. http://etd.iisc.ac.in/handle/2005/2839.

MLA Handbook (7th Edition):

Shastry, Vyasa Vikasa. “Some Processing and Mechanical Behavior Related Issues in Ti-Ni Based Shape Memory Alloys.” 2017. Web. 02 Mar 2021.

Vancouver:

Shastry VV. Some Processing and Mechanical Behavior Related Issues in Ti-Ni Based Shape Memory Alloys. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2017. [cited 2021 Mar 02]. Available from: http://etd.iisc.ac.in/handle/2005/2839.

Council of Science Editors:

Shastry VV. Some Processing and Mechanical Behavior Related Issues in Ti-Ni Based Shape Memory Alloys. [Doctoral Dissertation]. Indian Institute of Science; 2017. Available from: http://etd.iisc.ac.in/handle/2005/2839


NSYSU

24. Chen, Chun-hung. Communication reduction problem in Schur complement method on distributed memory architecture.

Degree: Master, Applied Mathematics, 2018, NSYSU

 A common approach to solving a large sparse linear system in parallel is using the k-way partition method to relabel the variables and equations so… (more)

Subjects/Keywords: large sparse linear system; distributed memory system; k-way partition; Schur complement; parallel computation

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APA (6th Edition):

Chen, C. (2018). Communication reduction problem in Schur complement method on distributed memory architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0030118-154212

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Chun-hung. “Communication reduction problem in Schur complement method on distributed memory architecture.” 2018. Thesis, NSYSU. Accessed March 02, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0030118-154212.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Chun-hung. “Communication reduction problem in Schur complement method on distributed memory architecture.” 2018. Web. 02 Mar 2021.

Vancouver:

Chen C. Communication reduction problem in Schur complement method on distributed memory architecture. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Mar 02]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0030118-154212.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen C. Communication reduction problem in Schur complement method on distributed memory architecture. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0030118-154212

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

25. Fan, Ziqi. Improving Storage Performance with Non-Volatile Memory-based Caching Systems.

Degree: PhD, Computer Science, 2017, University of Minnesota

 With the rapid development of new types of non-volatile memory (NVRAM), e.g., 3D Xpoint, NVDIMM, and STT-MRAM, these technologies have been or will be integrated… (more)

Subjects/Keywords: burst buffer; caching system; non-volatile memory; solid state drive; storage system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fan, Z. (2017). Improving Storage Performance with Non-Volatile Memory-based Caching Systems. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/188840

Chicago Manual of Style (16th Edition):

Fan, Ziqi. “Improving Storage Performance with Non-Volatile Memory-based Caching Systems.” 2017. Doctoral Dissertation, University of Minnesota. Accessed March 02, 2021. http://hdl.handle.net/11299/188840.

MLA Handbook (7th Edition):

Fan, Ziqi. “Improving Storage Performance with Non-Volatile Memory-based Caching Systems.” 2017. Web. 02 Mar 2021.

Vancouver:

Fan Z. Improving Storage Performance with Non-Volatile Memory-based Caching Systems. [Internet] [Doctoral dissertation]. University of Minnesota; 2017. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/11299/188840.

Council of Science Editors:

Fan Z. Improving Storage Performance with Non-Volatile Memory-based Caching Systems. [Doctoral Dissertation]. University of Minnesota; 2017. Available from: http://hdl.handle.net/11299/188840

26. Llull, Qiuyun. Microeconomic Models for Managing Shared Datacenters .

Degree: 2017, Duke University

  As demands for users’ applications’ data increase, the world’s computing platforms are moving towards more capable machines – servers and warehouse-scale datacenters. Diverse users… (more)

Subjects/Keywords: Computer engineering; Computer science; Datacenter; Memory System; Performance Prediction; Resource Allocation; Scheduling; System Management

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Llull, Q. (2017). Microeconomic Models for Managing Shared Datacenters . (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/14447

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Llull, Qiuyun. “Microeconomic Models for Managing Shared Datacenters .” 2017. Thesis, Duke University. Accessed March 02, 2021. http://hdl.handle.net/10161/14447.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Llull, Qiuyun. “Microeconomic Models for Managing Shared Datacenters .” 2017. Web. 02 Mar 2021.

Vancouver:

Llull Q. Microeconomic Models for Managing Shared Datacenters . [Internet] [Thesis]. Duke University; 2017. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10161/14447.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Llull Q. Microeconomic Models for Managing Shared Datacenters . [Thesis]. Duke University; 2017. Available from: http://hdl.handle.net/10161/14447

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

27. Noori, Nader. The symbolic working memory system.

Degree: PhD, Computer Science, 2013, University of Southern California

 The capacity of the brain in maintenance of task-relevant information over a short period of time is known to be crucial for performing a wide… (more)

Subjects/Keywords: working memory; short-term memory; cognition; brain; cognitive neuroscience; symbolic working memory; human brain; intellectual tasks; sensorimotor systems; symbolic intelligence; symbolically intelligent mind; embodied working memory system; grounded working memory system; mental task; memory

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Noori, N. (2013). The symbolic working memory system. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/356011/rec/7345

Chicago Manual of Style (16th Edition):

Noori, Nader. “The symbolic working memory system.” 2013. Doctoral Dissertation, University of Southern California. Accessed March 02, 2021. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/356011/rec/7345.

MLA Handbook (7th Edition):

Noori, Nader. “The symbolic working memory system.” 2013. Web. 02 Mar 2021.

Vancouver:

Noori N. The symbolic working memory system. [Internet] [Doctoral dissertation]. University of Southern California; 2013. [cited 2021 Mar 02]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/356011/rec/7345.

Council of Science Editors:

Noori N. The symbolic working memory system. [Doctoral Dissertation]. University of Southern California; 2013. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/356011/rec/7345


RMIT University

28. Abdullah, E. Control system design for a morphing unmanned air vehicle wing using shape memory alloy actuators.

Degree: 2011, RMIT University

  Morphing wing technology allows modification of aerodynamic behavior of the wing by changing its shape during flight. This can be used to achieve optimum flight… (more)

Subjects/Keywords: Fields of Research; Morphing wing; shape memory alloys; UAV; control system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Abdullah, E. (2011). Control system design for a morphing unmanned air vehicle wing using shape memory alloy actuators. (Thesis). RMIT University. Retrieved from http://researchbank.rmit.edu.au/view/rmit:160043

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Abdullah, E. “Control system design for a morphing unmanned air vehicle wing using shape memory alloy actuators.” 2011. Thesis, RMIT University. Accessed March 02, 2021. http://researchbank.rmit.edu.au/view/rmit:160043.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Abdullah, E. “Control system design for a morphing unmanned air vehicle wing using shape memory alloy actuators.” 2011. Web. 02 Mar 2021.

Vancouver:

Abdullah E. Control system design for a morphing unmanned air vehicle wing using shape memory alloy actuators. [Internet] [Thesis]. RMIT University; 2011. [cited 2021 Mar 02]. Available from: http://researchbank.rmit.edu.au/view/rmit:160043.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Abdullah E. Control system design for a morphing unmanned air vehicle wing using shape memory alloy actuators. [Thesis]. RMIT University; 2011. Available from: http://researchbank.rmit.edu.au/view/rmit:160043

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

29. Liu, Feng-yuan. Implementation of Hierarchical Architecture of Advanced Functionality of Memory Modules.

Degree: Master, Electrical Engineering, 2008, NSYSU

 Due to advancement of semiconductor technology, a system can be designed in a single chip, we call it a system on chip (SOC). An SOC… (more)

Subjects/Keywords: fault tolerant; memory; silicon intellectual properties; system on chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, F. (2008). Implementation of Hierarchical Architecture of Advanced Functionality of Memory Modules. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911108-192726

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Feng-yuan. “Implementation of Hierarchical Architecture of Advanced Functionality of Memory Modules.” 2008. Thesis, NSYSU. Accessed March 02, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911108-192726.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Feng-yuan. “Implementation of Hierarchical Architecture of Advanced Functionality of Memory Modules.” 2008. Web. 02 Mar 2021.

Vancouver:

Liu F. Implementation of Hierarchical Architecture of Advanced Functionality of Memory Modules. [Internet] [Thesis]. NSYSU; 2008. [cited 2021 Mar 02]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911108-192726.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu F. Implementation of Hierarchical Architecture of Advanced Functionality of Memory Modules. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911108-192726

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Otago

30. FU, Yan. Visual Perspective Effects on Action Memory .

Degree: 2014, University of Otago

 This thesis explores neural activity underlying visual perspective taking during action memory encoding and retrieval. The main hypothesis was that frontal regions, particularly those associated… (more)

Subjects/Keywords: action memory; visual perspective; ERP; Mirror Neuron System

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

FU, Y. (2014). Visual Perspective Effects on Action Memory . (Doctoral Dissertation). University of Otago. Retrieved from http://hdl.handle.net/10523/4818

Chicago Manual of Style (16th Edition):

FU, Yan. “Visual Perspective Effects on Action Memory .” 2014. Doctoral Dissertation, University of Otago. Accessed March 02, 2021. http://hdl.handle.net/10523/4818.

MLA Handbook (7th Edition):

FU, Yan. “Visual Perspective Effects on Action Memory .” 2014. Web. 02 Mar 2021.

Vancouver:

FU Y. Visual Perspective Effects on Action Memory . [Internet] [Doctoral dissertation]. University of Otago; 2014. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10523/4818.

Council of Science Editors:

FU Y. Visual Perspective Effects on Action Memory . [Doctoral Dissertation]. University of Otago; 2014. Available from: http://hdl.handle.net/10523/4818

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