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You searched for subject:(Master of Science Electrical AND Computer Engineering College of Engineering AND Architecture 2012 ). Showing records 1 – 30 of 125 total matches.

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1. Vazquez, Enrique Alvarez. Design of an Audio-Visual Display for Cross-Modal Experimentation.

Degree: MS, Electrical and Computer Engineering, 2012, North Dakota State University

 The present paper shows the characteristics of a hardware/software display capable of presenting, at different spatial locations, multiple audio-visual stimuli in real-time. The system has… (more)

Subjects/Keywords: Evoked potentials (Electrophysiology).; Intersensory effects.; Human information processing.; Master of Science / Electrical and Computer Engineering, College of Engineering and Architecture, 2012.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vazquez, E. A. (2012). Design of an Audio-Visual Display for Cross-Modal Experimentation. (Masters Thesis). North Dakota State University. Retrieved from http://hdl.handle.net/10365/21596

Chicago Manual of Style (16th Edition):

Vazquez, Enrique Alvarez. “Design of an Audio-Visual Display for Cross-Modal Experimentation.” 2012. Masters Thesis, North Dakota State University. Accessed April 26, 2018. http://hdl.handle.net/10365/21596.

MLA Handbook (7th Edition):

Vazquez, Enrique Alvarez. “Design of an Audio-Visual Display for Cross-Modal Experimentation.” 2012. Web. 26 Apr 2018.

Vancouver:

Vazquez EA. Design of an Audio-Visual Display for Cross-Modal Experimentation. [Internet] [Masters thesis]. North Dakota State University; 2012. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/10365/21596.

Council of Science Editors:

Vazquez EA. Design of an Audio-Visual Display for Cross-Modal Experimentation. [Masters Thesis]. North Dakota State University; 2012. Available from: http://hdl.handle.net/10365/21596

2. Sharma, Swetha Somshekar. Computer-Aided Microwave Design System (CAMDS): Improvement, Verification, and Device Fabrication.

Degree: MS, Electrical and Computer Engineering, 2012, North Dakota State University

 This paper presents a review of the Computer-Aided Microwave Design System (CAMDS) as originally developed by Divya Bais. Its goal was to deal with microwave… (more)

Subjects/Keywords: Master of Science / Electrical and Computer Engineering, College of Engineering and Architecture, 2012.; Microwave circuits  – Computer-aided design.; Strip transmission lines.; Advanced design system.

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APA (6th Edition):

Sharma, S. S. (2012). Computer-Aided Microwave Design System (CAMDS): Improvement, Verification, and Device Fabrication. (Masters Thesis). North Dakota State University. Retrieved from http://hdl.handle.net/10365/21660

Chicago Manual of Style (16th Edition):

Sharma, Swetha Somshekar. “Computer-Aided Microwave Design System (CAMDS): Improvement, Verification, and Device Fabrication.” 2012. Masters Thesis, North Dakota State University. Accessed April 26, 2018. http://hdl.handle.net/10365/21660.

MLA Handbook (7th Edition):

Sharma, Swetha Somshekar. “Computer-Aided Microwave Design System (CAMDS): Improvement, Verification, and Device Fabrication.” 2012. Web. 26 Apr 2018.

Vancouver:

Sharma SS. Computer-Aided Microwave Design System (CAMDS): Improvement, Verification, and Device Fabrication. [Internet] [Masters thesis]. North Dakota State University; 2012. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/10365/21660.

Council of Science Editors:

Sharma SS. Computer-Aided Microwave Design System (CAMDS): Improvement, Verification, and Device Fabrication. [Masters Thesis]. North Dakota State University; 2012. Available from: http://hdl.handle.net/10365/21660

3. Gopinath, Sushma. Estimating Tau (τ) from Left Ventricular Pressure Waveforms During Vena Caval Occlusions.

Degree: MS, Electrical and Computer Engineering, 2011, North Dakota State University

 Many people are dependent on artificial pacemakers to have a normal cardiac function. Due to this it is important to study the effects of pacing… (more)

Subjects/Keywords: Blood pressure  – Measurement  – Data processing.; Cardiac pacing.; Cardiac pacemakers.; Heart  – Contraction  – Regulation.; MATLAB.; Master of Science / Electrical and Computer Engineering, College of Engineering and Architecture, 2011.

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APA (6th Edition):

Gopinath, S. (2011). Estimating Tau (τ) from Left Ventricular Pressure Waveforms During Vena Caval Occlusions. (Masters Thesis). North Dakota State University. Retrieved from http://hdl.handle.net/10365/19224

Chicago Manual of Style (16th Edition):

Gopinath, Sushma. “Estimating Tau (τ) from Left Ventricular Pressure Waveforms During Vena Caval Occlusions.” 2011. Masters Thesis, North Dakota State University. Accessed April 26, 2018. http://hdl.handle.net/10365/19224.

MLA Handbook (7th Edition):

Gopinath, Sushma. “Estimating Tau (τ) from Left Ventricular Pressure Waveforms During Vena Caval Occlusions.” 2011. Web. 26 Apr 2018.

Vancouver:

Gopinath S. Estimating Tau (τ) from Left Ventricular Pressure Waveforms During Vena Caval Occlusions. [Internet] [Masters thesis]. North Dakota State University; 2011. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/10365/19224.

Council of Science Editors:

Gopinath S. Estimating Tau (τ) from Left Ventricular Pressure Waveforms During Vena Caval Occlusions. [Masters Thesis]. North Dakota State University; 2011. Available from: http://hdl.handle.net/10365/19224

4. Singh, Varinder Pal. Analysis of Power Line Communication Channel Model Using Communication Techniques.

Degree: MS, Electrical and Computer Engineering, 2013, North Dakota State University

 With the advent of technology, human dependency on power (electricity) and communication has grown beyond leaps and bounds. Many efforts have been made to continuously… (more)

Subjects/Keywords: Master of Science / Electrical and Computer Engineering, College of Engineering and Architecture, 2013.; Electric lines  – Carrier transmission.; Smart power grids.; Telecommunication lines.

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APA (6th Edition):

Singh, V. P. (2013). Analysis of Power Line Communication Channel Model Using Communication Techniques. (Masters Thesis). North Dakota State University. Retrieved from http://hdl.handle.net/10365/22737

Chicago Manual of Style (16th Edition):

Singh, Varinder Pal. “Analysis of Power Line Communication Channel Model Using Communication Techniques.” 2013. Masters Thesis, North Dakota State University. Accessed April 26, 2018. http://hdl.handle.net/10365/22737.

MLA Handbook (7th Edition):

Singh, Varinder Pal. “Analysis of Power Line Communication Channel Model Using Communication Techniques.” 2013. Web. 26 Apr 2018.

Vancouver:

Singh VP. Analysis of Power Line Communication Channel Model Using Communication Techniques. [Internet] [Masters thesis]. North Dakota State University; 2013. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/10365/22737.

Council of Science Editors:

Singh VP. Analysis of Power Line Communication Channel Model Using Communication Techniques. [Masters Thesis]. North Dakota State University; 2013. Available from: http://hdl.handle.net/10365/22737


MIT

5. Turakhia, Dishita Girish. Thirteen ways of looking : a theoretical inquiry in computational creative thinking ; Theoretical inquiry in computational creative thinking .

Degree: Department of Electrical Engineering and Computer Science, 2017, MIT

 The vision of this research is to propose a novel computational framework to study Creative Thinking. If we are to embed machines with creative thinking… (more)

Subjects/Keywords: Architecture.; Electrical Engineering and Computer Science.

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APA (6th Edition):

Turakhia, D. G. (2017). Thirteen ways of looking : a theoretical inquiry in computational creative thinking ; Theoretical inquiry in computational creative thinking . (Thesis). MIT. Retrieved from http://hdl.handle.net/1721.1/113918

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Turakhia, Dishita Girish. “Thirteen ways of looking : a theoretical inquiry in computational creative thinking ; Theoretical inquiry in computational creative thinking .” 2017. Thesis, MIT. Accessed April 26, 2018. http://hdl.handle.net/1721.1/113918.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Turakhia, Dishita Girish. “Thirteen ways of looking : a theoretical inquiry in computational creative thinking ; Theoretical inquiry in computational creative thinking .” 2017. Web. 26 Apr 2018.

Vancouver:

Turakhia DG. Thirteen ways of looking : a theoretical inquiry in computational creative thinking ; Theoretical inquiry in computational creative thinking . [Internet] [Thesis]. MIT; 2017. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/1721.1/113918.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Turakhia DG. Thirteen ways of looking : a theoretical inquiry in computational creative thinking ; Theoretical inquiry in computational creative thinking . [Thesis]. MIT; 2017. Available from: http://hdl.handle.net/1721.1/113918

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


MIT

6. Zaman, C̦ağrı Hakan. Hallucination machine : a body centric model of space perception ; Body centric model of space perception .

Degree: Department of Electrical Engineering and Computer Science, 2014, MIT

 In this thesis I present a novel approach to space perception. I provide a body-centric computational model, The Hallucination Machine, that integrates bodily knowledge with… (more)

Subjects/Keywords: Architecture.; Electrical Engineering and Computer Science.

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APA (6th Edition):

Zaman, C. H. (2014). Hallucination machine : a body centric model of space perception ; Body centric model of space perception . (Thesis). MIT. Retrieved from http://hdl.handle.net/1721.1/91425

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zaman, C̦ağrı Hakan. “Hallucination machine : a body centric model of space perception ; Body centric model of space perception .” 2014. Thesis, MIT. Accessed April 26, 2018. http://hdl.handle.net/1721.1/91425.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zaman, C̦ağrı Hakan. “Hallucination machine : a body centric model of space perception ; Body centric model of space perception .” 2014. Web. 26 Apr 2018.

Vancouver:

Zaman CH. Hallucination machine : a body centric model of space perception ; Body centric model of space perception . [Internet] [Thesis]. MIT; 2014. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/1721.1/91425.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zaman CH. Hallucination machine : a body centric model of space perception ; Body centric model of space perception . [Thesis]. MIT; 2014. Available from: http://hdl.handle.net/1721.1/91425

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


MIT

7. Cheng, Chin-Yi. Interactive design process based on augmented intelligence : a framework and toolkit for designers to interact and collaborate with AI algorithms ; Framework and toolkit for designers to interact and collaborate with AI algorithms .

Degree: Department of Electrical Engineering and Computer Science, 2017, MIT

 Designers can use artificial intelligence, such as Genetic Algorithms, to deal with the design problems which seem impossible to be quickly resolved by the human… (more)

Subjects/Keywords: Architecture.; Electrical Engineering and Computer Science.

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APA (6th Edition):

Cheng, C. (2017). Interactive design process based on augmented intelligence : a framework and toolkit for designers to interact and collaborate with AI algorithms ; Framework and toolkit for designers to interact and collaborate with AI algorithms . (Thesis). MIT. Retrieved from http://hdl.handle.net/1721.1/109017

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cheng, Chin-Yi. “Interactive design process based on augmented intelligence : a framework and toolkit for designers to interact and collaborate with AI algorithms ; Framework and toolkit for designers to interact and collaborate with AI algorithms .” 2017. Thesis, MIT. Accessed April 26, 2018. http://hdl.handle.net/1721.1/109017.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cheng, Chin-Yi. “Interactive design process based on augmented intelligence : a framework and toolkit for designers to interact and collaborate with AI algorithms ; Framework and toolkit for designers to interact and collaborate with AI algorithms .” 2017. Web. 26 Apr 2018.

Vancouver:

Cheng C. Interactive design process based on augmented intelligence : a framework and toolkit for designers to interact and collaborate with AI algorithms ; Framework and toolkit for designers to interact and collaborate with AI algorithms . [Internet] [Thesis]. MIT; 2017. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/1721.1/109017.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cheng C. Interactive design process based on augmented intelligence : a framework and toolkit for designers to interact and collaborate with AI algorithms ; Framework and toolkit for designers to interact and collaborate with AI algorithms . [Thesis]. MIT; 2017. Available from: http://hdl.handle.net/1721.1/109017

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


MIT

8. Charidis, Alexandros. Improvisational specification of design spaces .

Degree: Department of Electrical Engineering and Computer Science, 2017, MIT

 As a mathematical abstraction and as a model for automated problem solving, the classical notion of a design space has proven convenient for the sciences… (more)

Subjects/Keywords: Architecture.; Electrical Engineering and Computer Science.

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APA (6th Edition):

Charidis, A. (2017). Improvisational specification of design spaces . (Thesis). MIT. Retrieved from http://hdl.handle.net/1721.1/110867

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Charidis, Alexandros. “Improvisational specification of design spaces .” 2017. Thesis, MIT. Accessed April 26, 2018. http://hdl.handle.net/1721.1/110867.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Charidis, Alexandros. “Improvisational specification of design spaces .” 2017. Web. 26 Apr 2018.

Vancouver:

Charidis A. Improvisational specification of design spaces . [Internet] [Thesis]. MIT; 2017. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/1721.1/110867.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Charidis A. Improvisational specification of design spaces . [Thesis]. MIT; 2017. Available from: http://hdl.handle.net/1721.1/110867

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


MIT

9. Tibbits, Skylar J. E. Logic matter : digital logic as heuristics for physical self-guided-assembly .

Degree: MS, Electrical Engineering and Computer Science, 2010, MIT

 Given the increasing complexity of the physical structures surrounding our everyday environment  – buildings, machines, computers and almost every other physical object that humans interact… (more)

Subjects/Keywords: Architecture.; Electrical Engineering and Computer Science.

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APA (6th Edition):

Tibbits, S. J. E. (2010). Logic matter : digital logic as heuristics for physical self-guided-assembly . (Masters Thesis). MIT. Retrieved from http://hdl.handle.net/1721.1/64566

Chicago Manual of Style (16th Edition):

Tibbits, Skylar J E. “Logic matter : digital logic as heuristics for physical self-guided-assembly .” 2010. Masters Thesis, MIT. Accessed April 26, 2018. http://hdl.handle.net/1721.1/64566.

MLA Handbook (7th Edition):

Tibbits, Skylar J E. “Logic matter : digital logic as heuristics for physical self-guided-assembly .” 2010. Web. 26 Apr 2018.

Vancouver:

Tibbits SJE. Logic matter : digital logic as heuristics for physical self-guided-assembly . [Internet] [Masters thesis]. MIT; 2010. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/1721.1/64566.

Council of Science Editors:

Tibbits SJE. Logic matter : digital logic as heuristics for physical self-guided-assembly . [Masters Thesis]. MIT; 2010. Available from: http://hdl.handle.net/1721.1/64566


UCLA

10. Zhou, Peipei. A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture).

Degree: Electrical Engineering, 2014, UCLA

 Future processor will not be limited by the transistor resources, but will be mainly constrained by energy efficiency. Reconfigurable architecture offers higher energy efficiency than… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; Computer science; CGRA; composable architecture; computer architecture; full pipeline; reconfigurable architecture

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APA (6th Edition):

Zhou, P. (2014). A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture). (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9446s3nx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhou, Peipei. “A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture).” 2014. Thesis, UCLA. Accessed April 26, 2018. http://www.escholarship.org/uc/item/9446s3nx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhou, Peipei. “A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture).” 2014. Web. 26 Apr 2018.

Vancouver:

Zhou P. A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture). [Internet] [Thesis]. UCLA; 2014. [cited 2018 Apr 26]. Available from: http://www.escholarship.org/uc/item/9446s3nx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhou P. A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture). [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/9446s3nx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Irvine

11. Kim, Myoungseo. I/O Design and Core Power Management Issues in Heterogeneous Multi/Many-Core System-on-Chip.

Degree: Computer Science, 2016, University of California – Irvine

 Since dark silicon and the end of multicore scaling, multi/many-core system-on-a-chip (SoC) platform designs nowadays are facing some conflicting issues regarding product development. One is… (more)

Subjects/Keywords: Computer science; Computer engineering; Electrical engineering; Design Automation; Design Efficiency and Power Saving; Extended Amdahl's Law; Heterogeneous System Architecture; Multi/Many-Core System-on-a-Chip; Overhead of Data Preparation

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APA (6th Edition):

Kim, M. (2016). I/O Design and Core Power Management Issues in Heterogeneous Multi/Many-Core System-on-Chip. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/9g80m9bd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Myoungseo. “I/O Design and Core Power Management Issues in Heterogeneous Multi/Many-Core System-on-Chip.” 2016. Thesis, University of California – Irvine. Accessed April 26, 2018. http://www.escholarship.org/uc/item/9g80m9bd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Myoungseo. “I/O Design and Core Power Management Issues in Heterogeneous Multi/Many-Core System-on-Chip.” 2016. Web. 26 Apr 2018.

Vancouver:

Kim M. I/O Design and Core Power Management Issues in Heterogeneous Multi/Many-Core System-on-Chip. [Internet] [Thesis]. University of California – Irvine; 2016. [cited 2018 Apr 26]. Available from: http://www.escholarship.org/uc/item/9g80m9bd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim M. I/O Design and Core Power Management Issues in Heterogeneous Multi/Many-Core System-on-Chip. [Thesis]. University of California – Irvine; 2016. Available from: http://www.escholarship.org/uc/item/9g80m9bd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Duke University

12. Bower, Fred. Technology Impacts of CMOS Scaling on Microprocessor Core Design for Hard-Fault Tolerance in Single-Core Applications and Optimized Throughput in Throughput-Oriented Chip Multiprocessors.

Degree: 2010, Duke University

  The continued march of technological progress, epitomized by Moore’s Law provides the microarchitect with increasing numbers of transistors to employ as we continue to… (more)

Subjects/Keywords: Computer Science; Computer Engineering; Engineering, Electronics and Electrical; architecture; cache; chip multiprocessors; fault tolerance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bower, F. (2010). Technology Impacts of CMOS Scaling on Microprocessor Core Design for Hard-Fault Tolerance in Single-Core Applications and Optimized Throughput in Throughput-Oriented Chip Multiprocessors. (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/2391

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bower, Fred. “Technology Impacts of CMOS Scaling on Microprocessor Core Design for Hard-Fault Tolerance in Single-Core Applications and Optimized Throughput in Throughput-Oriented Chip Multiprocessors.” 2010. Thesis, Duke University. Accessed April 26, 2018. http://hdl.handle.net/10161/2391.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bower, Fred. “Technology Impacts of CMOS Scaling on Microprocessor Core Design for Hard-Fault Tolerance in Single-Core Applications and Optimized Throughput in Throughput-Oriented Chip Multiprocessors.” 2010. Web. 26 Apr 2018.

Vancouver:

Bower F. Technology Impacts of CMOS Scaling on Microprocessor Core Design for Hard-Fault Tolerance in Single-Core Applications and Optimized Throughput in Throughput-Oriented Chip Multiprocessors. [Internet] [Thesis]. Duke University; 2010. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/10161/2391.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bower F. Technology Impacts of CMOS Scaling on Microprocessor Core Design for Hard-Fault Tolerance in Single-Core Applications and Optimized Throughput in Throughput-Oriented Chip Multiprocessors. [Thesis]. Duke University; 2010. Available from: http://hdl.handle.net/10161/2391

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

13. Feng, Shuguang. Delivering Affordable Fault-tolerance to Commodity Computer Systems.

Degree: PhD, Computer Science & Engineering, 2011, University of Michigan

 To meet an insatiable consumer demand for greater performance at less power, silicon technology has scaled to unprecedented dimensions. This aggressive scaling has provided designers… (more)

Subjects/Keywords: Fault Tolerant Computing; Computer Architecture; Compiler Analysis; Computer Science; Electrical Engineering; Engineering

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APA (6th Edition):

Feng, S. (2011). Delivering Affordable Fault-tolerance to Commodity Computer Systems. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86483

Chicago Manual of Style (16th Edition):

Feng, Shuguang. “Delivering Affordable Fault-tolerance to Commodity Computer Systems.” 2011. Doctoral Dissertation, University of Michigan. Accessed April 26, 2018. http://hdl.handle.net/2027.42/86483.

MLA Handbook (7th Edition):

Feng, Shuguang. “Delivering Affordable Fault-tolerance to Commodity Computer Systems.” 2011. Web. 26 Apr 2018.

Vancouver:

Feng S. Delivering Affordable Fault-tolerance to Commodity Computer Systems. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/2027.42/86483.

Council of Science Editors:

Feng S. Delivering Affordable Fault-tolerance to Commodity Computer Systems. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86483


University of Central Florida

14. Dimitrov, Martin. Architectural Support For Improving System Hardware/software Reliability.

Degree: 2010, University of Central Florida

 It is a great challenge to build reliable computer systems with unreliable hardware and buggy software. On one hand, software bugs account for as much… (more)

Subjects/Keywords: Computer architecture; Computers  – Reliability; Debugging in computer science; Electrical and Computer Engineering; Electrical and Electronics; Engineering; Dissertations, Academic  – Engineering and Computer Science, Engineering and Computer Science  – Dissertations, Academic

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APA (6th Edition):

Dimitrov, M. (2010). Architectural Support For Improving System Hardware/software Reliability. (Doctoral Dissertation). University of Central Florida. Retrieved from http://stars.library.ucf.edu/etd/1524

Chicago Manual of Style (16th Edition):

Dimitrov, Martin. “Architectural Support For Improving System Hardware/software Reliability.” 2010. Doctoral Dissertation, University of Central Florida. Accessed April 26, 2018. http://stars.library.ucf.edu/etd/1524.

MLA Handbook (7th Edition):

Dimitrov, Martin. “Architectural Support For Improving System Hardware/software Reliability.” 2010. Web. 26 Apr 2018.

Vancouver:

Dimitrov M. Architectural Support For Improving System Hardware/software Reliability. [Internet] [Doctoral dissertation]. University of Central Florida; 2010. [cited 2018 Apr 26]. Available from: http://stars.library.ucf.edu/etd/1524.

Council of Science Editors:

Dimitrov M. Architectural Support For Improving System Hardware/software Reliability. [Doctoral Dissertation]. University of Central Florida; 2010. Available from: http://stars.library.ucf.edu/etd/1524


University of California – Berkeley

15. Jiang, Xiaofan. A High-Fidelity Energy Monitoring and Feedback Architecture for Reducing Electrical Consumption in Buildings.

Degree: Computer Science, 2010, University of California – Berkeley

 Existing solutions in commercial building energy monitoring are insufficient in identifying energy waste or for guiding improvement. This is because they only provide usage statistics… (more)

Subjects/Keywords: Computer Science; Electrical Engineering; architecture; building; energy; power; sensor network; wireless

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jiang, X. (2010). A High-Fidelity Energy Monitoring and Feedback Architecture for Reducing Electrical Consumption in Buildings. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/7wg8q9vd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jiang, Xiaofan. “A High-Fidelity Energy Monitoring and Feedback Architecture for Reducing Electrical Consumption in Buildings.” 2010. Thesis, University of California – Berkeley. Accessed April 26, 2018. http://www.escholarship.org/uc/item/7wg8q9vd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jiang, Xiaofan. “A High-Fidelity Energy Monitoring and Feedback Architecture for Reducing Electrical Consumption in Buildings.” 2010. Web. 26 Apr 2018.

Vancouver:

Jiang X. A High-Fidelity Energy Monitoring and Feedback Architecture for Reducing Electrical Consumption in Buildings. [Internet] [Thesis]. University of California – Berkeley; 2010. [cited 2018 Apr 26]. Available from: http://www.escholarship.org/uc/item/7wg8q9vd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jiang X. A High-Fidelity Energy Monitoring and Feedback Architecture for Reducing Electrical Consumption in Buildings. [Thesis]. University of California – Berkeley; 2010. Available from: http://www.escholarship.org/uc/item/7wg8q9vd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Irvine

16. Harris, Christopher Bryant. Generating Formal Verification Properties from Natural Language Hardware Specifications.

Degree: Electrical and Computer Engineering, 2015, University of California – Irvine

 Verification of modern digital systems can consume up to 70% of the design cycle. Verification engineers must create formal properties which reflect correct operation from… (more)

Subjects/Keywords: Computer engineering; Electrical engineering; Computer science; Assertion Based Verification; Computer Architecture; Electronic Design Automation; Formal Verification; Natural Language Processing

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APA (6th Edition):

Harris, C. B. (2015). Generating Formal Verification Properties from Natural Language Hardware Specifications. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/11d7k48g

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harris, Christopher Bryant. “Generating Formal Verification Properties from Natural Language Hardware Specifications.” 2015. Thesis, University of California – Irvine. Accessed April 26, 2018. http://www.escholarship.org/uc/item/11d7k48g.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harris, Christopher Bryant. “Generating Formal Verification Properties from Natural Language Hardware Specifications.” 2015. Web. 26 Apr 2018.

Vancouver:

Harris CB. Generating Formal Verification Properties from Natural Language Hardware Specifications. [Internet] [Thesis]. University of California – Irvine; 2015. [cited 2018 Apr 26]. Available from: http://www.escholarship.org/uc/item/11d7k48g.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harris CB. Generating Formal Verification Properties from Natural Language Hardware Specifications. [Thesis]. University of California – Irvine; 2015. Available from: http://www.escholarship.org/uc/item/11d7k48g

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

17. Gottscho, Mark William. Opportunistic Memory Systems in Presence of Hardware Variability.

Degree: Electrical Engineering, 2017, UCLA

 The memory system presents many problems in computer architecture and system design. An important challenge is worsening hardware variability that is caused by nanometer-scale manufacturing… (more)

Subjects/Keywords: Computer engineering; Electrical engineering; Computer science; computer architecture; error-correcting codes; hardware/software interface; memory systems; reliability; variation-aware

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APA (6th Edition):

Gottscho, M. W. (2017). Opportunistic Memory Systems in Presence of Hardware Variability. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/85c1r1q9

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gottscho, Mark William. “Opportunistic Memory Systems in Presence of Hardware Variability.” 2017. Thesis, UCLA. Accessed April 26, 2018. http://www.escholarship.org/uc/item/85c1r1q9.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gottscho, Mark William. “Opportunistic Memory Systems in Presence of Hardware Variability.” 2017. Web. 26 Apr 2018.

Vancouver:

Gottscho MW. Opportunistic Memory Systems in Presence of Hardware Variability. [Internet] [Thesis]. UCLA; 2017. [cited 2018 Apr 26]. Available from: http://www.escholarship.org/uc/item/85c1r1q9.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gottscho MW. Opportunistic Memory Systems in Presence of Hardware Variability. [Thesis]. UCLA; 2017. Available from: http://www.escholarship.org/uc/item/85c1r1q9

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


McMaster University

18. Ko, Ho Fai. New Algorithms and Architectures for Post-Silicon Validation.

Degree: PhD, 2009, McMaster University

  To identify design errors that escape pre-silicon verification, post-silicon validation is becoming an important step in the implementation fl.ow of digital integrated circuits. While… (more)

Subjects/Keywords: electrical and computer engineering; algorithm; architecture; silicon

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APA (6th Edition):

Ko, H. F. (2009). New Algorithms and Architectures for Post-Silicon Validation. (Doctoral Dissertation). McMaster University. Retrieved from http://hdl.handle.net/11375/17342

Chicago Manual of Style (16th Edition):

Ko, Ho Fai. “New Algorithms and Architectures for Post-Silicon Validation.” 2009. Doctoral Dissertation, McMaster University. Accessed April 26, 2018. http://hdl.handle.net/11375/17342.

MLA Handbook (7th Edition):

Ko, Ho Fai. “New Algorithms and Architectures for Post-Silicon Validation.” 2009. Web. 26 Apr 2018.

Vancouver:

Ko HF. New Algorithms and Architectures for Post-Silicon Validation. [Internet] [Doctoral dissertation]. McMaster University; 2009. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/11375/17342.

Council of Science Editors:

Ko HF. New Algorithms and Architectures for Post-Silicon Validation. [Doctoral Dissertation]. McMaster University; 2009. Available from: http://hdl.handle.net/11375/17342


MIT

19. Rafiuly, Paul, 1976-. Minimizing electricity costs with an auxiliary generator using stochastic programming .

Degree: MS, Electrical Engineering and Computer Science, 2000, MIT

 This thesis addresses the problem of minimizing a facility's electricity costs by generating optimal responses using an auxiliary generator as the parameter of the control… (more)

Subjects/Keywords: Architecture.; Electrical Engineering and Computer Science.

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APA (6th Edition):

Rafiuly, Paul, 1. (2000). Minimizing electricity costs with an auxiliary generator using stochastic programming . (Masters Thesis). MIT. Retrieved from http://hdl.handle.net/1721.1/69428

Chicago Manual of Style (16th Edition):

Rafiuly, Paul, 1976-. “Minimizing electricity costs with an auxiliary generator using stochastic programming .” 2000. Masters Thesis, MIT. Accessed April 26, 2018. http://hdl.handle.net/1721.1/69428.

MLA Handbook (7th Edition):

Rafiuly, Paul, 1976-. “Minimizing electricity costs with an auxiliary generator using stochastic programming .” 2000. Web. 26 Apr 2018.

Vancouver:

Rafiuly, Paul 1. Minimizing electricity costs with an auxiliary generator using stochastic programming . [Internet] [Masters thesis]. MIT; 2000. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/1721.1/69428.

Council of Science Editors:

Rafiuly, Paul 1. Minimizing electricity costs with an auxiliary generator using stochastic programming . [Masters Thesis]. MIT; 2000. Available from: http://hdl.handle.net/1721.1/69428


MIT

20. Papazian, Pegor H. (Pegor Hratch). Principles, opportunism and seeing in design : a computational approach .

Degree: MS, Electrical Engineering and Computer Science, 1991, MIT

 This thesis introduces elements of a theory of design activity and a computational framework for developing design systems. The theory stresses the opportunistic nature of… (more)

Subjects/Keywords: Architecture.; Electrical Engineering and Computer Science.

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APA (6th Edition):

Papazian, P. H. (. H. (1991). Principles, opportunism and seeing in design : a computational approach . (Masters Thesis). MIT. Retrieved from http://hdl.handle.net/1721.1/69534

Chicago Manual of Style (16th Edition):

Papazian, Pegor H (Pegor Hratch). “Principles, opportunism and seeing in design : a computational approach .” 1991. Masters Thesis, MIT. Accessed April 26, 2018. http://hdl.handle.net/1721.1/69534.

MLA Handbook (7th Edition):

Papazian, Pegor H (Pegor Hratch). “Principles, opportunism and seeing in design : a computational approach .” 1991. Web. 26 Apr 2018.

Vancouver:

Papazian PH(H. Principles, opportunism and seeing in design : a computational approach . [Internet] [Masters thesis]. MIT; 1991. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/1721.1/69534.

Council of Science Editors:

Papazian PH(H. Principles, opportunism and seeing in design : a computational approach . [Masters Thesis]. MIT; 1991. Available from: http://hdl.handle.net/1721.1/69534

21. Pohajda, Andrej. PRENOVA TEHNIŠKIH FAKULTET V MARIBORU.

Degree: 2015, Univerza v Mariboru

Magistrsko delo ponuja rešitve za potrebno prenovo tehničnih fakultet v Mariboru, ki vključujejo prenovo fasad, gradnjo fleksibilnih prostorov in ureditev dvorišč. Analiza obstoječih stavb fakultet… (more)

Subjects/Keywords: Maribor; Tehniške fakultete v Mariboru; Prenova; Dograditev; Fakulteta za gradbeništvo prometno inženirstvo in arhitekturo; Fakulteta za kemijo in kemijsko tehnologijo; Fakulteta za strojništvo; Fakulteta za elektrotehniko računalništvo in informatiko; Maribor; Technical faculties in Maribor; Renovation; Upgrading; Faculty of Civil Engineering Transport Engineering and Architecture; Faculty of Chemistry and Chemical Technology; Faculty of Mechanical Engineering; Faculty of Electrical Engineering and Computer Science; info:eu-repo/classification/udc/365.644(043.2)

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APA (6th Edition):

Pohajda, A. (2015). PRENOVA TEHNIŠKIH FAKULTET V MARIBORU. (Masters Thesis). Univerza v Mariboru. Retrieved from https://dk.um.si/IzpisGradiva.php?id=55183 ; https://dk.um.si/Dokument.php?id=82645&dn= ; http://www.cobiss.si/scripts/cobiss?command=DISPLAY&base=cobib&rid=19169814&fmt=11

Chicago Manual of Style (16th Edition):

Pohajda, Andrej. “PRENOVA TEHNIŠKIH FAKULTET V MARIBORU.” 2015. Masters Thesis, Univerza v Mariboru. Accessed April 26, 2018. https://dk.um.si/IzpisGradiva.php?id=55183 ; https://dk.um.si/Dokument.php?id=82645&dn= ; http://www.cobiss.si/scripts/cobiss?command=DISPLAY&base=cobib&rid=19169814&fmt=11.

MLA Handbook (7th Edition):

Pohajda, Andrej. “PRENOVA TEHNIŠKIH FAKULTET V MARIBORU.” 2015. Web. 26 Apr 2018.

Vancouver:

Pohajda A. PRENOVA TEHNIŠKIH FAKULTET V MARIBORU. [Internet] [Masters thesis]. Univerza v Mariboru; 2015. [cited 2018 Apr 26]. Available from: https://dk.um.si/IzpisGradiva.php?id=55183 ; https://dk.um.si/Dokument.php?id=82645&dn= ; http://www.cobiss.si/scripts/cobiss?command=DISPLAY&base=cobib&rid=19169814&fmt=11.

Council of Science Editors:

Pohajda A. PRENOVA TEHNIŠKIH FAKULTET V MARIBORU. [Masters Thesis]. Univerza v Mariboru; 2015. Available from: https://dk.um.si/IzpisGradiva.php?id=55183 ; https://dk.um.si/Dokument.php?id=82645&dn= ; http://www.cobiss.si/scripts/cobiss?command=DISPLAY&base=cobib&rid=19169814&fmt=11


Portland State University

22. Jothi, Komal. Dynamic Task Prediction for an SpMT Architecture Based on Control Independence.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2009, Portland State University

  Exploiting better performance from computer programs translates to finding more instructions to execute in parallel. Since most general purpose programs are written in an… (more)

Subjects/Keywords: Computer architecture; Parallel programming (Computer science); Microprocessors  – Programming; Simultaneous multithreading processors; Microprocessors  – Design and construction; Threads (Computer programs); Computer and Systems Architecture; Electrical and Computer Engineering

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APA (6th Edition):

Jothi, K. (2009). Dynamic Task Prediction for an SpMT Architecture Based on Control Independence. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/1707

Chicago Manual of Style (16th Edition):

Jothi, Komal. “Dynamic Task Prediction for an SpMT Architecture Based on Control Independence.” 2009. Masters Thesis, Portland State University. Accessed April 26, 2018. https://pdxscholar.library.pdx.edu/open_access_etds/1707.

MLA Handbook (7th Edition):

Jothi, Komal. “Dynamic Task Prediction for an SpMT Architecture Based on Control Independence.” 2009. Web. 26 Apr 2018.

Vancouver:

Jothi K. Dynamic Task Prediction for an SpMT Architecture Based on Control Independence. [Internet] [Masters thesis]. Portland State University; 2009. [cited 2018 Apr 26]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/1707.

Council of Science Editors:

Jothi K. Dynamic Task Prediction for an SpMT Architecture Based on Control Independence. [Masters Thesis]. Portland State University; 2009. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/1707


University of Central Florida

23. Wang, Ping. The Next Generation Botnet Attacks And Defenses.

Degree: 2010, University of Central Florida

 A “botnet” is a network of compromised computers (bots) that are controlled by an attacker (botmasters). Botnets are one of the most serious threats to… (more)

Subjects/Keywords: Computer networks  – Security measures; Computer security; Peer to peer architecture (Computer networks); Electrical and Computer Engineering; Electrical and Electronics; Engineering; Dissertations, Academic  – Engineering and Computer Science, Engineering and Computer Science  – Dissertations, Academic

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APA (6th Edition):

Wang, P. (2010). The Next Generation Botnet Attacks And Defenses. (Doctoral Dissertation). University of Central Florida. Retrieved from http://stars.library.ucf.edu/etd/1693

Chicago Manual of Style (16th Edition):

Wang, Ping. “The Next Generation Botnet Attacks And Defenses.” 2010. Doctoral Dissertation, University of Central Florida. Accessed April 26, 2018. http://stars.library.ucf.edu/etd/1693.

MLA Handbook (7th Edition):

Wang, Ping. “The Next Generation Botnet Attacks And Defenses.” 2010. Web. 26 Apr 2018.

Vancouver:

Wang P. The Next Generation Botnet Attacks And Defenses. [Internet] [Doctoral dissertation]. University of Central Florida; 2010. [cited 2018 Apr 26]. Available from: http://stars.library.ucf.edu/etd/1693.

Council of Science Editors:

Wang P. The Next Generation Botnet Attacks And Defenses. [Doctoral Dissertation]. University of Central Florida; 2010. Available from: http://stars.library.ucf.edu/etd/1693

24. Ahsan, Muhammad. Architecture Framework for Trapped-ion Quantum Computer based on Performance Simulation Tool.

Degree: 2015, Duke University

  The challenge of building scalable quantum computer lies in striking appropriate balance between designing a reliable system architecture from large number of faulty computational… (more)

Subjects/Keywords: Computer science; Electrical engineering; Physics; analysis Shor's algorithm; performance simulation tool; quantum architecture; quantum CAD; quantum computer design space; quantum computing

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APA (6th Edition):

Ahsan, M. (2015). Architecture Framework for Trapped-ion Quantum Computer based on Performance Simulation Tool. (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/10461

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ahsan, Muhammad. “Architecture Framework for Trapped-ion Quantum Computer based on Performance Simulation Tool.” 2015. Thesis, Duke University. Accessed April 26, 2018. http://hdl.handle.net/10161/10461.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ahsan, Muhammad. “Architecture Framework for Trapped-ion Quantum Computer based on Performance Simulation Tool.” 2015. Web. 26 Apr 2018.

Vancouver:

Ahsan M. Architecture Framework for Trapped-ion Quantum Computer based on Performance Simulation Tool. [Internet] [Thesis]. Duke University; 2015. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/10161/10461.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ahsan M. Architecture Framework for Trapped-ion Quantum Computer based on Performance Simulation Tool. [Thesis]. Duke University; 2015. Available from: http://hdl.handle.net/10161/10461

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


MIT

25. Anderson, Thomas Lee. The design of a multiprocessor development system .

Degree: MS, Electrical Engineering and Computer Science, 1982, MIT

Subjects/Keywords: Electrical Engineering and Computer Science.; Computer architecture; Multiprocessors

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APA (6th Edition):

Anderson, T. L. (1982). The design of a multiprocessor development system . (Masters Thesis). MIT. Retrieved from http://hdl.handle.net/1721.1/15750

Chicago Manual of Style (16th Edition):

Anderson, Thomas Lee. “The design of a multiprocessor development system .” 1982. Masters Thesis, MIT. Accessed April 26, 2018. http://hdl.handle.net/1721.1/15750.

MLA Handbook (7th Edition):

Anderson, Thomas Lee. “The design of a multiprocessor development system .” 1982. Web. 26 Apr 2018.

Vancouver:

Anderson TL. The design of a multiprocessor development system . [Internet] [Masters thesis]. MIT; 1982. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/1721.1/15750.

Council of Science Editors:

Anderson TL. The design of a multiprocessor development system . [Masters Thesis]. MIT; 1982. Available from: http://hdl.handle.net/1721.1/15750


Arizona State University

26. Mackay, Curtis Alexander. The Feasibility of Domain Specific Compilation for Spatially Programmable Architectures.

Degree: Masters, Thesis Electrical Engineering, 2016, Arizona State University

 Integrated circuits must be energy efficient. This efficiency affects all aspects of chip design, from the battery life of embedded devices to thermal heating on… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; compiler; domain efficiency; energy efficiency; spatial architecture

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APA (6th Edition):

Mackay, C. A. (2016). The Feasibility of Domain Specific Compilation for Spatially Programmable Architectures. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/40332

Chicago Manual of Style (16th Edition):

Mackay, Curtis Alexander. “The Feasibility of Domain Specific Compilation for Spatially Programmable Architectures.” 2016. Masters Thesis, Arizona State University. Accessed April 26, 2018. http://repository.asu.edu/items/40332.

MLA Handbook (7th Edition):

Mackay, Curtis Alexander. “The Feasibility of Domain Specific Compilation for Spatially Programmable Architectures.” 2016. Web. 26 Apr 2018.

Vancouver:

Mackay CA. The Feasibility of Domain Specific Compilation for Spatially Programmable Architectures. [Internet] [Masters thesis]. Arizona State University; 2016. [cited 2018 Apr 26]. Available from: http://repository.asu.edu/items/40332.

Council of Science Editors:

Mackay CA. The Feasibility of Domain Specific Compilation for Spatially Programmable Architectures. [Masters Thesis]. Arizona State University; 2016. Available from: http://repository.asu.edu/items/40332


California State University – Northridge

27. Malekal, Karthik Venkatesh. Implementation of memory efficient IP lookup architecture.

Degree: MS, Department of Elec & Comp Engr, 2014, California State University – Northridge

 The internet today has grown into a vast network of networks. It consists of a large number of smaller networks connecting millions of users together… (more)

Subjects/Keywords: IP Lookup architecture; Dissertations, Academic  – CSUN  – Engineering  – Electrical and Computer Engineering.

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APA (6th Edition):

Malekal, K. V. (2014). Implementation of memory efficient IP lookup architecture. (Masters Thesis). California State University – Northridge. Retrieved from http://hdl.handle.net/10211.3/121802

Chicago Manual of Style (16th Edition):

Malekal, Karthik Venkatesh. “Implementation of memory efficient IP lookup architecture.” 2014. Masters Thesis, California State University – Northridge. Accessed April 26, 2018. http://hdl.handle.net/10211.3/121802.

MLA Handbook (7th Edition):

Malekal, Karthik Venkatesh. “Implementation of memory efficient IP lookup architecture.” 2014. Web. 26 Apr 2018.

Vancouver:

Malekal KV. Implementation of memory efficient IP lookup architecture. [Internet] [Masters thesis]. California State University – Northridge; 2014. [cited 2018 Apr 26]. Available from: http://hdl.handle.net/10211.3/121802.

Council of Science Editors:

Malekal KV. Implementation of memory efficient IP lookup architecture. [Masters Thesis]. California State University – Northridge; 2014. Available from: http://hdl.handle.net/10211.3/121802


Portland State University

28. Woods, Walt. The Design of a Simple, Spiking Sparse Coding Algorithm for Memristive Hardware.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2016, Portland State University

  Calculating a sparse code for signals with high dimensionality, such as high-resolution images, takes substantial time to compute on a traditional computer architecture. Memristors… (more)

Subjects/Keywords: Computer architecture  – Design; Computer architecture  – Evaluation; Associative storage  – Design; Memristors; Electrical and Computer Engineering

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APA (6th Edition):

Woods, W. (2016). The Design of a Simple, Spiking Sparse Coding Algorithm for Memristive Hardware. (Masters Thesis). Portland State University. Retrieved from http://pdxscholar.library.pdx.edu/open_access_etds/2721

Chicago Manual of Style (16th Edition):

Woods, Walt. “The Design of a Simple, Spiking Sparse Coding Algorithm for Memristive Hardware.” 2016. Masters Thesis, Portland State University. Accessed April 26, 2018. http://pdxscholar.library.pdx.edu/open_access_etds/2721.

MLA Handbook (7th Edition):

Woods, Walt. “The Design of a Simple, Spiking Sparse Coding Algorithm for Memristive Hardware.” 2016. Web. 26 Apr 2018.

Vancouver:

Woods W. The Design of a Simple, Spiking Sparse Coding Algorithm for Memristive Hardware. [Internet] [Masters thesis]. Portland State University; 2016. [cited 2018 Apr 26]. Available from: http://pdxscholar.library.pdx.edu/open_access_etds/2721.

Council of Science Editors:

Woods W. The Design of a Simple, Spiking Sparse Coding Algorithm for Memristive Hardware. [Masters Thesis]. Portland State University; 2016. Available from: http://pdxscholar.library.pdx.edu/open_access_etds/2721


Portland State University

29. Rahman, Kamela Choudhury. Complete Design Methodology of a Massively Parallel and Pipelined Memristive Stateful IMPLY Logic Based Reconfigurable Architecture.

Degree: PhD, Electrical and Computer Engineering, 2016, Portland State University

  Continued dimensional scaling of CMOS processes is approaching fundamental limits and therefore, alternate new devices and microarchitectures are explored to address the growing need… (more)

Subjects/Keywords: Memristors; Computer architecture  – Design; Computer architecture  – Evaluation; Electrical and Computer Engineering; Nanoscience and Nanotechnology

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APA (6th Edition):

Rahman, K. C. (2016). Complete Design Methodology of a Massively Parallel and Pipelined Memristive Stateful IMPLY Logic Based Reconfigurable Architecture. (Doctoral Dissertation). Portland State University. Retrieved from http://pdxscholar.library.pdx.edu/open_access_etds/2956

Chicago Manual of Style (16th Edition):

Rahman, Kamela Choudhury. “Complete Design Methodology of a Massively Parallel and Pipelined Memristive Stateful IMPLY Logic Based Reconfigurable Architecture.” 2016. Doctoral Dissertation, Portland State University. Accessed April 26, 2018. http://pdxscholar.library.pdx.edu/open_access_etds/2956.

MLA Handbook (7th Edition):

Rahman, Kamela Choudhury. “Complete Design Methodology of a Massively Parallel and Pipelined Memristive Stateful IMPLY Logic Based Reconfigurable Architecture.” 2016. Web. 26 Apr 2018.

Vancouver:

Rahman KC. Complete Design Methodology of a Massively Parallel and Pipelined Memristive Stateful IMPLY Logic Based Reconfigurable Architecture. [Internet] [Doctoral dissertation]. Portland State University; 2016. [cited 2018 Apr 26]. Available from: http://pdxscholar.library.pdx.edu/open_access_etds/2956.

Council of Science Editors:

Rahman KC. Complete Design Methodology of a Massively Parallel and Pipelined Memristive Stateful IMPLY Logic Based Reconfigurable Architecture. [Doctoral Dissertation]. Portland State University; 2016. Available from: http://pdxscholar.library.pdx.edu/open_access_etds/2956


Utah State University

30. Chen, Hu. Exploiting Adaptive Techniques to Improve Processor Energy Efficiency.

Degree: PhD, Electrical and Computer Engineering, 2016, Utah State University

  Rapid device-miniaturization keeps on inducing challenges in building energy efficient microprocessors. As the size of the transistors continuously decreasing, more uncertainties emerge in their… (more)

Subjects/Keywords: Computer Architecture; Energy Efficiency; Adaptive Techniques; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, H. (2016). Exploiting Adaptive Techniques to Improve Processor Energy Efficiency. (Doctoral Dissertation). Utah State University. Retrieved from http://digitalcommons.usu.edu/etd/4985

Chicago Manual of Style (16th Edition):

Chen, Hu. “Exploiting Adaptive Techniques to Improve Processor Energy Efficiency.” 2016. Doctoral Dissertation, Utah State University. Accessed April 26, 2018. http://digitalcommons.usu.edu/etd/4985.

MLA Handbook (7th Edition):

Chen, Hu. “Exploiting Adaptive Techniques to Improve Processor Energy Efficiency.” 2016. Web. 26 Apr 2018.

Vancouver:

Chen H. Exploiting Adaptive Techniques to Improve Processor Energy Efficiency. [Internet] [Doctoral dissertation]. Utah State University; 2016. [cited 2018 Apr 26]. Available from: http://digitalcommons.usu.edu/etd/4985.

Council of Science Editors:

Chen H. Exploiting Adaptive Techniques to Improve Processor Energy Efficiency. [Doctoral Dissertation]. Utah State University; 2016. Available from: http://digitalcommons.usu.edu/etd/4985

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