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You searched for subject:(Many core). Showing records 1 – 30 of 96 total matches.

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University of Minnesota

1. Venkataraman, Hariharasudhan. Supporting Sequential Consistency through Ordered Network in Many-Core Systems.

Degree: M.S.E.E., Computer Engineering, 2017, University of Minnesota

 Recently, there are two trends in parallel computing. On one hand, emerging workloads have exhibited significant data-level parallelism; on the other hand, modern processors are… (more)

Subjects/Keywords: Many Core System; Sequential Consistency

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APA (6th Edition):

Venkataraman, H. (2017). Supporting Sequential Consistency through Ordered Network in Many-Core Systems. (Masters Thesis). University of Minnesota. Retrieved from http://hdl.handle.net/11299/194668

Chicago Manual of Style (16th Edition):

Venkataraman, Hariharasudhan. “Supporting Sequential Consistency through Ordered Network in Many-Core Systems.” 2017. Masters Thesis, University of Minnesota. Accessed December 09, 2019. http://hdl.handle.net/11299/194668.

MLA Handbook (7th Edition):

Venkataraman, Hariharasudhan. “Supporting Sequential Consistency through Ordered Network in Many-Core Systems.” 2017. Web. 09 Dec 2019.

Vancouver:

Venkataraman H. Supporting Sequential Consistency through Ordered Network in Many-Core Systems. [Internet] [Masters thesis]. University of Minnesota; 2017. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/11299/194668.

Council of Science Editors:

Venkataraman H. Supporting Sequential Consistency through Ordered Network in Many-Core Systems. [Masters Thesis]. University of Minnesota; 2017. Available from: http://hdl.handle.net/11299/194668


University of Southern California

2. Peng, Liu. Parallelization framework for scientific application kernels on multi-core/many-core platforms.

Degree: PhD, Computer Science, 2011, University of Southern California

 The advent of multi-core/many-core paradigm has provided unprecedented computing power, and it is of great significance to develop a parallelization framework for various scientific applications… (more)

Subjects/Keywords: multi/many core; parallel computing; scientific simulation

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APA (6th Edition):

Peng, L. (2011). Parallelization framework for scientific application kernels on multi-core/many-core platforms. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/624895/rec/4910

Chicago Manual of Style (16th Edition):

Peng, Liu. “Parallelization framework for scientific application kernels on multi-core/many-core platforms.” 2011. Doctoral Dissertation, University of Southern California. Accessed December 09, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/624895/rec/4910.

MLA Handbook (7th Edition):

Peng, Liu. “Parallelization framework for scientific application kernels on multi-core/many-core platforms.” 2011. Web. 09 Dec 2019.

Vancouver:

Peng L. Parallelization framework for scientific application kernels on multi-core/many-core platforms. [Internet] [Doctoral dissertation]. University of Southern California; 2011. [cited 2019 Dec 09]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/624895/rec/4910.

Council of Science Editors:

Peng L. Parallelization framework for scientific application kernels on multi-core/many-core platforms. [Doctoral Dissertation]. University of Southern California; 2011. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/624895/rec/4910


Universitat Autònoma de Barcelona

3. Fernandez Alonso, Eduard. Offloading Techniques to Improve Performance on MPI Applications in NoC-Based MPSoCs.

Degree: Departament de Ciències de la Computació, 2014, Universitat Autònoma de Barcelona

 Future embedded System-on-Chip (SoC) will probably be made up of tens or hundreds of heterogeneous Intellectual Properties (IP) cores, which will execute one parallel application… (more)

Subjects/Keywords: Many-core; FPGA; Parallel programming; Tecnologies; 519.1

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APA (6th Edition):

Fernandez Alonso, E. (2014). Offloading Techniques to Improve Performance on MPI Applications in NoC-Based MPSoCs. (Thesis). Universitat Autònoma de Barcelona. Retrieved from http://hdl.handle.net/10803/284889

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fernandez Alonso, Eduard. “Offloading Techniques to Improve Performance on MPI Applications in NoC-Based MPSoCs.” 2014. Thesis, Universitat Autònoma de Barcelona. Accessed December 09, 2019. http://hdl.handle.net/10803/284889.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fernandez Alonso, Eduard. “Offloading Techniques to Improve Performance on MPI Applications in NoC-Based MPSoCs.” 2014. Web. 09 Dec 2019.

Vancouver:

Fernandez Alonso E. Offloading Techniques to Improve Performance on MPI Applications in NoC-Based MPSoCs. [Internet] [Thesis]. Universitat Autònoma de Barcelona; 2014. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/10803/284889.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fernandez Alonso E. Offloading Techniques to Improve Performance on MPI Applications in NoC-Based MPSoCs. [Thesis]. Universitat Autònoma de Barcelona; 2014. Available from: http://hdl.handle.net/10803/284889

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New South Wales

4. Ahmadi, Koosha. Simulating run-time task migration in many-core systems.

Degree: Computer Science & Engineering, 2014, University of New South Wales

 With the ever increasing number of processing elements on Network-on-Chip multiprocessors, it is crucial to utilise the resources efficiently. Allocation of tasks to processing elements… (more)

Subjects/Keywords: Mapping; Task Migration; Many-Core Systems; Simulator

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APA (6th Edition):

Ahmadi, K. (2014). Simulating run-time task migration in many-core systems. (Masters Thesis). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/54223 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:13483/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Ahmadi, Koosha. “Simulating run-time task migration in many-core systems.” 2014. Masters Thesis, University of New South Wales. Accessed December 09, 2019. http://handle.unsw.edu.au/1959.4/54223 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:13483/SOURCE02?view=true.

MLA Handbook (7th Edition):

Ahmadi, Koosha. “Simulating run-time task migration in many-core systems.” 2014. Web. 09 Dec 2019.

Vancouver:

Ahmadi K. Simulating run-time task migration in many-core systems. [Internet] [Masters thesis]. University of New South Wales; 2014. [cited 2019 Dec 09]. Available from: http://handle.unsw.edu.au/1959.4/54223 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:13483/SOURCE02?view=true.

Council of Science Editors:

Ahmadi K. Simulating run-time task migration in many-core systems. [Masters Thesis]. University of New South Wales; 2014. Available from: http://handle.unsw.edu.au/1959.4/54223 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:13483/SOURCE02?view=true


University of Rochester

5. Zhang, Meilin (1982 - ). Reliable ultra-low-voltage cache design for many-core systems.

Degree: PhD, 2016, University of Rochester

 Energy efficiency and reliability are two main concerns in future many-core systems design. On the one hand, technology scaling makes it possible to integrate an… (more)

Subjects/Keywords: Cache; Many-Core; Reliability; Ultra-Low-Voltage

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APA (6th Edition):

Zhang, M. (. -. ). (2016). Reliable ultra-low-voltage cache design for many-core systems. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/30887

Chicago Manual of Style (16th Edition):

Zhang, Meilin (1982 - ). “Reliable ultra-low-voltage cache design for many-core systems.” 2016. Doctoral Dissertation, University of Rochester. Accessed December 09, 2019. http://hdl.handle.net/1802/30887.

MLA Handbook (7th Edition):

Zhang, Meilin (1982 - ). “Reliable ultra-low-voltage cache design for many-core systems.” 2016. Web. 09 Dec 2019.

Vancouver:

Zhang M(-). Reliable ultra-low-voltage cache design for many-core systems. [Internet] [Doctoral dissertation]. University of Rochester; 2016. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1802/30887.

Council of Science Editors:

Zhang M(-). Reliable ultra-low-voltage cache design for many-core systems. [Doctoral Dissertation]. University of Rochester; 2016. Available from: http://hdl.handle.net/1802/30887

6. Do, Xuan Khanh. Modèle de calcul et d'exécution pour des applications flots de données dynamiques avec contraintes temps réel : A model of programming languages for dynamic real-time streaming applications.

Degree: Docteur es, Informatique, 2016, Université Pierre et Marie Curie – Paris VI

 Il y a un intérêt croissant pour le développement d'applications sur les plates-formes multiprocesseurs homo- et hétérogènes en raison de l'extension de leur champ d'application… (more)

Subjects/Keywords: Many-Core; Parallélisme; Dataflow; Systèmes embarqués; Applications dynamiques; Ordonnancement; Dataflow; Many-Core; Scheduling; 004

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APA (6th Edition):

Do, X. K. (2016). Modèle de calcul et d'exécution pour des applications flots de données dynamiques avec contraintes temps réel : A model of programming languages for dynamic real-time streaming applications. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2016PA066522

Chicago Manual of Style (16th Edition):

Do, Xuan Khanh. “Modèle de calcul et d'exécution pour des applications flots de données dynamiques avec contraintes temps réel : A model of programming languages for dynamic real-time streaming applications.” 2016. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed December 09, 2019. http://www.theses.fr/2016PA066522.

MLA Handbook (7th Edition):

Do, Xuan Khanh. “Modèle de calcul et d'exécution pour des applications flots de données dynamiques avec contraintes temps réel : A model of programming languages for dynamic real-time streaming applications.” 2016. Web. 09 Dec 2019.

Vancouver:

Do XK. Modèle de calcul et d'exécution pour des applications flots de données dynamiques avec contraintes temps réel : A model of programming languages for dynamic real-time streaming applications. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2016. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2016PA066522.

Council of Science Editors:

Do XK. Modèle de calcul et d'exécution pour des applications flots de données dynamiques avec contraintes temps réel : A model of programming languages for dynamic real-time streaming applications. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2016. Available from: http://www.theses.fr/2016PA066522

7. Méndez Real, Maria. Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures : Isolation physique contre les attaques logiques par canaux cachés basées sur le cache dans des architectures many-core.

Degree: Docteur es, Stic, 2017, Lorient

L’évolution technologique ainsi que l’augmentation incessante de la puissance de calcul requise par les applications font des architectures ”many-core” la nouvelle tendance dans la conception… (more)

Subjects/Keywords: Architectures many-core; Multi-core architectures; Open Virtual Platforms; 005.8

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APA (6th Edition):

Méndez Real, M. (2017). Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures : Isolation physique contre les attaques logiques par canaux cachés basées sur le cache dans des architectures many-core. (Doctoral Dissertation). Lorient. Retrieved from http://www.theses.fr/2017LORIS454

Chicago Manual of Style (16th Edition):

Méndez Real, Maria. “Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures : Isolation physique contre les attaques logiques par canaux cachés basées sur le cache dans des architectures many-core.” 2017. Doctoral Dissertation, Lorient. Accessed December 09, 2019. http://www.theses.fr/2017LORIS454.

MLA Handbook (7th Edition):

Méndez Real, Maria. “Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures : Isolation physique contre les attaques logiques par canaux cachés basées sur le cache dans des architectures many-core.” 2017. Web. 09 Dec 2019.

Vancouver:

Méndez Real M. Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures : Isolation physique contre les attaques logiques par canaux cachés basées sur le cache dans des architectures many-core. [Internet] [Doctoral dissertation]. Lorient; 2017. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2017LORIS454.

Council of Science Editors:

Méndez Real M. Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures : Isolation physique contre les attaques logiques par canaux cachés basées sur le cache dans des architectures many-core. [Doctoral Dissertation]. Lorient; 2017. Available from: http://www.theses.fr/2017LORIS454


Virginia Tech

8. Zhang, Jing. Transforming and Optimizing Irregular Applications for Parallel Architectures.

Degree: PhD, Computer Science, 2018, Virginia Tech

 Parallel architectures, including multi-core processors, many-core processors, and multi-node systems, have become commonplace, as it is no longer feasible to improve single-core performance through increasing… (more)

Subjects/Keywords: Irregular Applications; Parallel Architectures; Multi-core; Many-core; Multi-node; Bioinformatics

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APA (6th Edition):

Zhang, J. (2018). Transforming and Optimizing Irregular Applications for Parallel Architectures. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/82069

Chicago Manual of Style (16th Edition):

Zhang, Jing. “Transforming and Optimizing Irregular Applications for Parallel Architectures.” 2018. Doctoral Dissertation, Virginia Tech. Accessed December 09, 2019. http://hdl.handle.net/10919/82069.

MLA Handbook (7th Edition):

Zhang, Jing. “Transforming and Optimizing Irregular Applications for Parallel Architectures.” 2018. Web. 09 Dec 2019.

Vancouver:

Zhang J. Transforming and Optimizing Irregular Applications for Parallel Architectures. [Internet] [Doctoral dissertation]. Virginia Tech; 2018. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/10919/82069.

Council of Science Editors:

Zhang J. Transforming and Optimizing Irregular Applications for Parallel Architectures. [Doctoral Dissertation]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/82069


University of New Mexico

9. Bezerra, George. Energy consumption in networks on chip : efficiency and scaling.

Degree: Department of Computer Science, 2012, University of New Mexico

 Computer architecture design is in a new era where performance is increased by replicating processing cores on a chip rather than making CPUs larger and… (more)

Subjects/Keywords: multi-core; many-core; energy consumption; communicaiton locality; scaling

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APA (6th Edition):

Bezerra, G. (2012). Energy consumption in networks on chip : efficiency and scaling. (Doctoral Dissertation). University of New Mexico. Retrieved from http://hdl.handle.net/1928/21020

Chicago Manual of Style (16th Edition):

Bezerra, George. “Energy consumption in networks on chip : efficiency and scaling.” 2012. Doctoral Dissertation, University of New Mexico. Accessed December 09, 2019. http://hdl.handle.net/1928/21020.

MLA Handbook (7th Edition):

Bezerra, George. “Energy consumption in networks on chip : efficiency and scaling.” 2012. Web. 09 Dec 2019.

Vancouver:

Bezerra G. Energy consumption in networks on chip : efficiency and scaling. [Internet] [Doctoral dissertation]. University of New Mexico; 2012. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1928/21020.

Council of Science Editors:

Bezerra G. Energy consumption in networks on chip : efficiency and scaling. [Doctoral Dissertation]. University of New Mexico; 2012. Available from: http://hdl.handle.net/1928/21020

10. Tekić Jelena. Оптимизација CFD симулације на групама вишејезгарних хетерогених архитектура.

Degree: 2019, University of Novi Sad

Предмет  истраживања  тезе  је  из области  паралелног  програмирања, имплементација  CFD  (Computational Fluid  Dynamics)  методе  на  више хетерогених  вишејезгарних  уређаја истовремено.  У  раду  је  приказано… (more)

Subjects/Keywords: OpenCL; Lattice Boltzman; GPU; many-core; multi-core

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APA (6th Edition):

Jelena, T. (2019). Оптимизација CFD симулације на групама вишејезгарних хетерогених архитектура. (Thesis). University of Novi Sad. Retrieved from https://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija156386637550062.pdf?controlNumber=(BISIS)110976&fileName=156386637550062.pdf&id=13241&source=OATD&language=en ; https://www.cris.uns.ac.rs/record.jsf?recordId=110976&source=OATD&language=en

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jelena, Tekić. “Оптимизација CFD симулације на групама вишејезгарних хетерогених архитектура.” 2019. Thesis, University of Novi Sad. Accessed December 09, 2019. https://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija156386637550062.pdf?controlNumber=(BISIS)110976&fileName=156386637550062.pdf&id=13241&source=OATD&language=en ; https://www.cris.uns.ac.rs/record.jsf?recordId=110976&source=OATD&language=en.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jelena, Tekić. “Оптимизација CFD симулације на групама вишејезгарних хетерогених архитектура.” 2019. Web. 09 Dec 2019.

Vancouver:

Jelena T. Оптимизација CFD симулације на групама вишејезгарних хетерогених архитектура. [Internet] [Thesis]. University of Novi Sad; 2019. [cited 2019 Dec 09]. Available from: https://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija156386637550062.pdf?controlNumber=(BISIS)110976&fileName=156386637550062.pdf&id=13241&source=OATD&language=en ; https://www.cris.uns.ac.rs/record.jsf?recordId=110976&source=OATD&language=en.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jelena T. Оптимизација CFD симулације на групама вишејезгарних хетерогених архитектура. [Thesis]. University of Novi Sad; 2019. Available from: https://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija156386637550062.pdf?controlNumber=(BISIS)110976&fileName=156386637550062.pdf&id=13241&source=OATD&language=en ; https://www.cris.uns.ac.rs/record.jsf?recordId=110976&source=OATD&language=en

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Brière, Alexandre. Modélisation système d'une architecture d'interconnexion RF reconfigurable pour les many-cœurs : System modeling of a reconfigurable RF interconnect architecture for manycore.

Degree: Docteur es, Informatique, 2017, Université Pierre et Marie Curie – Paris VI

La multiplication du nombre de cœurs de calcul présents sur une même puce va depair avec une augmentation des besoins en communication. De plus, la… (more)

Subjects/Keywords: NoC; RF; Dynamique; Reconfigurable; Hiérarchique; Many-Cœur; NoC; Many-core; Radio frequency; 004.5

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APA (6th Edition):

Brière, A. (2017). Modélisation système d'une architecture d'interconnexion RF reconfigurable pour les many-cœurs : System modeling of a reconfigurable RF interconnect architecture for manycore. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2017PA066296

Chicago Manual of Style (16th Edition):

Brière, Alexandre. “Modélisation système d'une architecture d'interconnexion RF reconfigurable pour les many-cœurs : System modeling of a reconfigurable RF interconnect architecture for manycore.” 2017. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed December 09, 2019. http://www.theses.fr/2017PA066296.

MLA Handbook (7th Edition):

Brière, Alexandre. “Modélisation système d'une architecture d'interconnexion RF reconfigurable pour les many-cœurs : System modeling of a reconfigurable RF interconnect architecture for manycore.” 2017. Web. 09 Dec 2019.

Vancouver:

Brière A. Modélisation système d'une architecture d'interconnexion RF reconfigurable pour les many-cœurs : System modeling of a reconfigurable RF interconnect architecture for manycore. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2017. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2017PA066296.

Council of Science Editors:

Brière A. Modélisation système d'une architecture d'interconnexion RF reconfigurable pour les many-cœurs : System modeling of a reconfigurable RF interconnect architecture for manycore. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2017. Available from: http://www.theses.fr/2017PA066296

12. Fuguet Tortolero, César. Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente : Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures.

Degree: Docteur es, Informatique, 2015, Université Pierre et Marie Curie – Paris VI

L'augmentation continue de la puissance de calcul requise par les applications telles que la cryptographie, la simulation, ou le traitement du signal a fait évoluer… (more)

Subjects/Keywords: Pannes franches; Many-Core; Localisation de pannes; Reconfiguration; Algorithmique distribuée; Réseau-Sur-Puce; Démarrage du processeur; Many-core; Fault-tolerance; 004

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APA (6th Edition):

Fuguet Tortolero, C. (2015). Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente : Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2015PA066462

Chicago Manual of Style (16th Edition):

Fuguet Tortolero, César. “Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente : Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures.” 2015. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed December 09, 2019. http://www.theses.fr/2015PA066462.

MLA Handbook (7th Edition):

Fuguet Tortolero, César. “Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente : Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures.” 2015. Web. 09 Dec 2019.

Vancouver:

Fuguet Tortolero C. Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente : Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2015. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2015PA066462.

Council of Science Editors:

Fuguet Tortolero C. Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente : Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2015. Available from: http://www.theses.fr/2015PA066462

13. Lo, Moustapha. Application des architectures many core dans les systèmes embarqués temps réel : Implementing a Real-time Avionic application on a Many-core Processor.

Degree: Docteur es, Informatique, 2019, Grenoble Alpes

Les processeurs mono-coeurs traditionnels ne sont plus suffisants pour répondre aux besoins croissants en performance des fonctions avioniques. Les processeurs multi/many-coeurs ont emergé ces dernières… (more)

Subjects/Keywords: Many-Core; Temps-Réel; Determinisme; Multi-Core; Algorithmes globaux; Algorithmes incrémentaux; Many-Core; Real-Time; Determinism; Multi-Core; Global algorithms; Incremental Algorithms; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lo, M. (2019). Application des architectures many core dans les systèmes embarqués temps réel : Implementing a Real-time Avionic application on a Many-core Processor. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2019GREAM002

Chicago Manual of Style (16th Edition):

Lo, Moustapha. “Application des architectures many core dans les systèmes embarqués temps réel : Implementing a Real-time Avionic application on a Many-core Processor.” 2019. Doctoral Dissertation, Grenoble Alpes. Accessed December 09, 2019. http://www.theses.fr/2019GREAM002.

MLA Handbook (7th Edition):

Lo, Moustapha. “Application des architectures many core dans les systèmes embarqués temps réel : Implementing a Real-time Avionic application on a Many-core Processor.” 2019. Web. 09 Dec 2019.

Vancouver:

Lo M. Application des architectures many core dans les systèmes embarqués temps réel : Implementing a Real-time Avionic application on a Many-core Processor. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2019. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2019GREAM002.

Council of Science Editors:

Lo M. Application des architectures many core dans les systèmes embarqués temps réel : Implementing a Real-time Avionic application on a Many-core Processor. [Doctoral Dissertation]. Grenoble Alpes; 2019. Available from: http://www.theses.fr/2019GREAM002


University of Tennessee – Knoxville

14. Ma, Teng. Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters.

Degree: 2012, University of Tennessee – Knoxville

 Multicore or many-core clusters have become the most prominent form of High Performance Computing (HPC) systems. Hardware complexity and hierarchies not only exist in the… (more)

Subjects/Keywords: MPI; kernel; hierarchical; collective; multi-core; many-core; Computational Engineering; Computer and Systems Architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ma, T. (2012). Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/1541

Chicago Manual of Style (16th Edition):

Ma, Teng. “Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters.” 2012. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed December 09, 2019. https://trace.tennessee.edu/utk_graddiss/1541.

MLA Handbook (7th Edition):

Ma, Teng. “Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters.” 2012. Web. 09 Dec 2019.

Vancouver:

Ma T. Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2012. [cited 2019 Dec 09]. Available from: https://trace.tennessee.edu/utk_graddiss/1541.

Council of Science Editors:

Ma T. Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2012. Available from: https://trace.tennessee.edu/utk_graddiss/1541


The Ohio State University

15. Singh, Kunal. High-Performance Sparse Matrix-Multi Vector Multiplication on Multi-Core Architecture.

Degree: MS, Computer Science and Engineering, 2018, The Ohio State University

 SpMM is a widely used primitive in many domains like Fluid Dynamics, DataAnalytics, Economic Modelling and Machine Learning. In Machine Learning and ArtificialNeural Network domain… (more)

Subjects/Keywords: Computer Science; SpMM; SpMDM; Sparse Dense Matrix Multiplication; Multi-core; Many-Core

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Singh, K. (2018). High-Performance Sparse Matrix-Multi Vector Multiplication on Multi-Core Architecture. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1524089757826551

Chicago Manual of Style (16th Edition):

Singh, Kunal. “High-Performance Sparse Matrix-Multi Vector Multiplication on Multi-Core Architecture.” 2018. Masters Thesis, The Ohio State University. Accessed December 09, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1524089757826551.

MLA Handbook (7th Edition):

Singh, Kunal. “High-Performance Sparse Matrix-Multi Vector Multiplication on Multi-Core Architecture.” 2018. Web. 09 Dec 2019.

Vancouver:

Singh K. High-Performance Sparse Matrix-Multi Vector Multiplication on Multi-Core Architecture. [Internet] [Masters thesis]. The Ohio State University; 2018. [cited 2019 Dec 09]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1524089757826551.

Council of Science Editors:

Singh K. High-Performance Sparse Matrix-Multi Vector Multiplication on Multi-Core Architecture. [Masters Thesis]. The Ohio State University; 2018. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1524089757826551


University of Cincinnati

16. Herrmann, Edward C. Threaded Dynamic Memory Management in Many-Core Processors.

Degree: MS, Engineering : Computer Engineering, 2010, University of Cincinnati

  In recent years the number of simultaneous threads supported by desktop processors has increased dramatically. As the number of cores in processors continue to… (more)

Subjects/Keywords: Electrical Engineering; dynamic memory; threaded library; many-core

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Herrmann, E. C. (2010). Threaded Dynamic Memory Management in Many-Core Processors. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1277132326

Chicago Manual of Style (16th Edition):

Herrmann, Edward C. “Threaded Dynamic Memory Management in Many-Core Processors.” 2010. Masters Thesis, University of Cincinnati. Accessed December 09, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1277132326.

MLA Handbook (7th Edition):

Herrmann, Edward C. “Threaded Dynamic Memory Management in Many-Core Processors.” 2010. Web. 09 Dec 2019.

Vancouver:

Herrmann EC. Threaded Dynamic Memory Management in Many-Core Processors. [Internet] [Masters thesis]. University of Cincinnati; 2010. [cited 2019 Dec 09]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1277132326.

Council of Science Editors:

Herrmann EC. Threaded Dynamic Memory Management in Many-Core Processors. [Masters Thesis]. University of Cincinnati; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1277132326


University of California – Irvine

17. Tajik, Hossein. Runtime Memory Management in Many-core Systems.

Degree: Computer Science, 2016, University of California – Irvine

 With the number of cores on a chip continuing to increase, we are moving towards an era where many-core platforms will soon be ubiquitous. Efficient… (more)

Subjects/Keywords: Computer science; Many-core; Memory Management; Runtime System; SPM

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APA (6th Edition):

Tajik, H. (2016). Runtime Memory Management in Many-core Systems. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/5g82h1fz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tajik, Hossein. “Runtime Memory Management in Many-core Systems.” 2016. Thesis, University of California – Irvine. Accessed December 09, 2019. http://www.escholarship.org/uc/item/5g82h1fz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tajik, Hossein. “Runtime Memory Management in Many-core Systems.” 2016. Web. 09 Dec 2019.

Vancouver:

Tajik H. Runtime Memory Management in Many-core Systems. [Internet] [Thesis]. University of California – Irvine; 2016. [cited 2019 Dec 09]. Available from: http://www.escholarship.org/uc/item/5g82h1fz.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tajik H. Runtime Memory Management in Many-core Systems. [Thesis]. University of California – Irvine; 2016. Available from: http://www.escholarship.org/uc/item/5g82h1fz

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université Catholique de Louvain

18. Rousseau, Bertrand. Evaluations of hardware platforms, methods and tools for low-volume software-defined signal processing applications.

Degree: 2011, Université Catholique de Louvain

Embedded signal processing applications evolve towards advanced applications supporting many standards and providing advanced functionalities. In those applications, the control and software parts are increasing… (more)

Subjects/Keywords: Digital signal processing; Dynamic partial reconfiguration; FPGA; Homogeneous many-core platforms

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APA (6th Edition):

Rousseau, B. (2011). Evaluations of hardware platforms, methods and tools for low-volume software-defined signal processing applications. (Thesis). Université Catholique de Louvain. Retrieved from http://hdl.handle.net/2078.1/70745

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rousseau, Bertrand. “Evaluations of hardware platforms, methods and tools for low-volume software-defined signal processing applications.” 2011. Thesis, Université Catholique de Louvain. Accessed December 09, 2019. http://hdl.handle.net/2078.1/70745.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rousseau, Bertrand. “Evaluations of hardware platforms, methods and tools for low-volume software-defined signal processing applications.” 2011. Web. 09 Dec 2019.

Vancouver:

Rousseau B. Evaluations of hardware platforms, methods and tools for low-volume software-defined signal processing applications. [Internet] [Thesis]. Université Catholique de Louvain; 2011. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2078.1/70745.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rousseau B. Evaluations of hardware platforms, methods and tools for low-volume software-defined signal processing applications. [Thesis]. Université Catholique de Louvain; 2011. Available from: http://hdl.handle.net/2078.1/70745

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


KTH

19. Trigonakis, Vasileios. Design of a Distributed Transactional Memory for Many-core systems.

Degree: Information and Communication Technology (ICT), 2011, KTH

  The emergence of Multi/Many-core systems signified an increasing need for parallel programming. Transactional Memory (TM) is a promising programming paradigm for creating concurrent applications.… (more)

Subjects/Keywords: Transactional Memory (TM); Contention Management (CM); Many-core Systems; TECHNOLOGY; TEKNIKVETENSKAP

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APA (6th Edition):

Trigonakis, V. (2011). Design of a Distributed Transactional Memory for Many-core systems. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-48339

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Trigonakis, Vasileios. “Design of a Distributed Transactional Memory for Many-core systems.” 2011. Thesis, KTH. Accessed December 09, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-48339.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Trigonakis, Vasileios. “Design of a Distributed Transactional Memory for Many-core systems.” 2011. Web. 09 Dec 2019.

Vancouver:

Trigonakis V. Design of a Distributed Transactional Memory for Many-core systems. [Internet] [Thesis]. KTH; 2011. [cited 2019 Dec 09]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-48339.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Trigonakis V. Design of a Distributed Transactional Memory for Many-core systems. [Thesis]. KTH; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-48339

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Halmstad University

20. Farahaninia, Farzad. Acceleration of Parallel Applications by Moving Code Instead of Data.

Degree: Information Technology, 2014, Halmstad University

  After the performance improvement rate in single-core processors decreased in 2000s, most CPU manufacturers have steered towards parallel computing. Parallel computing has been in… (more)

Subjects/Keywords: Many Core; Parallel Applications; Epiphany; LTE; Signal Processing; Embedded

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APA (6th Edition):

Farahaninia, F. (2014). Acceleration of Parallel Applications by Moving Code Instead of Data. (Thesis). Halmstad University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-29855

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Farahaninia, Farzad. “Acceleration of Parallel Applications by Moving Code Instead of Data.” 2014. Thesis, Halmstad University. Accessed December 09, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-29855.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Farahaninia, Farzad. “Acceleration of Parallel Applications by Moving Code Instead of Data.” 2014. Web. 09 Dec 2019.

Vancouver:

Farahaninia F. Acceleration of Parallel Applications by Moving Code Instead of Data. [Internet] [Thesis]. Halmstad University; 2014. [cited 2019 Dec 09]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-29855.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Farahaninia F. Acceleration of Parallel Applications by Moving Code Instead of Data. [Thesis]. Halmstad University; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-29855

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

21. De Klerk, J. Cache Balancer: A communication latency and utilization aware resource manager:.

Degree: 2014, Delft University of Technology

 The increasing number of processors in today's many-core architectures has lead to new issues regarding memory management. The performance of many-core processors is often limited… (more)

Subjects/Keywords: many-core processor; memory allocation; memory access latency

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APA (6th Edition):

De Klerk, J. (2014). Cache Balancer: A communication latency and utilization aware resource manager:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:e0fe8916-1196-45bf-bc84-4316e9c97982

Chicago Manual of Style (16th Edition):

De Klerk, J. “Cache Balancer: A communication latency and utilization aware resource manager:.” 2014. Masters Thesis, Delft University of Technology. Accessed December 09, 2019. http://resolver.tudelft.nl/uuid:e0fe8916-1196-45bf-bc84-4316e9c97982.

MLA Handbook (7th Edition):

De Klerk, J. “Cache Balancer: A communication latency and utilization aware resource manager:.” 2014. Web. 09 Dec 2019.

Vancouver:

De Klerk J. Cache Balancer: A communication latency and utilization aware resource manager:. [Internet] [Masters thesis]. Delft University of Technology; 2014. [cited 2019 Dec 09]. Available from: http://resolver.tudelft.nl/uuid:e0fe8916-1196-45bf-bc84-4316e9c97982.

Council of Science Editors:

De Klerk J. Cache Balancer: A communication latency and utilization aware resource manager:. [Masters Thesis]. Delft University of Technology; 2014. Available from: http://resolver.tudelft.nl/uuid:e0fe8916-1196-45bf-bc84-4316e9c97982

22. Sarrazin, Guillaume. Simulation fonctionnelle native pour des systèmes many-cœurs : Functional native simulation techniques for many-core systems.

Degree: Docteur es, Informatique, 2016, Grenoble Alpes

Le nombre de transistors dans une puce augmente constamment en suivant la conjecture de Moore, qui dit que le nombre de transistors dans une puce… (more)

Subjects/Keywords: Simulation native; Simulation compilé; Systèmes sur puce; Fpu; Many-Cœur; Native simulation; Compiled smulation; System-On-Chip; Fpu; Many-Core; 004

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APA (6th Edition):

Sarrazin, G. (2016). Simulation fonctionnelle native pour des systèmes many-cœurs : Functional native simulation techniques for many-core systems. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2016GREAM015

Chicago Manual of Style (16th Edition):

Sarrazin, Guillaume. “Simulation fonctionnelle native pour des systèmes many-cœurs : Functional native simulation techniques for many-core systems.” 2016. Doctoral Dissertation, Grenoble Alpes. Accessed December 09, 2019. http://www.theses.fr/2016GREAM015.

MLA Handbook (7th Edition):

Sarrazin, Guillaume. “Simulation fonctionnelle native pour des systèmes many-cœurs : Functional native simulation techniques for many-core systems.” 2016. Web. 09 Dec 2019.

Vancouver:

Sarrazin G. Simulation fonctionnelle native pour des systèmes many-cœurs : Functional native simulation techniques for many-core systems. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2016. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2016GREAM015.

Council of Science Editors:

Sarrazin G. Simulation fonctionnelle native pour des systèmes many-cœurs : Functional native simulation techniques for many-core systems. [Doctoral Dissertation]. Grenoble Alpes; 2016. Available from: http://www.theses.fr/2016GREAM015

23. Drebes, Andi. Dynamic optimization of data-flow task-parallel applications for large-scale NUMA systems : Optimisation dynamique des applications à base de tâches data-flow pour des machines NUMA.

Degree: Docteur es, Informatique, 2015, Université Pierre et Marie Curie – Paris VI

Au milieu des années deux mille, le développement de microprocesseurs a atteint un point à partir duquel l'augmentation de la fréquence de fonctionnement et la… (more)

Subjects/Keywords: Programmation parallèle; Runtime; Many-Coeur NUMA; Ordonnancement; Allocation mémoire; Analyse de performances; Paralel programs; Many-core NUMA; 004

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APA (6th Edition):

Drebes, A. (2015). Dynamic optimization of data-flow task-parallel applications for large-scale NUMA systems : Optimisation dynamique des applications à base de tâches data-flow pour des machines NUMA. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2015PA066330

Chicago Manual of Style (16th Edition):

Drebes, Andi. “Dynamic optimization of data-flow task-parallel applications for large-scale NUMA systems : Optimisation dynamique des applications à base de tâches data-flow pour des machines NUMA.” 2015. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed December 09, 2019. http://www.theses.fr/2015PA066330.

MLA Handbook (7th Edition):

Drebes, Andi. “Dynamic optimization of data-flow task-parallel applications for large-scale NUMA systems : Optimisation dynamique des applications à base de tâches data-flow pour des machines NUMA.” 2015. Web. 09 Dec 2019.

Vancouver:

Drebes A. Dynamic optimization of data-flow task-parallel applications for large-scale NUMA systems : Optimisation dynamique des applications à base de tâches data-flow pour des machines NUMA. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2015. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2015PA066330.

Council of Science Editors:

Drebes A. Dynamic optimization of data-flow task-parallel applications for large-scale NUMA systems : Optimisation dynamique des applications à base de tâches data-flow pour des machines NUMA. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2015. Available from: http://www.theses.fr/2015PA066330


Texas A&M University

24. Tripathy, Aalap. High Performance Information Filtering on Many-core Processors.

Degree: 2013, Texas A&M University

 The increasing amount of information accessible to a user digitally makes search difficult, time consuming and unsatisfactory. This has led to the development of active… (more)

Subjects/Keywords: GPGPU; SCC; Mapreduce; semantic information filtering; collaborative information filtering; recommendation system; many-core computing; many-core programming models; reconfigurable architectures; System on chip (SoC)

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APA (6th Edition):

Tripathy, A. (2013). High Performance Information Filtering on Many-core Processors. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/151862

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tripathy, Aalap. “High Performance Information Filtering on Many-core Processors.” 2013. Thesis, Texas A&M University. Accessed December 09, 2019. http://hdl.handle.net/1969.1/151862.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tripathy, Aalap. “High Performance Information Filtering on Many-core Processors.” 2013. Web. 09 Dec 2019.

Vancouver:

Tripathy A. High Performance Information Filtering on Many-core Processors. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1969.1/151862.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tripathy A. High Performance Information Filtering on Many-core Processors. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/151862

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Ramos Vargas, Pablo Francisco. Evaluation de la sensibilité face aux SEE et méthodologie pour la prédiction de taux d’erreurs d’applications implémentées dans des processeurs Multi-cœur et Many-cœur : Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors.

Degree: Docteur es, Nano electronique et nano technologies, 2017, Grenoble Alpes

La présente thèse vise à évaluer la sensibilité statique et dynamique face aux SEE de trois dispositifs COTS différents. Le premier est le processeur multi-cœurs… (more)

Subjects/Keywords: Fiabilité; Test; Injection de fautes; Processeurs many-Core; Single Event Upsets; Essai de radiation; Reliability; Testing; Fault injection; Many- core processors; Single Event Upsets; Radiation test; 600

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APA (6th Edition):

Ramos Vargas, P. F. (2017). Evaluation de la sensibilité face aux SEE et méthodologie pour la prédiction de taux d’erreurs d’applications implémentées dans des processeurs Multi-cœur et Many-cœur : Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2017GREAT022

Chicago Manual of Style (16th Edition):

Ramos Vargas, Pablo Francisco. “Evaluation de la sensibilité face aux SEE et méthodologie pour la prédiction de taux d’erreurs d’applications implémentées dans des processeurs Multi-cœur et Many-cœur : Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors.” 2017. Doctoral Dissertation, Grenoble Alpes. Accessed December 09, 2019. http://www.theses.fr/2017GREAT022.

MLA Handbook (7th Edition):

Ramos Vargas, Pablo Francisco. “Evaluation de la sensibilité face aux SEE et méthodologie pour la prédiction de taux d’erreurs d’applications implémentées dans des processeurs Multi-cœur et Many-cœur : Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors.” 2017. Web. 09 Dec 2019.

Vancouver:

Ramos Vargas PF. Evaluation de la sensibilité face aux SEE et méthodologie pour la prédiction de taux d’erreurs d’applications implémentées dans des processeurs Multi-cœur et Many-cœur : Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2017. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2017GREAT022.

Council of Science Editors:

Ramos Vargas PF. Evaluation de la sensibilité face aux SEE et méthodologie pour la prédiction de taux d’erreurs d’applications implémentées dans des processeurs Multi-cœur et Many-cœur : Evaluation of the SEE sensitivity and methodology for error rate prediction of applications implemented in Multi-core and Many-core processors. [Doctoral Dissertation]. Grenoble Alpes; 2017. Available from: http://www.theses.fr/2017GREAT022

26. Vargas Vallejo, Vanessa Carolina. Approche logicielle pour améliorer la fiabilité d’applications parallèles implémentées dans des processeurs multi-cœur et many-cœur : Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors.

Degree: Docteur es, Nano electronique et nano technologies, 2017, Grenoble Alpes

La grande capacité de calcul, flexibilité, faible consommation d'énergie, redondance intrinsèque et la haute performance fournie par les processeurs multi/many-cœur les rendent idéaux pour surmonter… (more)

Subjects/Keywords: Architectures parallèles; Multi-Cœur et many-Cœur; Fiabilité; Redondance; Multi-Processing mode; Injection de fautes; Parallel Architectures; Multi-Core and many-Core; Reliability; Redundancy; Multi-Processing mode; Fault injection; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vargas Vallejo, V. C. (2017). Approche logicielle pour améliorer la fiabilité d’applications parallèles implémentées dans des processeurs multi-cœur et many-cœur : Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2017GREAT042

Chicago Manual of Style (16th Edition):

Vargas Vallejo, Vanessa Carolina. “Approche logicielle pour améliorer la fiabilité d’applications parallèles implémentées dans des processeurs multi-cœur et many-cœur : Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors.” 2017. Doctoral Dissertation, Grenoble Alpes. Accessed December 09, 2019. http://www.theses.fr/2017GREAT042.

MLA Handbook (7th Edition):

Vargas Vallejo, Vanessa Carolina. “Approche logicielle pour améliorer la fiabilité d’applications parallèles implémentées dans des processeurs multi-cœur et many-cœur : Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors.” 2017. Web. 09 Dec 2019.

Vancouver:

Vargas Vallejo VC. Approche logicielle pour améliorer la fiabilité d’applications parallèles implémentées dans des processeurs multi-cœur et many-cœur : Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2017. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2017GREAT042.

Council of Science Editors:

Vargas Vallejo VC. Approche logicielle pour améliorer la fiabilité d’applications parallèles implémentées dans des processeurs multi-cœur et many-cœur : Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors. [Doctoral Dissertation]. Grenoble Alpes; 2017. Available from: http://www.theses.fr/2017GREAT042

27. Laville, Guillaume. Exécution efficace de systèmes Multi-Agents sur GPU : Efficient execution of multi-agent systems on GPU.

Degree: Docteur es, Informatique, 2014, Besançon

Ces dernières années ont consacré l’émergence du parallélisme dans la plupart des branches de l’informatique.Au niveau matériel, tout d’abord, du fait de la stagnation des… (more)

Subjects/Keywords: Framework de simulation; Système multi-agents; Many-core; GPU; Calcul haute performance; Simulation framework; Multi-agents system; Many-core; GPU; High-performance computing; 006

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Laville, G. (2014). Exécution efficace de systèmes Multi-Agents sur GPU : Efficient execution of multi-agent systems on GPU. (Doctoral Dissertation). Besançon. Retrieved from http://www.theses.fr/2014BESA2016

Chicago Manual of Style (16th Edition):

Laville, Guillaume. “Exécution efficace de systèmes Multi-Agents sur GPU : Efficient execution of multi-agent systems on GPU.” 2014. Doctoral Dissertation, Besançon. Accessed December 09, 2019. http://www.theses.fr/2014BESA2016.

MLA Handbook (7th Edition):

Laville, Guillaume. “Exécution efficace de systèmes Multi-Agents sur GPU : Efficient execution of multi-agent systems on GPU.” 2014. Web. 09 Dec 2019.

Vancouver:

Laville G. Exécution efficace de systèmes Multi-Agents sur GPU : Efficient execution of multi-agent systems on GPU. [Internet] [Doctoral dissertation]. Besançon; 2014. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2014BESA2016.

Council of Science Editors:

Laville G. Exécution efficace de systèmes Multi-Agents sur GPU : Efficient execution of multi-agent systems on GPU. [Doctoral Dissertation]. Besançon; 2014. Available from: http://www.theses.fr/2014BESA2016

28. Roussel, Adrien. Parallélisation sur un moteur exécutif à base de tâches des méthodes itératives pour la résolution de systèmes linéaires creux sur architecture multi et many coeurs : application aux méthodes de types décomposition de domaines multi-niveaux : Parallelization of iterative methods to solve sparse linear systems using task based runtime systems on multi and many-core architectures : application to Multi-Level Domain Decomposition methods.

Degree: Docteur es, Informatique, 2018, Grenoble Alpes

Les méthodes en simulation numérique dans le domaine de l’ingénierie pétrolière nécessitent la résolution de systèmes linéaires creux de grande taille et non structurés. La… (more)

Subjects/Keywords: Calcul parallèle; Décomposition de domaine; Moteur exécutif; Multi and Many-Core; Parallel computing; Domain decomposition methods; Runtime system; Multi and many-Core architecture; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roussel, A. (2018). Parallélisation sur un moteur exécutif à base de tâches des méthodes itératives pour la résolution de systèmes linéaires creux sur architecture multi et many coeurs : application aux méthodes de types décomposition de domaines multi-niveaux : Parallelization of iterative methods to solve sparse linear systems using task based runtime systems on multi and many-core architectures : application to Multi-Level Domain Decomposition methods. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2018GREAM010

Chicago Manual of Style (16th Edition):

Roussel, Adrien. “Parallélisation sur un moteur exécutif à base de tâches des méthodes itératives pour la résolution de systèmes linéaires creux sur architecture multi et many coeurs : application aux méthodes de types décomposition de domaines multi-niveaux : Parallelization of iterative methods to solve sparse linear systems using task based runtime systems on multi and many-core architectures : application to Multi-Level Domain Decomposition methods.” 2018. Doctoral Dissertation, Grenoble Alpes. Accessed December 09, 2019. http://www.theses.fr/2018GREAM010.

MLA Handbook (7th Edition):

Roussel, Adrien. “Parallélisation sur un moteur exécutif à base de tâches des méthodes itératives pour la résolution de systèmes linéaires creux sur architecture multi et many coeurs : application aux méthodes de types décomposition de domaines multi-niveaux : Parallelization of iterative methods to solve sparse linear systems using task based runtime systems on multi and many-core architectures : application to Multi-Level Domain Decomposition methods.” 2018. Web. 09 Dec 2019.

Vancouver:

Roussel A. Parallélisation sur un moteur exécutif à base de tâches des méthodes itératives pour la résolution de systèmes linéaires creux sur architecture multi et many coeurs : application aux méthodes de types décomposition de domaines multi-niveaux : Parallelization of iterative methods to solve sparse linear systems using task based runtime systems on multi and many-core architectures : application to Multi-Level Domain Decomposition methods. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2018. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2018GREAM010.

Council of Science Editors:

Roussel A. Parallélisation sur un moteur exécutif à base de tâches des méthodes itératives pour la résolution de systèmes linéaires creux sur architecture multi et many coeurs : application aux méthodes de types décomposition de domaines multi-niveaux : Parallelization of iterative methods to solve sparse linear systems using task based runtime systems on multi and many-core architectures : application to Multi-Level Domain Decomposition methods. [Doctoral Dissertation]. Grenoble Alpes; 2018. Available from: http://www.theses.fr/2018GREAM010

29. Ho, Minh Quan. Optimisation de transfert de données pour les processeurs pluri-coeurs, appliqué à l'algèbre linéaire et aux calculs sur stencils : Optimization of data transfer on many-core processors, applied to dense linear algebra and stencil computations.

Degree: Docteur es, Informatique, 2018, Grenoble Alpes

La prochaine cible de Exascale en calcul haute performance (High Performance Computing - HPC) et des récent accomplissements dans l'intelligence artificielle donnent l'émergence des architectures… (more)

Subjects/Keywords: Calcul haute performance; Processeur many-Core; Calcul numérique; Communication; Systèmes distribués; High performance computing (HPC); Many-Core processor; Numerical computation; Communication; Distributed systems; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ho, M. Q. (2018). Optimisation de transfert de données pour les processeurs pluri-coeurs, appliqué à l'algèbre linéaire et aux calculs sur stencils : Optimization of data transfer on many-core processors, applied to dense linear algebra and stencil computations. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2018GREAM042

Chicago Manual of Style (16th Edition):

Ho, Minh Quan. “Optimisation de transfert de données pour les processeurs pluri-coeurs, appliqué à l'algèbre linéaire et aux calculs sur stencils : Optimization of data transfer on many-core processors, applied to dense linear algebra and stencil computations.” 2018. Doctoral Dissertation, Grenoble Alpes. Accessed December 09, 2019. http://www.theses.fr/2018GREAM042.

MLA Handbook (7th Edition):

Ho, Minh Quan. “Optimisation de transfert de données pour les processeurs pluri-coeurs, appliqué à l'algèbre linéaire et aux calculs sur stencils : Optimization of data transfer on many-core processors, applied to dense linear algebra and stencil computations.” 2018. Web. 09 Dec 2019.

Vancouver:

Ho MQ. Optimisation de transfert de données pour les processeurs pluri-coeurs, appliqué à l'algèbre linéaire et aux calculs sur stencils : Optimization of data transfer on many-core processors, applied to dense linear algebra and stencil computations. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2018. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2018GREAM042.

Council of Science Editors:

Ho MQ. Optimisation de transfert de données pour les processeurs pluri-coeurs, appliqué à l'algèbre linéaire et aux calculs sur stencils : Optimization of data transfer on many-core processors, applied to dense linear algebra and stencil computations. [Doctoral Dissertation]. Grenoble Alpes; 2018. Available from: http://www.theses.fr/2018GREAM042


University of Illinois – Chicago

30. Panerati, Jacopo. Enhancing Self-Adaptive Computing Systems via Artificial Intelligence Techniques and Active Learning.

Degree: 2012, University of Illinois – Chicago

 Autonomic computing (AC) has been proposed as a solution to the increasing complexity of computer systems, threatening to make systems impossible to be managed by… (more)

Subjects/Keywords: multi-core; many-core; artificial intelligence; operating systems; reinforcement learning; active learning; learning; markov decision process; mdp

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Panerati, J. (2012). Enhancing Self-Adaptive Computing Systems via Artificial Intelligence Techniques and Active Learning. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/9179

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Panerati, Jacopo. “Enhancing Self-Adaptive Computing Systems via Artificial Intelligence Techniques and Active Learning.” 2012. Thesis, University of Illinois – Chicago. Accessed December 09, 2019. http://hdl.handle.net/10027/9179.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Panerati, Jacopo. “Enhancing Self-Adaptive Computing Systems via Artificial Intelligence Techniques and Active Learning.” 2012. Web. 09 Dec 2019.

Vancouver:

Panerati J. Enhancing Self-Adaptive Computing Systems via Artificial Intelligence Techniques and Active Learning. [Internet] [Thesis]. University of Illinois – Chicago; 2012. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/10027/9179.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Panerati J. Enhancing Self-Adaptive Computing Systems via Artificial Intelligence Techniques and Active Learning. [Thesis]. University of Illinois – Chicago; 2012. Available from: http://hdl.handle.net/10027/9179

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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