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You searched for subject:(MULTIPLE DATA STREAM ARCHITECTURES MULTIPROCESSORS COMPUTER SYSTEMS ). Showing records 1 – 30 of 171504 total matches.

[1] [2] [3] [4] [5] … [5717]

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ETH Zürich

1. Achermann, Reto. Message passing and bulk transport on heterogenous multiprocessors.

Degree: 2014, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); DATA COMMUNICATIONS (COMPUTER SYSTEMS); DATENKOMMUNIKATION (COMPUTERSYSTEME); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Achermann, R. (2014). Message passing and bulk transport on heterogenous multiprocessors. (Thesis). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/90919

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Achermann, Reto. “Message passing and bulk transport on heterogenous multiprocessors.” 2014. Thesis, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/90919.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Achermann, Reto. “Message passing and bulk transport on heterogenous multiprocessors.” 2014. Web. 29 Jan 2020.

Vancouver:

Achermann R. Message passing and bulk transport on heterogenous multiprocessors. [Internet] [Thesis]. ETH Zürich; 2014. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/90919.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Achermann R. Message passing and bulk transport on heterogenous multiprocessors. [Thesis]. ETH Zürich; 2014. Available from: http://hdl.handle.net/20.500.11850/90919

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ETH Zürich

2. Razavi, Kaveh. Performance isolation on multicore hardware.

Degree: 2011, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); PERFORMANCE (COMPUTER SYSTEMS); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); LEISTUNG (COMPUTERSYSTEME); PROCESS MANAGEMENT (OPERATING SYSTEMS); PROZESSVERWALTUNG + PROZESSMANAGEMENT (BETRIEBSSYSTEME); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA (6th Edition):

Razavi, K. (2011). Performance isolation on multicore hardware. (Thesis). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/41290

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Razavi, Kaveh. “Performance isolation on multicore hardware.” 2011. Thesis, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/41290.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Razavi, Kaveh. “Performance isolation on multicore hardware.” 2011. Web. 29 Jan 2020.

Vancouver:

Razavi K. Performance isolation on multicore hardware. [Internet] [Thesis]. ETH Zürich; 2011. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/41290.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Razavi K. Performance isolation on multicore hardware. [Thesis]. ETH Zürich; 2011. Available from: http://hdl.handle.net/20.500.11850/41290

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ETH Zürich

3. Haid, Wolfgang Christian Ferdinand. Design and performance analysis of multiprocessor streaming applications.

Degree: 2010, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); PERFORMANCE (COMPUTER SYSTEMS); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); LEISTUNG (COMPUTERSYSTEME); PROCESS MANAGEMENT (OPERATING SYSTEMS); PROZESSVERWALTUNG + PROZESSMANAGEMENT (BETRIEBSSYSTEME); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA (6th Edition):

Haid, W. C. F. (2010). Design and performance analysis of multiprocessor streaming applications. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/27971

Chicago Manual of Style (16th Edition):

Haid, Wolfgang Christian Ferdinand. “Design and performance analysis of multiprocessor streaming applications.” 2010. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/27971.

MLA Handbook (7th Edition):

Haid, Wolfgang Christian Ferdinand. “Design and performance analysis of multiprocessor streaming applications.” 2010. Web. 29 Jan 2020.

Vancouver:

Haid WCF. Design and performance analysis of multiprocessor streaming applications. [Internet] [Doctoral dissertation]. ETH Zürich; 2010. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/27971.

Council of Science Editors:

Haid WCF. Design and performance analysis of multiprocessor streaming applications. [Doctoral Dissertation]. ETH Zürich; 2010. Available from: http://hdl.handle.net/20.500.11850/27971


ETH Zürich

4. Bänziger, Patrick. Exploiting multi-core parallelism with pipelining to solve skyline queries.

Degree: 2013, ETH Zürich

Subjects/Keywords: PARALLELVERARBEITUNG + NEBENLÄUFIGKEIT (BETRIEBSSYSTEME); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); PIPELINE-PROZESSOREN (COMPUTERSYSTEME); PARALLEL PROCESSING + CONCURRENCY (OPERATING SYSTEMS); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); PIPELINE PROCESSORS (COMPUTER SYSTEMS); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA (6th Edition):

Bänziger, P. (2013). Exploiting multi-core parallelism with pipelining to solve skyline queries. (Thesis). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/154092

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bänziger, Patrick. “Exploiting multi-core parallelism with pipelining to solve skyline queries.” 2013. Thesis, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/154092.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bänziger, Patrick. “Exploiting multi-core parallelism with pipelining to solve skyline queries.” 2013. Web. 29 Jan 2020.

Vancouver:

Bänziger P. Exploiting multi-core parallelism with pipelining to solve skyline queries. [Internet] [Thesis]. ETH Zürich; 2013. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/154092.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bänziger P. Exploiting multi-core parallelism with pipelining to solve skyline queries. [Thesis]. ETH Zürich; 2013. Available from: http://hdl.handle.net/20.500.11850/154092

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ETH Zürich

5. Majó, Zoltán. Modeling memory system performance of NUMA multicore-multiprocessors.

Degree: 2014, ETH Zürich

Subjects/Keywords: PERFORMANCE (COMPUTER SYSTEMS); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); LEISTUNG (COMPUTERSYSTEME); SPEICHERORGANISATION + SPEICHERVERWALTUNG (BETRIEBSSYSTEME); STORAGE MANAGEMENT + MEMORY MANAGEMENT (OPERATING SYSTEMS); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Majó, Z. (2014). Modeling memory system performance of NUMA multicore-multiprocessors. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/86035

Chicago Manual of Style (16th Edition):

Majó, Zoltán. “Modeling memory system performance of NUMA multicore-multiprocessors.” 2014. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/86035.

MLA Handbook (7th Edition):

Majó, Zoltán. “Modeling memory system performance of NUMA multicore-multiprocessors.” 2014. Web. 29 Jan 2020.

Vancouver:

Majó Z. Modeling memory system performance of NUMA multicore-multiprocessors. [Internet] [Doctoral dissertation]. ETH Zürich; 2014. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/86035.

Council of Science Editors:

Majó Z. Modeling memory system performance of NUMA multicore-multiprocessors. [Doctoral Dissertation]. ETH Zürich; 2014. Available from: http://hdl.handle.net/20.500.11850/86035


ETH Zürich

6. Rinis, Ilias. Exploring scalable transactional data processing in a cluster of multicores.

Degree: 2012, ETH Zürich

Subjects/Keywords: PROZESSVERWALTUNG + PROZESSMANAGEMENT (BETRIEBSSYSTEME); PARALLELVERARBEITUNG + NEBENLÄUFIGKEIT (BETRIEBSSYSTEME); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); PROCESS MANAGEMENT (OPERATING SYSTEMS); PARALLEL PROCESSING + CONCURRENCY (OPERATING SYSTEMS); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA (6th Edition):

Rinis, I. (2012). Exploring scalable transactional data processing in a cluster of multicores. (Thesis). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/153929

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rinis, Ilias. “Exploring scalable transactional data processing in a cluster of multicores.” 2012. Thesis, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/153929.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rinis, Ilias. “Exploring scalable transactional data processing in a cluster of multicores.” 2012. Web. 29 Jan 2020.

Vancouver:

Rinis I. Exploring scalable transactional data processing in a cluster of multicores. [Internet] [Thesis]. ETH Zürich; 2012. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/153929.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rinis I. Exploring scalable transactional data processing in a cluster of multicores. [Thesis]. ETH Zürich; 2012. Available from: http://hdl.handle.net/20.500.11850/153929

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ETH Zürich

7. Wattenhofer, Roger. Distributed Counting: How to Bypass Bottlenecks.

Degree: 1998, ETH Zürich

Subjects/Keywords: PARALLELVERARBEITUNG + NEBENLÄUFIGKEIT (BETRIEBSSYSTEME); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); PARALLEL PROCESSING + CONCURRENCY (OPERATING SYSTEMS); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wattenhofer, R. (1998). Distributed Counting: How to Bypass Bottlenecks. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/143902

Chicago Manual of Style (16th Edition):

Wattenhofer, Roger. “Distributed Counting: How to Bypass Bottlenecks.” 1998. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/143902.

MLA Handbook (7th Edition):

Wattenhofer, Roger. “Distributed Counting: How to Bypass Bottlenecks.” 1998. Web. 29 Jan 2020.

Vancouver:

Wattenhofer R. Distributed Counting: How to Bypass Bottlenecks. [Internet] [Doctoral dissertation]. ETH Zürich; 1998. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/143902.

Council of Science Editors:

Wattenhofer R. Distributed Counting: How to Bypass Bottlenecks. [Doctoral Dissertation]. ETH Zürich; 1998. Available from: http://hdl.handle.net/20.500.11850/143902


ETH Zürich

8. Häcki, Roni. Consensus on a multicore machine.

Degree: 2015, ETH Zürich

Subjects/Keywords: MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); PROZESSVERWALTUNG + PROZESSMANAGEMENT (BETRIEBSSYSTEME); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); PROCESS MANAGEMENT (OPERATING SYSTEMS); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA (6th Edition):

Häcki, R. (2015). Consensus on a multicore machine. (Thesis). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/155498

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Häcki, Roni. “Consensus on a multicore machine.” 2015. Thesis, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/155498.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Häcki, Roni. “Consensus on a multicore machine.” 2015. Web. 29 Jan 2020.

Vancouver:

Häcki R. Consensus on a multicore machine. [Internet] [Thesis]. ETH Zürich; 2015. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/155498.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Häcki R. Consensus on a multicore machine. [Thesis]. ETH Zürich; 2015. Available from: http://hdl.handle.net/20.500.11850/155498

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ETH Zürich

9. Balkesen, Cagri. In-memory parallel join processing on multi-core processors.

Degree: 2014, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); PARALLELVERARBEITUNG + NEBENLÄUFIGKEIT (BETRIEBSSYSTEME); PARALLEL PROCESSORS + PARALLEL COMPUTERS + PARALLEL ARCHITECTURES (COMPUTER SYSTEMS); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); PARALLELPROZESSOREN + PARALLELCOMPUTER + PARALLELARCHITEKTUREN (COMPUTERSYSTEME); PARALLEL PROCESSING + CONCURRENCY (OPERATING SYSTEMS); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA (6th Edition):

Balkesen, C. (2014). In-memory parallel join processing on multi-core processors. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/85088

Chicago Manual of Style (16th Edition):

Balkesen, Cagri. “In-memory parallel join processing on multi-core processors.” 2014. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/85088.

MLA Handbook (7th Edition):

Balkesen, Cagri. “In-memory parallel join processing on multi-core processors.” 2014. Web. 29 Jan 2020.

Vancouver:

Balkesen C. In-memory parallel join processing on multi-core processors. [Internet] [Doctoral dissertation]. ETH Zürich; 2014. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/85088.

Council of Science Editors:

Balkesen C. In-memory parallel join processing on multi-core processors. [Doctoral Dissertation]. ETH Zürich; 2014. Available from: http://hdl.handle.net/20.500.11850/85088


ETH Zürich

10. Muller, Pieter Johannes. The active object system design and multiprocessor implementation.

Degree: 2002, ETH Zürich

Subjects/Keywords: SYSTEMANALYSE + SYSTEMENTWICKLUNG + SYSTEMENTWURF (COMPUTERSYSTEME); OBJEKTORIENTIERTE ANALYSE (SOFTWARE ENGINEERING); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); SYSTEMS ANALYSIS + SYSTEMS DEVELOPMENT + SYSTEMS DESIGN (COMPUTER SYSTEMS); OBJECT-ORIENTED ANALYSIS (SOFTWARE ENGINEERING); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Muller, P. J. (2002). The active object system design and multiprocessor implementation. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/147091

Chicago Manual of Style (16th Edition):

Muller, Pieter Johannes. “The active object system design and multiprocessor implementation.” 2002. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/147091.

MLA Handbook (7th Edition):

Muller, Pieter Johannes. “The active object system design and multiprocessor implementation.” 2002. Web. 29 Jan 2020.

Vancouver:

Muller PJ. The active object system design and multiprocessor implementation. [Internet] [Doctoral dissertation]. ETH Zürich; 2002. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/147091.

Council of Science Editors:

Muller PJ. The active object system design and multiprocessor implementation. [Doctoral Dissertation]. ETH Zürich; 2002. Available from: http://hdl.handle.net/20.500.11850/147091


ETH Zürich

11. Humbel, Lukas. Multicore Virtualization over a Multikernel.

Degree: 2013, ETH Zürich

Subjects/Keywords: PROZESSVERWALTUNG + PROZESSMANAGEMENT (BETRIEBSSYSTEME); SPEICHERORGANISATION + SPEICHERVERWALTUNG (BETRIEBSSYSTEME); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); PROCESS MANAGEMENT (OPERATING SYSTEMS); STORAGE MANAGEMENT + MEMORY MANAGEMENT (OPERATING SYSTEMS); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; Data processing, computer science; Data processing, computer science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Humbel, L. (2013). Multicore Virtualization over a Multikernel. (Thesis). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/154022

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Humbel, Lukas. “Multicore Virtualization over a Multikernel.” 2013. Thesis, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/154022.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Humbel, Lukas. “Multicore Virtualization over a Multikernel.” 2013. Web. 29 Jan 2020.

Vancouver:

Humbel L. Multicore Virtualization over a Multikernel. [Internet] [Thesis]. ETH Zürich; 2013. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/154022.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Humbel L. Multicore Virtualization over a Multikernel. [Thesis]. ETH Zürich; 2013. Available from: http://hdl.handle.net/20.500.11850/154022

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ETH Zürich

12. Cavadini, Marco. Concept and model of a multiprocessor system for high resolution image correlation.

Degree: 1999, ETH Zürich

Subjects/Keywords: DIGITALE BILDVERARBEITUNG; MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); ECHTZEITSYSTEME + EINGEBETTETE SYSTEME (COMPUTERSYSTEME); DIGITAL IMAGE PROCESSING; MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); REAL-TIME SYSTEMS + EMBEDDED SYSTEMS (COMPUTER SYSTEMS); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/621.3; Data processing, computer science; Electric engineering

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APA (6th Edition):

Cavadini, M. (1999). Concept and model of a multiprocessor system for high resolution image correlation. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/144121

Chicago Manual of Style (16th Edition):

Cavadini, Marco. “Concept and model of a multiprocessor system for high resolution image correlation.” 1999. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/144121.

MLA Handbook (7th Edition):

Cavadini, Marco. “Concept and model of a multiprocessor system for high resolution image correlation.” 1999. Web. 29 Jan 2020.

Vancouver:

Cavadini M. Concept and model of a multiprocessor system for high resolution image correlation. [Internet] [Doctoral dissertation]. ETH Zürich; 1999. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/144121.

Council of Science Editors:

Cavadini M. Concept and model of a multiprocessor system for high resolution image correlation. [Doctoral Dissertation]. ETH Zürich; 1999. Available from: http://hdl.handle.net/20.500.11850/144121


ETH Zürich

13. Stadler, Jacques. Towards dynamic threading support for OpenMP.

Degree: 2009, ETH Zürich

Subjects/Keywords: MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); VERTEILTE PROGRAMMIERUNG + PARALLELE PROGRAMMIERUNG (PROGRAMMIERMETHODEN); PROZESSVERWALTUNG + PROZESSMANAGEMENT (BETRIEBSSYSTEME); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); CONCURRENT PROGRAMMING + DISTRIBUTED PROGRAMMING + PARALLEL PROGRAMMING (PROGRAMMING METHODS); PROCESS MANAGEMENT (OPERATING SYSTEMS); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; Data processing, computer science; Data processing, computer science

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APA (6th Edition):

Stadler, J. (2009). Towards dynamic threading support for OpenMP. (Thesis). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/150926

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Stadler, Jacques. “Towards dynamic threading support for OpenMP.” 2009. Thesis, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/150926.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Stadler, Jacques. “Towards dynamic threading support for OpenMP.” 2009. Web. 29 Jan 2020.

Vancouver:

Stadler J. Towards dynamic threading support for OpenMP. [Internet] [Thesis]. ETH Zürich; 2009. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/150926.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Stadler J. Towards dynamic threading support for OpenMP. [Thesis]. ETH Zürich; 2009. Available from: http://hdl.handle.net/20.500.11850/150926

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ETH Zürich

14. Eidenbenz, Raphael. Coping with Selfishness in Distributed Systems: Mechanism Design in Multi-Core and Peer-to-Peer Systems.

Degree: 2012, ETH Zürich

Subjects/Keywords: PEER-TO-PEER NETWORKING (COMPUTER SYSTEMS); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); PROCESS MANAGEMENT (OPERATING SYSTEMS); PROZESSVERWALTUNG + PROZESSMANAGEMENT (BETRIEBSSYSTEME); PEER-TO-PEER NETWORKING (COMPUTERSYSTEME); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA (6th Edition):

Eidenbenz, R. (2012). Coping with Selfishness in Distributed Systems: Mechanism Design in Multi-Core and Peer-to-Peer Systems. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/49880

Chicago Manual of Style (16th Edition):

Eidenbenz, Raphael. “Coping with Selfishness in Distributed Systems: Mechanism Design in Multi-Core and Peer-to-Peer Systems.” 2012. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/49880.

MLA Handbook (7th Edition):

Eidenbenz, Raphael. “Coping with Selfishness in Distributed Systems: Mechanism Design in Multi-Core and Peer-to-Peer Systems.” 2012. Web. 29 Jan 2020.

Vancouver:

Eidenbenz R. Coping with Selfishness in Distributed Systems: Mechanism Design in Multi-Core and Peer-to-Peer Systems. [Internet] [Doctoral dissertation]. ETH Zürich; 2012. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/49880.

Council of Science Editors:

Eidenbenz R. Coping with Selfishness in Distributed Systems: Mechanism Design in Multi-Core and Peer-to-Peer Systems. [Doctoral Dissertation]. ETH Zürich; 2012. Available from: http://hdl.handle.net/20.500.11850/49880

15. Kaestle, Stefan. Machine-aware memory allocation and synchronization.

Degree: 2016, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); PARALLELVERARBEITUNG + NEBENLÄUFIGKEIT (BETRIEBSSYSTEME); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); SPEICHERORGANISATION + SPEICHERVERWALTUNG (BETRIEBSSYSTEME); PROCESS MANAGEMENT (OPERATING SYSTEMS); PROZESSVERWALTUNG + PROZESSMANAGEMENT (BETRIEBSSYSTEME); STORAGE MANAGEMENT + MEMORY MANAGEMENT (OPERATING SYSTEMS); PARALLEL PROCESSING + CONCURRENCY (OPERATING SYSTEMS); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA (6th Edition):

Kaestle, S. (2016). Machine-aware memory allocation and synchronization. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/126795

Chicago Manual of Style (16th Edition):

Kaestle, Stefan. “Machine-aware memory allocation and synchronization.” 2016. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/126795.

MLA Handbook (7th Edition):

Kaestle, Stefan. “Machine-aware memory allocation and synchronization.” 2016. Web. 29 Jan 2020.

Vancouver:

Kaestle S. Machine-aware memory allocation and synchronization. [Internet] [Doctoral dissertation]. ETH Zürich; 2016. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/126795.

Council of Science Editors:

Kaestle S. Machine-aware memory allocation and synchronization. [Doctoral Dissertation]. ETH Zürich; 2016. Available from: http://hdl.handle.net/20.500.11850/126795


ETH Zürich

16. Thoeni, Urban Andreas. Programming real-time multi-computers for signal processing.

Degree: 1992, ETH Zürich

Subjects/Keywords: ECHTZEITPROGRAMMIERUNG (PROGRAMMIERMETHODEN); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); SIGNALVERARBEITUNG (NACHRICHTENTECHNIK); REAL-TIME PROGRAMMING (PROGRAMMING METHODS); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); SIGNAL PROCESSING (TELECOMMUNICATIONS); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; Data processing, computer science; Data processing, computer science

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APA (6th Edition):

Thoeni, U. A. (1992). Programming real-time multi-computers for signal processing. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/140936

Chicago Manual of Style (16th Edition):

Thoeni, Urban Andreas. “Programming real-time multi-computers for signal processing.” 1992. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/140936.

MLA Handbook (7th Edition):

Thoeni, Urban Andreas. “Programming real-time multi-computers for signal processing.” 1992. Web. 29 Jan 2020.

Vancouver:

Thoeni UA. Programming real-time multi-computers for signal processing. [Internet] [Doctoral dissertation]. ETH Zürich; 1992. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/140936.

Council of Science Editors:

Thoeni UA. Programming real-time multi-computers for signal processing. [Doctoral Dissertation]. ETH Zürich; 1992. Available from: http://hdl.handle.net/20.500.11850/140936


ETH Zürich

17. Schranzhofer, Andreas. Efficiency and predictability in resource sharing multicore systems.

Degree: 2011, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); SYSTEM ON A CHIP, SOC (MIKROELEKTRONIK); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); PROCESS MANAGEMENT (OPERATING SYSTEMS); PROZESSVERWALTUNG + PROZESSMANAGEMENT (BETRIEBSSYSTEME); SYSTEM ON A CHIP, SOC (MICROELECTRONICS); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/621.3; Data processing, computer science; Electric engineering

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APA (6th Edition):

Schranzhofer, A. (2011). Efficiency and predictability in resource sharing multicore systems. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/42861

Chicago Manual of Style (16th Edition):

Schranzhofer, Andreas. “Efficiency and predictability in resource sharing multicore systems.” 2011. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/42861.

MLA Handbook (7th Edition):

Schranzhofer, Andreas. “Efficiency and predictability in resource sharing multicore systems.” 2011. Web. 29 Jan 2020.

Vancouver:

Schranzhofer A. Efficiency and predictability in resource sharing multicore systems. [Internet] [Doctoral dissertation]. ETH Zürich; 2011. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/42861.

Council of Science Editors:

Schranzhofer A. Efficiency and predictability in resource sharing multicore systems. [Doctoral Dissertation]. ETH Zürich; 2011. Available from: http://hdl.handle.net/20.500.11850/42861


ETH Zürich

18. Rai, Devendra. Temperature Aware Multiprocessing with Reliability Considerations.

Degree: 2015, ETH Zürich

Subjects/Keywords: COOLING/ELECTRICAL EQUIPMENTS, LIKE MACHINES, TRANSFORMERS, ETC. (ELECTRICAL ENGINEERING); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); KÜHLUNG/ELEKTRISCHER AUSRÜSTUNGEN, WIE MASCHINEN, TRANSFORMATOREN, USW. (ELEKTROTECHNIK); ZUVERLÄSSIGKEIT + TESTEN + FEHLERTOLERANZ (HARDWARE); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); RELIABILITY + TESTING + FAULT TOLERANCE (HARDWARE); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA (6th Edition):

Rai, D. (2015). Temperature Aware Multiprocessing with Reliability Considerations. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/106195

Chicago Manual of Style (16th Edition):

Rai, Devendra. “Temperature Aware Multiprocessing with Reliability Considerations.” 2015. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/106195.

MLA Handbook (7th Edition):

Rai, Devendra. “Temperature Aware Multiprocessing with Reliability Considerations.” 2015. Web. 29 Jan 2020.

Vancouver:

Rai D. Temperature Aware Multiprocessing with Reliability Considerations. [Internet] [Doctoral dissertation]. ETH Zürich; 2015. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/106195.

Council of Science Editors:

Rai D. Temperature Aware Multiprocessing with Reliability Considerations. [Doctoral Dissertation]. ETH Zürich; 2015. Available from: http://hdl.handle.net/20.500.11850/106195


ETH Zürich

19. Gross, Thomas. Exploiting Task-Order Information in Compilers for Shared-Memory Parallel Programs.

Degree: 2011, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); COMPILER (PROGRAMMIERSPRACHEN); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); COMPILERS (PROGRAMMING LANGUAGES); VERTEILTE PROGRAMMIERUNG + PARALLELE PROGRAMMIERUNG (PROGRAMMIERMETHODEN); CONCURRENT PROGRAMMING + DISTRIBUTED PROGRAMMING + PARALLEL PROGRAMMING (PROGRAMMING METHODS); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA (6th Edition):

Gross, T. (2011). Exploiting Task-Order Information in Compilers for Shared-Memory Parallel Programs. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/44737

Chicago Manual of Style (16th Edition):

Gross, Thomas. “Exploiting Task-Order Information in Compilers for Shared-Memory Parallel Programs.” 2011. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/44737.

MLA Handbook (7th Edition):

Gross, Thomas. “Exploiting Task-Order Information in Compilers for Shared-Memory Parallel Programs.” 2011. Web. 29 Jan 2020.

Vancouver:

Gross T. Exploiting Task-Order Information in Compilers for Shared-Memory Parallel Programs. [Internet] [Doctoral dissertation]. ETH Zürich; 2011. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/44737.

Council of Science Editors:

Gross T. Exploiting Task-Order Information in Compilers for Shared-Memory Parallel Programs. [Doctoral Dissertation]. ETH Zürich; 2011. Available from: http://hdl.handle.net/20.500.11850/44737


ETH Zürich

20. Giannopoulou, Georgia. Implementation of Mixed-Criticality Applications on Multi-Core Architectures.

Degree: 2017, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); REAL-TIME SYSTEMS + EMBEDDED SYSTEMS (COMPUTER SYSTEMS); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); ECHTZEITSYSTEME + EINGEBETTETE SYSTEME (COMPUTERSYSTEME); ZUVERLÄSSIGKEIT + FEHLERTOLERANZ (SOFTWARE ENGINEERING); RELIABILITY + FAULT-TOLERANCE (SOFTWARE ENGINEERING); SYSTEMS ANALYSIS + SYSTEMS DEVELOPMENT + SYSTEMS DESIGN (COMPUTER SYSTEMS); SYSTEMANALYSE + SYSTEMENTWICKLUNG + SYSTEMENTWURF (COMPUTERSYSTEME); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; Data processing, computer science; Data processing, computer science

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APA (6th Edition):

Giannopoulou, G. (2017). Implementation of Mixed-Criticality Applications on Multi-Core Architectures. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/125288

Chicago Manual of Style (16th Edition):

Giannopoulou, Georgia. “Implementation of Mixed-Criticality Applications on Multi-Core Architectures.” 2017. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/125288.

MLA Handbook (7th Edition):

Giannopoulou, Georgia. “Implementation of Mixed-Criticality Applications on Multi-Core Architectures.” 2017. Web. 29 Jan 2020.

Vancouver:

Giannopoulou G. Implementation of Mixed-Criticality Applications on Multi-Core Architectures. [Internet] [Doctoral dissertation]. ETH Zürich; 2017. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/125288.

Council of Science Editors:

Giannopoulou G. Implementation of Mixed-Criticality Applications on Multi-Core Architectures. [Doctoral Dissertation]. ETH Zürich; 2017. Available from: http://hdl.handle.net/20.500.11850/125288


ETH Zürich

21. Kaufmann, Helmut. Transaktionsorientierte Verwaltung und Suche von Dokumenten in einer Mehrprozessordatenbankumgebung.

Degree: 1997, ETH Zürich

Subjects/Keywords: MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); DATENBANKEN (INFORMATIONSSYSTEME); INFORMATIONSSYSTEME (INFORMATIK); INFORMATIONSSPEICHERUNG + INFORMATIONSGEWINNUNG (INFORMATIONSSYSTEME); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); DATABASES (INFORMATION SYSTEMS); INFORMATION SYSTEMS (COMPUTER SCIENCE); INFORMATION STORAGE + INFORMATION RETRIEVAL (INFORMATION SYSTEMS); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; Data processing, computer science; Data processing, computer science; Data processing, computer science

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APA (6th Edition):

Kaufmann, H. (1997). Transaktionsorientierte Verwaltung und Suche von Dokumenten in einer Mehrprozessordatenbankumgebung. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/143227

Chicago Manual of Style (16th Edition):

Kaufmann, Helmut. “Transaktionsorientierte Verwaltung und Suche von Dokumenten in einer Mehrprozessordatenbankumgebung.” 1997. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/143227.

MLA Handbook (7th Edition):

Kaufmann, Helmut. “Transaktionsorientierte Verwaltung und Suche von Dokumenten in einer Mehrprozessordatenbankumgebung.” 1997. Web. 29 Jan 2020.

Vancouver:

Kaufmann H. Transaktionsorientierte Verwaltung und Suche von Dokumenten in einer Mehrprozessordatenbankumgebung. [Internet] [Doctoral dissertation]. ETH Zürich; 1997. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/143227.

Council of Science Editors:

Kaufmann H. Transaktionsorientierte Verwaltung und Suche von Dokumenten in einer Mehrprozessordatenbankumgebung. [Doctoral Dissertation]. ETH Zürich; 1997. Available from: http://hdl.handle.net/20.500.11850/143227


ETH Zürich

22. Huang, Kai. Towards Many-Core Real-Time Embedded Systems: Software Design of Streaming Systems at System Level.

Degree: 2010, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); REAL-TIME SYSTEMS + EMBEDDED SYSTEMS (COMPUTER SYSTEMS); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); ECHTZEITSYSTEME + EINGEBETTETE SYSTEME (COMPUTERSYSTEME); SYSTEMPROGRAMMIERUNG (BETRIEBSSYSTEME); SYSTEMS PROGRAMMING (OPERATING SYSTEMS); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; Data processing, computer science; Data processing, computer science

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APA (6th Edition):

Huang, K. (2010). Towards Many-Core Real-Time Embedded Systems: Software Design of Streaming Systems at System Level. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/27972

Chicago Manual of Style (16th Edition):

Huang, Kai. “Towards Many-Core Real-Time Embedded Systems: Software Design of Streaming Systems at System Level.” 2010. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/27972.

MLA Handbook (7th Edition):

Huang, Kai. “Towards Many-Core Real-Time Embedded Systems: Software Design of Streaming Systems at System Level.” 2010. Web. 29 Jan 2020.

Vancouver:

Huang K. Towards Many-Core Real-Time Embedded Systems: Software Design of Streaming Systems at System Level. [Internet] [Doctoral dissertation]. ETH Zürich; 2010. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/27972.

Council of Science Editors:

Huang K. Towards Many-Core Real-Time Embedded Systems: Software Design of Streaming Systems at System Level. [Doctoral Dissertation]. ETH Zürich; 2010. Available from: http://hdl.handle.net/20.500.11850/27972


ETH Zürich

23. Schor, Lars U. Programming Framework for Reliable and Efficient Embedded Many-Core Systems.

Degree: 2014, ETH Zürich

Subjects/Keywords: PROGRAMMING ENVIRONMENTS (SOFTWARE ENGINEERING); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); REAL-TIME SYSTEMS + EMBEDDED SYSTEMS (OPERATING SYSTEMS); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); ECHTZEITSYSTEME + EINGEBETTETE SYSTEME (BETRIEBSSYSTEME); VERTEILTE PROGRAMMIERUNG + PARALLELE PROGRAMMIERUNG (PROGRAMMIERMETHODEN); CONCURRENT PROGRAMMING + DISTRIBUTED PROGRAMMING + PARALLEL PROGRAMMING (PROGRAMMING METHODS); PROGRAMMIERUMGEBUNGEN (SOFTWARE ENGINEERING); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; Data processing, computer science; Data processing, computer science

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APA (6th Edition):

Schor, L. U. (2014). Programming Framework for Reliable and Efficient Embedded Many-Core Systems. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/94206

Chicago Manual of Style (16th Edition):

Schor, Lars U. “Programming Framework for Reliable and Efficient Embedded Many-Core Systems.” 2014. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/94206.

MLA Handbook (7th Edition):

Schor, Lars U. “Programming Framework for Reliable and Efficient Embedded Many-Core Systems.” 2014. Web. 29 Jan 2020.

Vancouver:

Schor LU. Programming Framework for Reliable and Efficient Embedded Many-Core Systems. [Internet] [Doctoral dissertation]. ETH Zürich; 2014. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/94206.

Council of Science Editors:

Schor LU. Programming Framework for Reliable and Efficient Embedded Many-Core Systems. [Doctoral Dissertation]. ETH Zürich; 2014. Available from: http://hdl.handle.net/20.500.11850/94206


ETH Zürich

24. Fasnacht, Daniel Bernhard. Experimentation Platforms for Neuromorphic Event-Based Multi-Chip Systems.

Degree: 2016, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); NEURAL NETWORKS + NEUROMORPHIC SYSTEMS (NEUROLOGY); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); NEURONALE NETZWERKE + NEUROMORPHE SYSTEME (NEUROLOGIE); NEURONALE NETZWERKE (COMPUTERSYSTEME); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); NEURAL NETWORKS (COMPUTER SYSTEMS); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; Data processing, computer science; Data processing, computer science

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APA (6th Edition):

Fasnacht, D. B. (2016). Experimentation Platforms for Neuromorphic Event-Based Multi-Chip Systems. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/123065

Chicago Manual of Style (16th Edition):

Fasnacht, Daniel Bernhard. “Experimentation Platforms for Neuromorphic Event-Based Multi-Chip Systems.” 2016. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/123065.

MLA Handbook (7th Edition):

Fasnacht, Daniel Bernhard. “Experimentation Platforms for Neuromorphic Event-Based Multi-Chip Systems.” 2016. Web. 29 Jan 2020.

Vancouver:

Fasnacht DB. Experimentation Platforms for Neuromorphic Event-Based Multi-Chip Systems. [Internet] [Doctoral dissertation]. ETH Zürich; 2016. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/123065.

Council of Science Editors:

Fasnacht DB. Experimentation Platforms for Neuromorphic Event-Based Multi-Chip Systems. [Doctoral Dissertation]. ETH Zürich; 2016. Available from: http://hdl.handle.net/20.500.11850/123065


ETH Zürich

25. Negele, Florian. Combining Lock-Free Programming with Cooperative Multitasking for a Portable Multiprocessor Runtime System.

Degree: 2014, ETH Zürich

Subjects/Keywords: SPEZIELLE PROGRAMMIERMETHODEN; MEHRPROGRAMMBETRIEB (BETRIEBSSYSTEME); RECHENZEIT + LAUFZEIT (COMPUTERSYSTEME); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); CD-ROM (DOKUMENTENTYP); SPECIAL PROGRAMMING METHODS; MULTIPROCESSING + MULTIPROGRAMMING + MULTITASKING (OPERATING SYSTEMS); COMPUTING TIME + RUNNING TIME (COMPUTER SYSTEMS); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); CD-ROM (DOCUMENT TYPES); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; Data processing, computer science; Data processing, computer science

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APA (6th Edition):

Negele, F. (2014). Combining Lock-Free Programming with Cooperative Multitasking for a Portable Multiprocessor Runtime System. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/154828

Chicago Manual of Style (16th Edition):

Negele, Florian. “Combining Lock-Free Programming with Cooperative Multitasking for a Portable Multiprocessor Runtime System.” 2014. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/154828.

MLA Handbook (7th Edition):

Negele, Florian. “Combining Lock-Free Programming with Cooperative Multitasking for a Portable Multiprocessor Runtime System.” 2014. Web. 29 Jan 2020.

Vancouver:

Negele F. Combining Lock-Free Programming with Cooperative Multitasking for a Portable Multiprocessor Runtime System. [Internet] [Doctoral dissertation]. ETH Zürich; 2014. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/154828.

Council of Science Editors:

Negele F. Combining Lock-Free Programming with Cooperative Multitasking for a Portable Multiprocessor Runtime System. [Doctoral Dissertation]. ETH Zürich; 2014. Available from: http://hdl.handle.net/20.500.11850/154828


ETH Zürich

26. Baasch, Thierry. Computing Large-Scale Non-Smooth Dynamics on the GPU.

Degree: 2014, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); PARALLELVERARBEITUNG + NEBENLÄUFIGKEIT (BETRIEBSSYSTEME); NICHTLINEARE DYNAMISCHE SYSTEME (ANALYSIS); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); NONLINEAR DYNAMICAL SYSTEMS (MATHEMATICAL ANALYSIS); VERTEILTE PROGRAMMIERUNG + PARALLELE PROGRAMMIERUNG (PROGRAMMIERMETHODEN); COMPUTERSIMULATION; RELATIVE MOTION OF SYSTEMS OF SOLID BODIES, MANY-BODY PROBLEMS (MECHANICS); COMPUTER SIMULATION; PARALLEL PROCESSING + CONCURRENCY (OPERATING SYSTEMS); CONCURRENT PROGRAMMING + DISTRIBUTED PROGRAMMING + PARALLEL PROGRAMMING (PROGRAMMING METHODS); RELATIVBEWEGUNGEN VON SYSTEMEN FESTER KÖRPER, VIELKÖRPERPROBLEME (MECHANIK); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Baasch, T. (2014). Computing Large-Scale Non-Smooth Dynamics on the GPU. (Thesis). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/112778

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Baasch, Thierry. “Computing Large-Scale Non-Smooth Dynamics on the GPU.” 2014. Thesis, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/112778.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Baasch, Thierry. “Computing Large-Scale Non-Smooth Dynamics on the GPU.” 2014. Web. 29 Jan 2020.

Vancouver:

Baasch T. Computing Large-Scale Non-Smooth Dynamics on the GPU. [Internet] [Thesis]. ETH Zürich; 2014. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/112778.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Baasch T. Computing Large-Scale Non-Smooth Dynamics on the GPU. [Thesis]. ETH Zürich; 2014. Available from: http://hdl.handle.net/20.500.11850/112778

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ETH Zürich

27. Rossinelli, Diego. Multiresolution Flow Simulations on Multi/Many-Core Architectures.

Degree: 2011, ETH Zürich

Subjects/Keywords: COMPUTATIONAL FLUID DYNAMICS (FLUIDMECHANIK); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); NAVIER-STOKES EQUATION (FLUID DYNAMICS); VERTEILTE PROGRAMMIERUNG + PARALLELE PROGRAMMIERUNG (PROGRAMMIERMETHODEN); NAVIER-STOKES GLEICHUNG (FLUIDDYNAMIK); COMPUTATIONAL FLUID DYNAMICS (FLUID MECHANICS); MEHRGITTERVERFAHREN + GITTERERZEUGUNG (NUMERISCHE MATHEMATIK); CONCURRENT PROGRAMMING + DISTRIBUTED PROGRAMMING + PARALLEL PROGRAMMING (PROGRAMMING METHODS); MULTIGRID METHODS + GRID GENERATION (NUMERICAL MATHEMATICS); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/530; Data processing, computer science; Data processing, computer science; Physics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rossinelli, D. (2011). Multiresolution Flow Simulations on Multi/Many-Core Architectures. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/72890

Chicago Manual of Style (16th Edition):

Rossinelli, Diego. “Multiresolution Flow Simulations on Multi/Many-Core Architectures.” 2011. Doctoral Dissertation, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/72890.

MLA Handbook (7th Edition):

Rossinelli, Diego. “Multiresolution Flow Simulations on Multi/Many-Core Architectures.” 2011. Web. 29 Jan 2020.

Vancouver:

Rossinelli D. Multiresolution Flow Simulations on Multi/Many-Core Architectures. [Internet] [Doctoral dissertation]. ETH Zürich; 2011. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/72890.

Council of Science Editors:

Rossinelli D. Multiresolution Flow Simulations on Multi/Many-Core Architectures. [Doctoral Dissertation]. ETH Zürich; 2011. Available from: http://hdl.handle.net/20.500.11850/72890

28. Wang, Jingyi. Performance Analysis of Decision Tree Learning Algorithms on Multicore CPUs.

Degree: 2016, ETH Zürich

Subjects/Keywords: PROBLEMLÖSEN + PLANEN + SUCHEN (KÜNSTLICHE INTELLIGENZ); MASCHINELLES LERNEN (KÜNSTLICHE INTELLIGENZ); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); PROBLEM SOLVING + PLAN GENERATION + SEARCH (ARTIFICIAL INTELLIGENCE); MACHINE LEARNING (ARTIFICIAL INTELLIGENCE); MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; Data processing, computer science; Data processing, computer science

computer vision as input data and received a speedup of 8x in the decision tree training phase… …up and Test Data . 4.3.2 Results . . . . . . . . . . . . . . . Conclusion… …the attribute lists of a node . . . . . . . . . . . . . . . . . . . . . Data distribution in… …total execution time of sequential algorithms. This includes data loading, pre-sorting and… …write idx, assuming that there are two child nodes. (a) Each thread takes a data… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, J. (2016). Performance Analysis of Decision Tree Learning Algorithms on Multicore CPUs. (Thesis). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/156117

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Jingyi. “Performance Analysis of Decision Tree Learning Algorithms on Multicore CPUs.” 2016. Thesis, ETH Zürich. Accessed January 29, 2020. http://hdl.handle.net/20.500.11850/156117.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Jingyi. “Performance Analysis of Decision Tree Learning Algorithms on Multicore CPUs.” 2016. Web. 29 Jan 2020.

Vancouver:

Wang J. Performance Analysis of Decision Tree Learning Algorithms on Multicore CPUs. [Internet] [Thesis]. ETH Zürich; 2016. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/20.500.11850/156117.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang J. Performance Analysis of Decision Tree Learning Algorithms on Multicore CPUs. [Thesis]. ETH Zürich; 2016. Available from: http://hdl.handle.net/20.500.11850/156117

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

29. Si, Wenpei. Additive synchronous stream ciphers.

Degree: 2012, Hong Kong University of Science and Technology

 Both stream ciphers and block ciphers can be used to provide data confidentiality service. Stream ciphers are preferred in many applications, since they can destroy… (more)

Subjects/Keywords: Stream ciphers ; Data encryption (Computer science) ; Synchronous data transmission systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Si, W. (2012). Additive synchronous stream ciphers. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-7572 ; https://doi.org/10.14711/thesis-b1180147 ; http://repository.ust.hk/ir/bitstream/1783.1-7572/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Si, Wenpei. “Additive synchronous stream ciphers.” 2012. Thesis, Hong Kong University of Science and Technology. Accessed January 29, 2020. http://repository.ust.hk/ir/Record/1783.1-7572 ; https://doi.org/10.14711/thesis-b1180147 ; http://repository.ust.hk/ir/bitstream/1783.1-7572/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Si, Wenpei. “Additive synchronous stream ciphers.” 2012. Web. 29 Jan 2020.

Vancouver:

Si W. Additive synchronous stream ciphers. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2012. [cited 2020 Jan 29]. Available from: http://repository.ust.hk/ir/Record/1783.1-7572 ; https://doi.org/10.14711/thesis-b1180147 ; http://repository.ust.hk/ir/bitstream/1783.1-7572/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Si W. Additive synchronous stream ciphers. [Thesis]. Hong Kong University of Science and Technology; 2012. Available from: http://repository.ust.hk/ir/Record/1783.1-7572 ; https://doi.org/10.14711/thesis-b1180147 ; http://repository.ust.hk/ir/bitstream/1783.1-7572/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Portland State University

30. Howard, Philip William. Extending Relativistic Programming to Multiple Writers.

Degree: PhD, Computer Science, 2012, Portland State University

  For software to take advantage of modern multicore processors, it must be safely concurrent and it must scale. Many techniques that allow safe concurrency… (more)

Subjects/Keywords: Concurrency; Relativistic programming; Data structures; Synchronization; Multicore; Multiprocessors  – Programming; Systems programming (Computer science); Parallel programming (Computer science)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Howard, P. W. (2012). Extending Relativistic Programming to Multiple Writers. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/114

Chicago Manual of Style (16th Edition):

Howard, Philip William. “Extending Relativistic Programming to Multiple Writers.” 2012. Doctoral Dissertation, Portland State University. Accessed January 29, 2020. https://pdxscholar.library.pdx.edu/open_access_etds/114.

MLA Handbook (7th Edition):

Howard, Philip William. “Extending Relativistic Programming to Multiple Writers.” 2012. Web. 29 Jan 2020.

Vancouver:

Howard PW. Extending Relativistic Programming to Multiple Writers. [Internet] [Doctoral dissertation]. Portland State University; 2012. [cited 2020 Jan 29]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/114.

Council of Science Editors:

Howard PW. Extending Relativistic Programming to Multiple Writers. [Doctoral Dissertation]. Portland State University; 2012. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/114

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