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You searched for subject:(MOSFETs). Showing records 1 – 30 of 89 total matches.

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Penn State University

1. Mo, Chen. Electrical and temperature stress effects on power Mosfets.

Degree: 2015, Penn State University

 High electrical field and high temperature stresses are the two main factors that are critical in determining power metal-oxide-Si field effect transistor’s (MOSFET’s) reliability and… (more)

Subjects/Keywords: Electrical stress; temperature stress; Power MOSFETs

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mo, C. (2015). Electrical and temperature stress effects on power Mosfets. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/24986

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mo, Chen. “Electrical and temperature stress effects on power Mosfets.” 2015. Thesis, Penn State University. Accessed September 29, 2020. https://submit-etda.libraries.psu.edu/catalog/24986.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mo, Chen. “Electrical and temperature stress effects on power Mosfets.” 2015. Web. 29 Sep 2020.

Vancouver:

Mo C. Electrical and temperature stress effects on power Mosfets. [Internet] [Thesis]. Penn State University; 2015. [cited 2020 Sep 29]. Available from: https://submit-etda.libraries.psu.edu/catalog/24986.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mo C. Electrical and temperature stress effects on power Mosfets. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/24986

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

2. Gangadharan, Divya. Simulation Study of Device Characteristics and Short Channel Effects of Nanoscale Germanium Channel Double-Gate MOSFETs.

Degree: MS, Engineering : Electrical Engineering, 2008, University of Cincinnati

 In the endeavor to increase integrated circuit chip densities and improve performance, MOSFET dimensions have been rapidly decreasing over the past four decades. In the… (more)

Subjects/Keywords: Electrical Engineering; Engineering; MOSFETs; Germanium; double-gate

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APA (6th Edition):

Gangadharan, D. (2008). Simulation Study of Device Characteristics and Short Channel Effects of Nanoscale Germanium Channel Double-Gate MOSFETs. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1226530654

Chicago Manual of Style (16th Edition):

Gangadharan, Divya. “Simulation Study of Device Characteristics and Short Channel Effects of Nanoscale Germanium Channel Double-Gate MOSFETs.” 2008. Masters Thesis, University of Cincinnati. Accessed September 29, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1226530654.

MLA Handbook (7th Edition):

Gangadharan, Divya. “Simulation Study of Device Characteristics and Short Channel Effects of Nanoscale Germanium Channel Double-Gate MOSFETs.” 2008. Web. 29 Sep 2020.

Vancouver:

Gangadharan D. Simulation Study of Device Characteristics and Short Channel Effects of Nanoscale Germanium Channel Double-Gate MOSFETs. [Internet] [Masters thesis]. University of Cincinnati; 2008. [cited 2020 Sep 29]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1226530654.

Council of Science Editors:

Gangadharan D. Simulation Study of Device Characteristics and Short Channel Effects of Nanoscale Germanium Channel Double-Gate MOSFETs. [Masters Thesis]. University of Cincinnati; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1226530654


NSYSU

3. Kuo, Yuan-Jui. Electrical Properties and Physical Mechanisms of Advanced MOSFETs.

Degree: PhD, Electro-Optical Engineering, 2010, NSYSU

 In this thesis, we investigate the electrical properties and reliability of novel metal-oxide-semiconductor field-effect transistors (MOSFETs) for 65 nm technology node and below. Roughly, we… (more)

Subjects/Keywords: MOSFETs; metal gate; strained silicon; high-k

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APA (6th Edition):

Kuo, Y. (2010). Electrical Properties and Physical Mechanisms of Advanced MOSFETs. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1220110-174355

Chicago Manual of Style (16th Edition):

Kuo, Yuan-Jui. “Electrical Properties and Physical Mechanisms of Advanced MOSFETs.” 2010. Doctoral Dissertation, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1220110-174355.

MLA Handbook (7th Edition):

Kuo, Yuan-Jui. “Electrical Properties and Physical Mechanisms of Advanced MOSFETs.” 2010. Web. 29 Sep 2020.

Vancouver:

Kuo Y. Electrical Properties and Physical Mechanisms of Advanced MOSFETs. [Internet] [Doctoral dissertation]. NSYSU; 2010. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1220110-174355.

Council of Science Editors:

Kuo Y. Electrical Properties and Physical Mechanisms of Advanced MOSFETs. [Doctoral Dissertation]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1220110-174355


NSYSU

4. Liu, Kuan-Ju. Physical Mechanism and Reliability Analysis on Advanced SOI MOSFETs and FinFETs.

Degree: PhD, Physics, 2016, NSYSU

 Recently, electronic products combining display panels, memory devices, and portable devices have become more popular for consumers. These electronic products are mostly composed of metal-oxide-semiconductor… (more)

Subjects/Keywords: SOI; MOSFETs; PBS; hot carrier degradation; FinFETs

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APA (6th Edition):

Liu, K. (2016). Physical Mechanism and Reliability Analysis on Advanced SOI MOSFETs and FinFETs. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0708116-115120

Chicago Manual of Style (16th Edition):

Liu, Kuan-Ju. “Physical Mechanism and Reliability Analysis on Advanced SOI MOSFETs and FinFETs.” 2016. Doctoral Dissertation, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0708116-115120.

MLA Handbook (7th Edition):

Liu, Kuan-Ju. “Physical Mechanism and Reliability Analysis on Advanced SOI MOSFETs and FinFETs.” 2016. Web. 29 Sep 2020.

Vancouver:

Liu K. Physical Mechanism and Reliability Analysis on Advanced SOI MOSFETs and FinFETs. [Internet] [Doctoral dissertation]. NSYSU; 2016. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0708116-115120.

Council of Science Editors:

Liu K. Physical Mechanism and Reliability Analysis on Advanced SOI MOSFETs and FinFETs. [Doctoral Dissertation]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0708116-115120


NSYSU

5. Eng, Yi-Chuen. A Study of Additional-Body Effects in Isolation-Last Quasi-SOI MOSFETs.

Degree: PhD, Electrical Engineering, 2012, NSYSU

 As semiconductor device sizes continue to decrease, the traditional bulk CMOS technology is seen as an obstacle itself by the physical device limitations. One of… (more)

Subjects/Keywords: ZBO; ABEs; isolation-last; QSOI MOSFETs; BO

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APA (6th Edition):

Eng, Y. (2012). A Study of Additional-Body Effects in Isolation-Last Quasi-SOI MOSFETs. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-105314

Chicago Manual of Style (16th Edition):

Eng, Yi-Chuen. “A Study of Additional-Body Effects in Isolation-Last Quasi-SOI MOSFETs.” 2012. Doctoral Dissertation, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-105314.

MLA Handbook (7th Edition):

Eng, Yi-Chuen. “A Study of Additional-Body Effects in Isolation-Last Quasi-SOI MOSFETs.” 2012. Web. 29 Sep 2020.

Vancouver:

Eng Y. A Study of Additional-Body Effects in Isolation-Last Quasi-SOI MOSFETs. [Internet] [Doctoral dissertation]. NSYSU; 2012. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-105314.

Council of Science Editors:

Eng Y. A Study of Additional-Body Effects in Isolation-Last Quasi-SOI MOSFETs. [Doctoral Dissertation]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-105314


Virginia Tech

6. Wang , Wei. Power Module with Series-connected MOSFETs in Flip-chip Configuration.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 Power module design is needed for high system performance and reliability, especially in terms of high efficiency and high power density. Low parasitic impedance and… (more)

Subjects/Keywords: Power module; Series-connected power MOSFETs

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APA (6th Edition):

Wang , W. (2010). Power Module with Series-connected MOSFETs in Flip-chip Configuration. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36036

Chicago Manual of Style (16th Edition):

Wang , Wei. “Power Module with Series-connected MOSFETs in Flip-chip Configuration.” 2010. Masters Thesis, Virginia Tech. Accessed September 29, 2020. http://hdl.handle.net/10919/36036.

MLA Handbook (7th Edition):

Wang , Wei. “Power Module with Series-connected MOSFETs in Flip-chip Configuration.” 2010. Web. 29 Sep 2020.

Vancouver:

Wang W. Power Module with Series-connected MOSFETs in Flip-chip Configuration. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Sep 29]. Available from: http://hdl.handle.net/10919/36036.

Council of Science Editors:

Wang W. Power Module with Series-connected MOSFETs in Flip-chip Configuration. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/36036


University of Minnesota

7. Robbins, Matthew. Engineering Novel Transistors Based On Black Phosphorus.

Degree: PhD, Electrical Engineering, 2019, University of Minnesota

 Black phosphorus (BP), a layered 2D semiconductor that can be isolated to one monolayer thicknesses re-emerged in 2014 because of its promise for use in… (more)

Subjects/Keywords: 2D materials; black phosphorus; MOSFETs; TFETs

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APA (6th Edition):

Robbins, M. (2019). Engineering Novel Transistors Based On Black Phosphorus. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/213127

Chicago Manual of Style (16th Edition):

Robbins, Matthew. “Engineering Novel Transistors Based On Black Phosphorus.” 2019. Doctoral Dissertation, University of Minnesota. Accessed September 29, 2020. http://hdl.handle.net/11299/213127.

MLA Handbook (7th Edition):

Robbins, Matthew. “Engineering Novel Transistors Based On Black Phosphorus.” 2019. Web. 29 Sep 2020.

Vancouver:

Robbins M. Engineering Novel Transistors Based On Black Phosphorus. [Internet] [Doctoral dissertation]. University of Minnesota; 2019. [cited 2020 Sep 29]. Available from: http://hdl.handle.net/11299/213127.

Council of Science Editors:

Robbins M. Engineering Novel Transistors Based On Black Phosphorus. [Doctoral Dissertation]. University of Minnesota; 2019. Available from: http://hdl.handle.net/11299/213127


University of Toronto

8. Wang, Hao. Power MOSFETs with Enhanced Electrical Characteristics.

Degree: 2009, University of Toronto

The integration of high voltage power transistors with control circuitry to form smart Power Integrated Circuits (PIC) has numerous applications in the areas of industrial… (more)

Subjects/Keywords: Power MOSFETs; 0794

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APA (6th Edition):

Wang, H. (2009). Power MOSFETs with Enhanced Electrical Characteristics. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/24329

Chicago Manual of Style (16th Edition):

Wang, Hao. “Power MOSFETs with Enhanced Electrical Characteristics.” 2009. Doctoral Dissertation, University of Toronto. Accessed September 29, 2020. http://hdl.handle.net/1807/24329.

MLA Handbook (7th Edition):

Wang, Hao. “Power MOSFETs with Enhanced Electrical Characteristics.” 2009. Web. 29 Sep 2020.

Vancouver:

Wang H. Power MOSFETs with Enhanced Electrical Characteristics. [Internet] [Doctoral dissertation]. University of Toronto; 2009. [cited 2020 Sep 29]. Available from: http://hdl.handle.net/1807/24329.

Council of Science Editors:

Wang H. Power MOSFETs with Enhanced Electrical Characteristics. [Doctoral Dissertation]. University of Toronto; 2009. Available from: http://hdl.handle.net/1807/24329


University of New Mexico

9. Ghosh, Swapnadip. LARGE-AREA, WAFER-SCALE EPITAXIAL GROWTH OF GERMANIUM ON SILICON AND INTEGRATION OF HIGH-PERFORMANCE TRANSISTORS.

Degree: Electrical and Computer Engineering, 2015, University of New Mexico

 Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In… (more)

Subjects/Keywords: Germanium; Silicon; Epitaxy; MOSFETs; Quantum Dots

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APA (6th Edition):

Ghosh, S. (2015). LARGE-AREA, WAFER-SCALE EPITAXIAL GROWTH OF GERMANIUM ON SILICON AND INTEGRATION OF HIGH-PERFORMANCE TRANSISTORS. (Doctoral Dissertation). University of New Mexico. Retrieved from http://hdl.handle.net/1928/25778

Chicago Manual of Style (16th Edition):

Ghosh, Swapnadip. “LARGE-AREA, WAFER-SCALE EPITAXIAL GROWTH OF GERMANIUM ON SILICON AND INTEGRATION OF HIGH-PERFORMANCE TRANSISTORS.” 2015. Doctoral Dissertation, University of New Mexico. Accessed September 29, 2020. http://hdl.handle.net/1928/25778.

MLA Handbook (7th Edition):

Ghosh, Swapnadip. “LARGE-AREA, WAFER-SCALE EPITAXIAL GROWTH OF GERMANIUM ON SILICON AND INTEGRATION OF HIGH-PERFORMANCE TRANSISTORS.” 2015. Web. 29 Sep 2020.

Vancouver:

Ghosh S. LARGE-AREA, WAFER-SCALE EPITAXIAL GROWTH OF GERMANIUM ON SILICON AND INTEGRATION OF HIGH-PERFORMANCE TRANSISTORS. [Internet] [Doctoral dissertation]. University of New Mexico; 2015. [cited 2020 Sep 29]. Available from: http://hdl.handle.net/1928/25778.

Council of Science Editors:

Ghosh S. LARGE-AREA, WAFER-SCALE EPITAXIAL GROWTH OF GERMANIUM ON SILICON AND INTEGRATION OF HIGH-PERFORMANCE TRANSISTORS. [Doctoral Dissertation]. University of New Mexico; 2015. Available from: http://hdl.handle.net/1928/25778


University of South Carolina

10. Eskandari, Soheila. Modeling and Loss Analysis of SiC Power Semiconductor Devices for Switching Converter Applications.

Degree: PhD, Electrical Engineering, 2019, University of South Carolina

  Since its inception, power electronics has been to a large extent driven by the available power semiconductor devices. Switching power converter topologies, modes of… (more)

Subjects/Keywords: Electrical and Computer Engineering; Engineering; SiC MOSFETs

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APA (6th Edition):

Eskandari, S. (2019). Modeling and Loss Analysis of SiC Power Semiconductor Devices for Switching Converter Applications. (Doctoral Dissertation). University of South Carolina. Retrieved from https://scholarcommons.sc.edu/etd/5124

Chicago Manual of Style (16th Edition):

Eskandari, Soheila. “Modeling and Loss Analysis of SiC Power Semiconductor Devices for Switching Converter Applications.” 2019. Doctoral Dissertation, University of South Carolina. Accessed September 29, 2020. https://scholarcommons.sc.edu/etd/5124.

MLA Handbook (7th Edition):

Eskandari, Soheila. “Modeling and Loss Analysis of SiC Power Semiconductor Devices for Switching Converter Applications.” 2019. Web. 29 Sep 2020.

Vancouver:

Eskandari S. Modeling and Loss Analysis of SiC Power Semiconductor Devices for Switching Converter Applications. [Internet] [Doctoral dissertation]. University of South Carolina; 2019. [cited 2020 Sep 29]. Available from: https://scholarcommons.sc.edu/etd/5124.

Council of Science Editors:

Eskandari S. Modeling and Loss Analysis of SiC Power Semiconductor Devices for Switching Converter Applications. [Doctoral Dissertation]. University of South Carolina; 2019. Available from: https://scholarcommons.sc.edu/etd/5124


Louisiana State University

11. Subramanian, Sowmya. Ternary logic to binary bit conversion using multiple input floating gate MOSFETS in 0.5 micron n-well CMOS technology.

Degree: MSEE, Electrical and Computer Engineering, 2005, Louisiana State University

 In the present work, a CMOS ternary to binary bit conversion technique has been proposed using multiple input floating gate MOSFETs. The proposed circuit has… (more)

Subjects/Keywords: CMOS; MOSFETs; PSPICE

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APA (6th Edition):

Subramanian, S. (2005). Ternary logic to binary bit conversion using multiple input floating gate MOSFETS in 0.5 micron n-well CMOS technology. (Masters Thesis). Louisiana State University. Retrieved from etd-11162005-134520 ; https://digitalcommons.lsu.edu/gradschool_theses/86

Chicago Manual of Style (16th Edition):

Subramanian, Sowmya. “Ternary logic to binary bit conversion using multiple input floating gate MOSFETS in 0.5 micron n-well CMOS technology.” 2005. Masters Thesis, Louisiana State University. Accessed September 29, 2020. etd-11162005-134520 ; https://digitalcommons.lsu.edu/gradschool_theses/86.

MLA Handbook (7th Edition):

Subramanian, Sowmya. “Ternary logic to binary bit conversion using multiple input floating gate MOSFETS in 0.5 micron n-well CMOS technology.” 2005. Web. 29 Sep 2020.

Vancouver:

Subramanian S. Ternary logic to binary bit conversion using multiple input floating gate MOSFETS in 0.5 micron n-well CMOS technology. [Internet] [Masters thesis]. Louisiana State University; 2005. [cited 2020 Sep 29]. Available from: etd-11162005-134520 ; https://digitalcommons.lsu.edu/gradschool_theses/86.

Council of Science Editors:

Subramanian S. Ternary logic to binary bit conversion using multiple input floating gate MOSFETS in 0.5 micron n-well CMOS technology. [Masters Thesis]. Louisiana State University; 2005. Available from: etd-11162005-134520 ; https://digitalcommons.lsu.edu/gradschool_theses/86


Ohio University

12. Ting, Darwin Ta-Yueh. Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs.

Degree: MS, Electrical Engineering (Engineering and Technology), 2008, Ohio University

  The physical dimensions of bulk MOSFETs have been aggressively scaled down and these conventional devices will soon be experiencing limited improvements due to the… (more)

Subjects/Keywords: Electrical Engineering; VLSI; digital circuits; double-gate MOSFETs; threshold logic gates; SOI MOSFETs

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APA (6th Edition):

Ting, D. T. (2008). Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs. (Masters Thesis). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300

Chicago Manual of Style (16th Edition):

Ting, Darwin Ta-Yueh. “Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs.” 2008. Masters Thesis, Ohio University. Accessed September 29, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300.

MLA Handbook (7th Edition):

Ting, Darwin Ta-Yueh. “Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs.” 2008. Web. 29 Sep 2020.

Vancouver:

Ting DT. Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs. [Internet] [Masters thesis]. Ohio University; 2008. [cited 2020 Sep 29]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300.

Council of Science Editors:

Ting DT. Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs. [Masters Thesis]. Ohio University; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300


Université de Sherbrooke

13. Ridaoui, Mohamed. Fabrication et caractérisation de MOSFET III-V à faible bande interdite et canal ultra mince.

Degree: 2017, Université de Sherbrooke

 Abstract : Silicon-based devices dominate the semiconductor industry because of the low cost of this material, its technology availability and maturity. However, silicon has physical… (more)

Subjects/Keywords: Matériaux III-V (petit gap); MOSFETs; Ultra-thin body (UTB); Al2O3; Ni/III-V; Hyperfréquence; III-V material; MOSFETS; High frequency

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APA (6th Edition):

Ridaoui, M. (2017). Fabrication et caractérisation de MOSFET III-V à faible bande interdite et canal ultra mince. (Doctoral Dissertation). Université de Sherbrooke. Retrieved from http://hdl.handle.net/11143/11118

Chicago Manual of Style (16th Edition):

Ridaoui, Mohamed. “Fabrication et caractérisation de MOSFET III-V à faible bande interdite et canal ultra mince.” 2017. Doctoral Dissertation, Université de Sherbrooke. Accessed September 29, 2020. http://hdl.handle.net/11143/11118.

MLA Handbook (7th Edition):

Ridaoui, Mohamed. “Fabrication et caractérisation de MOSFET III-V à faible bande interdite et canal ultra mince.” 2017. Web. 29 Sep 2020.

Vancouver:

Ridaoui M. Fabrication et caractérisation de MOSFET III-V à faible bande interdite et canal ultra mince. [Internet] [Doctoral dissertation]. Université de Sherbrooke; 2017. [cited 2020 Sep 29]. Available from: http://hdl.handle.net/11143/11118.

Council of Science Editors:

Ridaoui M. Fabrication et caractérisation de MOSFET III-V à faible bande interdite et canal ultra mince. [Doctoral Dissertation]. Université de Sherbrooke; 2017. Available from: http://hdl.handle.net/11143/11118

14. Wu, Jianzhi. Analytic modeling of tunnel Field-Effect-Transistors and experimental investigation of GaN High-Electron-Mobility-Transistors.

Degree: Electrical Engineering (Applied Physics), 2016, University of California – San Diego

 High density and lower power drive the aggressive scaling down of CMOS transistors. Yet, the scaling of Si bulk MOSFETs are approaching physical limits, suffering… (more)

Subjects/Keywords: Electrical engineering; device physics; Modeling; MOSFETs; Quantum tunneling; semiconductor device

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APA (6th Edition):

Wu, J. (2016). Analytic modeling of tunnel Field-Effect-Transistors and experimental investigation of GaN High-Electron-Mobility-Transistors. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/15m4q7r7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Jianzhi. “Analytic modeling of tunnel Field-Effect-Transistors and experimental investigation of GaN High-Electron-Mobility-Transistors.” 2016. Thesis, University of California – San Diego. Accessed September 29, 2020. http://www.escholarship.org/uc/item/15m4q7r7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Jianzhi. “Analytic modeling of tunnel Field-Effect-Transistors and experimental investigation of GaN High-Electron-Mobility-Transistors.” 2016. Web. 29 Sep 2020.

Vancouver:

Wu J. Analytic modeling of tunnel Field-Effect-Transistors and experimental investigation of GaN High-Electron-Mobility-Transistors. [Internet] [Thesis]. University of California – San Diego; 2016. [cited 2020 Sep 29]. Available from: http://www.escholarship.org/uc/item/15m4q7r7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu J. Analytic modeling of tunnel Field-Effect-Transistors and experimental investigation of GaN High-Electron-Mobility-Transistors. [Thesis]. University of California – San Diego; 2016. Available from: http://www.escholarship.org/uc/item/15m4q7r7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Sydney

15. Dao, Nguyen Cong. Characterisation and Modelling of Bulk CMOS Transistors over the 5 – 300 K Temperature Range .

Degree: 2017, University of Sydney

 With the increasing interest in MOSFET device operation in extremely cold environments, circuit designs for low temperature applications have attracted recent attention. Device characterisation and… (more)

Subjects/Keywords: Cryogenic Electronics; MOSFETs; Parameter Extraction; Current Matching; SPICE model

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APA (6th Edition):

Dao, N. C. (2017). Characterisation and Modelling of Bulk CMOS Transistors over the 5 – 300 K Temperature Range . (Thesis). University of Sydney. Retrieved from http://hdl.handle.net/2123/17591

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dao, Nguyen Cong. “Characterisation and Modelling of Bulk CMOS Transistors over the 5 – 300 K Temperature Range .” 2017. Thesis, University of Sydney. Accessed September 29, 2020. http://hdl.handle.net/2123/17591.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dao, Nguyen Cong. “Characterisation and Modelling of Bulk CMOS Transistors over the 5 – 300 K Temperature Range .” 2017. Web. 29 Sep 2020.

Vancouver:

Dao NC. Characterisation and Modelling of Bulk CMOS Transistors over the 5 – 300 K Temperature Range . [Internet] [Thesis]. University of Sydney; 2017. [cited 2020 Sep 29]. Available from: http://hdl.handle.net/2123/17591.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dao NC. Characterisation and Modelling of Bulk CMOS Transistors over the 5 – 300 K Temperature Range . [Thesis]. University of Sydney; 2017. Available from: http://hdl.handle.net/2123/17591

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

16. McCarthy, Ivana. High-k Gate dielectric materials for CMOS.

Degree: 2010, University of Minnesota

University of Minnesota M.S. thesis. August 2010. Major:Electrical Engineering. Advisor: Stephen A. Campbell. 1 computer file (PDF); v, 32 pages. Ill. (some col.)

Abstract summary not available

Subjects/Keywords: MOSFETs; Switching speed; Physical gate oxide; Oxide; Moore’s Law; Electrical engineering

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APA (6th Edition):

McCarthy, I. (2010). High-k Gate dielectric materials for CMOS. (Masters Thesis). University of Minnesota. Retrieved from http://purl.umn.edu/102363

Chicago Manual of Style (16th Edition):

McCarthy, Ivana. “High-k Gate dielectric materials for CMOS.” 2010. Masters Thesis, University of Minnesota. Accessed September 29, 2020. http://purl.umn.edu/102363.

MLA Handbook (7th Edition):

McCarthy, Ivana. “High-k Gate dielectric materials for CMOS.” 2010. Web. 29 Sep 2020.

Vancouver:

McCarthy I. High-k Gate dielectric materials for CMOS. [Internet] [Masters thesis]. University of Minnesota; 2010. [cited 2020 Sep 29]. Available from: http://purl.umn.edu/102363.

Council of Science Editors:

McCarthy I. High-k Gate dielectric materials for CMOS. [Masters Thesis]. University of Minnesota; 2010. Available from: http://purl.umn.edu/102363


NSYSU

17. Chen , Li-Hui. Electrical Analysis and Physical Mechanism of Hot Carrier Degradation in SOI MOSFETs.

Degree: Master, Electro-Optical Engineering, 2017, NSYSU

 Metal-oxide-semiconductor field effect transistor (MOSFET) is the most important device for advanced integrated circuits. The main advantages of a MOSFET are lower fabrication costs per… (more)

Subjects/Keywords: RPO; SOI; MOSFETs; hole injection; hot carrier degradation

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APA (6th Edition):

Chen , L. (2017). Electrical Analysis and Physical Mechanism of Hot Carrier Degradation in SOI MOSFETs. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154440

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen , Li-Hui. “Electrical Analysis and Physical Mechanism of Hot Carrier Degradation in SOI MOSFETs.” 2017. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154440.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen , Li-Hui. “Electrical Analysis and Physical Mechanism of Hot Carrier Degradation in SOI MOSFETs.” 2017. Web. 29 Sep 2020.

Vancouver:

Chen L. Electrical Analysis and Physical Mechanism of Hot Carrier Degradation in SOI MOSFETs. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154440.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen L. Electrical Analysis and Physical Mechanism of Hot Carrier Degradation in SOI MOSFETs. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154440

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

18. Sharan, Neha. Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry.

Degree: PhD, Faculty of Engineering, 2018, Indian Institute of Science

 Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so… (more)

Subjects/Keywords: Metal Semiconductor Field Effect Transistors (MOSFET); Common Double Gate (CDG) MOSFETs-Compact Modeling; Electronic Circuits-Design; Transistor Circuits; MOSFETs-Core Model; Double Gate MOSFETs; Asymmetric CDG MOSFETs; Semiconductor Device Modeling; Gate Oxide Thickness Asymmetry; Gate Oxide Asymmetry; Electronic Systems Engineering

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APA (6th Edition):

Sharan, N. (2018). Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/3489

Chicago Manual of Style (16th Edition):

Sharan, Neha. “Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry.” 2018. Doctoral Dissertation, Indian Institute of Science. Accessed September 29, 2020. http://etd.iisc.ac.in/handle/2005/3489.

MLA Handbook (7th Edition):

Sharan, Neha. “Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry.” 2018. Web. 29 Sep 2020.

Vancouver:

Sharan N. Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2018. [cited 2020 Sep 29]. Available from: http://etd.iisc.ac.in/handle/2005/3489.

Council of Science Editors:

Sharan N. Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry. [Doctoral Dissertation]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/3489


Virginia Tech

19. Mao, Yincan. Passive Balancing of Switching Transients between Paralleled SiC MOSFETs.

Degree: PhD, Electrical Engineering, 2018, Virginia Tech

 The SiC MOSFET has attracted interest due to its superior characteristics compared to its Si counterpart. Several SiC MOSFETs are usually paralleled to increase current… (more)

Subjects/Keywords: paralleled SiC MOSFETs; dynamic balancing; passive compensation; magnetic coupling; modeling

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APA (6th Edition):

Mao, Y. (2018). Passive Balancing of Switching Transients between Paralleled SiC MOSFETs. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/82203

Chicago Manual of Style (16th Edition):

Mao, Yincan. “Passive Balancing of Switching Transients between Paralleled SiC MOSFETs.” 2018. Doctoral Dissertation, Virginia Tech. Accessed September 29, 2020. http://hdl.handle.net/10919/82203.

MLA Handbook (7th Edition):

Mao, Yincan. “Passive Balancing of Switching Transients between Paralleled SiC MOSFETs.” 2018. Web. 29 Sep 2020.

Vancouver:

Mao Y. Passive Balancing of Switching Transients between Paralleled SiC MOSFETs. [Internet] [Doctoral dissertation]. Virginia Tech; 2018. [cited 2020 Sep 29]. Available from: http://hdl.handle.net/10919/82203.

Council of Science Editors:

Mao Y. Passive Balancing of Switching Transients between Paralleled SiC MOSFETs. [Doctoral Dissertation]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/82203


University of Cambridge

20. Kang, Hyemin. Theory of Superjunction Devices.

Degree: PhD, 2020, University of Cambridge

 Since the first ideal specific resistance model by Fujihira in 1997 and the first commercial superjunction MOSFET by Infineon technology in 1998, the technology and… (more)

Subjects/Keywords: Power device; MOSFETs; Superjunction; Analytic model; Figures of Merit; Dynamic; Capacitance

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APA (6th Edition):

Kang, H. (2020). Theory of Superjunction Devices. (Doctoral Dissertation). University of Cambridge. Retrieved from https://www.repository.cam.ac.uk/handle/1810/303158

Chicago Manual of Style (16th Edition):

Kang, Hyemin. “Theory of Superjunction Devices.” 2020. Doctoral Dissertation, University of Cambridge. Accessed September 29, 2020. https://www.repository.cam.ac.uk/handle/1810/303158.

MLA Handbook (7th Edition):

Kang, Hyemin. “Theory of Superjunction Devices.” 2020. Web. 29 Sep 2020.

Vancouver:

Kang H. Theory of Superjunction Devices. [Internet] [Doctoral dissertation]. University of Cambridge; 2020. [cited 2020 Sep 29]. Available from: https://www.repository.cam.ac.uk/handle/1810/303158.

Council of Science Editors:

Kang H. Theory of Superjunction Devices. [Doctoral Dissertation]. University of Cambridge; 2020. Available from: https://www.repository.cam.ac.uk/handle/1810/303158


University of Toronto

21. Yoo, Abraham. Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage Power MOSFETs.

Degree: 2010, University of Toronto

In this thesis, next generation low-voltage integrated power semiconductor devices are proposed and analyzed in terms of device structure and layout optimization techniques. Both approaches… (more)

Subjects/Keywords: power MOSFETs; Superjunction; 0794; 0544

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APA (6th Edition):

Yoo, A. (2010). Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage Power MOSFETs. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/26392

Chicago Manual of Style (16th Edition):

Yoo, Abraham. “Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage Power MOSFETs.” 2010. Doctoral Dissertation, University of Toronto. Accessed September 29, 2020. http://hdl.handle.net/1807/26392.

MLA Handbook (7th Edition):

Yoo, Abraham. “Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage Power MOSFETs.” 2010. Web. 29 Sep 2020.

Vancouver:

Yoo A. Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage Power MOSFETs. [Internet] [Doctoral dissertation]. University of Toronto; 2010. [cited 2020 Sep 29]. Available from: http://hdl.handle.net/1807/26392.

Council of Science Editors:

Yoo A. Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage Power MOSFETs. [Doctoral Dissertation]. University of Toronto; 2010. Available from: http://hdl.handle.net/1807/26392


University of Minnesota

22. Haratipour, Nazila. Two-Dimensional Black Phosphorus for High Performance Field Effect Transistors.

Degree: PhD, Electrical Engineering, 2017, University of Minnesota

 Two-dimensional (2D) materials are a potential platform for scaled logic devices, sensor applications, flexible electronics and other innovative device concepts. Black phosphorus (BP) has recently… (more)

Subjects/Keywords: 2D materials; Black phosphorus; contact resistance; crystal orientation; MOSFETs; Schottky

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APA (6th Edition):

Haratipour, N. (2017). Two-Dimensional Black Phosphorus for High Performance Field Effect Transistors. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/200176

Chicago Manual of Style (16th Edition):

Haratipour, Nazila. “Two-Dimensional Black Phosphorus for High Performance Field Effect Transistors.” 2017. Doctoral Dissertation, University of Minnesota. Accessed September 29, 2020. http://hdl.handle.net/11299/200176.

MLA Handbook (7th Edition):

Haratipour, Nazila. “Two-Dimensional Black Phosphorus for High Performance Field Effect Transistors.” 2017. Web. 29 Sep 2020.

Vancouver:

Haratipour N. Two-Dimensional Black Phosphorus for High Performance Field Effect Transistors. [Internet] [Doctoral dissertation]. University of Minnesota; 2017. [cited 2020 Sep 29]. Available from: http://hdl.handle.net/11299/200176.

Council of Science Editors:

Haratipour N. Two-Dimensional Black Phosphorus for High Performance Field Effect Transistors. [Doctoral Dissertation]. University of Minnesota; 2017. Available from: http://hdl.handle.net/11299/200176

23. Hayes, James Hunter. Modeling and Tracking Degradation in Electronic Components.

Degree: PhD, Electrical and Computer Engineering (Holcomb Dept. of), 2017, Clemson University

 This dissertation develops models for electrical components that are useful for describing or predicting their behavior in certain applications. The three models presented are physics-based… (more)

Subjects/Keywords: Capacitors; MLCCs; Modeling; MOSFETs

…solutions can provide useful information about device lifetime, especially for integrated MOSFETs… …The setup used in this work to degrade MOSFETs is shown in Fig. 1.9. The ESD simulator was a… …of transistors in a power inverter. In this study, MOSFETs degraded by ESD exhibited… …A. Saxena, P. Wysocki, S. Saha, and K. Goebel, “Towards prognostics of power MOSFETs… …Z. Peng, and D. Cao, “A smart gate drive with self-diagnosis for power MOSFETs and IGBTs… 

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APA (6th Edition):

Hayes, J. H. (2017). Modeling and Tracking Degradation in Electronic Components. (Doctoral Dissertation). Clemson University. Retrieved from https://tigerprints.clemson.edu/all_dissertations/2064

Chicago Manual of Style (16th Edition):

Hayes, James Hunter. “Modeling and Tracking Degradation in Electronic Components.” 2017. Doctoral Dissertation, Clemson University. Accessed September 29, 2020. https://tigerprints.clemson.edu/all_dissertations/2064.

MLA Handbook (7th Edition):

Hayes, James Hunter. “Modeling and Tracking Degradation in Electronic Components.” 2017. Web. 29 Sep 2020.

Vancouver:

Hayes JH. Modeling and Tracking Degradation in Electronic Components. [Internet] [Doctoral dissertation]. Clemson University; 2017. [cited 2020 Sep 29]. Available from: https://tigerprints.clemson.edu/all_dissertations/2064.

Council of Science Editors:

Hayes JH. Modeling and Tracking Degradation in Electronic Components. [Doctoral Dissertation]. Clemson University; 2017. Available from: https://tigerprints.clemson.edu/all_dissertations/2064


University of Canterbury

24. Fricker, Katherine. Collateral exposure: the additional dose from radiation treatment.

Degree: MS, Physics, 2012, University of Canterbury

 For patients receiving radiation therapy, there is a risk of developing radiation induced carcinomas, especially if they have a long life expectancy. However, radiotherapy is… (more)

Subjects/Keywords: Secondary cancer risk; Gafchromic film; MOSFETs; seminoma; breast treatment

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APA (6th Edition):

Fricker, K. (2012). Collateral exposure: the additional dose from radiation treatment. (Masters Thesis). University of Canterbury. Retrieved from http://dx.doi.org/10.26021/7258

Chicago Manual of Style (16th Edition):

Fricker, Katherine. “Collateral exposure: the additional dose from radiation treatment.” 2012. Masters Thesis, University of Canterbury. Accessed September 29, 2020. http://dx.doi.org/10.26021/7258.

MLA Handbook (7th Edition):

Fricker, Katherine. “Collateral exposure: the additional dose from radiation treatment.” 2012. Web. 29 Sep 2020.

Vancouver:

Fricker K. Collateral exposure: the additional dose from radiation treatment. [Internet] [Masters thesis]. University of Canterbury; 2012. [cited 2020 Sep 29]. Available from: http://dx.doi.org/10.26021/7258.

Council of Science Editors:

Fricker K. Collateral exposure: the additional dose from radiation treatment. [Masters Thesis]. University of Canterbury; 2012. Available from: http://dx.doi.org/10.26021/7258


University of Cambridge

25. Kang, Hyemin. Theory of superjunction devices.

Degree: PhD, 2020, University of Cambridge

 Since the first ideal specific resistance model by Fujihira in 1997 and the first commercial superjunction MOSFET by Infineon technology in 1998, the technology and… (more)

Subjects/Keywords: Power device; MOSFETs; Superjunction; Analytic model; Figures of Merit; Dynamic; Capacitance

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APA (6th Edition):

Kang, H. (2020). Theory of superjunction devices. (Doctoral Dissertation). University of Cambridge. Retrieved from https://www.repository.cam.ac.uk/handle/1810/303158 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.801759

Chicago Manual of Style (16th Edition):

Kang, Hyemin. “Theory of superjunction devices.” 2020. Doctoral Dissertation, University of Cambridge. Accessed September 29, 2020. https://www.repository.cam.ac.uk/handle/1810/303158 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.801759.

MLA Handbook (7th Edition):

Kang, Hyemin. “Theory of superjunction devices.” 2020. Web. 29 Sep 2020.

Vancouver:

Kang H. Theory of superjunction devices. [Internet] [Doctoral dissertation]. University of Cambridge; 2020. [cited 2020 Sep 29]. Available from: https://www.repository.cam.ac.uk/handle/1810/303158 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.801759.

Council of Science Editors:

Kang H. Theory of superjunction devices. [Doctoral Dissertation]. University of Cambridge; 2020. Available from: https://www.repository.cam.ac.uk/handle/1810/303158 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.801759

26. GONG XIAO. Extending Si CMOS: InGaAs and GeSn High Mobility Channel Transistors for Future High Speed and Low Power Applications.

Degree: 2013, National University of Singapore

Subjects/Keywords: InGaA; GeSn; high mobility channels; N-MOSFETs; P-MOSFETs; CMOS

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APA (6th Edition):

XIAO, G. (2013). Extending Si CMOS: InGaAs and GeSn High Mobility Channel Transistors for Future High Speed and Low Power Applications. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/38840

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

XIAO, GONG. “Extending Si CMOS: InGaAs and GeSn High Mobility Channel Transistors for Future High Speed and Low Power Applications.” 2013. Thesis, National University of Singapore. Accessed September 29, 2020. http://scholarbank.nus.edu.sg/handle/10635/38840.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

XIAO, GONG. “Extending Si CMOS: InGaAs and GeSn High Mobility Channel Transistors for Future High Speed and Low Power Applications.” 2013. Web. 29 Sep 2020.

Vancouver:

XIAO G. Extending Si CMOS: InGaAs and GeSn High Mobility Channel Transistors for Future High Speed and Low Power Applications. [Internet] [Thesis]. National University of Singapore; 2013. [cited 2020 Sep 29]. Available from: http://scholarbank.nus.edu.sg/handle/10635/38840.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

XIAO G. Extending Si CMOS: InGaAs and GeSn High Mobility Channel Transistors for Future High Speed and Low Power Applications. [Thesis]. National University of Singapore; 2013. Available from: http://scholarbank.nus.edu.sg/handle/10635/38840

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Jouha, Wadia. Etude et modélisation des dégradations des composants de puissance grand gap soumis à des contraintes thermiques et électriques : Study and modeling of large gap power components degradations subjected to thermal and electrical constraints.

Degree: Docteur es, Physique, 2018, Normandie; Université Abdelmalek Essaâdi (Tétouan)

Ce travail vise à étudier la robustesse de trois générations de MOSFET SiC de puissance (Silicon Carbide Metal Oxide Semiconductor Field E_ect Transistors). Plusieurs approches… (more)

Subjects/Keywords: MOSFETs SiC; Fiabilité; Robustesse; Modélisation; Simulation physique; Vieillissement; HTRB; ESD; Caractérisations électriques; MOSFETs SiC; Reliability; Robustness; Modeling; Physical simulation; Aging; HTRB; ESD; Electrical Characterizations; 621.381 52

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APA (6th Edition):

Jouha, W. (2018). Etude et modélisation des dégradations des composants de puissance grand gap soumis à des contraintes thermiques et électriques : Study and modeling of large gap power components degradations subjected to thermal and electrical constraints. (Doctoral Dissertation). Normandie; Université Abdelmalek Essaâdi (Tétouan). Retrieved from http://www.theses.fr/2018NORMR083

Chicago Manual of Style (16th Edition):

Jouha, Wadia. “Etude et modélisation des dégradations des composants de puissance grand gap soumis à des contraintes thermiques et électriques : Study and modeling of large gap power components degradations subjected to thermal and electrical constraints.” 2018. Doctoral Dissertation, Normandie; Université Abdelmalek Essaâdi (Tétouan). Accessed September 29, 2020. http://www.theses.fr/2018NORMR083.

MLA Handbook (7th Edition):

Jouha, Wadia. “Etude et modélisation des dégradations des composants de puissance grand gap soumis à des contraintes thermiques et électriques : Study and modeling of large gap power components degradations subjected to thermal and electrical constraints.” 2018. Web. 29 Sep 2020.

Vancouver:

Jouha W. Etude et modélisation des dégradations des composants de puissance grand gap soumis à des contraintes thermiques et électriques : Study and modeling of large gap power components degradations subjected to thermal and electrical constraints. [Internet] [Doctoral dissertation]. Normandie; Université Abdelmalek Essaâdi (Tétouan); 2018. [cited 2020 Sep 29]. Available from: http://www.theses.fr/2018NORMR083.

Council of Science Editors:

Jouha W. Etude et modélisation des dégradations des composants de puissance grand gap soumis à des contraintes thermiques et électriques : Study and modeling of large gap power components degradations subjected to thermal and electrical constraints. [Doctoral Dissertation]. Normandie; Université Abdelmalek Essaâdi (Tétouan); 2018. Available from: http://www.theses.fr/2018NORMR083


NSYSU

28. Lo, Wen-Hung. Physical Mechanism of Reliability Analysis on SOI and High-k/Metal Gate MOSFETs.

Degree: PhD, Physics, 2013, NSYSU

 This dissertation studies physical mechanisms and reliability analysis on Silicon-on-Insulator (SOI) and high-K/metal gate MOSFETs. For the part of bias temperature instability (BTI), we investigate… (more)

Subjects/Keywords: MOSFETs; Silicon-on-Insulator; high-K/metal gate; bias temperature instability; hot carrier stress

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APA (6th Edition):

Lo, W. (2013). Physical Mechanism of Reliability Analysis on SOI and High-k/Metal Gate MOSFETs. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623113-230228

Chicago Manual of Style (16th Edition):

Lo, Wen-Hung. “Physical Mechanism of Reliability Analysis on SOI and High-k/Metal Gate MOSFETs.” 2013. Doctoral Dissertation, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623113-230228.

MLA Handbook (7th Edition):

Lo, Wen-Hung. “Physical Mechanism of Reliability Analysis on SOI and High-k/Metal Gate MOSFETs.” 2013. Web. 29 Sep 2020.

Vancouver:

Lo W. Physical Mechanism of Reliability Analysis on SOI and High-k/Metal Gate MOSFETs. [Internet] [Doctoral dissertation]. NSYSU; 2013. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623113-230228.

Council of Science Editors:

Lo W. Physical Mechanism of Reliability Analysis on SOI and High-k/Metal Gate MOSFETs. [Doctoral Dissertation]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623113-230228


NSYSU

29. Tsai, Jyun-Yu. The evolutional mechanisms of hot carrier degradation in advanced high-k/metal gate MOSFETs.

Degree: PhD, Physics, 2015, NSYSU

 To achieve high speed, the continuous scaling down of metal oxide semiconductor field electrical field transistors is driving conventional SiO2-based dielectric to be only a… (more)

Subjects/Keywords: electron-electron scattering; high-K/metal gate; short channel effect; hot carrier degradation; MOSFETs

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APA (6th Edition):

Tsai, J. (2015). The evolutional mechanisms of hot carrier degradation in advanced high-k/metal gate MOSFETs. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0615115-172714

Chicago Manual of Style (16th Edition):

Tsai, Jyun-Yu. “The evolutional mechanisms of hot carrier degradation in advanced high-k/metal gate MOSFETs.” 2015. Doctoral Dissertation, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0615115-172714.

MLA Handbook (7th Edition):

Tsai, Jyun-Yu. “The evolutional mechanisms of hot carrier degradation in advanced high-k/metal gate MOSFETs.” 2015. Web. 29 Sep 2020.

Vancouver:

Tsai J. The evolutional mechanisms of hot carrier degradation in advanced high-k/metal gate MOSFETs. [Internet] [Doctoral dissertation]. NSYSU; 2015. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0615115-172714.

Council of Science Editors:

Tsai J. The evolutional mechanisms of hot carrier degradation in advanced high-k/metal gate MOSFETs. [Doctoral Dissertation]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0615115-172714


Virginia Tech

30. Miao, Zichen. Packaging and Magnetic Integration for Reliable Switching of Paralleled SiC MOSFETs.

Degree: PhD, Electrical Engineering, 2018, Virginia Tech

 Silicon carbide (SiC) outperform Si chips in terms of high blocking voltage capability, low on-resistance, high-temperature operation, and high switching frequency. Several SiC MOSFETs are… (more)

Subjects/Keywords: Packaging; cross-turn-on; magnetic integration; module; paralleled SiC MOSFETs; current balancing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Miao, Z. (2018). Packaging and Magnetic Integration for Reliable Switching of Paralleled SiC MOSFETs. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84497

Chicago Manual of Style (16th Edition):

Miao, Zichen. “Packaging and Magnetic Integration for Reliable Switching of Paralleled SiC MOSFETs.” 2018. Doctoral Dissertation, Virginia Tech. Accessed September 29, 2020. http://hdl.handle.net/10919/84497.

MLA Handbook (7th Edition):

Miao, Zichen. “Packaging and Magnetic Integration for Reliable Switching of Paralleled SiC MOSFETs.” 2018. Web. 29 Sep 2020.

Vancouver:

Miao Z. Packaging and Magnetic Integration for Reliable Switching of Paralleled SiC MOSFETs. [Internet] [Doctoral dissertation]. Virginia Tech; 2018. [cited 2020 Sep 29]. Available from: http://hdl.handle.net/10919/84497.

Council of Science Editors:

Miao Z. Packaging and Magnetic Integration for Reliable Switching of Paralleled SiC MOSFETs. [Doctoral Dissertation]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/84497

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