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You searched for subject:(Low power application). Showing records 1 – 19 of 19 total matches.

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Brunel University

1. Bin Mohd Rozlan, Mohd Helmy Hakimie. DC/AC inverter based switched capacitor circuit topology with reduced number of components for low power applications.

Degree: PhD, 2017, Brunel University

 This thesis presents a new DC/AC inverter circuit which is based on a switched-capacitor circuit topology with reduced components (power switch and capacitor) count for… (more)

Subjects/Keywords: DC/AC inverter; Switched-capacitor topology; Low total harmonics distortion; Low power domestic application; Reduced component count

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APA (6th Edition):

Bin Mohd Rozlan, M. H. H. (2017). DC/AC inverter based switched capacitor circuit topology with reduced number of components for low power applications. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/16009 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.764886

Chicago Manual of Style (16th Edition):

Bin Mohd Rozlan, Mohd Helmy Hakimie. “DC/AC inverter based switched capacitor circuit topology with reduced number of components for low power applications.” 2017. Doctoral Dissertation, Brunel University. Accessed January 29, 2020. http://bura.brunel.ac.uk/handle/2438/16009 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.764886.

MLA Handbook (7th Edition):

Bin Mohd Rozlan, Mohd Helmy Hakimie. “DC/AC inverter based switched capacitor circuit topology with reduced number of components for low power applications.” 2017. Web. 29 Jan 2020.

Vancouver:

Bin Mohd Rozlan MHH. DC/AC inverter based switched capacitor circuit topology with reduced number of components for low power applications. [Internet] [Doctoral dissertation]. Brunel University; 2017. [cited 2020 Jan 29]. Available from: http://bura.brunel.ac.uk/handle/2438/16009 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.764886.

Council of Science Editors:

Bin Mohd Rozlan MHH. DC/AC inverter based switched capacitor circuit topology with reduced number of components for low power applications. [Doctoral Dissertation]. Brunel University; 2017. Available from: http://bura.brunel.ac.uk/handle/2438/16009 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.764886

2. Pouiklis, Georgios. Ανάπτυξη ψηφιακών ηλεκτρονικών χαμηλής ισχύος, σε ολοκληρωμένα κυκλώματα μικτού σήματος για διαστημικές εφαρμογές.

Degree: 2016, Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ)

The basic target of the present dissertation is the development and validation of design methodology for space applications’ digital circuits. The research followed three interrelated… (more)

Subjects/Keywords: Χαμηλή κατανάλωση ισχύος; Ολοκληρωμένα κυκλώματα; Διαστημική; Low power circuits; Low power consumption; Application specific integrated circuits (ASICS); Design of integrated circuits; Aerospace industry

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APA (6th Edition):

Pouiklis, G. (2016). Ανάπτυξη ψηφιακών ηλεκτρονικών χαμηλής ισχύος, σε ολοκληρωμένα κυκλώματα μικτού σήματος για διαστημικές εφαρμογές. (Thesis). Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ). Retrieved from http://hdl.handle.net/10442/hedi/40523

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pouiklis, Georgios. “Ανάπτυξη ψηφιακών ηλεκτρονικών χαμηλής ισχύος, σε ολοκληρωμένα κυκλώματα μικτού σήματος για διαστημικές εφαρμογές.” 2016. Thesis, Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ). Accessed January 29, 2020. http://hdl.handle.net/10442/hedi/40523.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pouiklis, Georgios. “Ανάπτυξη ψηφιακών ηλεκτρονικών χαμηλής ισχύος, σε ολοκληρωμένα κυκλώματα μικτού σήματος για διαστημικές εφαρμογές.” 2016. Web. 29 Jan 2020.

Vancouver:

Pouiklis G. Ανάπτυξη ψηφιακών ηλεκτρονικών χαμηλής ισχύος, σε ολοκληρωμένα κυκλώματα μικτού σήματος για διαστημικές εφαρμογές. [Internet] [Thesis]. Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); 2016. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10442/hedi/40523.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pouiklis G. Ανάπτυξη ψηφιακών ηλεκτρονικών χαμηλής ισχύος, σε ολοκληρωμένα κυκλώματα μικτού σήματος για διαστημικές εφαρμογές. [Thesis]. Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); 2016. Available from: http://hdl.handle.net/10442/hedi/40523

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Lin, Sheng-En. Design and Evaluation of an Improved 10-bit Integrating CMOS ADC.

Degree: Master, Electrical Engineering, 2017, NSYSU

 The analog-to-digital converter (ADC) is an essential component in modern mixed-signal system applications. This thesis presents the design and evaluation of a single-slope integrating ADC… (more)

Subjects/Keywords: single-slope integrating ADC; voltage-to-time converter; low power circuit design; application-specific integrated circuit (ASIC); biological-signal recording system

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APA (6th Edition):

Lin, S. (2017). Design and Evaluation of an Improved 10-bit Integrating CMOS ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Sheng-En. “Design and Evaluation of an Improved 10-bit Integrating CMOS ADC.” 2017. Thesis, NSYSU. Accessed January 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Sheng-En. “Design and Evaluation of an Improved 10-bit Integrating CMOS ADC.” 2017. Web. 29 Jan 2020.

Vancouver:

Lin S. Design and Evaluation of an Improved 10-bit Integrating CMOS ADC. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Jan 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin S. Design and Evaluation of an Improved 10-bit Integrating CMOS ADC. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

4. Chandra, Dhruba. Speech Recognition Co-processor.

Degree: PhD, Computer Engineering, 2008, North Carolina State University

 With computing trend moving towards ubiquitous computing propelled by the advances in embedded mobile processors and battery technology, speech recognition is becoming an essential part… (more)

Subjects/Keywords: Application Specific; Low Power; ASIC; Speech Recognition

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APA (6th Edition):

Chandra, D. (2008). Speech Recognition Co-processor. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/3421

Chicago Manual of Style (16th Edition):

Chandra, Dhruba. “Speech Recognition Co-processor.” 2008. Doctoral Dissertation, North Carolina State University. Accessed January 29, 2020. http://www.lib.ncsu.edu/resolver/1840.16/3421.

MLA Handbook (7th Edition):

Chandra, Dhruba. “Speech Recognition Co-processor.” 2008. Web. 29 Jan 2020.

Vancouver:

Chandra D. Speech Recognition Co-processor. [Internet] [Doctoral dissertation]. North Carolina State University; 2008. [cited 2020 Jan 29]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3421.

Council of Science Editors:

Chandra D. Speech Recognition Co-processor. [Doctoral Dissertation]. North Carolina State University; 2008. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3421


NSYSU

5. Chuang, Sheng-Chih. Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System.

Degree: Master, Electrical Engineering, 2015, NSYSU

 This thesis describes the design and evaluation of an integrated circuit (ASIC) implement eight parallel signal channels providing analog-amplitude delay-and-add functionality. This implementation is a… (more)

Subjects/Keywords: Nerve cuff recording; Electroneurogram; Sample-and-hold circuit; Application-specific integrated circuit (ASIC); Low power circuit; Velocity selective recording

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APA (6th Edition):

Chuang, S. (2015). Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chuang, Sheng-Chih. “Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System.” 2015. Thesis, NSYSU. Accessed January 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chuang, Sheng-Chih. “Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System.” 2015. Web. 29 Jan 2020.

Vancouver:

Chuang S. Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Jan 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chuang S. Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0212115-134634

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

6. Yeh, Chih-Shen. Synchronous-Conduction-Mode Tapped-Inductor Buck Converter for Low-Power, High-Density Application.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 General-purpose step-down converter is essential in electronic system for processing energy from high-voltage rail to low-voltage circuits. The applications can be found at the auxiliary… (more)

Subjects/Keywords: coupled inductor; zero-voltage switching; non-isolated dc-dc converter; high step-down; high switching frequency; low-power application

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APA (6th Edition):

Yeh, C. (2017). Synchronous-Conduction-Mode Tapped-Inductor Buck Converter for Low-Power, High-Density Application. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/81722

Chicago Manual of Style (16th Edition):

Yeh, Chih-Shen. “Synchronous-Conduction-Mode Tapped-Inductor Buck Converter for Low-Power, High-Density Application.” 2017. Masters Thesis, Virginia Tech. Accessed January 29, 2020. http://hdl.handle.net/10919/81722.

MLA Handbook (7th Edition):

Yeh, Chih-Shen. “Synchronous-Conduction-Mode Tapped-Inductor Buck Converter for Low-Power, High-Density Application.” 2017. Web. 29 Jan 2020.

Vancouver:

Yeh C. Synchronous-Conduction-Mode Tapped-Inductor Buck Converter for Low-Power, High-Density Application. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10919/81722.

Council of Science Editors:

Yeh C. Synchronous-Conduction-Mode Tapped-Inductor Buck Converter for Low-Power, High-Density Application. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/81722


University of Southern California

7. Safarian, Zahra. Energy aware integrated circuits for communication and biomedical applications.

Degree: PhD, Electrical Engineering, 2014, University of Southern California

 The thesis presents system level and block level integrated circuit solutions for low power wirelessly powered passive sensors, specifically biomedical implants and RFID systems. The… (more)

Subjects/Keywords: energy harvesting; passive transponder; rectifier; RF identification (RFID); CMOS; frequency conversion; frequency divider; nonlinear circuits; oscillators; subharmonic generation; biomedical application; event detection; low power; neural recording system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Safarian, Z. (2014). Energy aware integrated circuits for communication and biomedical applications. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/412271/rec/2347

Chicago Manual of Style (16th Edition):

Safarian, Zahra. “Energy aware integrated circuits for communication and biomedical applications.” 2014. Doctoral Dissertation, University of Southern California. Accessed January 29, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/412271/rec/2347.

MLA Handbook (7th Edition):

Safarian, Zahra. “Energy aware integrated circuits for communication and biomedical applications.” 2014. Web. 29 Jan 2020.

Vancouver:

Safarian Z. Energy aware integrated circuits for communication and biomedical applications. [Internet] [Doctoral dissertation]. University of Southern California; 2014. [cited 2020 Jan 29]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/412271/rec/2347.

Council of Science Editors:

Safarian Z. Energy aware integrated circuits for communication and biomedical applications. [Doctoral Dissertation]. University of Southern California; 2014. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/412271/rec/2347


Virginia Tech

8. Zhang, Zhiye. Sintering of Micro-scale and Nanscale Silver Paste for Power Semiconductor Devices Attachment.

Degree: PhD, Electrical and Computer Engineering, 2005, Virginia Tech

 Die attachment is one of the most important processes in the packaging of power semiconductor devices. The current die-attach materials/techniques, including conductive adhesives and reflowed… (more)

Subjects/Keywords: low-temperature sintering; Power packaging; nanoscale silver paste; die-attach; high-temperature application

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APA (6th Edition):

Zhang, Z. (2005). Sintering of Micro-scale and Nanscale Silver Paste for Power Semiconductor Devices Attachment. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/28902

Chicago Manual of Style (16th Edition):

Zhang, Zhiye. “Sintering of Micro-scale and Nanscale Silver Paste for Power Semiconductor Devices Attachment.” 2005. Doctoral Dissertation, Virginia Tech. Accessed January 29, 2020. http://hdl.handle.net/10919/28902.

MLA Handbook (7th Edition):

Zhang, Zhiye. “Sintering of Micro-scale and Nanscale Silver Paste for Power Semiconductor Devices Attachment.” 2005. Web. 29 Jan 2020.

Vancouver:

Zhang Z. Sintering of Micro-scale and Nanscale Silver Paste for Power Semiconductor Devices Attachment. [Internet] [Doctoral dissertation]. Virginia Tech; 2005. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/10919/28902.

Council of Science Editors:

Zhang Z. Sintering of Micro-scale and Nanscale Silver Paste for Power Semiconductor Devices Attachment. [Doctoral Dissertation]. Virginia Tech; 2005. Available from: http://hdl.handle.net/10919/28902


Brno University of Technology

9. Verčimák, Mário. Měření a vyhodnocování spotřeby zařízení IoT .

Degree: 2017, Brno University of Technology

 Táto práca sa zaoberá vyhodnocovaniu napájania a spotreby IoT zariadení. Ďalej sa zaoberá rozborom profilu odberu prúdu týchto zariadení ako aj rozborom vhodného napájacieho zdroja.… (more)

Subjects/Keywords: IoT zariadenia; Batérie; DC/DC meniče; LTC3335; kulombmeter; prúdový monitor; merací prípravok; nadradená aplikácia; IoT devices; battery; DC/DC converter; LTC3335; coulomb meter; current monitor; low-power; application

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APA (6th Edition):

Verčimák, M. (2017). Měření a vyhodnocování spotřeby zařízení IoT . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/65114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Verčimák, Mário. “Měření a vyhodnocování spotřeby zařízení IoT .” 2017. Thesis, Brno University of Technology. Accessed January 29, 2020. http://hdl.handle.net/11012/65114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Verčimák, Mário. “Měření a vyhodnocování spotřeby zařízení IoT .” 2017. Web. 29 Jan 2020.

Vancouver:

Verčimák M. Měření a vyhodnocování spotřeby zařízení IoT . [Internet] [Thesis]. Brno University of Technology; 2017. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/11012/65114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Verčimák M. Měření a vyhodnocování spotřeby zařízení IoT . [Thesis]. Brno University of Technology; 2017. Available from: http://hdl.handle.net/11012/65114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. KO KO WIN. Solar and thermal energy scavenging system for low power application.

Degree: 2011, National University of Singapore

Subjects/Keywords: Solar; Thermal; DCDC Converter; Low power application; Energy Harvesting; DCM System

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APA (6th Edition):

WIN, K. K. (2011). Solar and thermal energy scavenging system for low power application. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/30718

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

WIN, KO KO. “Solar and thermal energy scavenging system for low power application.” 2011. Thesis, National University of Singapore. Accessed January 29, 2020. http://scholarbank.nus.edu.sg/handle/10635/30718.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

WIN, KO KO. “Solar and thermal energy scavenging system for low power application.” 2011. Web. 29 Jan 2020.

Vancouver:

WIN KK. Solar and thermal energy scavenging system for low power application. [Internet] [Thesis]. National University of Singapore; 2011. [cited 2020 Jan 29]. Available from: http://scholarbank.nus.edu.sg/handle/10635/30718.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

WIN KK. Solar and thermal energy scavenging system for low power application. [Thesis]. National University of Singapore; 2011. Available from: http://scholarbank.nus.edu.sg/handle/10635/30718

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

11. Ardi, Shanai. A Nonlinear Programming Approach for Dynamic Voltage Scaling.

Degree: Computer and Information Science, 2005, Linköping University

  Embedded computing systems in portable devices need to be energy efficient, yet they have to deliver adequate performance to the often computationally expensive applications.… (more)

Subjects/Keywords: Datorsystem; Low Power Design; Dynamic Voltage Scaling; Nonlinear Programming; AMPL; Application Program Interface.; Datorsystem; Information Systems; Systemvetenskap, informationssystem och informatik

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APA (6th Edition):

Ardi, S. (2005). A Nonlinear Programming Approach for Dynamic Voltage Scaling. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2774

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ardi, Shanai. “A Nonlinear Programming Approach for Dynamic Voltage Scaling.” 2005. Thesis, Linköping University. Accessed January 29, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2774.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ardi, Shanai. “A Nonlinear Programming Approach for Dynamic Voltage Scaling.” 2005. Web. 29 Jan 2020.

Vancouver:

Ardi S. A Nonlinear Programming Approach for Dynamic Voltage Scaling. [Internet] [Thesis]. Linköping University; 2005. [cited 2020 Jan 29]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2774.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ardi S. A Nonlinear Programming Approach for Dynamic Voltage Scaling. [Thesis]. Linköping University; 2005. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2774

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Le Pelleter, Tugdual. Méthode de discrétisation adaptée à une logique événementielle pour l'utra-faible consommation : application à la reconnaissance de signaux physiologiques : Discretization method adapted to an event-logic architecture for ultra-low power consumption : a physiological pattern recognition application.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2015, Grenoble Alpes

Les systèmes embarqués mobiles font partis intégrante de notre quotidien. Afin de les rendre plus adaptésaux usages, ils ont été miniaturisés et leur autonomie a… (more)

Subjects/Keywords: Système embarqué; Implant médical; Faible consommation; Reconnaissance de formes; Échantillonnage par traversée de niveaux; Automate fini déterministe; Logique événementielle; Logique asynchrone; Consommation électrique; Réseau de portes programmables; Circuit intégré propre à une application; Mobile embedded system; Medical implant; Low-power consumption; Pattern recognition; Levelcrossing sampling scheme; Deterministic finite automata; Event-logic; Asynchronous logic; Power consumption; Field-programmable gate array; Application specific integrated circuit; 620

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APA (6th Edition):

Le Pelleter, T. (2015). Méthode de discrétisation adaptée à une logique événementielle pour l'utra-faible consommation : application à la reconnaissance de signaux physiologiques : Discretization method adapted to an event-logic architecture for ultra-low power consumption : a physiological pattern recognition application. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2015GREAT043

Chicago Manual of Style (16th Edition):

Le Pelleter, Tugdual. “Méthode de discrétisation adaptée à une logique événementielle pour l'utra-faible consommation : application à la reconnaissance de signaux physiologiques : Discretization method adapted to an event-logic architecture for ultra-low power consumption : a physiological pattern recognition application.” 2015. Doctoral Dissertation, Grenoble Alpes. Accessed January 29, 2020. http://www.theses.fr/2015GREAT043.

MLA Handbook (7th Edition):

Le Pelleter, Tugdual. “Méthode de discrétisation adaptée à une logique événementielle pour l'utra-faible consommation : application à la reconnaissance de signaux physiologiques : Discretization method adapted to an event-logic architecture for ultra-low power consumption : a physiological pattern recognition application.” 2015. Web. 29 Jan 2020.

Vancouver:

Le Pelleter T. Méthode de discrétisation adaptée à une logique événementielle pour l'utra-faible consommation : application à la reconnaissance de signaux physiologiques : Discretization method adapted to an event-logic architecture for ultra-low power consumption : a physiological pattern recognition application. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2015. [cited 2020 Jan 29]. Available from: http://www.theses.fr/2015GREAT043.

Council of Science Editors:

Le Pelleter T. Méthode de discrétisation adaptée à une logique événementielle pour l'utra-faible consommation : application à la reconnaissance de signaux physiologiques : Discretization method adapted to an event-logic architecture for ultra-low power consumption : a physiological pattern recognition application. [Doctoral Dissertation]. Grenoble Alpes; 2015. Available from: http://www.theses.fr/2015GREAT043


Delft University of Technology

13. Strydis, C. Universal Processor Architecture for Biomedical Implants: The SiMS Project.

Degree: 2011, Delft University of Technology

 HEALTHCARE in the 21st century is changing rapidly. In advanced countries, in particular, healthcare is moving from a public to a more personalized nature. However,… (more)

Subjects/Keywords: biomedical; implant; architecture; low power; energy; embedded; monitoring; stimulation; cache; branch prediction; design-space exploration; genetic; benchmark; compression; encryption; checksum; synthetic application; SiMS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Strydis, C. (2011). Universal Processor Architecture for Biomedical Implants: The SiMS Project. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:348a976d-5fcf-4dec-ba03-01e12b465025 ; urn:NBN:nl:ui:24-uuid:348a976d-5fcf-4dec-ba03-01e12b465025 ; urn:NBN:nl:ui:24-uuid:348a976d-5fcf-4dec-ba03-01e12b465025 ; http://resolver.tudelft.nl/uuid:348a976d-5fcf-4dec-ba03-01e12b465025

Chicago Manual of Style (16th Edition):

Strydis, C. “Universal Processor Architecture for Biomedical Implants: The SiMS Project.” 2011. Doctoral Dissertation, Delft University of Technology. Accessed January 29, 2020. http://resolver.tudelft.nl/uuid:348a976d-5fcf-4dec-ba03-01e12b465025 ; urn:NBN:nl:ui:24-uuid:348a976d-5fcf-4dec-ba03-01e12b465025 ; urn:NBN:nl:ui:24-uuid:348a976d-5fcf-4dec-ba03-01e12b465025 ; http://resolver.tudelft.nl/uuid:348a976d-5fcf-4dec-ba03-01e12b465025.

MLA Handbook (7th Edition):

Strydis, C. “Universal Processor Architecture for Biomedical Implants: The SiMS Project.” 2011. Web. 29 Jan 2020.

Vancouver:

Strydis C. Universal Processor Architecture for Biomedical Implants: The SiMS Project. [Internet] [Doctoral dissertation]. Delft University of Technology; 2011. [cited 2020 Jan 29]. Available from: http://resolver.tudelft.nl/uuid:348a976d-5fcf-4dec-ba03-01e12b465025 ; urn:NBN:nl:ui:24-uuid:348a976d-5fcf-4dec-ba03-01e12b465025 ; urn:NBN:nl:ui:24-uuid:348a976d-5fcf-4dec-ba03-01e12b465025 ; http://resolver.tudelft.nl/uuid:348a976d-5fcf-4dec-ba03-01e12b465025.

Council of Science Editors:

Strydis C. Universal Processor Architecture for Biomedical Implants: The SiMS Project. [Doctoral Dissertation]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:348a976d-5fcf-4dec-ba03-01e12b465025 ; urn:NBN:nl:ui:24-uuid:348a976d-5fcf-4dec-ba03-01e12b465025 ; urn:NBN:nl:ui:24-uuid:348a976d-5fcf-4dec-ba03-01e12b465025 ; http://resolver.tudelft.nl/uuid:348a976d-5fcf-4dec-ba03-01e12b465025

14. Dasika, Ganesh Suryanarayan. Power-Efficient Accelerators for High-Performance Applications.

Degree: PhD, Computer Science & Engineering, 2011, University of Michigan

 Computers, regardless of their function, are always better if they can operate more quickly. The addition of computation resources allows for improved response times, greater… (more)

Subjects/Keywords: High-performance Computing; Low-power Computing; Power-efficient Computing; SIMD Architectures; Streaming Architectures; Application-specific Processors; Computer Science; Electrical Engineering; Engineering

…Design for Portable, Low-Power Medical Ultrasound . . . 158 IX. Conclusions… …communication; portable and low-power medical imaging; and scientific, throughputoriented computing… …video. Portable and low-power medical imaging: Medical imaging is one of the most effective… …scientific computing and a low-power processor for extremely portable medical ultrasound devices… …consequently, increased interest in reducing the intensity and power of the x-rays. Using low-power… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dasika, G. S. (2011). Power-Efficient Accelerators for High-Performance Applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86478

Chicago Manual of Style (16th Edition):

Dasika, Ganesh Suryanarayan. “Power-Efficient Accelerators for High-Performance Applications.” 2011. Doctoral Dissertation, University of Michigan. Accessed January 29, 2020. http://hdl.handle.net/2027.42/86478.

MLA Handbook (7th Edition):

Dasika, Ganesh Suryanarayan. “Power-Efficient Accelerators for High-Performance Applications.” 2011. Web. 29 Jan 2020.

Vancouver:

Dasika GS. Power-Efficient Accelerators for High-Performance Applications. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/2027.42/86478.

Council of Science Editors:

Dasika GS. Power-Efficient Accelerators for High-Performance Applications. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86478


Delft University of Technology

15. Nadeem, M. Adaptive, Low-power Architectures for Embedded Multimedia Systems; with focus on H.264/AVC video codec.

Degree: 2014, Delft University of Technology

Subjects/Keywords: Low-power Architectures; VLIW processor; Softcore Processor; Application-specific Custom Instructions; Embedded Multimedia Systems; Reduced Complexity Video Compression Algorithms; Video Codec H.264/AVC; Run-time Adaptive Processor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nadeem, M. (2014). Adaptive, Low-power Architectures for Embedded Multimedia Systems; with focus on H.264/AVC video codec. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4 ; urn:NBN:nl:ui:24-uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4 ; urn:NBN:nl:ui:24-uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4 ; http://resolver.tudelft.nl/uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4

Chicago Manual of Style (16th Edition):

Nadeem, M. “Adaptive, Low-power Architectures for Embedded Multimedia Systems; with focus on H.264/AVC video codec.” 2014. Doctoral Dissertation, Delft University of Technology. Accessed January 29, 2020. http://resolver.tudelft.nl/uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4 ; urn:NBN:nl:ui:24-uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4 ; urn:NBN:nl:ui:24-uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4 ; http://resolver.tudelft.nl/uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4.

MLA Handbook (7th Edition):

Nadeem, M. “Adaptive, Low-power Architectures for Embedded Multimedia Systems; with focus on H.264/AVC video codec.” 2014. Web. 29 Jan 2020.

Vancouver:

Nadeem M. Adaptive, Low-power Architectures for Embedded Multimedia Systems; with focus on H.264/AVC video codec. [Internet] [Doctoral dissertation]. Delft University of Technology; 2014. [cited 2020 Jan 29]. Available from: http://resolver.tudelft.nl/uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4 ; urn:NBN:nl:ui:24-uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4 ; urn:NBN:nl:ui:24-uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4 ; http://resolver.tudelft.nl/uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4.

Council of Science Editors:

Nadeem M. Adaptive, Low-power Architectures for Embedded Multimedia Systems; with focus on H.264/AVC video codec. [Doctoral Dissertation]. Delft University of Technology; 2014. Available from: http://resolver.tudelft.nl/uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4 ; urn:NBN:nl:ui:24-uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4 ; urn:NBN:nl:ui:24-uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4 ; http://resolver.tudelft.nl/uuid:b0741a29-dac2-413d-96d3-d11945b4c8f4

16. Jafarian, Hossein. Low-power ASIC design with integrated multiple sensor system.

Degree: 2013, IUPUI

Indiana University-Purdue University Indianapolis (IUPUI)

A novel method of power management and sequential monitoring of several sensors is proposed in this work. Application specific integrated… (more)

Subjects/Keywords: LOW-POWER, ASIC DESIGN, MULTIPLE SENSOR SYSTEM; Application-specific integrated circuits  – Research; Application specific integrated circuits  – Design and construction; Low voltage integrated circuits  – Analysis; Metal oxide semiconductors, Complementary  – Research; Digital electronics; Sensor networks; Voltage-controlled oscillators; Integrated circuits; Analog-to-digital converters; Digital-to-analog converters

…on-chip is a low-power and low-voltage system for continuous real-time application for… …University, August 2013. Low-Power ASIC Design with Integrated Multiple Sensor System. Major… …technologies have attempted low-power consumption [1–10]. The products could be used in… …ECG data while the chip consumes only 19 µW. The low amount of power consumption is suited… …harvesting, dynamic power management, low voltage boost circuit, bio-signal front-ends, and radio… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jafarian, H. (2013). Low-power ASIC design with integrated multiple sensor system. (Thesis). IUPUI. Retrieved from http://hdl.handle.net/1805/3745

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jafarian, Hossein. “Low-power ASIC design with integrated multiple sensor system.” 2013. Thesis, IUPUI. Accessed January 29, 2020. http://hdl.handle.net/1805/3745.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jafarian, Hossein. “Low-power ASIC design with integrated multiple sensor system.” 2013. Web. 29 Jan 2020.

Vancouver:

Jafarian H. Low-power ASIC design with integrated multiple sensor system. [Internet] [Thesis]. IUPUI; 2013. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1805/3745.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jafarian H. Low-power ASIC design with integrated multiple sensor system. [Thesis]. IUPUI; 2013. Available from: http://hdl.handle.net/1805/3745

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

17. Zhang, Heng. High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications.

Degree: 2012, Texas A&M University

 The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards… (more)

Subjects/Keywords: High frequency linearization; single-stage; ultrawideband(UWB); low noise amplifier (LNA); common gate (CG); low power; RF; capacitive cross-coupling; noise figure; noise reduction; linearity improvement; linearity; linearization; IIP2; IIP3; 1dB compression point; distortion cancelling; broadband LNA; CMOS technology scaling; design guidelines; ADC; pipeline ADC; cyclic ADC; SAR ADC; time-to-digital converter; video application; multi-standard receiver; analog power scaling; reconfigurable; programmable; scalable; adaptive

…105 4.3 Proposed Low Power Single-Stage UWB CG-LNA ..................................... 108… …139 5.3 Low Power High Efficiency ADCs… …156 Table 5.3. State-of-art low power high efficiency opamp-less ADCs… …offset cancellation technique for a low power cyclic ADC. 6) Proposes a speed… …adaptive ADCs, ultra-low power ADCs, and time-domain ADCs as the three new trends. A low power… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, H. (2012). High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8609

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Heng. “High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications.” 2012. Thesis, Texas A&M University. Accessed January 29, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8609.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Heng. “High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications.” 2012. Web. 29 Jan 2020.

Vancouver:

Zhang H. High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Jan 29]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8609.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang H. High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8609

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Luleå University of Technology

18. Martinez, Lisandro. Space radiation analysis : radiation effects and particle interaction outside Earth Magnetosphere using GRAS and GEANT4.

Degree: 2009, Luleå University of Technology

Detailed analyses of galactic cosmic rays (GCR), solar proton events (SPE), and solar fluence effects have been conducted using SPENVIS and CREME96 data files… (more)

Subjects/Keywords: Technology; Space Science; technology; radiation; space radiation; space; physics; cancer; GEANT4; GRAS; ICRU sphere; AG: Antigravity; ALARA: As Low As Reasonably Achievable; ASTAR: stopping power and range tables for helium ions; BERT: Bertini Cascade Model; BNTR: Bimodal Nuclear Thermal Rocket; CERN: European Organization for Nuclear Research; CHIPS: Chiral Invariant Phase Space; CPU: Central Processing Unit; CREME96: Cosmic Ray Effects on Micro Electronics; DOSTEL: DOSimetry TELescopes; ESA: European Space Agency; GCR: Galactic Cosmic Rays; GDML: Geometry Description Markup Language; GEANT4: toolkit for the simulation of the passage of; particles through matter; GNC: Guidance Navigation and Control; GRAS: Geant4 Radiation Analysis for Space; HEP: High Energy Parameterized; ICRU: International Commission on Radiation Units and; Measurements; IMF: Interplanetary Magnetic Field; IMLEO: Initial Mass in Low Earth Orbit; INFI: Instituto Natzionale di Fisica Nuclear); ISP: Specific Impulse; ISS: International Space Station; JPL: Jet Propulsion Laboratory; LEO: Low Earth Orbit; LEP: Low Energy Parameterized; MPD: Magneto Plasma Dynamics; MULASSIS: MUlti‐:LAyered Shielding Simulation Software; NASA: National Aeronautics and Space Administration; NCRP: National Council of Radiation Protection; NEP: Nuclear Electric Propulsion; NERVA: Nuclear Engine Rocket Vehicle Application; NIST: National Institute of Standards and Technology; NTR: Nuclear Thermal Rocket; PSTAR: stopping power and range tables for protons; QGS: Quark Gluon String; S/C: Spacecraft; SPE: Solar Proton Events; SEP: Solar Electric Propulsion; SPENVIS: Space Environment Information System; TEPC: Tissue Equivalent Proportional Counter; TMI: Trans Mars Insertion; TPS: Thermal Protection System; Teknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Martinez, L. (2009). Space radiation analysis : radiation effects and particle interaction outside Earth Magnetosphere using GRAS and GEANT4. (Thesis). Luleå University of Technology. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-48735

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Martinez, Lisandro. “Space radiation analysis : radiation effects and particle interaction outside Earth Magnetosphere using GRAS and GEANT4.” 2009. Thesis, Luleå University of Technology. Accessed January 29, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-48735.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Martinez, Lisandro. “Space radiation analysis : radiation effects and particle interaction outside Earth Magnetosphere using GRAS and GEANT4.” 2009. Web. 29 Jan 2020.

Vancouver:

Martinez L. Space radiation analysis : radiation effects and particle interaction outside Earth Magnetosphere using GRAS and GEANT4. [Internet] [Thesis]. Luleå University of Technology; 2009. [cited 2020 Jan 29]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-48735.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Martinez L. Space radiation analysis : radiation effects and particle interaction outside Earth Magnetosphere using GRAS and GEANT4. [Thesis]. Luleå University of Technology; 2009. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-48735

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Mallangi, Siva Sai Reddy. Low-Power Policies Based on DVFS for the MUSEIC v2 System-on-Chip.

Degree: Information and Communication Technology (ICT), 2017, KTH

Multi functional health monitoring wearable devices are quite prominent these days. Usually these devices are battery-operated and consequently are limited by their battery life… (more)

Subjects/Keywords: Multi functional health monitoring wearable devices are quite prominent these days. Usually these devices are battery-operated and consequently are limited by their battery life (from few hours to a few weeks depending on the application). Of late; it was realized that these devices; which are currently being operated at fixed voltage and frequency; are capable of operating at multiple voltages and frequencies. By switching these voltages and frequencies to lower values based upon power requirements; these devices can achieve tremendous benefits in the form of energy savings. Dynamic Voltage and Frequency Scaling (DVFS) techniques have proven to be handy in this situation for an efficient trade-off between energy and timely behavior. Within imec; wearable devices make use of the indigenously developed MUSEIC v2 (Multi Sensor Integrated circuit - version 2.0). This system is optimized for efficient and accurate collection; processing; and transfer of data from multiple (health) sensors. MUSEIC v2 has limited means in controlling the voltage and frequency dynamically. In this thesis we explore how traditional DVFS techniques can be applied to the MUSEIC v2. Experiments were conducted to find out the optimum power modes to efficiently operate and also to scale up-down the supply voltage and frequency. Considering the overhead caused when switching voltage and frequency; transition analysis was also done. Real-time and non real-time benchmarks were implemented based on these techniques and their performance results were obtained and analyzed. In this process; several state of the art scheduling algorithms and scaling techniques were reviewed in identifying a suitable technique. Using our proposed scaling technique implementation; we have achieved 86.95% power reduction in average; in contrast to the conventional way of the MUSEIC v2 chip’s processor operating at a fixed voltage and frequency. Techniques that include light sleep and deep sleep mode were also studied and implemented; which tested the system’s capability in accommodating Dynamic Power Management (DPM) techniques that can achieve greater benefits. A novel approach for implementing the deep sleep mechanism was also proposed and found that it can obtain up to 71.54% power savings; when compared to a traditional way of executing deep sleep mode. Keywords - low-power; DVFS; DPM; energy; wearable devices; voltage and frequency scal- ing; låg effekt; DVFS; DPM; energi; bärbara enheter; spänning och frekvensskalning; Computer and Information Sciences; Data- och informationsvetenskap; Electrical Engineering, Electronic Engineering, Information Engineering; Elektroteknik och elektronik

…slow-down the processor or switch to low-power mode, while ideally the performance of… …done by building low-power policies such as DVFS and DPM techniques on top of the existing… …8 1 Introduction Chapter 2 3 4 5 6 7 Short description Introduction to low-power… …frequency scaling technique implementation on the ECG application. Discussion also involves power… …Assuming for executing an application/program, Pavg is the average power consumption calculated… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mallangi, S. S. R. (2017). Low-Power Policies Based on DVFS for the MUSEIC v2 System-on-Chip. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-229443

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mallangi, Siva Sai Reddy. “Low-Power Policies Based on DVFS for the MUSEIC v2 System-on-Chip.” 2017. Thesis, KTH. Accessed January 29, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-229443.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mallangi, Siva Sai Reddy. “Low-Power Policies Based on DVFS for the MUSEIC v2 System-on-Chip.” 2017. Web. 29 Jan 2020.

Vancouver:

Mallangi SSR. Low-Power Policies Based on DVFS for the MUSEIC v2 System-on-Chip. [Internet] [Thesis]. KTH; 2017. [cited 2020 Jan 29]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-229443.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mallangi SSR. Low-Power Policies Based on DVFS for the MUSEIC v2 System-on-Chip. [Thesis]. KTH; 2017. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-229443

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.