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You searched for subject:(Loop tiling Computer science ). Showing records 1 – 30 of 202670 total matches.

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University of Minnesota

1. Mehta, Sanyam. Scalable compiler optimizations for improving the memory system performance in multi- and many-core processors.

Degree: PhD, Computer Science, 2014, University of Minnesota

 The last decade has seen the transition from unicore processors to their multi-core (and now many-core) counterparts. This transition has brought about renewed focus on… (more)

Subjects/Keywords: Compiler optimizations; Compiler scalability; Data prefetching; Loop fusion; Loop tiling; Memory performance; Computer science

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APA (6th Edition):

Mehta, S. (2014). Scalable compiler optimizations for improving the memory system performance in multi- and many-core processors. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/168274

Chicago Manual of Style (16th Edition):

Mehta, Sanyam. “Scalable compiler optimizations for improving the memory system performance in multi- and many-core processors.” 2014. Doctoral Dissertation, University of Minnesota. Accessed May 06, 2021. http://hdl.handle.net/11299/168274.

MLA Handbook (7th Edition):

Mehta, Sanyam. “Scalable compiler optimizations for improving the memory system performance in multi- and many-core processors.” 2014. Web. 06 May 2021.

Vancouver:

Mehta S. Scalable compiler optimizations for improving the memory system performance in multi- and many-core processors. [Internet] [Doctoral dissertation]. University of Minnesota; 2014. [cited 2021 May 06]. Available from: http://hdl.handle.net/11299/168274.

Council of Science Editors:

Mehta S. Scalable compiler optimizations for improving the memory system performance in multi- and many-core processors. [Doctoral Dissertation]. University of Minnesota; 2014. Available from: http://hdl.handle.net/11299/168274


The Ohio State University

2. Bernard Selvaraj, Anand Joseph. Effects of Loop Tiling using Primetile and Dyntile.

Degree: MS, Computer Science and Engineering, 2010, The Ohio State University

Loop tiling is one of the most important compiler optimization techniques. A multilevel tiled code can improve the running time of the program by… (more)

Subjects/Keywords: Computer Science; Loop Tiling; Primetile; Dyntile

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APA (6th Edition):

Bernard Selvaraj, A. J. (2010). Effects of Loop Tiling using Primetile and Dyntile. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1285012179

Chicago Manual of Style (16th Edition):

Bernard Selvaraj, Anand Joseph. “Effects of Loop Tiling using Primetile and Dyntile.” 2010. Masters Thesis, The Ohio State University. Accessed May 06, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1285012179.

MLA Handbook (7th Edition):

Bernard Selvaraj, Anand Joseph. “Effects of Loop Tiling using Primetile and Dyntile.” 2010. Web. 06 May 2021.

Vancouver:

Bernard Selvaraj AJ. Effects of Loop Tiling using Primetile and Dyntile. [Internet] [Masters thesis]. The Ohio State University; 2010. [cited 2021 May 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1285012179.

Council of Science Editors:

Bernard Selvaraj AJ. Effects of Loop Tiling using Primetile and Dyntile. [Masters Thesis]. The Ohio State University; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1285012179


Montana State University

3. Tomascak, Andrew Joseph. Fixed-size geometric covering to minimize the number of disconnected components.

Degree: MS, College of Engineering, 2003, Montana State University

Subjects/Keywords: Three-dimensional imaging; Loop tiling (Computer science)

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APA (6th Edition):

Tomascak, A. J. (2003). Fixed-size geometric covering to minimize the number of disconnected components. (Masters Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/8365

Chicago Manual of Style (16th Edition):

Tomascak, Andrew Joseph. “Fixed-size geometric covering to minimize the number of disconnected components.” 2003. Masters Thesis, Montana State University. Accessed May 06, 2021. https://scholarworks.montana.edu/xmlui/handle/1/8365.

MLA Handbook (7th Edition):

Tomascak, Andrew Joseph. “Fixed-size geometric covering to minimize the number of disconnected components.” 2003. Web. 06 May 2021.

Vancouver:

Tomascak AJ. Fixed-size geometric covering to minimize the number of disconnected components. [Internet] [Masters thesis]. Montana State University; 2003. [cited 2021 May 06]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/8365.

Council of Science Editors:

Tomascak AJ. Fixed-size geometric covering to minimize the number of disconnected components. [Masters Thesis]. Montana State University; 2003. Available from: https://scholarworks.montana.edu/xmlui/handle/1/8365


The Ohio State University

4. Henretty, Thomas Steel. Performance Optimization of Stencil Computations on Modern SIMD Architectures.

Degree: PhD, Computer Science and Engineering, 2014, The Ohio State University

 Performance of scientific computing codes on modern high-performance computing(HPC) systems has, in some cases, not achieved a significant percentage of thesystem’s peak performance. Three of… (more)

Subjects/Keywords: Computer Science; stencil; SIMD; PDE; DLT; SDSL; domain specific language; stream alignment conflict; split tiling; nested split tiling; hybrid split tiling

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APA (6th Edition):

Henretty, T. S. (2014). Performance Optimization of Stencil Computations on Modern SIMD Architectures. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1408937226

Chicago Manual of Style (16th Edition):

Henretty, Thomas Steel. “Performance Optimization of Stencil Computations on Modern SIMD Architectures.” 2014. Doctoral Dissertation, The Ohio State University. Accessed May 06, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1408937226.

MLA Handbook (7th Edition):

Henretty, Thomas Steel. “Performance Optimization of Stencil Computations on Modern SIMD Architectures.” 2014. Web. 06 May 2021.

Vancouver:

Henretty TS. Performance Optimization of Stencil Computations on Modern SIMD Architectures. [Internet] [Doctoral dissertation]. The Ohio State University; 2014. [cited 2021 May 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1408937226.

Council of Science Editors:

Henretty TS. Performance Optimization of Stencil Computations on Modern SIMD Architectures. [Doctoral Dissertation]. The Ohio State University; 2014. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1408937226


Indian Institute of Science

5. Bhaskaracharya, Somashekaracharya G. Automatic Storage Optimization of Arrays Affine Loop Nests.

Degree: PhD, Faculty of Engineering, 2018, Indian Institute of Science

 Efficient memory usage is crucial for data-intensive applications as a smaller memory footprint ensures better cache performance and allows one to run a larger problem… (more)

Subjects/Keywords: Automatic Storage Optimization; Dataflow Programs; Affine Loop Nests; Lattice-Boltzmann Method; Diamond Tiling; Blur Filter - Interleaved Schedule; Blur filter - Tiled Execution; Affine Hyperplane; Polyhedral Model; Polyhedral Storage Optimizer; Polyhedral Compilation; PolyGLoT; Polyhedral Loop Transformation; Graphical Dataflow Language; Intra-Array Sorage Optimization; Arrays Storage Optimization; Computer Science

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APA (6th Edition):

Bhaskaracharya, S. G. (2018). Automatic Storage Optimization of Arrays Affine Loop Nests. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/3208

Chicago Manual of Style (16th Edition):

Bhaskaracharya, Somashekaracharya G. “Automatic Storage Optimization of Arrays Affine Loop Nests.” 2018. Doctoral Dissertation, Indian Institute of Science. Accessed May 06, 2021. http://etd.iisc.ac.in/handle/2005/3208.

MLA Handbook (7th Edition):

Bhaskaracharya, Somashekaracharya G. “Automatic Storage Optimization of Arrays Affine Loop Nests.” 2018. Web. 06 May 2021.

Vancouver:

Bhaskaracharya SG. Automatic Storage Optimization of Arrays Affine Loop Nests. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2018. [cited 2021 May 06]. Available from: http://etd.iisc.ac.in/handle/2005/3208.

Council of Science Editors:

Bhaskaracharya SG. Automatic Storage Optimization of Arrays Affine Loop Nests. [Doctoral Dissertation]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/3208

6. Hartono, Albert. Tools for Performance Optimizations and Tuning of Affine Loop Nests.

Degree: PhD, Computer Science and Engineering, 2009, The Ohio State University

  Multicore processors have become mainstream and the number of cores in a chip will continue to increase every year. Programming these architectures to effectively… (more)

Subjects/Keywords: Computer Science; compilers; loop optimizations; parametric tiling; loop parallelization; wavefront parallelism; empirical tuning; annotation-based optimizations

…M.S. Computer Science Indiana University, Bloomington, Indiana Jan 2002–May 2003… …Associate Instructor Computer Science Department Indiana University, Bloomington, Indiana Jun 2003… …Computer Science and Engineering Dept. The Ohio State University Columbus, Ohio Jun 2004–Sept… …Givens Research Fellow Math. and Computer Science Division Argonne National Laboratory Argonne… …Computational Science (ICCS), 2005. FIELDS OF STUDY Major Field: Computer Science and… 

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APA (6th Edition):

Hartono, A. (2009). Tools for Performance Optimizations and Tuning of Affine Loop Nests. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1259685041

Chicago Manual of Style (16th Edition):

Hartono, Albert. “Tools for Performance Optimizations and Tuning of Affine Loop Nests.” 2009. Doctoral Dissertation, The Ohio State University. Accessed May 06, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1259685041.

MLA Handbook (7th Edition):

Hartono, Albert. “Tools for Performance Optimizations and Tuning of Affine Loop Nests.” 2009. Web. 06 May 2021.

Vancouver:

Hartono A. Tools for Performance Optimizations and Tuning of Affine Loop Nests. [Internet] [Doctoral dissertation]. The Ohio State University; 2009. [cited 2021 May 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1259685041.

Council of Science Editors:

Hartono A. Tools for Performance Optimizations and Tuning of Affine Loop Nests. [Doctoral Dissertation]. The Ohio State University; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1259685041


University of Delaware

7. Shrestha, Sunil. A framework for group locality aware multithreading.

Degree: PhD, University of Delaware, Department of Electrical and Computer Engineering, 2015, University of Delaware

 When powerful computational cores are matched against limited resources such as bandwidth and memory, competition across computational units can result in serious performance degradation due… (more)

Subjects/Keywords: Threads (Computer programs); Tiling (Mathematics); Memory management (Computer science); Database management.

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APA (6th Edition):

Shrestha, S. (2015). A framework for group locality aware multithreading. (Doctoral Dissertation). University of Delaware. Retrieved from http://udspace.udel.edu/handle/19716/17515

Chicago Manual of Style (16th Edition):

Shrestha, Sunil. “A framework for group locality aware multithreading.” 2015. Doctoral Dissertation, University of Delaware. Accessed May 06, 2021. http://udspace.udel.edu/handle/19716/17515.

MLA Handbook (7th Edition):

Shrestha, Sunil. “A framework for group locality aware multithreading.” 2015. Web. 06 May 2021.

Vancouver:

Shrestha S. A framework for group locality aware multithreading. [Internet] [Doctoral dissertation]. University of Delaware; 2015. [cited 2021 May 06]. Available from: http://udspace.udel.edu/handle/19716/17515.

Council of Science Editors:

Shrestha S. A framework for group locality aware multithreading. [Doctoral Dissertation]. University of Delaware; 2015. Available from: http://udspace.udel.edu/handle/19716/17515


Colorado State University

8. Kim, DaeGon. Parameterized and multi-level tiled loop generation.

Degree: PhD, Computer Science, 2010, Colorado State University

Tiling is a loop transformation that decomposes computations into a set of smaller computation blocks. The transformation has been proven to be useful for many… (more)

Subjects/Keywords: tiling; polyhedral model; parallelization; optimization; compiler; code generation; Loop tiling (Computer science); Compilers (Computer programs); Loops (Group theory); Parallel processing (Electronic computers)

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APA (6th Edition):

Kim, D. (2010). Parameterized and multi-level tiled loop generation. (Doctoral Dissertation). Colorado State University. Retrieved from http://hdl.handle.net/10217/39103

Chicago Manual of Style (16th Edition):

Kim, DaeGon. “Parameterized and multi-level tiled loop generation.” 2010. Doctoral Dissertation, Colorado State University. Accessed May 06, 2021. http://hdl.handle.net/10217/39103.

MLA Handbook (7th Edition):

Kim, DaeGon. “Parameterized and multi-level tiled loop generation.” 2010. Web. 06 May 2021.

Vancouver:

Kim D. Parameterized and multi-level tiled loop generation. [Internet] [Doctoral dissertation]. Colorado State University; 2010. [cited 2021 May 06]. Available from: http://hdl.handle.net/10217/39103.

Council of Science Editors:

Kim D. Parameterized and multi-level tiled loop generation. [Doctoral Dissertation]. Colorado State University; 2010. Available from: http://hdl.handle.net/10217/39103


University of New South Wales

9. Di, Peng. Automatic Parallelization of Tiled Stencil Loop Nests on GPUs.

Degree: Computer Science & Engineering, 2013, University of New South Wales

 This thesis attempts to design and implement a compiler framework based on the polyhedral model. The compiler automatically parallelizes loop nests; especially stencil kernels, into… (more)

Subjects/Keywords: Compiler; GPU; Loop tiling; Parallel computing

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APA (6th Edition):

Di, P. (2013). Automatic Parallelization of Tiled Stencil Loop Nests on GPUs. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/53495 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:12190/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Di, Peng. “Automatic Parallelization of Tiled Stencil Loop Nests on GPUs.” 2013. Doctoral Dissertation, University of New South Wales. Accessed May 06, 2021. http://handle.unsw.edu.au/1959.4/53495 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:12190/SOURCE02?view=true.

MLA Handbook (7th Edition):

Di, Peng. “Automatic Parallelization of Tiled Stencil Loop Nests on GPUs.” 2013. Web. 06 May 2021.

Vancouver:

Di P. Automatic Parallelization of Tiled Stencil Loop Nests on GPUs. [Internet] [Doctoral dissertation]. University of New South Wales; 2013. [cited 2021 May 06]. Available from: http://handle.unsw.edu.au/1959.4/53495 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:12190/SOURCE02?view=true.

Council of Science Editors:

Di P. Automatic Parallelization of Tiled Stencil Loop Nests on GPUs. [Doctoral Dissertation]. University of New South Wales; 2013. Available from: http://handle.unsw.edu.au/1959.4/53495 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:12190/SOURCE02?view=true


Indian Institute of Science

10. Pananilath, Irshad Muhammed. An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations.

Degree: MSc Engg, Faculty of Engineering, 2018, Indian Institute of Science

 Lattice-Boltzmann method(LBM), a promising new particle-based simulation technique for complex and multiscale fluid flows, has seen tremendous adoption in recent years in computational fluid dynamics.… (more)

Subjects/Keywords: Lattice-Boltzmann Computations; Computational Fluid Dynamics; Tiling Stencil Computations; Single Instruction Multiple Data (SIMD); Parallel Computers; Parallel Processing; Loop Transformations; Lattice-Boltzman Method (LBM); Lattice Boltzman Method; Lattice-Boltzmann Equation; Computer Science

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APA (6th Edition):

Pananilath, I. M. (2018). An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/3259

Chicago Manual of Style (16th Edition):

Pananilath, Irshad Muhammed. “An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations.” 2018. Masters Thesis, Indian Institute of Science. Accessed May 06, 2021. http://etd.iisc.ac.in/handle/2005/3259.

MLA Handbook (7th Edition):

Pananilath, Irshad Muhammed. “An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations.” 2018. Web. 06 May 2021.

Vancouver:

Pananilath IM. An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations. [Internet] [Masters thesis]. Indian Institute of Science; 2018. [cited 2021 May 06]. Available from: http://etd.iisc.ac.in/handle/2005/3259.

Council of Science Editors:

Pananilath IM. An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations. [Masters Thesis]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/3259


Indian Institute of Science

11. Bandishti, Vinayaka Prakasha. Tiling Stencil Computations To Maximize Parallelism.

Degree: MSc Engg, Faculty of Engineering, 2017, Indian Institute of Science

 Stencil computations are iterative kernels often used to simulate the change in a discretized spatial domain overtime (e.g., computational fluid dynamics) or to solve for… (more)

Subjects/Keywords: Stencil Computations; Concurrent Start-Up; Tiling Hyperplanes; Periodic Stencils; Compilers (Computer Programs); Multiprocessors; Computer Architecture; Parallelism (Computer Architecture); Tiling Stencil Computations; Automatic Parallelizers; Pluto-Source Level Automatic Parallelizer; Computer Science

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APA (6th Edition):

Bandishti, V. P. (2017). Tiling Stencil Computations To Maximize Parallelism. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/2619

Chicago Manual of Style (16th Edition):

Bandishti, Vinayaka Prakasha. “Tiling Stencil Computations To Maximize Parallelism.” 2017. Masters Thesis, Indian Institute of Science. Accessed May 06, 2021. http://etd.iisc.ac.in/handle/2005/2619.

MLA Handbook (7th Edition):

Bandishti, Vinayaka Prakasha. “Tiling Stencil Computations To Maximize Parallelism.” 2017. Web. 06 May 2021.

Vancouver:

Bandishti VP. Tiling Stencil Computations To Maximize Parallelism. [Internet] [Masters thesis]. Indian Institute of Science; 2017. [cited 2021 May 06]. Available from: http://etd.iisc.ac.in/handle/2005/2619.

Council of Science Editors:

Bandishti VP. Tiling Stencil Computations To Maximize Parallelism. [Masters Thesis]. Indian Institute of Science; 2017. Available from: http://etd.iisc.ac.in/handle/2005/2619


The Ohio State University

12. Jhally, Gaganjit Singh. Sampling of Dynamic Dependence Graphs for Data Locality Analysis.

Degree: MS, Computer Science and Engineering, 2016, The Ohio State University

 Data locality is a critical factor which affects the execution time of applications today. With major advances being made in reducing the computation time of… (more)

Subjects/Keywords: Computer Science; Data movement costs, cache miss cost, time tiling technique, sampling, dynamic analysis

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APA (6th Edition):

Jhally, G. S. (2016). Sampling of Dynamic Dependence Graphs for Data Locality Analysis. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1462885420

Chicago Manual of Style (16th Edition):

Jhally, Gaganjit Singh. “Sampling of Dynamic Dependence Graphs for Data Locality Analysis.” 2016. Masters Thesis, The Ohio State University. Accessed May 06, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1462885420.

MLA Handbook (7th Edition):

Jhally, Gaganjit Singh. “Sampling of Dynamic Dependence Graphs for Data Locality Analysis.” 2016. Web. 06 May 2021.

Vancouver:

Jhally GS. Sampling of Dynamic Dependence Graphs for Data Locality Analysis. [Internet] [Masters thesis]. The Ohio State University; 2016. [cited 2021 May 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1462885420.

Council of Science Editors:

Jhally GS. Sampling of Dynamic Dependence Graphs for Data Locality Analysis. [Masters Thesis]. The Ohio State University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1462885420


The Ohio State University

13. Rajaraman, Bhargavi. IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS.

Degree: MS, Computer Science and Engineering, 2009, The Ohio State University

Tiling is a crucial loop transformation for generating high-performance code on modern architectures to expose coarse grain parallelism in multi-core architectures and to maximize data… (more)

Subjects/Keywords: Computer Science; Register tiling; CLooG; ROSE; TLOG

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APA (6th Edition):

Rajaraman, B. (2009). IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1245123518

Chicago Manual of Style (16th Edition):

Rajaraman, Bhargavi. “IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS.” 2009. Masters Thesis, The Ohio State University. Accessed May 06, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1245123518.

MLA Handbook (7th Edition):

Rajaraman, Bhargavi. “IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS.” 2009. Web. 06 May 2021.

Vancouver:

Rajaraman B. IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS. [Internet] [Masters thesis]. The Ohio State University; 2009. [cited 2021 May 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1245123518.

Council of Science Editors:

Rajaraman B. IMPLEMENTATION AND EVALUATION OF REGISTER TILING FOR PERFECTLY NESTED LOOPS. [Masters Thesis]. The Ohio State University; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1245123518


The Ohio State University

14. Sreenivasa Murthy, Giridhar. Optimal Loop Unrolling for GPGPU Programs.

Degree: MS, Computer Science and Engineering, 2009, The Ohio State University

  Graphics Processing Units (GPUs) are massively parallel, many-coreprocessors with tremendous computational power and very high memorybandwidth. GPUs are primarily designed for accelerating 3D graphicsapplications… (more)

Subjects/Keywords: Computer Science; GPGPU; Compiler Optimizations; Loop Transformations; Loop Unrolling

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APA (6th Edition):

Sreenivasa Murthy, G. (2009). Optimal Loop Unrolling for GPGPU Programs. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1253131903

Chicago Manual of Style (16th Edition):

Sreenivasa Murthy, Giridhar. “Optimal Loop Unrolling for GPGPU Programs.” 2009. Masters Thesis, The Ohio State University. Accessed May 06, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1253131903.

MLA Handbook (7th Edition):

Sreenivasa Murthy, Giridhar. “Optimal Loop Unrolling for GPGPU Programs.” 2009. Web. 06 May 2021.

Vancouver:

Sreenivasa Murthy G. Optimal Loop Unrolling for GPGPU Programs. [Internet] [Masters thesis]. The Ohio State University; 2009. [cited 2021 May 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1253131903.

Council of Science Editors:

Sreenivasa Murthy G. Optimal Loop Unrolling for GPGPU Programs. [Masters Thesis]. The Ohio State University; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1253131903


Indian Institute of Science

15. Mullapudi, Ravi Teja. Polymage : Automatic Optimization for Image Processing Pipelines.

Degree: MSc Engg, Faculty of Engineering, 2018, Indian Institute of Science

 Image processing pipelines are ubiquitous. Every image captured by a camera and every image uploaded on social networks like Google+or Facebook is processed by a… (more)

Subjects/Keywords: Polymage; Image Processing; Polyhydral Optimization; Image Processing Pipelines; Domain Specific Languages; Compiler Optimiation; Multicore Processing; Parallel Computing; Code Generation; Tiling; Pipeline Graphs; Computer Science

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APA (6th Edition):

Mullapudi, R. T. (2018). Polymage : Automatic Optimization for Image Processing Pipelines. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/3757

Chicago Manual of Style (16th Edition):

Mullapudi, Ravi Teja. “Polymage : Automatic Optimization for Image Processing Pipelines.” 2018. Masters Thesis, Indian Institute of Science. Accessed May 06, 2021. http://etd.iisc.ac.in/handle/2005/3757.

MLA Handbook (7th Edition):

Mullapudi, Ravi Teja. “Polymage : Automatic Optimization for Image Processing Pipelines.” 2018. Web. 06 May 2021.

Vancouver:

Mullapudi RT. Polymage : Automatic Optimization for Image Processing Pipelines. [Internet] [Masters thesis]. Indian Institute of Science; 2018. [cited 2021 May 06]. Available from: http://etd.iisc.ac.in/handle/2005/3757.

Council of Science Editors:

Mullapudi RT. Polymage : Automatic Optimization for Image Processing Pipelines. [Masters Thesis]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/3757

16. Chidambarnathan, Yogesh. Characterizing the Effectiveness of Compilers in Vectorizing Polyhedrally Transformed Code.

Degree: MS, Computer Science and Engineering, 2013, The Ohio State University

 Many of the compute intensive applications spend most of their time inside nested loops. Hence optimization of these nested loops can provide significant improvements in… (more)

Subjects/Keywords: Computer Science; Vectorization; Tiling; Polyhedral model; PAPI; Pluto; Ptile

…unrolling, tiling, loop permutation etc. Each of them change the structure of the loop in order to… …parallelization on affine loop nests [1]. 2) Parametric Tiling using PTile with full tile… …52 4.2 Case 1: Tiling reduces percentage vectorization for both PLuTo and PTile…....52 4.3… …Case 2: Better vectorization happens with PTile than with no tiling ...54 4.4 Case 3… …better than PLuTo in terms of vectorization ….......57 4.6 Case 5: Tiling does not affect the… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chidambarnathan, Y. (2013). Characterizing the Effectiveness of Compilers in Vectorizing Polyhedrally Transformed Code. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1357321939

Chicago Manual of Style (16th Edition):

Chidambarnathan, Yogesh. “Characterizing the Effectiveness of Compilers in Vectorizing Polyhedrally Transformed Code.” 2013. Masters Thesis, The Ohio State University. Accessed May 06, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1357321939.

MLA Handbook (7th Edition):

Chidambarnathan, Yogesh. “Characterizing the Effectiveness of Compilers in Vectorizing Polyhedrally Transformed Code.” 2013. Web. 06 May 2021.

Vancouver:

Chidambarnathan Y. Characterizing the Effectiveness of Compilers in Vectorizing Polyhedrally Transformed Code. [Internet] [Masters thesis]. The Ohio State University; 2013. [cited 2021 May 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1357321939.

Council of Science Editors:

Chidambarnathan Y. Characterizing the Effectiveness of Compilers in Vectorizing Polyhedrally Transformed Code. [Masters Thesis]. The Ohio State University; 2013. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1357321939


University of California – Irvine

17. Shivam, Aniket. Polygonal Iteration Space Partitioning using the Polyhedral Model.

Degree: Computer Science, 2016, University of California – Irvine

Loop-nests in most scientific applications perform repetitive operations on array(s) and account for most of the program execution time. Traditional loop transformations, such as tiling,… (more)

Subjects/Keywords: Computer science; Loop Transformations; Non-Uniform Reuse Pattern Loops; Polygonal Iteration Space Partitioning; Polyhedral Model

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shivam, A. (2016). Polygonal Iteration Space Partitioning using the Polyhedral Model. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/6fr1t6km

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shivam, Aniket. “Polygonal Iteration Space Partitioning using the Polyhedral Model.” 2016. Thesis, University of California – Irvine. Accessed May 06, 2021. http://www.escholarship.org/uc/item/6fr1t6km.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shivam, Aniket. “Polygonal Iteration Space Partitioning using the Polyhedral Model.” 2016. Web. 06 May 2021.

Vancouver:

Shivam A. Polygonal Iteration Space Partitioning using the Polyhedral Model. [Internet] [Thesis]. University of California – Irvine; 2016. [cited 2021 May 06]. Available from: http://www.escholarship.org/uc/item/6fr1t6km.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shivam A. Polygonal Iteration Space Partitioning using the Polyhedral Model. [Thesis]. University of California – Irvine; 2016. Available from: http://www.escholarship.org/uc/item/6fr1t6km

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Merced

18. Beltran, Alex. Optimizing HVAC Systems using Occupant Detection and User Thermal Preferences.

Degree: Electrical Engineering and Computer Science, 2017, University of California – Merced

 Buildings are a crucial part of our daily lives and people spend 87% of their timeinside buildings. To maintain thermal comfort in buildings a significant… (more)

Subjects/Keywords: Electrical engineering; Computer science; human-in-the-loop; model predictive control; wireless sensor networks

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Beltran, A. (2017). Optimizing HVAC Systems using Occupant Detection and User Thermal Preferences. (Thesis). University of California – Merced. Retrieved from http://www.escholarship.org/uc/item/903009qq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Beltran, Alex. “Optimizing HVAC Systems using Occupant Detection and User Thermal Preferences.” 2017. Thesis, University of California – Merced. Accessed May 06, 2021. http://www.escholarship.org/uc/item/903009qq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Beltran, Alex. “Optimizing HVAC Systems using Occupant Detection and User Thermal Preferences.” 2017. Web. 06 May 2021.

Vancouver:

Beltran A. Optimizing HVAC Systems using Occupant Detection and User Thermal Preferences. [Internet] [Thesis]. University of California – Merced; 2017. [cited 2021 May 06]. Available from: http://www.escholarship.org/uc/item/903009qq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Beltran A. Optimizing HVAC Systems using Occupant Detection and User Thermal Preferences. [Thesis]. University of California – Merced; 2017. Available from: http://www.escholarship.org/uc/item/903009qq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Western Ontario

19. Dong, Qin. Oligonucleotide Design for Whole Genome Tiling Arrays.

Degree: 2014, University of Western Ontario

 Oligonucleotides are short, single-stranded fragments of DNA or RNA, designed to readily bind with a unique part in the target sequence. They have many important… (more)

Subjects/Keywords: DNA; oligonucleotide; tiling arrays; microarrays; Bioinformatics; Other Computer Sciences

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dong, Q. (2014). Oligonucleotide Design for Whole Genome Tiling Arrays. (Thesis). University of Western Ontario. Retrieved from https://ir.lib.uwo.ca/etd/1875

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dong, Qin. “Oligonucleotide Design for Whole Genome Tiling Arrays.” 2014. Thesis, University of Western Ontario. Accessed May 06, 2021. https://ir.lib.uwo.ca/etd/1875.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dong, Qin. “Oligonucleotide Design for Whole Genome Tiling Arrays.” 2014. Web. 06 May 2021.

Vancouver:

Dong Q. Oligonucleotide Design for Whole Genome Tiling Arrays. [Internet] [Thesis]. University of Western Ontario; 2014. [cited 2021 May 06]. Available from: https://ir.lib.uwo.ca/etd/1875.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dong Q. Oligonucleotide Design for Whole Genome Tiling Arrays. [Thesis]. University of Western Ontario; 2014. Available from: https://ir.lib.uwo.ca/etd/1875

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Rochester

20. Bao, Bin (1982 - ). Peer-aware program optimization.

Degree: PhD, 2013, University of Rochester

 Most existing program optimization techniques are based on the code or the behavior of the target program, which means they can be characterized as self-aware.… (more)

Subjects/Keywords: Defensive loop tiling; Dynamic computation and communication pipelining; Peer-aware; Program collaboration; Program interference; Program optimization.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bao, B. (. -. ). (2013). Peer-aware program optimization. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/26831

Chicago Manual of Style (16th Edition):

Bao, Bin (1982 - ). “Peer-aware program optimization.” 2013. Doctoral Dissertation, University of Rochester. Accessed May 06, 2021. http://hdl.handle.net/1802/26831.

MLA Handbook (7th Edition):

Bao, Bin (1982 - ). “Peer-aware program optimization.” 2013. Web. 06 May 2021.

Vancouver:

Bao B(-). Peer-aware program optimization. [Internet] [Doctoral dissertation]. University of Rochester; 2013. [cited 2021 May 06]. Available from: http://hdl.handle.net/1802/26831.

Council of Science Editors:

Bao B(-). Peer-aware program optimization. [Doctoral Dissertation]. University of Rochester; 2013. Available from: http://hdl.handle.net/1802/26831

21. Dangi, Siddharth. Closed-loop decoder adaptation algorithms for brain-machine interface systems.

Degree: Electrical Engineering & Computer Sciences, 2015, University of California – Berkeley

 Brain-machine interfaces (BMIs) aim to assist patients suffering from neurological injuries and disease by enabling them to use their own neural activity to control external… (more)

Subjects/Keywords: Electrical engineering; Computer science; Neurosciences; BCI; BMI; brain-computer interface; brain-machine interface; CLDA; closed-loop decoder adaptation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dangi, S. (2015). Closed-loop decoder adaptation algorithms for brain-machine interface systems. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/5xx451th

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dangi, Siddharth. “Closed-loop decoder adaptation algorithms for brain-machine interface systems.” 2015. Thesis, University of California – Berkeley. Accessed May 06, 2021. http://www.escholarship.org/uc/item/5xx451th.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dangi, Siddharth. “Closed-loop decoder adaptation algorithms for brain-machine interface systems.” 2015. Web. 06 May 2021.

Vancouver:

Dangi S. Closed-loop decoder adaptation algorithms for brain-machine interface systems. [Internet] [Thesis]. University of California – Berkeley; 2015. [cited 2021 May 06]. Available from: http://www.escholarship.org/uc/item/5xx451th.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dangi S. Closed-loop decoder adaptation algorithms for brain-machine interface systems. [Thesis]. University of California – Berkeley; 2015. Available from: http://www.escholarship.org/uc/item/5xx451th

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Louisiana State University

22. Panyala, Ajay. Search-based Model-driven Loop Optimizations for Tensor Contractions.

Degree: PhD, Computer Sciences, 2014, Louisiana State University

 Complex tensor contraction expressions arise in accurate electronic structure models in quantum chemistry, such as the coupled cluster method. The Tensor Contraction Engine (TCE) is… (more)

Subjects/Keywords: Cost Models; Index permutation; Compiler Optimizations; Quantum Chemistry; High performance computing; Tensor Contractions; electronic structure calculations; Loop Fusion; Loop Tiling; GPGPUs; Layout optimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Panyala, A. (2014). Search-based Model-driven Loop Optimizations for Tensor Contractions. (Doctoral Dissertation). Louisiana State University. Retrieved from etd-06262014-234749 ; https://digitalcommons.lsu.edu/gradschool_dissertations/3717

Chicago Manual of Style (16th Edition):

Panyala, Ajay. “Search-based Model-driven Loop Optimizations for Tensor Contractions.” 2014. Doctoral Dissertation, Louisiana State University. Accessed May 06, 2021. etd-06262014-234749 ; https://digitalcommons.lsu.edu/gradschool_dissertations/3717.

MLA Handbook (7th Edition):

Panyala, Ajay. “Search-based Model-driven Loop Optimizations for Tensor Contractions.” 2014. Web. 06 May 2021.

Vancouver:

Panyala A. Search-based Model-driven Loop Optimizations for Tensor Contractions. [Internet] [Doctoral dissertation]. Louisiana State University; 2014. [cited 2021 May 06]. Available from: etd-06262014-234749 ; https://digitalcommons.lsu.edu/gradschool_dissertations/3717.

Council of Science Editors:

Panyala A. Search-based Model-driven Loop Optimizations for Tensor Contractions. [Doctoral Dissertation]. Louisiana State University; 2014. Available from: etd-06262014-234749 ; https://digitalcommons.lsu.edu/gradschool_dissertations/3717


Bowling Green State University

23. Tang, Woon Khang. Automated Coronal Loop Segmentation Using Snake-Based Algorithm.

Degree: MS, Computer Science, 2010, Bowling Green State University

 In this thesis, an automated technique, G-snake, for segmenting the coronal loops fromintensity images of the Sun's corona is studied. G-snake involves use of the… (more)

Subjects/Keywords: Computer Science; G-snake; loop structures; CORONAL LOOP SEGMENTATION; point of the snake

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tang, W. K. (2010). Automated Coronal Loop Segmentation Using Snake-Based Algorithm. (Masters Thesis). Bowling Green State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=bgsu1277139373

Chicago Manual of Style (16th Edition):

Tang, Woon Khang. “Automated Coronal Loop Segmentation Using Snake-Based Algorithm.” 2010. Masters Thesis, Bowling Green State University. Accessed May 06, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=bgsu1277139373.

MLA Handbook (7th Edition):

Tang, Woon Khang. “Automated Coronal Loop Segmentation Using Snake-Based Algorithm.” 2010. Web. 06 May 2021.

Vancouver:

Tang WK. Automated Coronal Loop Segmentation Using Snake-Based Algorithm. [Internet] [Masters thesis]. Bowling Green State University; 2010. [cited 2021 May 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=bgsu1277139373.

Council of Science Editors:

Tang WK. Automated Coronal Loop Segmentation Using Snake-Based Algorithm. [Masters Thesis]. Bowling Green State University; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=bgsu1277139373


University of California – Berkeley

24. Driggs Campbell, Katherine Rose. Tools for Trustworthy Autonomy: Robust Predictions, Intuitive Control, and Optimized Interaction.

Degree: Electrical Engineering & Computer Sciences, 2017, University of California – Berkeley

 In the near future, robotics will impact nearly every aspect of life. Yet for technology to smoothly integrate into society, we need interactive systems to… (more)

Subjects/Keywords: Robotics; Electrical engineering; Computer science; autonomous vehicles; human-in-the-loop; human modeling; robotics; robust predictions

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APA (6th Edition):

Driggs Campbell, K. R. (2017). Tools for Trustworthy Autonomy: Robust Predictions, Intuitive Control, and Optimized Interaction. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/7vh936w7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Driggs Campbell, Katherine Rose. “Tools for Trustworthy Autonomy: Robust Predictions, Intuitive Control, and Optimized Interaction.” 2017. Thesis, University of California – Berkeley. Accessed May 06, 2021. http://www.escholarship.org/uc/item/7vh936w7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Driggs Campbell, Katherine Rose. “Tools for Trustworthy Autonomy: Robust Predictions, Intuitive Control, and Optimized Interaction.” 2017. Web. 06 May 2021.

Vancouver:

Driggs Campbell KR. Tools for Trustworthy Autonomy: Robust Predictions, Intuitive Control, and Optimized Interaction. [Internet] [Thesis]. University of California – Berkeley; 2017. [cited 2021 May 06]. Available from: http://www.escholarship.org/uc/item/7vh936w7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Driggs Campbell KR. Tools for Trustworthy Autonomy: Robust Predictions, Intuitive Control, and Optimized Interaction. [Thesis]. University of California – Berkeley; 2017. Available from: http://www.escholarship.org/uc/item/7vh936w7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

25. Mehrara, Mojtaba. Compiler and Runtime Techniques for Automatic Parallelization of Sequential Applications.

Degree: PhD, Computer Science & Engineering, 2011, University of Michigan

 Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performance for most… (more)

Subjects/Keywords: Speculative Parallelization; Software Transactional Memory; JavaScript Parallelization; Multicore Compilation; Dynamic Parallelization; Loop Level Parallelism; Computer Science; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mehrara, M. (2011). Compiler and Runtime Techniques for Automatic Parallelization of Sequential Applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86499

Chicago Manual of Style (16th Edition):

Mehrara, Mojtaba. “Compiler and Runtime Techniques for Automatic Parallelization of Sequential Applications.” 2011. Doctoral Dissertation, University of Michigan. Accessed May 06, 2021. http://hdl.handle.net/2027.42/86499.

MLA Handbook (7th Edition):

Mehrara, Mojtaba. “Compiler and Runtime Techniques for Automatic Parallelization of Sequential Applications.” 2011. Web. 06 May 2021.

Vancouver:

Mehrara M. Compiler and Runtime Techniques for Automatic Parallelization of Sequential Applications. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2021 May 06]. Available from: http://hdl.handle.net/2027.42/86499.

Council of Science Editors:

Mehrara M. Compiler and Runtime Techniques for Automatic Parallelization of Sequential Applications. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86499


Duke University

26. Tripathy, Chittaranjan. Novel Algorithms for Protein Structure Determination from Sparse NMR Data .

Degree: 2012, Duke University

  Nuclear magnetic resonance (NMR) spectroscopy is an established technique for macromolecular structure determination at atomic resolution. However, the majority of the current structure determination… (more)

Subjects/Keywords: Computer science; Inverse Kinematics; Protein Loop; Protein Structure; Residual chemical shift anisotropy; Residual dipolar coupling; Sphero-conic

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APA (6th Edition):

Tripathy, C. (2012). Novel Algorithms for Protein Structure Determination from Sparse NMR Data . (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/5596

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tripathy, Chittaranjan. “Novel Algorithms for Protein Structure Determination from Sparse NMR Data .” 2012. Thesis, Duke University. Accessed May 06, 2021. http://hdl.handle.net/10161/5596.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tripathy, Chittaranjan. “Novel Algorithms for Protein Structure Determination from Sparse NMR Data .” 2012. Web. 06 May 2021.

Vancouver:

Tripathy C. Novel Algorithms for Protein Structure Determination from Sparse NMR Data . [Internet] [Thesis]. Duke University; 2012. [cited 2021 May 06]. Available from: http://hdl.handle.net/10161/5596.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tripathy C. Novel Algorithms for Protein Structure Determination from Sparse NMR Data . [Thesis]. Duke University; 2012. Available from: http://hdl.handle.net/10161/5596

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


The Ohio State University

27. Liang, Jiongqian. Human-in-the-loop Machine Learning: Algorithms and Applications.

Degree: PhD, Computer Science and Engineering, 2018, The Ohio State University

 Machine learning is the process of learning meaningful patterns and extracting useful knowledge from data using computational and statistical techniques. While the overall goal is… (more)

Subjects/Keywords: Computer Science; machine learning; human-in-the-loop; human guidance; outlier detection; graph mining; graph embedding

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APA (6th Edition):

Liang, J. (2018). Human-in-the-loop Machine Learning: Algorithms and Applications. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1523988406039076

Chicago Manual of Style (16th Edition):

Liang, Jiongqian. “Human-in-the-loop Machine Learning: Algorithms and Applications.” 2018. Doctoral Dissertation, The Ohio State University. Accessed May 06, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1523988406039076.

MLA Handbook (7th Edition):

Liang, Jiongqian. “Human-in-the-loop Machine Learning: Algorithms and Applications.” 2018. Web. 06 May 2021.

Vancouver:

Liang J. Human-in-the-loop Machine Learning: Algorithms and Applications. [Internet] [Doctoral dissertation]. The Ohio State University; 2018. [cited 2021 May 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1523988406039076.

Council of Science Editors:

Liang J. Human-in-the-loop Machine Learning: Algorithms and Applications. [Doctoral Dissertation]. The Ohio State University; 2018. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1523988406039076

28. Shi, Hailong. Optimizing Memory Cost With Loop Transformations.

Degree: MS, Computer Science, 2011, Wright State University

  Embedded systems are usually constrained in terms of timing, power,and memory. Many embedded applications, especially in the multi-media and telecom domains, are inherently data… (more)

Subjects/Keywords: Computer Science; Memory Cost; Loop transformation

…program (a). 8 2.4 (a) A two-level loop. (b) The corresponding… …b) The code of the retimed MDFG. . . . . . . . . . . 10 2.6 An example loop… …16 3.2 An example loop… …17 3.3 Loop permutation is used to legalize loop fusion… …21 3.4 (a)An example loop’s Loop Dependence Graph. (b) Retiming the… 

Page 1 Page 2 Page 3 Page 4 Page 5

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APA (6th Edition):

Shi, H. (2011). Optimizing Memory Cost With Loop Transformations. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1316355360

Chicago Manual of Style (16th Edition):

Shi, Hailong. “Optimizing Memory Cost With Loop Transformations.” 2011. Masters Thesis, Wright State University. Accessed May 06, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=wright1316355360.

MLA Handbook (7th Edition):

Shi, Hailong. “Optimizing Memory Cost With Loop Transformations.” 2011. Web. 06 May 2021.

Vancouver:

Shi H. Optimizing Memory Cost With Loop Transformations. [Internet] [Masters thesis]. Wright State University; 2011. [cited 2021 May 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1316355360.

Council of Science Editors:

Shi H. Optimizing Memory Cost With Loop Transformations. [Masters Thesis]. Wright State University; 2011. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1316355360


University of Michigan

29. Jin, Zhongjun. Democratizing Self-Service Data Preparation through Example Guided Program Synthesis.

Degree: PhD, Computer Science & Engineering, 2020, University of Michigan

 The majority of real-world data we can access today have one thing in common: they are not immediately usable in their original state. Trapped in… (more)

Subjects/Keywords: data preparation; program synthesis; human-in-the-loop; programming by example; data transformation; data wrangling; Computer Science; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jin, Z. (2020). Democratizing Self-Service Data Preparation through Example Guided Program Synthesis. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/163059

Chicago Manual of Style (16th Edition):

Jin, Zhongjun. “Democratizing Self-Service Data Preparation through Example Guided Program Synthesis.” 2020. Doctoral Dissertation, University of Michigan. Accessed May 06, 2021. http://hdl.handle.net/2027.42/163059.

MLA Handbook (7th Edition):

Jin, Zhongjun. “Democratizing Self-Service Data Preparation through Example Guided Program Synthesis.” 2020. Web. 06 May 2021.

Vancouver:

Jin Z. Democratizing Self-Service Data Preparation through Example Guided Program Synthesis. [Internet] [Doctoral dissertation]. University of Michigan; 2020. [cited 2021 May 06]. Available from: http://hdl.handle.net/2027.42/163059.

Council of Science Editors:

Jin Z. Democratizing Self-Service Data Preparation through Example Guided Program Synthesis. [Doctoral Dissertation]. University of Michigan; 2020. Available from: http://hdl.handle.net/2027.42/163059


Purdue University

30. Liu, Chenyang. Improving programmability and performance for scientific applications.

Degree: PhD, Electrical and Computer Engineering, 2016, Purdue University

  With modern advancements in hardware and software technology scaling towards new limits, our compute machines are reaching new potentials to tackle more challenging problems.… (more)

Subjects/Keywords: Applied sciences; Algorithm design; Concurrent collections; Parallel programming; Task parallelism; Tiling; Computer Engineering

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APA (6th Edition):

Liu, C. (2016). Improving programmability and performance for scientific applications. (Doctoral Dissertation). Purdue University. Retrieved from https://docs.lib.purdue.edu/open_access_dissertations/967

Chicago Manual of Style (16th Edition):

Liu, Chenyang. “Improving programmability and performance for scientific applications.” 2016. Doctoral Dissertation, Purdue University. Accessed May 06, 2021. https://docs.lib.purdue.edu/open_access_dissertations/967.

MLA Handbook (7th Edition):

Liu, Chenyang. “Improving programmability and performance for scientific applications.” 2016. Web. 06 May 2021.

Vancouver:

Liu C. Improving programmability and performance for scientific applications. [Internet] [Doctoral dissertation]. Purdue University; 2016. [cited 2021 May 06]. Available from: https://docs.lib.purdue.edu/open_access_dissertations/967.

Council of Science Editors:

Liu C. Improving programmability and performance for scientific applications. [Doctoral Dissertation]. Purdue University; 2016. Available from: https://docs.lib.purdue.edu/open_access_dissertations/967

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