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You searched for subject:(Logic synthesis). Showing records 1 – 30 of 105 total matches.

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1. Zhu, Qiang. Multi-level Logic Simplification Using Local Don't Care Extraction Based on Stepwise Enhancement : 逐次拡大に基いた局所ドントケア抽出法を用いた多段論理回路の簡単化; チクジ カクダイ ニ モトヅイタ キョクショ ドントケア チュウシュツホウ オ モチイタ タダン ロンリ カイロ ノ カンタンカ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: Logic Synthesis

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APA (6th Edition):

Zhu, Q. (n.d.). Multi-level Logic Simplification Using Local Don't Care Extraction Based on Stepwise Enhancement : 逐次拡大に基いた局所ドントケア抽出法を用いた多段論理回路の簡単化; チクジ カクダイ ニ モトヅイタ キョクショ ドントケア チュウシュツホウ オ モチイタ タダン ロンリ カイロ ノ カンタンカ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/1352

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhu, Qiang. “Multi-level Logic Simplification Using Local Don't Care Extraction Based on Stepwise Enhancement : 逐次拡大に基いた局所ドントケア抽出法を用いた多段論理回路の簡単化; チクジ カクダイ ニ モトヅイタ キョクショ ドントケア チュウシュツホウ オ モチイタ タダン ロンリ カイロ ノ カンタンカ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed March 06, 2021. http://hdl.handle.net/10061/1352.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhu, Qiang. “Multi-level Logic Simplification Using Local Don't Care Extraction Based on Stepwise Enhancement : 逐次拡大に基いた局所ドントケア抽出法を用いた多段論理回路の簡単化; チクジ カクダイ ニ モトヅイタ キョクショ ドントケア チュウシュツホウ オ モチイタ タダン ロンリ カイロ ノ カンタンカ.” Web. 06 Mar 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Zhu Q. Multi-level Logic Simplification Using Local Don't Care Extraction Based on Stepwise Enhancement : 逐次拡大に基いた局所ドントケア抽出法を用いた多段論理回路の簡単化; チクジ カクダイ ニ モトヅイタ キョクショ ドントケア チュウシュツホウ オ モチイタ タダン ロンリ カイロ ノ カンタンカ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10061/1352.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Zhu Q. Multi-level Logic Simplification Using Local Don't Care Extraction Based on Stepwise Enhancement : 逐次拡大に基いた局所ドントケア抽出法を用いた多段論理回路の簡単化; チクジ カクダイ ニ モトヅイタ キョクショ ドントケア チュウシュツホウ オ モチイタ タダン ロンリ カイロ ノ カンタンカ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/1352

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


University College Cork

2. Grandhi, Satish Kumar. Reliable chip design from low powered unreliable components.

Degree: 2019, University College Cork

 The pace of technological improvement of the semiconductor market is driven by Moore’s Law, enabling chip transistor density to double every two years. The transistors… (more)

Subjects/Keywords: LDPC; AIG; Logic synthesis; Reliability

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Grandhi, S. K. (2019). Reliable chip design from low powered unreliable components. (Thesis). University College Cork. Retrieved from http://hdl.handle.net/10468/8610

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Grandhi, Satish Kumar. “Reliable chip design from low powered unreliable components.” 2019. Thesis, University College Cork. Accessed March 06, 2021. http://hdl.handle.net/10468/8610.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Grandhi, Satish Kumar. “Reliable chip design from low powered unreliable components.” 2019. Web. 06 Mar 2021.

Vancouver:

Grandhi SK. Reliable chip design from low powered unreliable components. [Internet] [Thesis]. University College Cork; 2019. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10468/8610.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Grandhi SK. Reliable chip design from low powered unreliable components. [Thesis]. University College Cork; 2019. Available from: http://hdl.handle.net/10468/8610

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rice University

3. Rahbar, Afsaneh. Learning Program Invariants from Proof Corpora.

Degree: MS, Engineering, 2018, Rice University

 In program verification, loop invariants are of particular interest. Indeed, writing a correct and useful invariant is as challenging as verifying the program itself. Current… (more)

Subjects/Keywords: Invariants; Proof Synthesis; Program verification; Hoare logic

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APA (6th Edition):

Rahbar, A. (2018). Learning Program Invariants from Proof Corpora. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/105626

Chicago Manual of Style (16th Edition):

Rahbar, Afsaneh. “Learning Program Invariants from Proof Corpora.” 2018. Masters Thesis, Rice University. Accessed March 06, 2021. http://hdl.handle.net/1911/105626.

MLA Handbook (7th Edition):

Rahbar, Afsaneh. “Learning Program Invariants from Proof Corpora.” 2018. Web. 06 Mar 2021.

Vancouver:

Rahbar A. Learning Program Invariants from Proof Corpora. [Internet] [Masters thesis]. Rice University; 2018. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1911/105626.

Council of Science Editors:

Rahbar A. Learning Program Invariants from Proof Corpora. [Masters Thesis]. Rice University; 2018. Available from: http://hdl.handle.net/1911/105626


Vanderbilt University

4. Limbrick, Daniel Brian. Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

 Radiation-induced soft errors are becoming a dominant reliability-failure mechanism in modern CMOS technologies. In nanometer technologies, the effects are not limited to the storage elements… (more)

Subjects/Keywords: reliability-aware synthesis; single event transient; pulse width; combinational logic; soft error; logic synthesis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Limbrick, D. B. (2012). Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14920

Chicago Manual of Style (16th Edition):

Limbrick, Daniel Brian. “Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed March 06, 2021. http://hdl.handle.net/1803/14920.

MLA Handbook (7th Edition):

Limbrick, Daniel Brian. “Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits.” 2012. Web. 06 Mar 2021.

Vancouver:

Limbrick DB. Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1803/14920.

Council of Science Editors:

Limbrick DB. Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/14920


Universidade do Rio Grande do Sul

5. Neutzling, Augusto. Thereshold logic technology mapping for emerging nanotechnologies.

Degree: 2017, Universidade do Rio Grande do Sul

Threshold logic is a powerful alternative paradigm for realizing Boolean functions in digital circuit design. A threshold logic function (TLF) can be roughly defined as… (more)

Subjects/Keywords: Logic synthesis; Microeletrônica; Circuitos digitais; Digital circuit; Technology mapping; Threshold logic; Majority logic; Nanotechnologies

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Neutzling, A. (2017). Thereshold logic technology mapping for emerging nanotechnologies. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/180356

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Neutzling, Augusto. “Thereshold logic technology mapping for emerging nanotechnologies.” 2017. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021. http://hdl.handle.net/10183/180356.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Neutzling, Augusto. “Thereshold logic technology mapping for emerging nanotechnologies.” 2017. Web. 06 Mar 2021.

Vancouver:

Neutzling A. Thereshold logic technology mapping for emerging nanotechnologies. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2017. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10183/180356.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Neutzling A. Thereshold logic technology mapping for emerging nanotechnologies. [Thesis]. Universidade do Rio Grande do Sul; 2017. Available from: http://hdl.handle.net/10183/180356

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

6. Silva, Augusto Neutzling. Syhthesis of thereshold logic based circuits.

Degree: 2014, Universidade do Rio Grande do Sul

In this work, a novel method to synthesize digital integrated circuits (ICs) based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite… (more)

Subjects/Keywords: Digital circuits; Microeletrônica; Logic synthesis; Circuitos digitais; Threshold logic; Emerging technologies

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APA (6th Edition):

Silva, A. N. (2014). Syhthesis of thereshold logic based circuits. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/119435

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Silva, Augusto Neutzling. “Syhthesis of thereshold logic based circuits.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021. http://hdl.handle.net/10183/119435.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Silva, Augusto Neutzling. “Syhthesis of thereshold logic based circuits.” 2014. Web. 06 Mar 2021.

Vancouver:

Silva AN. Syhthesis of thereshold logic based circuits. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10183/119435.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Silva AN. Syhthesis of thereshold logic based circuits. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/119435

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

7. Li, Peng. Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing.

Degree: PhD, Electrical Engineering, 2013, University of Minnesota

 Most digital systems operate on a positional representation of data, such as binary encoding. An alternative is to operate on random bit streams where the… (more)

Subjects/Keywords: Fault-tolerance; Logic synthesis; Sequential logic; Stochastic computing

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APA (6th Edition):

Li, P. (2013). Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/155955

Chicago Manual of Style (16th Edition):

Li, Peng. “Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing.” 2013. Doctoral Dissertation, University of Minnesota. Accessed March 06, 2021. http://purl.umn.edu/155955.

MLA Handbook (7th Edition):

Li, Peng. “Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing.” 2013. Web. 06 Mar 2021.

Vancouver:

Li P. Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing. [Internet] [Doctoral dissertation]. University of Minnesota; 2013. [cited 2021 Mar 06]. Available from: http://purl.umn.edu/155955.

Council of Science Editors:

Li P. Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing. [Doctoral Dissertation]. University of Minnesota; 2013. Available from: http://purl.umn.edu/155955


Lehigh University

8. Reuther, Dana. Four-bar Three-position Mechanism Synthesis Using the Principles of Fuzzy Logic Mathematics.

Degree: MS, Mechanical Engineering, 2014, Lehigh University

 The human mind is very imprecise and uncertain most of the time. We are allowed to think as we wish, as things really are. This,… (more)

Subjects/Keywords: Fuzzy Logic; Linkage Synthesis; Mechanism Synthesis; Uncertainty; Engineering; Mechanical Engineering

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APA (6th Edition):

Reuther, D. (2014). Four-bar Three-position Mechanism Synthesis Using the Principles of Fuzzy Logic Mathematics. (Thesis). Lehigh University. Retrieved from https://preserve.lehigh.edu/etd/1604

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Reuther, Dana. “Four-bar Three-position Mechanism Synthesis Using the Principles of Fuzzy Logic Mathematics.” 2014. Thesis, Lehigh University. Accessed March 06, 2021. https://preserve.lehigh.edu/etd/1604.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Reuther, Dana. “Four-bar Three-position Mechanism Synthesis Using the Principles of Fuzzy Logic Mathematics.” 2014. Web. 06 Mar 2021.

Vancouver:

Reuther D. Four-bar Three-position Mechanism Synthesis Using the Principles of Fuzzy Logic Mathematics. [Internet] [Thesis]. Lehigh University; 2014. [cited 2021 Mar 06]. Available from: https://preserve.lehigh.edu/etd/1604.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Reuther D. Four-bar Three-position Mechanism Synthesis Using the Principles of Fuzzy Logic Mathematics. [Thesis]. Lehigh University; 2014. Available from: https://preserve.lehigh.edu/etd/1604

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Mohammadgholi Songhori, Ebrahim. TinyGarble: Efficient, Scalable, and Versatile Privacy-Preserving Computation Through Sequential Garbled Circuit.

Degree: PhD, Engineering, 2017, Rice University

 Privacy-preserving computation is a standing challenge central to several modern-world applications which require computing on sensitive data. Secure Function Evaluation (SFE) refers to provably secure… (more)

Subjects/Keywords: Privacy-Preserving Computation; Logic Synthesis; Garbled Circuit; Secure Function Evaluation; Logic Design

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7

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APA (6th Edition):

Mohammadgholi Songhori, E. (2017). TinyGarble: Efficient, Scalable, and Versatile Privacy-Preserving Computation Through Sequential Garbled Circuit. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/96146

Chicago Manual of Style (16th Edition):

Mohammadgholi Songhori, Ebrahim. “TinyGarble: Efficient, Scalable, and Versatile Privacy-Preserving Computation Through Sequential Garbled Circuit.” 2017. Doctoral Dissertation, Rice University. Accessed March 06, 2021. http://hdl.handle.net/1911/96146.

MLA Handbook (7th Edition):

Mohammadgholi Songhori, Ebrahim. “TinyGarble: Efficient, Scalable, and Versatile Privacy-Preserving Computation Through Sequential Garbled Circuit.” 2017. Web. 06 Mar 2021.

Vancouver:

Mohammadgholi Songhori E. TinyGarble: Efficient, Scalable, and Versatile Privacy-Preserving Computation Through Sequential Garbled Circuit. [Internet] [Doctoral dissertation]. Rice University; 2017. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1911/96146.

Council of Science Editors:

Mohammadgholi Songhori E. TinyGarble: Efficient, Scalable, and Versatile Privacy-Preserving Computation Through Sequential Garbled Circuit. [Doctoral Dissertation]. Rice University; 2017. Available from: http://hdl.handle.net/1911/96146


Portland State University

10. Chaudhari, Gunavant Dinkar. Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2011, Portland State University

  Most part of my thesis is devoted to efficient automated logic synthesis of oracle processors. These Oracle Processors are of interest to several modern… (more)

Subjects/Keywords: Oracle processors; Automated logic synthesis; Processing speed; Multiprocessors; Parallel processing (Electronic computers); Logic circuits

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APA (6th Edition):

Chaudhari, G. D. (2011). Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/11

Chicago Manual of Style (16th Edition):

Chaudhari, Gunavant Dinkar. “Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles.” 2011. Masters Thesis, Portland State University. Accessed March 06, 2021. https://pdxscholar.library.pdx.edu/open_access_etds/11.

MLA Handbook (7th Edition):

Chaudhari, Gunavant Dinkar. “Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles.” 2011. Web. 06 Mar 2021.

Vancouver:

Chaudhari GD. Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles. [Internet] [Masters thesis]. Portland State University; 2011. [cited 2021 Mar 06]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/11.

Council of Science Editors:

Chaudhari GD. Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles. [Masters Thesis]. Portland State University; 2011. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/11


University of Minnesota

11. Qian, Weikang. Digital yet deliberately random: synthesizing logical computation on stochastic bit streams.

Degree: PhD, Electrical engineering, 2011, University of Minnesota

 Most digital circuits process information that is encoded as zeros and ones deterministically. For example, the arithmetic unit of a modern computer performs calculations on… (more)

Subjects/Keywords: Cube; Logic Synthesis; Minterm; Probabilistic Logic; Stochastic Bit Streams; Stochastic Computation; Electrical Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Qian, W. (2011). Digital yet deliberately random: synthesizing logical computation on stochastic bit streams. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/113525

Chicago Manual of Style (16th Edition):

Qian, Weikang. “Digital yet deliberately random: synthesizing logical computation on stochastic bit streams.” 2011. Doctoral Dissertation, University of Minnesota. Accessed March 06, 2021. http://purl.umn.edu/113525.

MLA Handbook (7th Edition):

Qian, Weikang. “Digital yet deliberately random: synthesizing logical computation on stochastic bit streams.” 2011. Web. 06 Mar 2021.

Vancouver:

Qian W. Digital yet deliberately random: synthesizing logical computation on stochastic bit streams. [Internet] [Doctoral dissertation]. University of Minnesota; 2011. [cited 2021 Mar 06]. Available from: http://purl.umn.edu/113525.

Council of Science Editors:

Qian W. Digital yet deliberately random: synthesizing logical computation on stochastic bit streams. [Doctoral Dissertation]. University of Minnesota; 2011. Available from: http://purl.umn.edu/113525


Universidade do Rio Grande do Sul

12. Martins, Mayler Gama Alvarenga. Applications of functional composition for CMOS and emerging technologies.

Degree: 2015, Universidade do Rio Grande do Sul

The advances in semiconductor industry over the last decades have been strongly based on continuous scaling down of dimensions in manufactured CMOS devices. The use… (more)

Subjects/Keywords: Microeletrônica; Functional composition; Cmos; Logic synthesis; Emerging technologies; Circuit resynthesis; Approximate circuits; Threshold logic; Majority logic; Spin-diodes; Memristors

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APA (6th Edition):

Martins, M. G. A. (2015). Applications of functional composition for CMOS and emerging technologies. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/164452

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Martins, Mayler Gama Alvarenga. “Applications of functional composition for CMOS and emerging technologies.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021. http://hdl.handle.net/10183/164452.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Martins, Mayler Gama Alvarenga. “Applications of functional composition for CMOS and emerging technologies.” 2015. Web. 06 Mar 2021.

Vancouver:

Martins MGA. Applications of functional composition for CMOS and emerging technologies. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10183/164452.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Martins MGA. Applications of functional composition for CMOS and emerging technologies. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/164452

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Portland State University

13. Singhal, Rahul. Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA).

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2011, Portland State University

  Semiconductor industry seems to approach a wall where physical geometry and power density issues could possibly render the device fabrication infeasible. Quantum-dot Cellular Automata… (more)

Subjects/Keywords: Logic synthesis; QCA clocking; QCA layout; Regular structures; Cellular automata; Quantum dots; Logic circuits  – Computer-aided design; Logic design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Singhal, R. (2011). Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA). (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/196

Chicago Manual of Style (16th Edition):

Singhal, Rahul. “Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA).” 2011. Masters Thesis, Portland State University. Accessed March 06, 2021. https://pdxscholar.library.pdx.edu/open_access_etds/196.

MLA Handbook (7th Edition):

Singhal, Rahul. “Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA).” 2011. Web. 06 Mar 2021.

Vancouver:

Singhal R. Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA). [Internet] [Masters thesis]. Portland State University; 2011. [cited 2021 Mar 06]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/196.

Council of Science Editors:

Singhal R. Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA). [Masters Thesis]. Portland State University; 2011. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/196


Cornell University

14. Liu, Gai. Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors.

Degree: PhD, Electrical and Computer Engineering, 2018, Cornell University

 Technology scaling, architectural innovations, and electronic design automation (EDA) are the three pillars supporting the exponential growth in computer hardware performance for the past six… (more)

Subjects/Keywords: Architectural Synthesis; Cross-Stage Optimization; Electronic Design Automation; Logic Synthesis; Computer engineering; Engineering

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APA (6th Edition):

Liu, G. (2018). Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/64855

Chicago Manual of Style (16th Edition):

Liu, Gai. “Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors.” 2018. Doctoral Dissertation, Cornell University. Accessed March 06, 2021. http://hdl.handle.net/1813/64855.

MLA Handbook (7th Edition):

Liu, Gai. “Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors.” 2018. Web. 06 Mar 2021.

Vancouver:

Liu G. Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors. [Internet] [Doctoral dissertation]. Cornell University; 2018. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1813/64855.

Council of Science Editors:

Liu G. Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors. [Doctoral Dissertation]. Cornell University; 2018. Available from: http://hdl.handle.net/1813/64855


UCLA

15. Feng, Zhe. Logic Synthesis for FPGA Reliability.

Degree: Electrical Engineering, 2013, UCLA

Logic synthesis is one of the key stages in the computer-aided design (CAD) flow for a field programmable gate array (FPGA) based design. It usually… (more)

Subjects/Keywords: Electrical engineering; FPGA; Logic synthesis; Reliability; Soft error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Feng, Z. (2013). Logic Synthesis for FPGA Reliability. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/7w7602f5

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Feng, Zhe. “Logic Synthesis for FPGA Reliability.” 2013. Thesis, UCLA. Accessed March 06, 2021. http://www.escholarship.org/uc/item/7w7602f5.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Feng, Zhe. “Logic Synthesis for FPGA Reliability.” 2013. Web. 06 Mar 2021.

Vancouver:

Feng Z. Logic Synthesis for FPGA Reliability. [Internet] [Thesis]. UCLA; 2013. [cited 2021 Mar 06]. Available from: http://www.escholarship.org/uc/item/7w7602f5.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Feng Z. Logic Synthesis for FPGA Reliability. [Thesis]. UCLA; 2013. Available from: http://www.escholarship.org/uc/item/7w7602f5

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

16. Lin, Pey Chang K. Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks.

Degree: PhD, Electrical Engineering, 2013, Texas A&M University

 In the quest to understand cell behavior and cure genetic diseases such as cancer, the fundamental approach being taken is undergoing a gradual change. It… (more)

Subjects/Keywords: Genomics; Logic Synthesis; Boolean Satisfiability; Gene Regulatory Networks

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APA (6th Edition):

Lin, P. C. K. (2013). Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/151088

Chicago Manual of Style (16th Edition):

Lin, Pey Chang K. “Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks.” 2013. Doctoral Dissertation, Texas A&M University. Accessed March 06, 2021. http://hdl.handle.net/1969.1/151088.

MLA Handbook (7th Edition):

Lin, Pey Chang K. “Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks.” 2013. Web. 06 Mar 2021.

Vancouver:

Lin PCK. Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks. [Internet] [Doctoral dissertation]. Texas A&M University; 2013. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1969.1/151088.

Council of Science Editors:

Lin PCK. Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks. [Doctoral Dissertation]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/151088

17. Düdder, Boris. Automatic synthesis of component & connector software architectures with bounded combinatory logic.

Degree: 2014, Technische Universität Dortmund

 Combinatory logic synthesis is a new type-based approach towards automatic synthesis of software from components in a repository. In this thesis we show how the… (more)

Subjects/Keywords: Logic; Software; Engineering; Architecture; Concurrency; Theorem prover; Synthesis; 004

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APA (6th Edition):

Düdder, B. (2014). Automatic synthesis of component & connector software architectures with bounded combinatory logic. (Doctoral Dissertation). Technische Universität Dortmund. Retrieved from http://dx.doi.org/10.17877/DE290R-6528

Chicago Manual of Style (16th Edition):

Düdder, Boris. “Automatic synthesis of component & connector software architectures with bounded combinatory logic.” 2014. Doctoral Dissertation, Technische Universität Dortmund. Accessed March 06, 2021. http://dx.doi.org/10.17877/DE290R-6528.

MLA Handbook (7th Edition):

Düdder, Boris. “Automatic synthesis of component & connector software architectures with bounded combinatory logic.” 2014. Web. 06 Mar 2021.

Vancouver:

Düdder B. Automatic synthesis of component & connector software architectures with bounded combinatory logic. [Internet] [Doctoral dissertation]. Technische Universität Dortmund; 2014. [cited 2021 Mar 06]. Available from: http://dx.doi.org/10.17877/DE290R-6528.

Council of Science Editors:

Düdder B. Automatic synthesis of component & connector software architectures with bounded combinatory logic. [Doctoral Dissertation]. Technische Universität Dortmund; 2014. Available from: http://dx.doi.org/10.17877/DE290R-6528


University of Newcastle

18. Fenn, Shannon Kayde. Target curricula for multi-target classification: the role of internal meta-features in machine teaching.

Degree: PhD, 2020, University of Newcastle

Research Doctorate - Doctor of Philosophy (PhD)

In machine learning, methods inspired by human teaching practices such as the use of curricula, have been fruitful.… (more)

Subjects/Keywords: target curriculum; logic synthesis; Boolean networks; intrinsic dimension; supervised learning

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APA (6th Edition):

Fenn, S. K. (2020). Target curricula for multi-target classification: the role of internal meta-features in machine teaching. (Doctoral Dissertation). University of Newcastle. Retrieved from http://hdl.handle.net/1959.13/1411958

Chicago Manual of Style (16th Edition):

Fenn, Shannon Kayde. “Target curricula for multi-target classification: the role of internal meta-features in machine teaching.” 2020. Doctoral Dissertation, University of Newcastle. Accessed March 06, 2021. http://hdl.handle.net/1959.13/1411958.

MLA Handbook (7th Edition):

Fenn, Shannon Kayde. “Target curricula for multi-target classification: the role of internal meta-features in machine teaching.” 2020. Web. 06 Mar 2021.

Vancouver:

Fenn SK. Target curricula for multi-target classification: the role of internal meta-features in machine teaching. [Internet] [Doctoral dissertation]. University of Newcastle; 2020. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1959.13/1411958.

Council of Science Editors:

Fenn SK. Target curricula for multi-target classification: the role of internal meta-features in machine teaching. [Doctoral Dissertation]. University of Newcastle; 2020. Available from: http://hdl.handle.net/1959.13/1411958


University of Southern California

19. Shin, Doochul. Techniques for design and synthesis of approximate digital circuits for error-tolerant applications.

Degree: PhD, Computer Engineering, 2011, University of Southern California

 As VLSI technology node scales to nano-scale, dramatic improvements in most attributes of circuits, especially delay and yield, provided by scaling are beginning to decrease.… (more)

Subjects/Keywords: circuit design; error tolerance; logic synthesis; yield improvement

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shin, D. (2011). Techniques for design and synthesis of approximate digital circuits for error-tolerant applications. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6372

Chicago Manual of Style (16th Edition):

Shin, Doochul. “Techniques for design and synthesis of approximate digital circuits for error-tolerant applications.” 2011. Doctoral Dissertation, University of Southern California. Accessed March 06, 2021. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6372.

MLA Handbook (7th Edition):

Shin, Doochul. “Techniques for design and synthesis of approximate digital circuits for error-tolerant applications.” 2011. Web. 06 Mar 2021.

Vancouver:

Shin D. Techniques for design and synthesis of approximate digital circuits for error-tolerant applications. [Internet] [Doctoral dissertation]. University of Southern California; 2011. [cited 2021 Mar 06]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6372.

Council of Science Editors:

Shin D. Techniques for design and synthesis of approximate digital circuits for error-tolerant applications. [Doctoral Dissertation]. University of Southern California; 2011. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6372


Lehigh University

20. ALHINDI, AHMED. Three-position Dimensional Synthesis of Four-Bar Mechanism for Function Generation Using Fuzzy Logic Mathematics.

Degree: MS, Mechanical Engineering, 2019, Lehigh University

  Dimensional synthesis of the four-bar mechanism could not be determined precisely due to many constraints such as manufacturing tolerance, joint clearance, thermal deformation, the… (more)

Subjects/Keywords: Dimensional Synthesis; Four-Bar Mechanism; Function Generation; Fuzzy Logic; Mechanical Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

ALHINDI, A. (2019). Three-position Dimensional Synthesis of Four-Bar Mechanism for Function Generation Using Fuzzy Logic Mathematics. (Thesis). Lehigh University. Retrieved from https://preserve.lehigh.edu/etd/5628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

ALHINDI, AHMED. “Three-position Dimensional Synthesis of Four-Bar Mechanism for Function Generation Using Fuzzy Logic Mathematics.” 2019. Thesis, Lehigh University. Accessed March 06, 2021. https://preserve.lehigh.edu/etd/5628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

ALHINDI, AHMED. “Three-position Dimensional Synthesis of Four-Bar Mechanism for Function Generation Using Fuzzy Logic Mathematics.” 2019. Web. 06 Mar 2021.

Vancouver:

ALHINDI A. Three-position Dimensional Synthesis of Four-Bar Mechanism for Function Generation Using Fuzzy Logic Mathematics. [Internet] [Thesis]. Lehigh University; 2019. [cited 2021 Mar 06]. Available from: https://preserve.lehigh.edu/etd/5628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

ALHINDI A. Three-position Dimensional Synthesis of Four-Bar Mechanism for Function Generation Using Fuzzy Logic Mathematics. [Thesis]. Lehigh University; 2019. Available from: https://preserve.lehigh.edu/etd/5628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

21. Elbayoumi, Mahmoud Atef Mahmoud Sayed. Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 According to Moore's law, Integrated Chips (IC) doubles its capacity every 18 months. This causes an exponential increase of the available area, and hence,the complexity… (more)

Subjects/Keywords: Verification; logic synthesis; SAT; BDDs; Low power; timing aware

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Elbayoumi, M. A. M. S. (2015). Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51221

Chicago Manual of Style (16th Edition):

Elbayoumi, Mahmoud Atef Mahmoud Sayed. “Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms.” 2015. Doctoral Dissertation, Virginia Tech. Accessed March 06, 2021. http://hdl.handle.net/10919/51221.

MLA Handbook (7th Edition):

Elbayoumi, Mahmoud Atef Mahmoud Sayed. “Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms.” 2015. Web. 06 Mar 2021.

Vancouver:

Elbayoumi MAMS. Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10919/51221.

Council of Science Editors:

Elbayoumi MAMS. Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51221


IUPUI

22. Yadav, Avinash. Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness.

Degree: 2020, IUPUI

Indiana University-Purdue University Indianapolis (IUPUI)

In this thesis, we investigated the 7 nm FinFET technology for its delay-power product performance. In our study, we explored… (more)

Subjects/Keywords: FinFET; ALU; 6T SRAM; Robustness; Logic Synthesis; Physical Design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yadav, A. (2020). Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness. (Thesis). IUPUI. Retrieved from http://hdl.handle.net/1805/24772

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yadav, Avinash. “Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness.” 2020. Thesis, IUPUI. Accessed March 06, 2021. http://hdl.handle.net/1805/24772.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yadav, Avinash. “Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness.” 2020. Web. 06 Mar 2021.

Vancouver:

Yadav A. Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness. [Internet] [Thesis]. IUPUI; 2020. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1805/24772.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yadav A. Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness. [Thesis]. IUPUI; 2020. Available from: http://hdl.handle.net/1805/24772

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

23. Martinello Junior, Osvaldo. KL-cuts : a new approach for logic synthesis targeting multiple output blocks.

Degree: 2010, Universidade do Rio Grande do Sul

Esta dissertação introduz o conceito de cortes KL, o que permite controlar tanto o número K de entradas como o número L de saídas em… (more)

Subjects/Keywords: AIG; Microeletrônica; Cut enumeration; 3D; KL-cuts; Testes : Circuitos integrados; Circuitos integrados; Logic design; Logic synthesis; Multiple output blocks; Technology mapping

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Martinello Junior, O. (2010). KL-cuts : a new approach for logic synthesis targeting multiple output blocks. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/26503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Martinello Junior, Osvaldo. “KL-cuts : a new approach for logic synthesis targeting multiple output blocks.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021. http://hdl.handle.net/10183/26503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Martinello Junior, Osvaldo. “KL-cuts : a new approach for logic synthesis targeting multiple output blocks.” 2010. Web. 06 Mar 2021.

Vancouver:

Martinello Junior O. KL-cuts : a new approach for logic synthesis targeting multiple output blocks. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10183/26503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Martinello Junior O. KL-cuts : a new approach for logic synthesis targeting multiple output blocks. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/26503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

24. Figueiró, Thiago Rosa. Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition.

Degree: 2010, Universidade do Rio Grande do Sul

O emprego de ferramentas de automação de projetos de circuitos integrados permitiu que projetos complexos atingissem time-to-market e custos de produção factíveis. Neste contexto, o… (more)

Subjects/Keywords: Logic synthesis; Microeletrônica; And-inverter graph; Processamento : Imagem; Design automation; CAD; Digital circuits; Logic gates; Design flow; Technology mapping

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APA (6th Edition):

Figueiró, T. R. (2010). Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/27663

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Figueiró, Thiago Rosa. “Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021. http://hdl.handle.net/10183/27663.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Figueiró, Thiago Rosa. “Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition.” 2010. Web. 06 Mar 2021.

Vancouver:

Figueiró TR. Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10183/27663.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Figueiró TR. Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/27663

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

25. Schneider, Felipe Ribeiro. Building transistor-level networks following the lower bound on the number of stacked switches.

Degree: 2007, Universidade do Rio Grande do Sul

Em portas lógicas CMOS, tanto o atraso de propagação como a curva de saída estão fortemente ligados ao número de dispositivos PMOS e NMOS conectados… (more)

Subjects/Keywords: Microeletrônica; Logic style; Redes : Computadores; Logic synthesis; Cell libraries

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APA (6th Edition):

Schneider, F. R. (2007). Building transistor-level networks following the lower bound on the number of stacked switches. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/55446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Schneider, Felipe Ribeiro. “Building transistor-level networks following the lower bound on the number of stacked switches.” 2007. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021. http://hdl.handle.net/10183/55446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Schneider, Felipe Ribeiro. “Building transistor-level networks following the lower bound on the number of stacked switches.” 2007. Web. 06 Mar 2021.

Vancouver:

Schneider FR. Building transistor-level networks following the lower bound on the number of stacked switches. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2007. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10183/55446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Schneider FR. Building transistor-level networks following the lower bound on the number of stacked switches. [Thesis]. Universidade do Rio Grande do Sul; 2007. Available from: http://hdl.handle.net/10183/55446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

26. Matos, Jody Maick Araujo de. Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools.

Degree: 2014, Universidade do Rio Grande do Sul

This master’s thesis introduces a set of graph-based algorithms for obtaining reduced transistor count VLSI circuits using simple cells. These algorithms are mainly focused on… (more)

Subjects/Keywords: Microeletrônica; Benchmark circuits; Transistor count; Algoritmos; Vlsi : Circuitos integrados : Eletronica; Logic synthesis; Technology mapping

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Matos, J. M. A. d. (2014). Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/147759

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Matos, Jody Maick Araujo de. “Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021. http://hdl.handle.net/10183/147759.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Matos, Jody Maick Araujo de. “Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools.” 2014. Web. 06 Mar 2021.

Vancouver:

Matos JMAd. Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10183/147759.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Matos JMAd. Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/147759

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

27. Callegaro, Vinicius. Minimização ótima de classes especiais de funções booleanas.

Degree: 2016, Universidade do Rio Grande do Sul

The problem of factoring and decomposing Boolean functions is Σ-complete 2 for general functions. Efficient and exact algorithms can be created for an existing class… (more)

Subjects/Keywords: Logic synthesis; Microeletrônica; Funções booleanas; Factoring; Decomposition; Read-once; Disjoint-support decomposition; Read-polarity-once

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APA (6th Edition):

Callegaro, V. (2016). Minimização ótima de classes especiais de funções booleanas. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/148342

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Callegaro, Vinicius. “Minimização ótima de classes especiais de funções booleanas.” 2016. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021. http://hdl.handle.net/10183/148342.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Callegaro, Vinicius. “Minimização ótima de classes especiais de funções booleanas.” 2016. Web. 06 Mar 2021.

Vancouver:

Callegaro V. Minimização ótima de classes especiais de funções booleanas. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2016. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10183/148342.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Callegaro V. Minimização ótima de classes especiais de funções booleanas. [Thesis]. Universidade do Rio Grande do Sul; 2016. Available from: http://hdl.handle.net/10183/148342

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

28. Huang, Ching-Hua. Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In recent years, the popularity of handheld smart devices.In order to the demand of consumer and rapid progress of the technological process; Although the design… (more)

Subjects/Keywords: Chip Tape-out; Logic Synthesis; Syetem-on-Chip; Three-dimensional Graphics; Layout

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APA (6th Edition):

Huang, C. (2014). Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Ching-Hua. “Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC.” 2014. Thesis, NSYSU. Accessed March 06, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Ching-Hua. “Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC.” 2014. Web. 06 Mar 2021.

Vancouver:

Huang C. Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Mar 06]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang C. Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

29. Oh, Yoonna. Constructive logic and layout synthesis.

Degree: PhD, Computer science, 2006, University of Michigan

 This dissertation examines the extension of constructive library-aware logic synthesis to the physical placement stage of integrated circuit design. Constructive logic synthesis differs from traditional… (more)

Subjects/Keywords: Constructive Logic; Layout; Synthesis; Technology Mapping

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oh, Y. (2006). Constructive logic and layout synthesis. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/126529

Chicago Manual of Style (16th Edition):

Oh, Yoonna. “Constructive logic and layout synthesis.” 2006. Doctoral Dissertation, University of Michigan. Accessed March 06, 2021. http://hdl.handle.net/2027.42/126529.

MLA Handbook (7th Edition):

Oh, Yoonna. “Constructive logic and layout synthesis.” 2006. Web. 06 Mar 2021.

Vancouver:

Oh Y. Constructive logic and layout synthesis. [Internet] [Doctoral dissertation]. University of Michigan; 2006. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/2027.42/126529.

Council of Science Editors:

Oh Y. Constructive logic and layout synthesis. [Doctoral Dissertation]. University of Michigan; 2006. Available from: http://hdl.handle.net/2027.42/126529


University of Waterloo

30. Ravishankar, Chirag. Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs.

Degree: 2012, University of Waterloo

 Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times… (more)

Subjects/Keywords: Field-programmable gate arrays; Power optimization; low-power design; logic synthesis; technology mapping

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ravishankar, C. (2012). Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/6644

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ravishankar, Chirag. “Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs.” 2012. Thesis, University of Waterloo. Accessed March 06, 2021. http://hdl.handle.net/10012/6644.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ravishankar, Chirag. “Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs.” 2012. Web. 06 Mar 2021.

Vancouver:

Ravishankar C. Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs. [Internet] [Thesis]. University of Waterloo; 2012. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10012/6644.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ravishankar C. Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs. [Thesis]. University of Waterloo; 2012. Available from: http://hdl.handle.net/10012/6644

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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