You searched for subject:(Logic synthesis).
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1.
Zhu, Qiang.
Multi-level Logic Simplification Using Local Don't Care Extraction Based on Stepwise Enhancement : 逐次拡大に基いた局所ドントケア抽出法を用いた多段論理回路の簡単化; チクジ カクダイ ニ モトヅイタ キョクショ ドントケア チュウシュツホウ オ モチイタ タダン ロンリ カイロ ノ カンタンカ.
Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学
URL: http://hdl.handle.net/10061/1352 
Subjects/Keywords: Logic Synthesis
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APA (6th Edition):
Zhu, Q. (n.d.). Multi-level Logic Simplification Using Local Don't Care Extraction Based on Stepwise Enhancement : 逐次拡大に基いた局所ドントケア抽出法を用いた多段論理回路の簡単化; チクジ カクダイ ニ モトヅイタ キョクショ ドントケア チュウシュツホウ オ モチイタ タダン ロンリ カイロ ノ カンタンカ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/1352
Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Zhu, Qiang. “Multi-level Logic Simplification Using Local Don't Care Extraction Based on Stepwise Enhancement : 逐次拡大に基いた局所ドントケア抽出法を用いた多段論理回路の簡単化; チクジ カクダイ ニ モトヅイタ キョクショ ドントケア チュウシュツホウ オ モチイタ タダン ロンリ カイロ ノ カンタンカ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed March 06, 2021.
http://hdl.handle.net/10061/1352.
Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Zhu, Qiang. “Multi-level Logic Simplification Using Local Don't Care Extraction Based on Stepwise Enhancement : 逐次拡大に基いた局所ドントケア抽出法を用いた多段論理回路の簡単化; チクジ カクダイ ニ モトヅイタ キョクショ ドントケア チュウシュツホウ オ モチイタ タダン ロンリ カイロ ノ カンタンカ.” Web. 06 Mar 2021.
Note: this citation may be lacking information needed for this citation format:
No year of publication.
Vancouver:
Zhu Q. Multi-level Logic Simplification Using Local Don't Care Extraction Based on Stepwise Enhancement : 逐次拡大に基いた局所ドントケア抽出法を用いた多段論理回路の簡単化; チクジ カクダイ ニ モトヅイタ キョクショ ドントケア チュウシュツホウ オ モチイタ タダン ロンリ カイロ ノ カンタンカ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Mar 06].
Available from: http://hdl.handle.net/10061/1352.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.
Council of Science Editors:
Zhu Q. Multi-level Logic Simplification Using Local Don't Care Extraction Based on Stepwise Enhancement : 逐次拡大に基いた局所ドントケア抽出法を用いた多段論理回路の簡単化; チクジ カクダイ ニ モトヅイタ キョクショ ドントケア チュウシュツホウ オ モチイタ タダン ロンリ カイロ ノ カンタンカ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/1352
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.
University College Cork
2.
Grandhi, Satish Kumar.
Reliable chip design from low powered unreliable components.
Degree: 2019, University College Cork
URL: http://hdl.handle.net/10468/8610
► The pace of technological improvement of the semiconductor market is driven by Moore’s Law, enabling chip transistor density to double every two years. The transistors…
(more)
▼ The pace of technological improvement of the semiconductor market is driven by Moore’s Law, enabling chip transistor density to double every two years. The transistors would continue to decline in cost and size but increase in power. The continuous transistor scaling and extremely lower power constraints in modern Very Large Scale Integrated(VLSI) chips can potentially supersede the benefits of the technology shrinking due to reliability issues. As VLSI technology scales into nanoscale regime, fundamental physical limits are approached, and higher levels of variability, performance degradation, and higher rates of manufacturing defects are experienced. Soft errors, which traditionally affected only the memories, are now also resulting in
logic circuit reliability degradation. A solution to these limitations is to integrate reliability assessment techniques into the Integrated Circuit(IC) design flow. This thesis investigates four aspects of reliability driven circuit design: a)Reliability estimation; b) Reliability optimization; c) Fault-tolerant techniques, and d) Delay degradation analysis. To guide the reliability driven
synthesis and optimization of combinational circuits, highly accurate probability based reliability estimation methodology christened Conditional Probabilistic Error Propagation(CPEP) algorithm is developed to compute the impact of gate failures on the circuit output. CPEP guides the proposed rewriting based
logic optimization algorithm employing local transformations. The main idea behind this methodology is to replace parts of the circuit with functionally equivalent but more reliable counterparts chosen from a precomputed subset of Negation-Permutation-Negation(NPN) classes of 4-variable functions. Cut enumeration and Boolean matching driven by reliability-aware optimization algorithm are used to identify the best possible replacement candidates. Experiments on a set of MCNC benchmark circuits and 8051 functional microcontroller units indicate that the proposed framework can achieve up to 75% reduction of output error probability. On average, about 14% SER reduction is obtained at the expense of very low area overhead of 6.57% that results in 13.52% higher power consumption. The next contribution of the research describes a novel methodology to design fault tolerant circuitry by employing the error correction codes known as Codeword Prediction Encoder(CPE). Traditional fault tolerant techniques analyze the circuit reliability issue from a static point of view neglecting the dynamic errors. In the context of communication and storage, the study of novel methods for reliable data transmission under unreliable hardware is an increasing priority. The idea of CPE is adapted from the field of forward error correction for telecommunications focusing on both encoding aspects and error correction capabilities. The proposed Augmented Encoding solution consists of computing an augmented codeword that contains both the codeword to be transmitted on the channel and extra parity bits. A Computer Aided…
Advisors/Committee Members: Popovici, Emanuel.
Subjects/Keywords: LDPC; AIG; Logic synthesis; Reliability
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APA (6th Edition):
Grandhi, S. K. (2019). Reliable chip design from low powered unreliable components. (Thesis). University College Cork. Retrieved from http://hdl.handle.net/10468/8610
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Grandhi, Satish Kumar. “Reliable chip design from low powered unreliable components.” 2019. Thesis, University College Cork. Accessed March 06, 2021.
http://hdl.handle.net/10468/8610.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Grandhi, Satish Kumar. “Reliable chip design from low powered unreliable components.” 2019. Web. 06 Mar 2021.
Vancouver:
Grandhi SK. Reliable chip design from low powered unreliable components. [Internet] [Thesis]. University College Cork; 2019. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/10468/8610.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Grandhi SK. Reliable chip design from low powered unreliable components. [Thesis]. University College Cork; 2019. Available from: http://hdl.handle.net/10468/8610
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Rice University
3.
Rahbar, Afsaneh.
Learning Program Invariants from Proof Corpora.
Degree: MS, Engineering, 2018, Rice University
URL: http://hdl.handle.net/1911/105626
► In program verification, loop invariants are of particular interest. Indeed, writing a correct and useful invariant is as challenging as verifying the program itself. Current…
(more)
▼ In program verification, loop invariants are of particular interest. Indeed, writing
a correct and useful invariant is as challenging as verifying the program itself.
Current approaches to solving the problem of automatically generating invariants either
generate invariants by analyzing the program or using machine learning to learn
from program input and output examples, counterexamples, and so on. Each of these
approaches works on particular type of programs and specific data structures. In
this thesis, we describe the technique we have developed for generating these loop
invariants automatically. We introduce a more general learning technique that learns
from a database of annotated verified programs. Our new data-driven approach uses
the existing proofs to learn proof templates, or as we call them proof blocks. In
our method, the algorithm iterates over all possible proof block formulas by using
logical connectors until it finds an appropriate invariant formula. We evaluated our
approach on benchmarks and demonstrated the potential of our technique in verification
of programs. Using the approach of learning from verified annotated programs
makes invariant generation easier and reduces the burden on the verification engineer.
Advisors/Committee Members: Chaudhuri, Swarat (advisor).
Subjects/Keywords: Invariants; Proof Synthesis; Program verification; Hoare logic
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APA (6th Edition):
Rahbar, A. (2018). Learning Program Invariants from Proof Corpora. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/105626
Chicago Manual of Style (16th Edition):
Rahbar, Afsaneh. “Learning Program Invariants from Proof Corpora.” 2018. Masters Thesis, Rice University. Accessed March 06, 2021.
http://hdl.handle.net/1911/105626.
MLA Handbook (7th Edition):
Rahbar, Afsaneh. “Learning Program Invariants from Proof Corpora.” 2018. Web. 06 Mar 2021.
Vancouver:
Rahbar A. Learning Program Invariants from Proof Corpora. [Internet] [Masters thesis]. Rice University; 2018. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/1911/105626.
Council of Science Editors:
Rahbar A. Learning Program Invariants from Proof Corpora. [Masters Thesis]. Rice University; 2018. Available from: http://hdl.handle.net/1911/105626
Vanderbilt University
4.
Limbrick, Daniel Brian.
Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits.
Degree: PhD, Electrical Engineering, 2012, Vanderbilt University
URL: http://hdl.handle.net/1803/14920
► Radiation-induced soft errors are becoming a dominant reliability-failure mechanism in modern CMOS technologies. In nanometer technologies, the effects are not limited to the storage elements…
(more)
▼ Radiation-induced soft errors are becoming a dominant reliability-failure mechanism in modern CMOS technologies. In nanometer technologies, the effects are not limited to the storage elements of a digital system, but also include vulnerabilities in the combinational
logic. Reliability-aware
synthesis has emerged as a method to mitigate the effects of soft errors in combinational
logic. Few studies have focused on the inherent impact that
logic synthesis algorithms have on circuit topology, and therefore reliability. This dissertation investigates the impact that area and delay optimizations, computational effort, and standard cell availability have on the error propagation probability of individual circuit nodes. Additionally, this work identifies circuit characteristics that can be used during
synthesis that help in choosing the most reliable circuit implementation. Finally, an approach to minimize circuit vulnerability based on cell selection is introduced.
Advisors/Committee Members: Dr. Bharat Bhuva (committee member), Dr. Lloyd Massengill (committee member), Dr. Gabor Karsai (committee member), Dr. Mark Ellingham (committee member), Dr. William H. Robinson (Committee Chair).
Subjects/Keywords: reliability-aware synthesis; single event transient; pulse width; combinational logic; soft error; logic synthesis
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APA (6th Edition):
Limbrick, D. B. (2012). Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14920
Chicago Manual of Style (16th Edition):
Limbrick, Daniel Brian. “Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed March 06, 2021.
http://hdl.handle.net/1803/14920.
MLA Handbook (7th Edition):
Limbrick, Daniel Brian. “Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits.” 2012. Web. 06 Mar 2021.
Vancouver:
Limbrick DB. Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/1803/14920.
Council of Science Editors:
Limbrick DB. Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/14920
Universidade do Rio Grande do Sul
5.
Neutzling, Augusto.
Thereshold logic technology mapping for emerging nanotechnologies.
Degree: 2017, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/180356
► Threshold logic is a powerful alternative paradigm for realizing Boolean functions in digital circuit design. A threshold logic function (TLF) can be roughly defined as…
(more)
▼ Threshold logic is a powerful alternative paradigm for realizing Boolean functions in digital circuit design. A threshold logic function (TLF) can be roughly defined as a Boolean function in which the output is evaluated in terms of input weights and a threshold value. Although the subject has been investigated since the 1960’s, the lack of effective hardware implementation for threshold functions led to a loss of interest in developing a threshold logic design flow. However, for some emerging technologies, such as memristors, spintronic, quantum cellular automata (QCA) and resonant tunneling devices (RTD), such a logic design strategy seems to be more appropriate than the traditional switch-based CMOS circuitry. Thus, research and development of synthesis and verification methods applicable to large, multi-level threshold circuits are desired. Existing state-of-the-art threshold logic synthesis tools rely on locally resynthesizing each single-output node out of circuits initially mapped disregarding thresholdness. This work presents the first effective technology mapping approach for threshold logic gates (TLGs), which is based on identifying threshold logic functions during the mapping. This enables to explore the entire circuit-level search space, seeking a threshold logic covering. As a consequence, we improve both area and performance results, as well as the synthesis scalability. A second contribution introduced in this thesis improves the quality of results by efficiently exploring redundant cuts. The technology mapper, we propose herein, is also able to target different threshold-based area estimations: the total summation of input weights and threshold values; the total summation of gate inputs; and the total number of TLGs. Finally, we propose a TLF-based approach to perform logic synthesis for majority-gatebased emerging nanotechnologies.
Lógica de Limiar (Threshold Logic) é um promissor paradigma alternativo para implementar funções Booleanas is projetos de circuitos digitais. Uma função limiar pode ser definida como uma função Booleana onde a saída é avaliada em termos dos pesos das entradas e um valor de threshold. Embora esse assunto tenha sido investigado desde a década de 1960, a lacuna por implementações em hardware eficientes para funções threshold resultaram em um menor interesse no desenvolvimento de um fluxo de projeto baseado em threshold logic. No entanto, para algumas tecnologias emergentes como memristors, spintronic e diodos de tunelamento ressonantes (RTD), essa estratégia de projeto se mostra mais apropriada que os circuitos CMOS tradicionais baseados em chaves lógicas. Portanto, a pesquisa e o desenvolvimentos de métodos de síntese e verificação aplicáveis a circuitos threshold multi-níveis são necessárias. As ferramentas estado-da-arte para a síntese de circuitos threshold realizam um mapeamento tecnologico genérico, sem considerar informações de propriedades threshold, e depois realizam uma resíntese para cada nodo do circuito mapeado. Este trabalho apresenta a primeira abordagem…
Advisors/Committee Members: Ribas, Renato Perez.
Subjects/Keywords: Logic synthesis; Microeletrônica; Circuitos digitais; Digital circuit; Technology mapping; Threshold logic; Majority logic; Nanotechnologies
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APA (6th Edition):
Neutzling, A. (2017). Thereshold logic technology mapping for emerging nanotechnologies. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/180356
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Neutzling, Augusto. “Thereshold logic technology mapping for emerging nanotechnologies.” 2017. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021.
http://hdl.handle.net/10183/180356.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Neutzling, Augusto. “Thereshold logic technology mapping for emerging nanotechnologies.” 2017. Web. 06 Mar 2021.
Vancouver:
Neutzling A. Thereshold logic technology mapping for emerging nanotechnologies. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2017. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/10183/180356.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Neutzling A. Thereshold logic technology mapping for emerging nanotechnologies. [Thesis]. Universidade do Rio Grande do Sul; 2017. Available from: http://hdl.handle.net/10183/180356
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade do Rio Grande do Sul
6.
Silva, Augusto Neutzling.
Syhthesis of thereshold logic based circuits.
Degree: 2014, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/119435
► In this work, a novel method to synthesize digital integrated circuits (ICs) based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite…
(more)
▼ In this work, a novel method to synthesize digital integrated circuits (ICs) based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite relevant, since threshold logic has been revisited as a promising alternative to conventional CMOS IC design due to its suitability to emerging technologies, such as resonant tunneling diodes, memristors and spintronics devices. Identification and synthesis of threshold logic functions (TLF) are fundamental steps for the development of an IC design flow based on threshold logic. The first contribution is a heuristic algorithm to identify if a function can be implemented as a single TLG. Furthermore, if a function is not detected as a TLF, the method uses the functional composition approach to generate an optimized TLG network that implements the target function. The identification method is able to assign optimal variable weights and optimal threshold value to implement the function. It is the first heuristic algorithm that is not based on integer linear programming (ILP) that is able to identify all threshold functions with up to six variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is more than six. Differently from ILP based approaches, the proposed algorithm is scalable. The average execution time is less than 1 ms per function. The second major contribution is the constructive process applied to generate optimized TLG networks taking into account multiple goals and design costs, like gate count, logic depth and number of interconnections. Experiments carried out over MCNC benchmark circuits show an average gate count reduction of 32%, reaching up to 54% of reduction in some cases, when compared to related approaches.
Circuitos baseados em portas lógicas de limiar (threshold logic gates – TLG) vem sendo estudados como uma alternativa promissora em relação ao tradicional estilo lógico CMOS, baseado no operadores AND e OR, na construção de circuitos integrados digitais. TLGs são capazes de implementar funções Booleanas mais complexas em uma única porta lógica. Diversos novos dispositivos, candidatos a substituir o transistor MOS, não se comportam como chaves lógicas e são intrinsicamente mais adequados à implementação de TLGs. Exemplos desses dispositivos são os memristores, spintronica, diodos de tunelamento ressonante (RTD), autômatos celulares quânticos (QCA) e dispositivos de tunelamento de elétron único (SET). Para o desenvolvimento de um fluxo de projeto de circuitos integrados baseados em lógica threshold, duas etapas são fundamentais: (1) identificar se uma dada função Booleana corresponde a uma função lógica threshold (TLF), isto é, pode ser implementada em um único TLG e computar os pesos desse TLG; (2) se uma função não é identificada como TLF, outro método de síntese lógica deve construir uma rede de TLGs otimizada que implemente a função. Este trabalho propõe métodos para atacar cada um desses dois problemas, e os resultados superam os métodos do estado-da-arte. O…
Advisors/Committee Members: Ribas, Renato Perez.
Subjects/Keywords: Digital circuits; Microeletrônica; Logic synthesis; Circuitos digitais; Threshold logic; Emerging technologies
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APA ·
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APA (6th Edition):
Silva, A. N. (2014). Syhthesis of thereshold logic based circuits. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/119435
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Silva, Augusto Neutzling. “Syhthesis of thereshold logic based circuits.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021.
http://hdl.handle.net/10183/119435.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Silva, Augusto Neutzling. “Syhthesis of thereshold logic based circuits.” 2014. Web. 06 Mar 2021.
Vancouver:
Silva AN. Syhthesis of thereshold logic based circuits. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/10183/119435.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Silva AN. Syhthesis of thereshold logic based circuits. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/119435
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Minnesota
7.
Li, Peng.
Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing.
Degree: PhD, Electrical Engineering, 2013, University of Minnesota
URL: http://purl.umn.edu/155955
► Most digital systems operate on a positional representation of data, such as binary encoding. An alternative is to operate on random bit streams where the…
(more)
▼ Most digital systems operate on a positional representation of data, such as binary encoding. An alternative is to operate on random bit streams where the signal value is encoded by the probability of obtaining a one versus a zero. This representation is much less compact than the binary encoding. However, complex operations can be performed with very simple logic. Furthermore, since the representation is uniform, with all bits weighted equally, it is highly tolerant of soft errors (i.e., bit flips). Complex algorithms, such as artificial neural networks (ANN), low-density parity-check (LPDC) error-correcting coding, and kernel density estimation (KDE)-based image segmentation, can be implemented using stochastic encoding with much lower hardware cost and higher fault-tolerance. For example, the hardware area of the stochastic implementation of the KDE-based image segmentation is only 1.2% of the corresponding deterministic implementation, and it can tolerate more than 30% soft errors. Compared to conventional fault-tolerant techniques, such as triple-module redundance (TMR), the stochastic implementations of the complex algorithms normally consumes equivalent or less energy and have better fault-tolerance. For example, the TMR implementation of the KDE-based implementation can only tolerate up to 10% soft errors, but consumes the same energy as the stochastic implementation. In addition, thanks to the simple construction of the stochastic computing elements, it makes the rounting much easier, which is a big issue for very large scale integrated circuit (VLSI) deterministic implementations of these complex algorithms. Both combinational and sequential constructs have been proposed for operating on stochastic bit streams. Prior work has shown that combinational logic can implement multiplication and scaled addition effectively while finite-state machines (FSMs) can implement complex functions such as exponentiation and tanh effectively. Although the combinational logic-based stochastic computing elements had been well studied, they are inefficient for complex operations. The FSM-based stochastic computing elements are very efficient for complex operations. However, only three FSM-based stochastic computing elements were proposed by prior work, which limits the applications of stochastic computing. To implement more applications and functions stochastically, this dissertation focuses on the FSM-based stochastic computing. We first analyze the FSM-based stochastic computing elements proposed by prior work, which had largely been validated empirically. In this dissertation, we provide a rigorous mathematical treatment of the FSM-based stochastic computing elements. This gives us intuition about how to construct arbitrary functions stochastically using the FSM. Then, based on the existing stochastic computing elements, we implement five digital image processing algorithms as case studies. So far as we know, this is the first time these digital image processing algorithms are implemented stochastically. For all the five…
Subjects/Keywords: Fault-tolerance; Logic synthesis; Sequential logic; Stochastic computing
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to Zotero / EndNote / Reference
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APA (6th Edition):
Li, P. (2013). Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/155955
Chicago Manual of Style (16th Edition):
Li, Peng. “Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing.” 2013. Doctoral Dissertation, University of Minnesota. Accessed March 06, 2021.
http://purl.umn.edu/155955.
MLA Handbook (7th Edition):
Li, Peng. “Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing.” 2013. Web. 06 Mar 2021.
Vancouver:
Li P. Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing. [Internet] [Doctoral dissertation]. University of Minnesota; 2013. [cited 2021 Mar 06].
Available from: http://purl.umn.edu/155955.
Council of Science Editors:
Li P. Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing. [Doctoral Dissertation]. University of Minnesota; 2013. Available from: http://purl.umn.edu/155955
Lehigh University
8.
Reuther, Dana.
Four-bar Three-position Mechanism Synthesis Using the Principles of Fuzzy Logic Mathematics.
Degree: MS, Mechanical Engineering, 2014, Lehigh University
URL: https://preserve.lehigh.edu/etd/1604
► The human mind is very imprecise and uncertain most of the time. We are allowed to think as we wish, as things really are. This,…
(more)
▼ The human mind is very imprecise and uncertain most of the time. We are allowed to think as we wish, as things really are. This, however, is not how computers are designed to allow us to solve realistic problems. Now the question arises: how do we represent uncertainty and impreciseness using very accurate devices? In order to add flexibility into mechanical design, fuzzy
logic can be used to represent the imprecise data, such as how humans think. Fuzzy
logic allows the use of representing more than one value for a specific variable; it also allows the user to specify the shape the data takes (the membership function) which could be a function of the problem at hand. While incorporating fuzzy
logic into design, the design becomes more imprecise in the sense that its variables represent more than one value, yet the design becomes more accurate when considering how the human brain interprets these variables.
Advisors/Committee Members: Chew, Meng-Sang.
Subjects/Keywords: Fuzzy Logic; Linkage Synthesis; Mechanism Synthesis; Uncertainty; Engineering; Mechanical Engineering
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APA (6th Edition):
Reuther, D. (2014). Four-bar Three-position Mechanism Synthesis Using the Principles of Fuzzy Logic Mathematics. (Thesis). Lehigh University. Retrieved from https://preserve.lehigh.edu/etd/1604
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Reuther, Dana. “Four-bar Three-position Mechanism Synthesis Using the Principles of Fuzzy Logic Mathematics.” 2014. Thesis, Lehigh University. Accessed March 06, 2021.
https://preserve.lehigh.edu/etd/1604.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Reuther, Dana. “Four-bar Three-position Mechanism Synthesis Using the Principles of Fuzzy Logic Mathematics.” 2014. Web. 06 Mar 2021.
Vancouver:
Reuther D. Four-bar Three-position Mechanism Synthesis Using the Principles of Fuzzy Logic Mathematics. [Internet] [Thesis]. Lehigh University; 2014. [cited 2021 Mar 06].
Available from: https://preserve.lehigh.edu/etd/1604.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Reuther D. Four-bar Three-position Mechanism Synthesis Using the Principles of Fuzzy Logic Mathematics. [Thesis]. Lehigh University; 2014. Available from: https://preserve.lehigh.edu/etd/1604
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
9.
Mohammadgholi Songhori, Ebrahim.
TinyGarble: Efficient, Scalable, and Versatile Privacy-Preserving Computation Through Sequential Garbled Circuit.
Degree: PhD, Engineering, 2017, Rice University
URL: http://hdl.handle.net/1911/96146
► Privacy-preserving computation is a standing challenge central to several modern-world applications which require computing on sensitive data. Secure Function Evaluation (SFE) refers to provably secure…
(more)
▼ Privacy-preserving computation is a standing challenge central to several modern-world applications which require computing on sensitive data. Secure Function Evaluation (SFE) refers to provably secure techniques aiming to address this problem by enabling multiple parties to compute an arbitrary function jointly on their private inputs. The most promising two-party SFE method is called the Garbled Circuit (GC) protocol introduced by Andrew Yao. The protocol relays on representing the function as a Boolean circuit and encrypting/communicating at the
logic gate level. Despite several significant improvements in GC, efficiency, scalability and ease-of-use of the available methods are limited by the naive circuit representation as a directed acyclic graph, ad-hoc
logic optimizations, and custom compilers. In this thesis, we proposed a holistic solution to enhance the efficiency, scalability, and simplicity of the GC protocol. Our approach has three main pillars to address these key challenges: GC
synthesis, sequential GC, and garbled processor. The GC
synthesis is a novel automated methodology based on
logic synthesis techniques for generating optimized Boolean circuits for the GC protocol. Using sequential GC, we achieve an unprecedented level of compactness and scalability using sequential circuit descriptions. We combine GC
synthesis and sequential GC in an open-source framework called TinyGarble. The preliminary implementation of benchmark functions using TinyGarble demonstrates a high degree of memory-footprint compactness as well as improvement in overall efficiency compared to results of existing tools. Our sequential description also enables us, for the first time, to design and realize a garbled processor to reduce the problem of private function evaluation to a conventional SFE problem. In addition, the garbled processor allows users to develop SFE applications in high-level languages (e.g., C) and eliminates the need for Boolean circuit generation. We present ARM2GC, a garbled processor framework based on TinyGarble and the ARM processor. It allows users to develop GC applications using high-level programming languages with comparable efficiency to the best previous results. The primary enabler to make this construction practical and efficient is the introduction of SkipGate, a new algorithm that omits the communication cost of a Boolean gate when its output is independent of the private data. Benchmark evaluations demonstrate efficiency and usability of ARM2GC compared with the prior art in high-level GC compilation.
Advisors/Committee Members: Koushanfar, Farinaz (advisor), Cavallaro, Joseph (advisor).
Subjects/Keywords: Privacy-Preserving Computation; Logic Synthesis; Garbled Circuit; Secure Function Evaluation; Logic Design
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APA (6th Edition):
Mohammadgholi Songhori, E. (2017). TinyGarble: Efficient, Scalable, and Versatile Privacy-Preserving Computation Through Sequential Garbled Circuit. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/96146
Chicago Manual of Style (16th Edition):
Mohammadgholi Songhori, Ebrahim. “TinyGarble: Efficient, Scalable, and Versatile Privacy-Preserving Computation Through Sequential Garbled Circuit.” 2017. Doctoral Dissertation, Rice University. Accessed March 06, 2021.
http://hdl.handle.net/1911/96146.
MLA Handbook (7th Edition):
Mohammadgholi Songhori, Ebrahim. “TinyGarble: Efficient, Scalable, and Versatile Privacy-Preserving Computation Through Sequential Garbled Circuit.” 2017. Web. 06 Mar 2021.
Vancouver:
Mohammadgholi Songhori E. TinyGarble: Efficient, Scalable, and Versatile Privacy-Preserving Computation Through Sequential Garbled Circuit. [Internet] [Doctoral dissertation]. Rice University; 2017. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/1911/96146.
Council of Science Editors:
Mohammadgholi Songhori E. TinyGarble: Efficient, Scalable, and Versatile Privacy-Preserving Computation Through Sequential Garbled Circuit. [Doctoral Dissertation]. Rice University; 2017. Available from: http://hdl.handle.net/1911/96146
Portland State University
10.
Chaudhari, Gunavant Dinkar.
Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles.
Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2011, Portland State University
URL: https://pdxscholar.library.pdx.edu/open_access_etds/11
► Most part of my thesis is devoted to efficient automated logic synthesis of oracle processors. These Oracle Processors are of interest to several modern…
(more)
▼ Most part of my thesis is devoted to efficient automated
logic synthesis of oracle processors. These Oracle Processors are of interest to several modern technologies, including Scheduling and Allocation, Image Processing and Robot Vision, Computer Aided Design, Games and Puzzles, and Cellular Automata, but so far the most important practical application is to build
logic circuits to solve various practical Constraint Satisfaction Problems in Intelligent Robotics. For instance, robot path planning can be reduced to Satisfiability. In short, an oracle is a circuit that has some proposition of solution on the inputs and answers yes/no to this proposition. In other language, it is a predicate or a concept-checking machine. Oracles have many applications in AI and theoretical computer science but so far they were not used much in hardware architectures. Systematic
logic synthesis methodologies for oracle circuits were so far not a
subject of a special research. It is not known how big advantages these processors will bring when compared to parallel processing with CUDA/GPU processors, or standard PC processing. My interest in this thesis is only in architectural and
logic synthesis aspects and not in physical (technological) design aspects of these circuits. In future, these circuits will be realized using reversible, nano and some new technologies, but the interest in this thesis is not in the future realization technologies. We want just to answer the following question: Is there any speed advantage of the new oracle-based architectures, when compared with standard serial or parallel processors?
Advisors/Committee Members: Marek Perkowski.
Subjects/Keywords: Oracle processors; Automated logic synthesis; Processing speed; Multiprocessors; Parallel processing (Electronic computers); Logic circuits
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APA (6th Edition):
Chaudhari, G. D. (2011). Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/11
Chicago Manual of Style (16th Edition):
Chaudhari, Gunavant Dinkar. “Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles.” 2011. Masters Thesis, Portland State University. Accessed March 06, 2021.
https://pdxscholar.library.pdx.edu/open_access_etds/11.
MLA Handbook (7th Edition):
Chaudhari, Gunavant Dinkar. “Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles.” 2011. Web. 06 Mar 2021.
Vancouver:
Chaudhari GD. Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles. [Internet] [Masters thesis]. Portland State University; 2011. [cited 2021 Mar 06].
Available from: https://pdxscholar.library.pdx.edu/open_access_etds/11.
Council of Science Editors:
Chaudhari GD. Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles. [Masters Thesis]. Portland State University; 2011. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/11
University of Minnesota
11.
Qian, Weikang.
Digital yet deliberately random: synthesizing logical computation on stochastic bit streams.
Degree: PhD, Electrical engineering, 2011, University of Minnesota
URL: http://purl.umn.edu/113525
► Most digital circuits process information that is encoded as zeros and ones deterministically. For example, the arithmetic unit of a modern computer performs calculations on…
(more)
▼ Most digital circuits process information that is encoded as zeros and ones deterministically. For example, the arithmetic unit of a modern computer performs calculations on deterministic integer or floating-point values represented in binary radix. However, digital computation need not be deterministic. In this dissertation, we consider an alternative paradigm: digital circuits that compute on stochastic sequences of zeros and ones. Such circuits can implement complex arithmetic operations with very simple hardware. For instance, multiplication can be performed with a single AND gate. Also they are highly tolerant of soft errors (i.e., bit flips). In the first part of the dissertation, we present a general method for synthesizing digital circuitry that computes on stochastic bit streams. Our method can be used to synthesize arbitrary polynomial functions. Through polynomial approximations, it can also be used to synthesize non-polynomial functions. Experiments on polynomial functions and functions used in image processing show that our method produces circuits that are highly tolerant of soft errors. The accuracy degrades gracefully with the error rate. For applications that mandate simple hardware, producing relatively low precision computation very reliably, our method is a winning proposition.
A premise for the stochastic paradigm is the availability of stochastic bit streams with the requisite probabilities. Physical random sources can be exploited to generate such random bit streams. Generally, each source has a fixed bias and so provides bits that have a specific probability of being one versus zero. If many different probability values are required, it can be difficult or expensive to generate all of these directly from physical sources. In the second part of the dissertation, we demonstrate novel techniques for synthesizing combinational logic that transforms a set of source probabilities into different target probabilities. We consider three scenarios in terms of whether the source probabilities are specified and whether they can be duplicated. We present solutions to all of these three scenarios.
In the final part of the dissertation, we consider optimizing the circuits that compute on stochastic bit streams. We focus on a fundamental problem pertaining to generating probabilities: how to synthesize optimal two-level logic circuits to generate arbitrary probability values from unbiased input probability values of 0.5? This motivates a novel logic synthesis problem: find a Boolean function with exactly a given number of minterms and having a sum-of-product expression with the minimum number of products. A crucial step towards solving the problem is to determine whether there exists a set of cubes to satisfy a given intersection pattern of these cubes and, if it exists, to synthesize a set of cubes. We show a necessary and sufficient condition for the existence of a set of cubes to satisfy a given intersection pattern. We also show that the synthesis problem can be reduced to the problem of finding a…
Subjects/Keywords: Cube; Logic Synthesis; Minterm; Probabilistic Logic; Stochastic Bit Streams; Stochastic Computation; Electrical Engineering
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APA (6th Edition):
Qian, W. (2011). Digital yet deliberately random: synthesizing logical computation on stochastic bit streams. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/113525
Chicago Manual of Style (16th Edition):
Qian, Weikang. “Digital yet deliberately random: synthesizing logical computation on stochastic bit streams.” 2011. Doctoral Dissertation, University of Minnesota. Accessed March 06, 2021.
http://purl.umn.edu/113525.
MLA Handbook (7th Edition):
Qian, Weikang. “Digital yet deliberately random: synthesizing logical computation on stochastic bit streams.” 2011. Web. 06 Mar 2021.
Vancouver:
Qian W. Digital yet deliberately random: synthesizing logical computation on stochastic bit streams. [Internet] [Doctoral dissertation]. University of Minnesota; 2011. [cited 2021 Mar 06].
Available from: http://purl.umn.edu/113525.
Council of Science Editors:
Qian W. Digital yet deliberately random: synthesizing logical computation on stochastic bit streams. [Doctoral Dissertation]. University of Minnesota; 2011. Available from: http://purl.umn.edu/113525
Universidade do Rio Grande do Sul
12.
Martins, Mayler Gama Alvarenga.
Applications of functional composition for CMOS and emerging technologies.
Degree: 2015, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/164452
► The advances in semiconductor industry over the last decades have been strongly based on continuous scaling down of dimensions in manufactured CMOS devices. The use…
(more)
▼ The advances in semiconductor industry over the last decades have been strongly based on continuous scaling down of dimensions in manufactured CMOS devices. The use of CMOS devices profoundly relies on AND/OR/Inverter logic. As the CMOS scaling is reaching its physical limits, researchers increase the effort to prolong the CMOS life. Also, it is necessary to investigate alternative devices, which in many cases implies the use of different basic logic operations. As the commercial synthesis tools are not able to handle these technologies efficiently, there is an opportunity to research alternative logic implementations better suited for these new devices. This thesis focuses on presenting efficient algorithms to design circuits in both CMOS and new technologies while integrating these algorithms into regular design flows. For this task, we apply the functional composition technique, to efficiently synthesize both CMOS and emerging technologies. The functional composition is a bottom-up synthesis approach, providing flexibility to implement algorithms with optimal or suboptimal results for different technologies. To investigate how the functional composition compares to the state-of-the-art synthesis methods, we propose to apply this synthesis paradigm into six different scenarios. Two of them focus on CMOS-based circuits, and other four are based on emerging technologies. Regarding CMOSbased circuits, we investigate functional composition to investigate multi-output factorization in a circuit resynthesis flow. Also, we manipulate approximate functions to synthesize approximate triple modular redundancy (ATMR) modules. Concerning emerging technologies, we explore functional composition over spin-diode circuits and other promising approaches based on different logic implementations: threshold logic, majority logic, and implication logic. Results present a considerable improvement over the state-of-the-art methods for both CMOS and emerging technologies applications, demonstrating the ability to handle different technologies and showing the possibility to improve technologies not explored yet.
Os avanços da indústria de semicondutores nas últimas décadas foram baseados fortemente na contínua redução de tamanho dos dispositivos CMOS fabricados. Os usos de dispositivos CMOS dependem profundamente da lógica de portas E/OU/INV. À medida que os dispositivos CMOS estão atingindo oslimites fisicos, pesquisadores aumento esforço para prolongar a vida útil da tecnologia CMOS. Também é necessário investigar dispositivos alternativos, que em muitos casos implicam no uso de operações lógicas básicas diferentes. Como as ferramentas comerciais de síntese não são capazes de manipular eficientemente estas tecnologias Esta tese de doutorado foca em produzir algoritmos eficientes para projeto de circuitos tanto em CMOS quanto em novas tecnologias, integrando estes algorithmos em fluxos de projeto. Para esta tarefa, aplicamos a técnica da composição functional, para sintetizar eficiente tanto em CMOS quanto em tecnologias emergentes. A…
Advisors/Committee Members: Reis, Andre Inacio.
Subjects/Keywords: Microeletrônica; Functional composition; Cmos; Logic synthesis; Emerging technologies; Circuit resynthesis; Approximate circuits; Threshold logic; Majority logic; Spin-diodes; Memristors
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Manager
APA (6th Edition):
Martins, M. G. A. (2015). Applications of functional composition for CMOS and emerging technologies. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/164452
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Martins, Mayler Gama Alvarenga. “Applications of functional composition for CMOS and emerging technologies.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021.
http://hdl.handle.net/10183/164452.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Martins, Mayler Gama Alvarenga. “Applications of functional composition for CMOS and emerging technologies.” 2015. Web. 06 Mar 2021.
Vancouver:
Martins MGA. Applications of functional composition for CMOS and emerging technologies. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/10183/164452.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Martins MGA. Applications of functional composition for CMOS and emerging technologies. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/164452
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Portland State University
13.
Singhal, Rahul.
Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA).
Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2011, Portland State University
URL: https://pdxscholar.library.pdx.edu/open_access_etds/196
► Semiconductor industry seems to approach a wall where physical geometry and power density issues could possibly render the device fabrication infeasible. Quantum-dot Cellular Automata…
(more)
▼ Semiconductor industry seems to approach a wall where physical geometry and power density issues could possibly render the device fabrication infeasible. Quantum-dot Cellular Automata (QCA) is a new nanotechnology that claims to offer the potential of manufacturing even denser integrated circuits, which can operate at high frequencies and low power consumption. In QCA technology, the signal propagation occurs as a result of electrostatic interaction among the electrons as opposed to flow to the electrons in a wire. The basic building block of QCA technology is a QCA cell which encodes binary information with the relative position of electrons in it. A QCA cell can be used either as a wire or as
logic. In QCA, the directionality of the signal flow is controlled by phase-shifted electric field generated on a separate layer than QCA cell layer. This process is called clocking of QCA circuits. The
logic realization using regular structures such as PLAs have played a significant role in the semiconductor field due to their manufacturability, behavioral predictability and the ease of
logic mapping. Along with these benefits, regular structures in QCA's would allow for uniform QCA clocking structure. The clocking structure is important because the pioneers of QCA technology propose it to be fabricated in CMOS technology. This thesis presents a detailed design implementation and a comparative analysis of
logic realization using regular structures, namely Shannon-Lattices and PLAs for QCAs. A software tool was developed as a part of this research, which automatically generates complete QCA-Shannon-Lattice and QCA-PLA layouts for single-output Boolean functions based on an input macro-cell library. The equations for latency and throughput for the new QCA-PLA and QCA-Shannon-Lattice design implementations were also formulated. The correctness of the equations was verified by performing simulations of the tool-generate layouts with QCADesigner. A brief design trade-off analysis between the tool-generated regular structure implementation and the unstructured custom layout in QCA is presented for the full-adder circuit.
Advisors/Committee Members: Marek A. Perkowski.
Subjects/Keywords: Logic synthesis; QCA clocking; QCA layout; Regular structures; Cellular automata; Quantum dots; Logic circuits – Computer-aided design; Logic design
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APA (6th Edition):
Singhal, R. (2011). Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA). (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/196
Chicago Manual of Style (16th Edition):
Singhal, Rahul. “Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA).” 2011. Masters Thesis, Portland State University. Accessed March 06, 2021.
https://pdxscholar.library.pdx.edu/open_access_etds/196.
MLA Handbook (7th Edition):
Singhal, Rahul. “Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA).” 2011. Web. 06 Mar 2021.
Vancouver:
Singhal R. Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA). [Internet] [Masters thesis]. Portland State University; 2011. [cited 2021 Mar 06].
Available from: https://pdxscholar.library.pdx.edu/open_access_etds/196.
Council of Science Editors:
Singhal R. Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA). [Masters Thesis]. Portland State University; 2011. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/196
Cornell University
14.
Liu, Gai.
Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors.
Degree: PhD, Electrical and Computer Engineering, 2018, Cornell University
URL: http://hdl.handle.net/1813/64855
► Technology scaling, architectural innovations, and electronic design automation (EDA) are the three pillars supporting the exponential growth in computer hardware performance for the past six…
(more)
▼ Technology scaling, architectural innovations, and electronic design automation (EDA) are the three pillars supporting the exponential growth in computer hardware performance for the past six decades. With the traditional CMOS scaling approaching its end, there is an urgent need to explore novel techniques in the latter two aspects to sustain the long-standing trend of ever increasing computing performance and energy efficiency. This thesis studies new
logic and architectural
synthesis techniques that aim to significantly improve both productivity and quality for the digital hardware design. We re-examine the boundaries in the traditional EDA flow with the goals of (i) identifying and overcoming deficiencies in existing, well-established
logic-level optimization methods, and (ii) raising the level of abstraction to ease architectural-level exploration for hardware specialization. A common theme in this thesis is cross-stage optimization, where the
synthesis decisions at an early stage are made aware of downstream optimization in an efficient manner to maximize the quality of results (QoRs). More specifically, we apply cross-stage optimization to tackle four challenging
synthesis problems at
logic and architectural level. At the
logic level, we investigate both exact and approximate
synthesis techniques: (P1) PIMap improves the quality of
logic optimization by iteratively restructuring the
logic network guided by technology mapping; (P2) SCALS generates approximate circuits with statistical guarantees. At the architectural level, we target both specialized and programmable engines: (P3) ElasticFlow compiles irregular loop nests into specialized accelerators optimized for average-case performance; (P4) ASSIST synthesizes an instruction set architecture (ISA) description into programmable processor.
Advisors/Committee Members: Zhang, Zhiru (chair), Lal, Amit (committee member), Studer, Christoph (committee member), Sampson, Adrian L (committee member).
Subjects/Keywords: Architectural Synthesis; Cross-Stage Optimization; Electronic Design Automation; Logic Synthesis; Computer engineering; Engineering
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APA (6th Edition):
Liu, G. (2018). Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/64855
Chicago Manual of Style (16th Edition):
Liu, Gai. “Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors.” 2018. Doctoral Dissertation, Cornell University. Accessed March 06, 2021.
http://hdl.handle.net/1813/64855.
MLA Handbook (7th Edition):
Liu, Gai. “Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors.” 2018. Web. 06 Mar 2021.
Vancouver:
Liu G. Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors. [Internet] [Doctoral dissertation]. Cornell University; 2018. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/1813/64855.
Council of Science Editors:
Liu G. Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors. [Doctoral Dissertation]. Cornell University; 2018. Available from: http://hdl.handle.net/1813/64855
UCLA
15.
Feng, Zhe.
Logic Synthesis for FPGA Reliability.
Degree: Electrical Engineering, 2013, UCLA
URL: http://www.escholarship.org/uc/item/7w7602f5
► Logic synthesis is one of the key stages in the computer-aided design (CAD) flow for a field programmable gate array (FPGA) based design. It usually…
(more)
▼ Logic synthesis is one of the key stages in the computer-aided design (CAD) flow for a field programmable gate array (FPGA) based design. It usually consists of a series of optimization iterations to improve the quality of results (QoR) of the design. Besides the traditional optimization objectives (e.g., performance, area, power), the reliability is becoming a main concern as modern FPGAs have advanced to 20nm technology, due to reduction in core voltage, decrease in transistor geometry, and increase in switching speed. However, existing techniques for enhancing the reliability of FPGA based designs fall behind industrial needs in terms of cost (e.g., area and power overhead), CAD flow, runtime, and the FPGA architecture.To address the problems, this dissertation proposes several novel logic synthesis algorithms. The first algorithm seeks a formal method to improve the reliability of FPGA based designs while incurring minimal area and power overhead. The algorithm formulates the problem of the FPGA reliability under random faults as a stochastic satisfiability (SSAT) based Boolean matching, and employs robust templates to rewrite the look-up table (LUT) based netlist, to maximize the stochastic yield rate. To ensure not breaking the current CAD flow, a logic synthesis algorithm is presented that performs a SAT-based in-place reconfiguration in the LUT to mask soft errors, without changing of the functionality and topology of the LUT based netlist. In addition, the dissertation proposes three fast in-place logic synthesis algorithms targeting the modern FPGA architecture including both LUTs and interconnects, which perform simulation guided netlist analyses and utilize don't cares in the netlist to enhance the reliability of the design. The effectiveness of the proposed algorithms are verified by experimental results.
Subjects/Keywords: Electrical engineering; FPGA; Logic synthesis; Reliability; Soft error
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APA (6th Edition):
Feng, Z. (2013). Logic Synthesis for FPGA Reliability. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/7w7602f5
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Feng, Zhe. “Logic Synthesis for FPGA Reliability.” 2013. Thesis, UCLA. Accessed March 06, 2021.
http://www.escholarship.org/uc/item/7w7602f5.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Feng, Zhe. “Logic Synthesis for FPGA Reliability.” 2013. Web. 06 Mar 2021.
Vancouver:
Feng Z. Logic Synthesis for FPGA Reliability. [Internet] [Thesis]. UCLA; 2013. [cited 2021 Mar 06].
Available from: http://www.escholarship.org/uc/item/7w7602f5.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Feng Z. Logic Synthesis for FPGA Reliability. [Thesis]. UCLA; 2013. Available from: http://www.escholarship.org/uc/item/7w7602f5
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Texas A&M University
16.
Lin, Pey Chang K.
Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks.
Degree: PhD, Electrical Engineering, 2013, Texas A&M University
URL: http://hdl.handle.net/1969.1/151088
► In the quest to understand cell behavior and cure genetic diseases such as cancer, the fundamental approach being taken is undergoing a gradual change. It…
(more)
▼ In the quest to understand cell behavior and cure genetic diseases such as cancer, the fundamental approach being taken is undergoing a gradual change. It is becoming more acceptable to view these diseases as an engineering problem, and systems engineering approaches are being deployed to tackle genetic diseases. In this light, we believe that
logic synthesis techniques can play a very important role. Several techniques from the field of
logic synthesis can be adapted to assist in the arguably huge effort of modeling cell behavior, inferring biological networks, and controlling genetic diseases. Genes interact with other genes in a Gene Regulatory Network (GRN) and can be modeled as a Boolean Network (BN) or equivalently as a Finite State Machine (FSM). As the expression of genes deter- mine cell behavior, important problems include (i) inferring the GRN from observed gene expression data from biological measurements, and (ii) using the inferred GRN to explain how genetic diseases occur and determine the ”best” therapy towards treatment of disease.
We report results on the application of
logic synthesis techniques that we have developed to address both these problems. In the first technique, we present Boolean Satisfiability (SAT) based approaches to infer the predictor (logical support) of each gene that regulates melanoma, using gene expression data from patients who are suffering from the disease. From the output of such a tool, biologists can construct targeted experiments to understand the
logic functions that regulate a particular target gene. Our second technique builds upon the first, in which we use a
logic synthesis technique; implemented using SAT, to determine gene regulating functions for predictors and gene expression data. This technique determines a BN (or family of BNs) to describe the GRN and is validated on a synthetic network and the p53 network. The first two techniques assume binary valued gene expression data. In the third technique, we utilize continuous (analog) expression data, and present an algorithm to infer and rank predictors using modified Zhegalkin polynomials. We demonstrate our method to rank predictors for genes in the mutated mammalian and melanoma networks. The final technique assumes that the GRN is known, and uses weighted partial Max-SAT (WPMS) towards cancer therapy. In this technique, the GRN is assumed to be known. Cancer is modeled using a stuck-at fault model, and ATPG techniques are used to characterize genes leading to cancer and select drugs to treat cancer. To steer the GRN state towards a desirable healthy state, the optimal selection of drugs is formulated using WPMS. Our techniques can be used to find a set of drugs with the least side-effects, and is demonstrated in the context of growth factor pathways for colon cancer.
Advisors/Committee Members: Khatri, Sunil (advisor), Dougherty, Edward (committee member), Gratz, Paul (committee member), Williams, Tiffani (committee member), Balazsi, Gabor (committee member).
Subjects/Keywords: Genomics; Logic Synthesis; Boolean Satisfiability; Gene Regulatory Networks
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APA (6th Edition):
Lin, P. C. K. (2013). Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/151088
Chicago Manual of Style (16th Edition):
Lin, Pey Chang K. “Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks.” 2013. Doctoral Dissertation, Texas A&M University. Accessed March 06, 2021.
http://hdl.handle.net/1969.1/151088.
MLA Handbook (7th Edition):
Lin, Pey Chang K. “Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks.” 2013. Web. 06 Mar 2021.
Vancouver:
Lin PCK. Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks. [Internet] [Doctoral dissertation]. Texas A&M University; 2013. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/1969.1/151088.
Council of Science Editors:
Lin PCK. Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks. [Doctoral Dissertation]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/151088
17.
Düdder, Boris.
Automatic synthesis of component & connector software architectures with bounded combinatory logic.
Degree: 2014, Technische Universität Dortmund
URL: http://dx.doi.org/10.17877/DE290R-6528
► Combinatory logic synthesis is a new type-based approach towards automatic synthesis of software from components in a repository. In this thesis we show how the…
(more)
▼ Combinatory
logic synthesis is a new type-based approach towards automatic
synthesis of software from components in a repository. In this thesis we show how the type-based approach can naturally be used to exploit taxonomic conceptual structures in software architectures and component repositories to enable automatic composition and configuration of components, and also code generation, by associating taxonomic concepts to architectural building blocks such as, in particular, software connectors. Components of a repository are exposed for
synthesis as typed combinators, where intersection types are used to represent concepts that specify intended usage and functionality of a component. An algorithm for solving the type inhabitation problem in combinatory
logic - does there exist a composition of combinators with a given type? - is then used to automate the retrieval, composition, and configuration of suitable building blocks with respect to a goal
specification. Since type inhabitation has high computational complexity, heuristic optimizations for the inhabitation algorithm are essential for making the approach practical. We discuss particularly important (theoretical and pragmatic) optimization strategies and evaluate them by experiments. Furthermore, we apply this
synthesis approach to define a method for software connector
synthesis for realistic software architectures based on a type theoretic model. We conduct experiments with a rapid prototyping tool that employs this method on complex concrete ERP- and e-Commerce-systems and discuss the results.
Advisors/Committee Members: Rehof, Jakob (advisor), Henglein, Fritz (referee).
Subjects/Keywords: Logic; Software; Engineering; Architecture; Concurrency; Theorem prover; Synthesis; 004
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APA (6th Edition):
Düdder, B. (2014). Automatic synthesis of component & connector software architectures with bounded combinatory logic. (Doctoral Dissertation). Technische Universität Dortmund. Retrieved from http://dx.doi.org/10.17877/DE290R-6528
Chicago Manual of Style (16th Edition):
Düdder, Boris. “Automatic synthesis of component & connector software architectures with bounded combinatory logic.” 2014. Doctoral Dissertation, Technische Universität Dortmund. Accessed March 06, 2021.
http://dx.doi.org/10.17877/DE290R-6528.
MLA Handbook (7th Edition):
Düdder, Boris. “Automatic synthesis of component & connector software architectures with bounded combinatory logic.” 2014. Web. 06 Mar 2021.
Vancouver:
Düdder B. Automatic synthesis of component & connector software architectures with bounded combinatory logic. [Internet] [Doctoral dissertation]. Technische Universität Dortmund; 2014. [cited 2021 Mar 06].
Available from: http://dx.doi.org/10.17877/DE290R-6528.
Council of Science Editors:
Düdder B. Automatic synthesis of component & connector software architectures with bounded combinatory logic. [Doctoral Dissertation]. Technische Universität Dortmund; 2014. Available from: http://dx.doi.org/10.17877/DE290R-6528
University of Newcastle
18.
Fenn, Shannon Kayde.
Target curricula for multi-target classification: the role of internal meta-features in machine teaching.
Degree: PhD, 2020, University of Newcastle
URL: http://hdl.handle.net/1959.13/1411958
► Research Doctorate - Doctor of Philosophy (PhD)
In machine learning, methods inspired by human teaching practices such as the use of curricula, have been fruitful.…
(more)
▼ Research Doctorate - Doctor of Philosophy (PhD)
In machine learning, methods inspired by human teaching practices such as the use of curricula, have been fruitful. The bulk of such work has focused on applying a curriculum to the training examples presented to the learning algorithm. However, when there are multiple targets in the learning problem it is also possible to conceive of a curriculum being applied with respect to them. This type of curriculum has received significantly less attention and the key unresolved challenges lay in determining the relative difficulty of learning each target. Logic synthesis is an important aspect of Electronic Design Automation. With the increasing complexity and breadth of designs however comes a significant cost in expert human effort. The most common optimisation-based approaches to automating logic design unfortunately face exponential growth in representation size. Machine learning, which builds models from limited example data, offers a potential remedy to this. The majority of circuit synthesis problems are inherently multi-target making them a good test-bed for target curriculum methods. In this thesis I explore possibilities for target curriculum methods in small-sample machine learning problems using logic synthesis as a test-bed. Using a principle of probably common utility and using intrinsic dimension as a proxy for complexity, I detail two a priori methods, and one self-paced method for generating target-curricula. I also explore a number of ways of applying target curricula within Boolean and neural networks. The results of these studies suggest that target curricula are highly effective in the right circumstances and that using them to directly train digital circuit designs is a compelling direction for future design automation.
Advisors/Committee Members: University of Newcastle. Faculty of Engineering & Built Environment, School of Electrical Engineering and Computing.
Subjects/Keywords: target curriculum; logic synthesis; Boolean networks; intrinsic dimension; supervised learning
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Export
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APA (6th Edition):
Fenn, S. K. (2020). Target curricula for multi-target classification: the role of internal meta-features in machine teaching. (Doctoral Dissertation). University of Newcastle. Retrieved from http://hdl.handle.net/1959.13/1411958
Chicago Manual of Style (16th Edition):
Fenn, Shannon Kayde. “Target curricula for multi-target classification: the role of internal meta-features in machine teaching.” 2020. Doctoral Dissertation, University of Newcastle. Accessed March 06, 2021.
http://hdl.handle.net/1959.13/1411958.
MLA Handbook (7th Edition):
Fenn, Shannon Kayde. “Target curricula for multi-target classification: the role of internal meta-features in machine teaching.” 2020. Web. 06 Mar 2021.
Vancouver:
Fenn SK. Target curricula for multi-target classification: the role of internal meta-features in machine teaching. [Internet] [Doctoral dissertation]. University of Newcastle; 2020. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/1959.13/1411958.
Council of Science Editors:
Fenn SK. Target curricula for multi-target classification: the role of internal meta-features in machine teaching. [Doctoral Dissertation]. University of Newcastle; 2020. Available from: http://hdl.handle.net/1959.13/1411958
University of Southern California
19.
Shin, Doochul.
Techniques for design and synthesis of approximate digital
circuits for error-tolerant applications.
Degree: PhD, Computer Engineering, 2011, University of Southern California
URL: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6372
► As VLSI technology node scales to nano-scale, dramatic improvements in most attributes of circuits, especially delay and yield, provided by scaling are beginning to decrease.…
(more)
▼ As VLSI technology node scales to nano-scale, dramatic
improvements in most attributes of circuits, especially delay and
yield, provided by scaling are beginning to decrease. One of the
main reasons for this trend is the increase in non-idealities, such
as increasing defect rates and increasing variations due to the
manufacturing process. The concept of error tolerance has been
proposed earlier to mitigate the effect of the non-idealities. Main
concept of error tolerance is that for a wide variety of
applications including audio, video, graphics, and wireless
communications, defective chips that produce erroneous values at
its outputs can be acceptable, provided the errors are of certain
types and their severities are within application-specified
thresholds. Previous research on error tolerance focused on
identifying such defective but acceptable chips during
post-fabrication testing to improve yield. ❧ This Ph.D.
dissertation proposes, a new approach to exploit error tolerance
based on the following observation: If certain deviations from the
nominal output values are acceptable, then we can exploit this
flexibility during circuit design or
synthesis to reduce circuit's
area, delay, and power and as a consequence to increase yield. In
this thesis, we introduce approximate design technique for several
different scenarios of original implementation of the circuit as
well as different cost metrics to be improved. Original circuit and
error tolerance threshold is assumed to be given for developing
approximate design methodology. In the application level analysis,
we show the existence of error tolerance in the application level
with the defined error tolerance metrics as well as the
relationship between error tolerance metric and traditional quality
metric of information. Then, we introduce approximate circuit
design methodology for error tolerance applications in gate level
implementation of original circuit. Two different techniques have
been proposed that is to simplify circuit using forward and
backward removal by injecting stuck-at faults and substitute
sub-function of the circuit with another sub-function in the
circuit. Approximate design methodology for Boolean function
(typically in the form of a truth table) level also has been
explored. Main idea is to expand original cubes by complementing
minterms in original function. The expansion of original cubes can
be considered as area decrease in circuit implemented by the
function. To select good candidate minterms in the circuit, we
deterministically prune the candidate minterms that cannot reduce
area when complemented. Finally, we explore the case when the
objective is to improve parametric yield of the circuit in gate
level implementation of generic combinational circuit. To improve
parametric yield, we not only focus on reducing critical delay but
reducing number of critical and near-critical paths. Critical delay
and number of critical and near-critical path reduction reduces
probability of the circuit to have delay greater than required
delay. Experiment…
Advisors/Committee Members: Gupta, Sandeep K. (Committee Chair), Ortega, Antonio (Committee Member), Medvidovic, Nenad (Committee Member).
Subjects/Keywords: circuit design; error tolerance; logic synthesis; yield improvement
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APA ·
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Export
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Manager
APA (6th Edition):
Shin, D. (2011). Techniques for design and synthesis of approximate digital
circuits for error-tolerant applications. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6372
Chicago Manual of Style (16th Edition):
Shin, Doochul. “Techniques for design and synthesis of approximate digital
circuits for error-tolerant applications.” 2011. Doctoral Dissertation, University of Southern California. Accessed March 06, 2021.
http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6372.
MLA Handbook (7th Edition):
Shin, Doochul. “Techniques for design and synthesis of approximate digital
circuits for error-tolerant applications.” 2011. Web. 06 Mar 2021.
Vancouver:
Shin D. Techniques for design and synthesis of approximate digital
circuits for error-tolerant applications. [Internet] [Doctoral dissertation]. University of Southern California; 2011. [cited 2021 Mar 06].
Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6372.
Council of Science Editors:
Shin D. Techniques for design and synthesis of approximate digital
circuits for error-tolerant applications. [Doctoral Dissertation]. University of Southern California; 2011. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6372
Lehigh University
20.
ALHINDI, AHMED.
Three-position Dimensional Synthesis of Four-Bar Mechanism for Function Generation Using Fuzzy Logic Mathematics.
Degree: MS, Mechanical Engineering, 2019, Lehigh University
URL: https://preserve.lehigh.edu/etd/5628
► Dimensional synthesis of the four-bar mechanism could not be determined precisely due to many constraints such as manufacturing tolerance, joint clearance, thermal deformation, the…
(more)
▼ Dimensional
synthesis of the four-bar mechanism could not be determined precisely due to many constraints such as manufacturing tolerance, joint clearance, thermal deformation, the deflection and so on. All of these constraints are included in the uncertainty of the dimensions of the four-bar mechanism. In this research, this uncertainty will be modeled based on the fuzziness one of the precision points of Freudenstein's equation that builds intervals of link’s dimensions with membership functions. They represents the probability of the dimensions value depending on the uncertainty of the positions of the precision point itself rather than uncertainty of the external information about the mechanism dimensions. The results of the fuzzy
synthesis will be defuzzified using the centroid defuzzification method to get the dimensions of the mechanism. Then, the resultant function from the fuzzy
synthesis is comparing with the crisp one to study the range and limits of the fuzziness operation in the generated function.
Advisors/Committee Members: Meng-Sang Chew.
Subjects/Keywords: Dimensional Synthesis; Four-Bar Mechanism; Function Generation; Fuzzy Logic; Mechanical Engineering
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APA ·
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APA (6th Edition):
ALHINDI, A. (2019). Three-position Dimensional Synthesis of Four-Bar Mechanism for Function Generation Using Fuzzy Logic Mathematics. (Thesis). Lehigh University. Retrieved from https://preserve.lehigh.edu/etd/5628
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
ALHINDI, AHMED. “Three-position Dimensional Synthesis of Four-Bar Mechanism for Function Generation Using Fuzzy Logic Mathematics.” 2019. Thesis, Lehigh University. Accessed March 06, 2021.
https://preserve.lehigh.edu/etd/5628.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
ALHINDI, AHMED. “Three-position Dimensional Synthesis of Four-Bar Mechanism for Function Generation Using Fuzzy Logic Mathematics.” 2019. Web. 06 Mar 2021.
Vancouver:
ALHINDI A. Three-position Dimensional Synthesis of Four-Bar Mechanism for Function Generation Using Fuzzy Logic Mathematics. [Internet] [Thesis]. Lehigh University; 2019. [cited 2021 Mar 06].
Available from: https://preserve.lehigh.edu/etd/5628.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
ALHINDI A. Three-position Dimensional Synthesis of Four-Bar Mechanism for Function Generation Using Fuzzy Logic Mathematics. [Thesis]. Lehigh University; 2019. Available from: https://preserve.lehigh.edu/etd/5628
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Virginia Tech
21.
Elbayoumi, Mahmoud Atef Mahmoud Sayed.
Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms.
Degree: PhD, Computer Engineering, 2015, Virginia Tech
URL: http://hdl.handle.net/10919/51221
► According to Moore's law, Integrated Chips (IC) doubles its capacity every 18 months. This causes an exponential increase of the available area, and hence,the complexity…
(more)
▼ According to Moore's law, Integrated Chips (IC) doubles its capacity every 18 months. This causes an exponential increase of the available area, and hence,the complexity of modern digital designs. This consistent enormous gross challenges different research areas in Electronic Design Automation (EDA). Thus, various EDA applications such as equivalence checking, model checking, Automatic Test Pattern Generation (ATPG), functional Bi-decomposition, and technology mapping need to keep pace with these challenges. In this thesis, we are concerned with improving the quality and performance of different EDA algorithms particularly in area of hardware verification and
synthesis.
First, we introduce algorithms to manipulate Reduced Ordered Binary Decision Diagrams (ROBDD) on multi-core machines. In order to perform multiple BDD operations concurrently, our algorithm uses a breadth-first search (BFS). As ROBDD algorithms are memory-intensive, maintaining locality of data is an important issue. Therefore, we propose the usage of Hopscotch hashing technique for both Unique Table and BFS Queues to improve the construction time of ROBDD on the parallel platform. Hopscotch hashing technique not only improves the locality of the manipulating data, but also provides a way to cache recently performed BDD operation. Consequently, The time and space usage can be traded off.
Secondly, we used static implications to enhance the performance of SAT-based Bounded Model Checking (BMC) problem. we propose a parallel deduction engine to efficiently utilize low-cost off-shelf multi-core processors to compute the implications. With this engine, we can significantly reduce the computational processing time in analyzing the deduced implications. Secondly, we formulate the clause filter problem as an elegant set-covering problem. Thirdly, we propose a novel greedy algorithm based on the Johnson's algorithm to find the optimal set of clauses that would accelerate BMC solution.
Thirdly, we proposed a novel
synthesis paradigm to achieve timing-closure called Timing-Aware CUt Enumeration (TACUE). In TACUE, optimization is conducted through three aspects: First, we propose a new divide-and-conquer strategy that generates multiple sub-cuts on the critical parts of the circuit. Secondly, cut enumeration have been applied in two cutting strategies. In the topology-aware cutting strategy, we preserve the general topology of the circuit by applying TACUE in only self-contained cuts. Meanwhile, the topology-masking cutting strategy investigates circuit cuts beyond their current topology. Thirdly, we proposed an efficient parallel
synthesis framework to reduce computation time for synthesizing TACUE sub-cuts. We conducted experiments on large and difficult industrial benchmarks.
Finally, we proposed the first scalable SAT-based approaches for Observability Dont Care (ODC) clock gating. Moreover we intelligently choose those inductive invariants candidates such that their validation will benefit the purpose in clock-gating-based low-power design.
Advisors/Committee Members: Hsiao, Michael S. (committeechair), Wang, Chao (committee member), Riad, Sedki Mohamed (committee member), Shukla, Sandeep K. (committee member), Shimozono, Mark M. (committee member), El-Nainay, Mustafa Yousry (committee member).
Subjects/Keywords: Verification; logic synthesis; SAT; BDDs; Low power; timing aware
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APA (6th Edition):
Elbayoumi, M. A. M. S. (2015). Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51221
Chicago Manual of Style (16th Edition):
Elbayoumi, Mahmoud Atef Mahmoud Sayed. “Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms.” 2015. Doctoral Dissertation, Virginia Tech. Accessed March 06, 2021.
http://hdl.handle.net/10919/51221.
MLA Handbook (7th Edition):
Elbayoumi, Mahmoud Atef Mahmoud Sayed. “Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms.” 2015. Web. 06 Mar 2021.
Vancouver:
Elbayoumi MAMS. Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/10919/51221.
Council of Science Editors:
Elbayoumi MAMS. Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51221
IUPUI
22.
Yadav, Avinash.
Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness.
Degree: 2020, IUPUI
URL: http://hdl.handle.net/1805/24772
► Indiana University-Purdue University Indianapolis (IUPUI)
In this thesis, we investigated the 7 nm FinFET technology for its delay-power product performance. In our study, we explored…
(more)
▼ Indiana University-Purdue University Indianapolis (IUPUI)
In this thesis, we investigated the 7 nm FinFET technology for its delay-power product performance. In our study, we explored the ASAP7 library from Arizona State University, developed in collaboration with ARM Holdings. The FinFET technology was chosen since it has a subthreshold slope of 60mV/decade that enables cells to function at 0.7V supply voltage at the nominal corner. An emphasis was focused on characterizing the Non-Ideal effects, delay variation, and power for the FinFET device. An exhaustive analysis of the INVx1 delay variation for different operating conditions was also included, to assess the robustness.
The 7nm FinFET device was then employed into 6T SRAM cells and 16 function ALU. The SRAM cells were approached with advanced multi-corner stability evaluation. The system-level architecture of the ALU has demonstrated an ultra-low power system operating at 1 GHz clock frequency.
Advisors/Committee Members: Rizkalla, Maher E., Ytterdal, Trond, Lee, John J..
Subjects/Keywords: FinFET; ALU; 6T SRAM; Robustness; Logic Synthesis; Physical Design
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APA ·
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Manager
APA (6th Edition):
Yadav, A. (2020). Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness. (Thesis). IUPUI. Retrieved from http://hdl.handle.net/1805/24772
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Yadav, Avinash. “Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness.” 2020. Thesis, IUPUI. Accessed March 06, 2021.
http://hdl.handle.net/1805/24772.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Yadav, Avinash. “Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness.” 2020. Web. 06 Mar 2021.
Vancouver:
Yadav A. Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness. [Internet] [Thesis]. IUPUI; 2020. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/1805/24772.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Yadav A. Multi-Threshold Low Power-Delay Product Memory And Datapath Components Utilizing Advanced FinFET Technology Emphasizing The Reliability And Robustness. [Thesis]. IUPUI; 2020. Available from: http://hdl.handle.net/1805/24772
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade do Rio Grande do Sul
23.
Martinello Junior, Osvaldo.
KL-cuts : a new approach for logic synthesis targeting multiple output blocks.
Degree: 2010, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/26503
► Esta dissertação introduz o conceito de cortes KL, o que permite controlar tanto o número K de entradas como o número L de saídas em…
(more)
▼ Esta dissertação introduz o conceito de cortes KL, o que permite controlar tanto o número K de entradas como o número L de saídas em uma região de um circuito. O projeto de um circuito digital pode ser dividido em duas fases: síntese lógica e síntese física. Dentro de síntese lógica, um dos principais passos é o mapeamento tecnológico. Tradicionalmente, o processo de mapeamento tecnológico somente lida com funções de saída única, para a construção de circuitos. O objetivo deste método é explorar o uso de blocos de múltiplas saídas no mapeamento tecnológico. Para prover escalabilidade, o conceito de fatoração de cortes é estendido para os cortes KL. Algoritmos para enumerar esses cortes e também para enumerar alguns subconjuntos de cortes com características específicas são apresentados e os resultados são mostrados. Como exemplos de aplicações práticas, diferentes algoritmos de cobertura são propostos. O algoritmo guloso é uma alternativa simples e produz bons resultados em área, mas é muito restritivo, pois não é factível em mapeamento orientado à atraso. Outro algoritmo de cobertura apresentado é uma extensão do algoritmo de fluxo de área e permite a utilização de cortes com várias saídas, mantendo possível a consideração de outros custos. Um algoritmo de correspondência Booleana que é capaz de lidar com blocos com múltiplas saídas também é descrito. Isso permite a utilização de uma biblioteca padrão com células com mais de uma saída no mapeamento tecnológico. Os resultados mostram a viabilidade e utilidade do método.
This thesis introduces the concept of KL-feasible cuts, which allows controlling both the number K of inputs and the number L of outputs in a circuit region. The design of a digital circuit can roughly be divided in two phases: logic synthesis and physical synthesis. Within logic synthesis, one of the main steps is the technology mapping. Traditionally, the technology mapping process only handles single output functions, in order to construct circuits. The objective of this method is to explore the use of multiple output blocks on technology mapping. To provide scalability, the concept of factor cuts is extended to KL-cuts. Algorithms for enumerating these cuts and also for enumerating some subsets of cuts with some special characteristics are presented and results are shown. As examples of practical applications, different covering algorithms are proposed. The greedy algorithm is a simple alternative and produces good results in area, but it is too restrictive, as it is not practical in timing oriented mapping. The other covering algorithm presented is an extension to the area flow algorithm and allows cuts with multiple outputs to be used while making possible the control of some other costs. A Boolean matching algorithm that is able to handle multiple output blocks is also described, which permits the use of a standard cell library with more than one output on technology mapping. The results show the viability and usefulness of the method.
Advisors/Committee Members: Ribas, Renato Perez.
Subjects/Keywords: AIG; Microeletrônica; Cut enumeration; 3D; KL-cuts; Testes : Circuitos integrados; Circuitos integrados; Logic design; Logic synthesis; Multiple output blocks; Technology mapping
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APA (6th Edition):
Martinello Junior, O. (2010). KL-cuts : a new approach for logic synthesis targeting multiple output blocks. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/26503
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Martinello Junior, Osvaldo. “KL-cuts : a new approach for logic synthesis targeting multiple output blocks.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021.
http://hdl.handle.net/10183/26503.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Martinello Junior, Osvaldo. “KL-cuts : a new approach for logic synthesis targeting multiple output blocks.” 2010. Web. 06 Mar 2021.
Vancouver:
Martinello Junior O. KL-cuts : a new approach for logic synthesis targeting multiple output blocks. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/10183/26503.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Martinello Junior O. KL-cuts : a new approach for logic synthesis targeting multiple output blocks. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/26503
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade do Rio Grande do Sul
24.
Figueiró, Thiago Rosa.
Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition.
Degree: 2010, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/27663
► O emprego de ferramentas de automação de projetos de circuitos integrados permitiu que projetos complexos atingissem time-to-market e custos de produção factíveis. Neste contexto, o…
(more)
▼ O emprego de ferramentas de automação de projetos de circuitos integrados permitiu que projetos complexos atingissem time-to-market e custos de produção factíveis. Neste contexto, o processo de síntese lógica é uma etapa fundamental no fluxo de projeto. O passo independente de tecnologia (parte do processo de síntese lógica, que é realizada sem considerar características físicas) é tradicionalmente realizado sobre equações. O desenvolvimento de novos algoritmos de otimização multi-nível recentemente migrou para o emprego de And-Inverter Graphs (AIGs). O número de nodos e a altura de um grafo apresentam melhor correlação com os resultados em área e atraso de um circuito, se comparados com as características de outras formas de representação. Neste trabalho, um algoritmo de síntese lógica independente de tecnologia, que funciona sobre uma estrutura de AIGs, é proposto. Uma nova abordagem para a construção de AIGs, baseada no novo paradigma de síntese chamado de composição funcional, é apresentado. Esta abordagem consiste em construir o AIG final através da associação de AIGs mais simples, em uma abordagem bottom-up. Durante a construção do grafo, o método controla as características dos grafos intermediários e finais, a partir da aplicação de uma função de custo, como forma de avaliação da qualidade desses AIGs. O objetivo é a minimização do número de nodos e da altura do AIG final. Este algoritmo de síntese lógica multi-objetivo apresenta características interessantes e vantagens quando comparado com abordagens tradicionais. Além disso, este trabalho apresenta a síntese de funções com múltiplas saídas em AIGs, o que melhora a característica de compartilhamento de estruturas, melhorando o circuito resultante. Resultados mostraram a melhora em torno de 5% em número de nodos, quando comparados com os resultados obtidos com a ferramenta ABC.
The use of design automation tools has allowed complex projects to reach feasible time-to-market and cost parameters. In this context, logic synthesis is a critical procedure in the design flow. The technology independent step (part of the logic synthesis which is performed regardless any physical property) is traditionally performed over equations. The development of new multi-level optimization algorithms has recently shifted towards the use of And-Inverter-Graphs (AIGs). The number of nodes and the graphs depth in AIGs present better correlation with resulting circuit area and delay than any characteristic of other representations. In this work, a technology independent synthesis algorithm that works on top of an AIG data structure is proposed. A novel approach for AIG construction, based on a new synthesis paradigm called functional composition, is introduced. This approach consists in building the final AIG by associating simpler AIGs, in a bottom-up approach. The method controls, during the graphs construction, the characteristics of final and intermediate graphs by applying a cost function as a way to evaluate the quality of those AIGs. The goal is to minimize the number of…
Advisors/Committee Members: Reis, Andre Inacio.
Subjects/Keywords: Logic synthesis; Microeletrônica; And-inverter graph; Processamento : Imagem; Design automation; CAD; Digital circuits; Logic gates; Design flow; Technology mapping
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APA ·
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APA (6th Edition):
Figueiró, T. R. (2010). Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/27663
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Figueiró, Thiago Rosa. “Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021.
http://hdl.handle.net/10183/27663.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Figueiró, Thiago Rosa. “Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition.” 2010. Web. 06 Mar 2021.
Vancouver:
Figueiró TR. Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/10183/27663.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Figueiró TR. Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/27663
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade do Rio Grande do Sul
25.
Schneider, Felipe Ribeiro.
Building transistor-level networks following the lower bound on the number of stacked switches.
Degree: 2007, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/55446
► Em portas lógicas CMOS, tanto o atraso de propagação como a curva de saída estão fortemente ligados ao número de dispositivos PMOS e NMOS conectados…
(more)
▼ Em portas lógicas CMOS, tanto o atraso de propagação como a curva de saída estão fortemente ligados ao número de dispositivos PMOS e NMOS conectados em série nas redes de carga e descarga, respectivamente. O estilo lógico ‘standard CMOS’ é, em geral, otimizado para um dos planos, apresentando então o arranjo complementar no plano oposto. Consequentemente, o número mínimo de transistores em série não é necessariamente alcançado. Neste trabalho, apresenta-se um método para encontrar o menor número de chaves (transistores) em série necessários para se implementar portas lógicas complexas CMOS. Um novo estilo lógico CMOS, derivado de tal método, é então proposto e comparado ao estilo CMOS convencional através do uso de uma ferramenta de caracterização comercial. A caracterização elétrica de conjuntos de funções de 3 a 6 entradas foi realizada para avaliar o novo método, apresentando significativos ganhos em velocidade, sem perdas em dissipação de potência ou em área.
Both the propagation delay and the output slope in CMOS gates are strongly related to the number of stacked PMOS and NMOS devices in the pull-up and pull-down networks, respectively. The standard CMOS logic style is usually optimized targeting one logic plane, presenting then the complemented topology in the other one. As a consequence, the minimum number of stacked transistors is not necessarily achieved. In this work, a method to find the lower bound of stacked switches (transistors) in CMOS complex gates is presented. A novel CMOS logic style, derived from such method, is then proposed and compared to conventional CMOS style through a commercial cell characterizer. Electrical characterization of sets of 3- to 6-input functions was done in order to evaluate the new method. Significant gains in propagation delay were obtained without penalty in power dissipation or area.
Advisors/Committee Members: Reis, Andre Inacio.
Subjects/Keywords: Microeletrônica; Logic style; Redes : Computadores; Logic synthesis; Cell libraries
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APA ·
Chicago ·
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Export
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APA (6th Edition):
Schneider, F. R. (2007). Building transistor-level networks following the lower bound on the number of stacked switches. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/55446
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Schneider, Felipe Ribeiro. “Building transistor-level networks following the lower bound on the number of stacked switches.” 2007. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021.
http://hdl.handle.net/10183/55446.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Schneider, Felipe Ribeiro. “Building transistor-level networks following the lower bound on the number of stacked switches.” 2007. Web. 06 Mar 2021.
Vancouver:
Schneider FR. Building transistor-level networks following the lower bound on the number of stacked switches. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2007. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/10183/55446.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Schneider FR. Building transistor-level networks following the lower bound on the number of stacked switches. [Thesis]. Universidade do Rio Grande do Sul; 2007. Available from: http://hdl.handle.net/10183/55446
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade do Rio Grande do Sul
26.
Matos, Jody Maick Araujo de.
Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools.
Degree: 2014, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/147759
► This master’s thesis introduces a set of graph-based algorithms for obtaining reduced transistor count VLSI circuits using simple cells. These algorithms are mainly focused on…
(more)
▼ This master’s thesis introduces a set of graph-based algorithms for obtaining reduced transistor count VLSI circuits using simple cells. These algorithms are mainly focused on minimizing node count in AIG representations and mapping this optimized AIG using simple cells (NAND2 and NOR2) with a minimal number of inverters. Due to the AIG node count minimization, the logic sharing is probably highly present in the optimized AIG, what may derive intermediate circuits containing cells with unfeasible fanout in current technology nodes. In order to fix these occurrences, this intermediate circuit is subjected to an algorithm for fanout limitation. The proposed algorithms were applied over a set of benchmark circuits and the obtained results have shown the usefulness of the method. The circuits generated by the methods proposed herein have, in average, 32% less transistor than the previous reference on transistor count using simple cells. Additionally, when comparing the presented results in terms of transistor count against works advocating for complex cells, our results have demonstrated that previous approaches are sometimes far from the minimum transistor count that can be obtained with the efficient use of a reduced cell library composed by only a few number of simple cells. The simple-cells-based circuits obtained after applying the algorithms proposed herein have presented a lower transistor count in many cases when compared to previously published results using complex (static CMOS and PTL) cells.
Esta dissertação de mestrado introduz um conjunto de algoritmos baseados em grafos para a obtenção de circuitos VLSI com um número reduzido de transistores utilziando células simples. Esses algoritmos têm um foco principal na minimização do número de nodos em representações AIG e mapear essa estrutura otimizada utilizando células simples (NAND2 e NOR2) com um número mínimo de inversores. Devido à minimização de nodos, o AIG tem um alto compartilhamento lógico, o que pode derivar circuitos intermediários contendo células com fanouts infactíveis para os nodos tecnológicos atuais. De forma a resolver essas ocorrências, o circuito intermediário é submetido a um algoritmo para limitação de fanout. Os algoritmos propostos foram aplicados num conjunto de circuitos de benchmark e os resultados obtidos mostram a utilidade do método. Os circuitos resultantes tiveram, em média, 32% menos transistores do que as referências anteriores em números de transistores utilizando células simples. Adicionalmente, quando comparando esses resultados com trabalhos que utilizam células complexas, nossos números demonstraram que abordagens anteriores estão algumas vezes longe do número mínimo de transistores que pode ser obtido com o uso eficiente de uma biblioteca reduzida de células, composta por poucas células simples. Os circuitos baseados em células simples obtidos com a aplicação dos algoritmos proposto neste trabalho apresentam um menor número de transistores em muitos casos quando comparados aos resultados previamente publicados…
Advisors/Committee Members: Reis, Andre Inacio.
Subjects/Keywords: Microeletrônica; Benchmark circuits; Transistor count; Algoritmos; Vlsi : Circuitos integrados : Eletronica; Logic synthesis; Technology mapping
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APA ·
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APA (6th Edition):
Matos, J. M. A. d. (2014). Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/147759
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Matos, Jody Maick Araujo de. “Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021.
http://hdl.handle.net/10183/147759.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Matos, Jody Maick Araujo de. “Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools.” 2014. Web. 06 Mar 2021.
Vancouver:
Matos JMAd. Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/10183/147759.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Matos JMAd. Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/147759
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade do Rio Grande do Sul
27.
Callegaro, Vinicius.
Minimização ótima de classes especiais de funções booleanas.
Degree: 2016, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/148342
► The problem of factoring and decomposing Boolean functions is Σ-complete 2 for general functions. Efficient and exact algorithms can be created for an existing class…
(more)
▼ The problem of factoring and decomposing Boolean functions is Σ-complete 2 for general functions. Efficient and exact algorithms can be created for an existing class of functions known as read-once, disjoint-support decomposable and read-polarity-once functions. A factored form is called read-once (RO) if each variable appears only once. A Boolean function is RO if it can be represented by an RO form. For example, the function represented by = 1 2+ 1 3 4+ 1 3 5 is a RO function, since it can be factored into = 1( 2+ 3( 4+ 5)). A Boolean function f(X) can be decomposed using simpler subfunctions g and h, such that ( )=ℎ( ( 1), 2) being X1, X2 ≠ ∅, and X1 ∪ X2 = X. A disjoint-support decomposition (DSD) is a special case of functional decomposition, where the input sets X1 and X2 do not share any element, i.e., X1 ∩ X2 = ∅. Roughly speaking, DSD functions can be represented by a read-once expression where the exclusive-or operator (⊕) can also be used as base operation. For example, = 1( 2⊕( 4+ 5)). A read-polarity-once (RPO) form is a factored form where each polarity (positive or negative) of a variable appears at most once. A Boolean function is RPO if it can be represented by an RPO factored form. For example the function = 1̅̅̅ 2 4+ 1 3+ 2 3 is RPO, since it can factored into =( 1̅̅̅ 4+ 3)( 1+ 2). This dissertation presents four new algorithms for synthesis of Boolean functions. The first contribution is a synthesis method for read-once functions based on a divide-and-conquer strategy. The second and third contributions are two algorithms for synthesis of DSD functions: a top-down approach that checks if there is an OR, AND or XOR decomposition based on sum-of-products, product-of-sums and exclusive-sum-of-products inputs, respectively; and a method that runs in a bottom-up fashion and is based on Boolean difference and cofactor analysis. The last contribution is a new method to synthesize RPO functions which is based on the analysis of positive and negative transition sets. Results show the efficacy and efficiency of the four proposed methods.
O problema de fatorar e decompor funções Booleanas é Σ-completo 2 para funções gerais. Algoritmos eficientes e exatos podem ser criados para classes de funções existentes como funções read-once, disjoint-support decomposable e read-polarity-once. Uma forma fatorada é chamada de read-once (RO) se cada variável aparece uma única vez. Uma função Booleana é RO se existe uma forma fatorada RO que a representa. Por exemplo, a função representada por = 1 2+ 1 3 4+ 1 3 5 é uma função RO, pois pode ser fatorada em = 1( 2+ 3( 4+ 5)). Uma função Booleana f(X) pode ser decomposta usando funções mais simples g e h de forma que ( )=ℎ( ( 1), 2) sendo X1, X2 ≠ ∅, e X1 ∪ X2 = X. Uma decomposição disjunta de suporte (disjoint-support decomposition – DSD) é um caso especial de decomposição funcional, onde o conjunto de entradas X1 e X2 não compartilham elementos, i.e., X1 ∩ X2 = ∅. Por exemplo, a função = 1 2̅̅̅ 3+ 1 2 3̅̅̅ 4̅̅̅+ 1 2̅̅̅ 4 é DSD, pois existe uma decomposição tal…
Advisors/Committee Members: Reis, Andre Inacio.
Subjects/Keywords: Logic synthesis; Microeletrônica; Funções booleanas; Factoring; Decomposition; Read-once; Disjoint-support decomposition; Read-polarity-once
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APA ·
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APA (6th Edition):
Callegaro, V. (2016). Minimização ótima de classes especiais de funções booleanas. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/148342
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Callegaro, Vinicius. “Minimização ótima de classes especiais de funções booleanas.” 2016. Thesis, Universidade do Rio Grande do Sul. Accessed March 06, 2021.
http://hdl.handle.net/10183/148342.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Callegaro, Vinicius. “Minimização ótima de classes especiais de funções booleanas.” 2016. Web. 06 Mar 2021.
Vancouver:
Callegaro V. Minimização ótima de classes especiais de funções booleanas. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2016. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/10183/148342.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Callegaro V. Minimização ótima de classes especiais de funções booleanas. [Thesis]. Universidade do Rio Grande do Sul; 2016. Available from: http://hdl.handle.net/10183/148342
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
28.
Huang, Ching-Hua.
Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC.
Degree: Master, Computer Science and Engineering, 2014, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344
► In recent years, the popularity of handheld smart devices.In order to the demand of consumer and rapid progress of the technological process; Although the design…
(more)
▼ In recent years, the popularity of handheld smart devices.In order to the demand of consumer and rapid progress of the technological process; Although the design is becoming complex, but the area is still delicate and thin.Todayâs circuit design, its level have been SoC which consist of more than millions
logic gates, so the Electronic Design Automation tools has a indispensable role in the design and verification flow.
Due to the National Science Program, "3D graphics acceleration system" had to chip tape-out. In the front-end process, hardware through the Hardware Description Language to design the sub module-Silicon Intellectual Property; software was developing the Applition Interface and Compiler. Finally, we integrated the ARM7-like CPU and AMBA which were proposed from our laboratory into a system. Since the system integration was a huge task need to considering more, increasing the complexity and performance of verification. Therefore, it was achieved rapid verification by the FPGA Emulation and SystemC, and it's much easier to meet the constraint of time to market.
Unlike the Front-End process, Back-End processes more emphasis on the impact of process technology and the use of electronic design automation tools to assist in the development of validation. This paper mainly discusses the problems faced by the segment of the process, and how to make the chip in the design process can still maintain a certain degree of stability and effectiveness, and finally through the Chip Implementation Center (CIC) and Taiwan Semiconductor Manufatring Company (TSMC) signing downline commission to achieve the target wafer. In August 2011 and February 2014 reached two SoC chip off the assembly line, respectively 3DG ES1.0 SoC and 3DG ES2.0 SoC.
In this Research, the goal is pass the back-end implementation and verification process. The difficulties and challenges encountered in the process will be detailed in this thesis, this experience will give follow-up over who can make more success in the real chip.
Advisors/Committee Members: Yun-Nan Chang (chair), Da-Wei Chang (chair), Ing-Jer Huang (committee member), Chung-Fu Kao (chair), Chung-Ho Chen (chair).
Subjects/Keywords: Chip Tape-out; Logic Synthesis; Syetem-on-Chip; Three-dimensional Graphics; Layout
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APA ·
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APA (6th Edition):
Huang, C. (2014). Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Huang, Ching-Hua. “Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC.” 2014. Thesis, NSYSU. Accessed March 06, 2021.
http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Huang, Ching-Hua. “Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC.” 2014. Web. 06 Mar 2021.
Vancouver:
Huang C. Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Mar 06].
Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Huang C. Chip Implementation and Verification of an OpenGL ES2.0 3D Graphics SoC. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0804114-111344
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Michigan
29.
Oh, Yoonna.
Constructive logic and layout synthesis.
Degree: PhD, Computer science, 2006, University of Michigan
URL: http://hdl.handle.net/2027.42/126529
► This dissertation examines the extension of constructive library-aware logic synthesis to the physical placement stage of integrated circuit design. Constructive logic synthesis differs from traditional…
(more)
▼ This dissertation examines the extension of constructive library-aware
logic synthesis to the physical placement stage of integrated circuit design. Constructive
logic synthesis differs from traditional
synthesis approaches in that it builds a circuit netlist incrementally starting from the primary inputs and proceeding towards the primary outputs. In each iteration of this procedure, the semantic structure of the unsynthesized
logic functions is utilized to identify and extract a small subcircuit that consists of library primitives reflecting that structure. In particular, functional symmetry is used to obtain support-reducing decompositions that lead to high-quality implementations in terms of both area and delay. Effectively, the algorithm interleaves the steps of technology-independent decomposition and technology-dependent mapping into library cells in a way that mitigates its greedy nature. Conjecturing that the addition of a placement step to this methodology would further improve
synthesis quality we developed the COLOSSEUM system which synthesizes circuits by incremental decomposition, mapping, and placement. We describe the algorithms used in COLOSSEUM and analyze the quality of the designs it generates under a variety of options for decomposition and placement. The empirical results we obtained, however, suggest that adding a placement step to constructive
synthesis produces no noticeable improvement in design quality. This strongly suggests that our original conjecture is false, and we examine possible reasons for such a negative result.
Advisors/Committee Members: Sakallah, Karem A. (advisor).
Subjects/Keywords: Constructive Logic; Layout; Synthesis; Technology Mapping
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APA ·
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APA (6th Edition):
Oh, Y. (2006). Constructive logic and layout synthesis. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/126529
Chicago Manual of Style (16th Edition):
Oh, Yoonna. “Constructive logic and layout synthesis.” 2006. Doctoral Dissertation, University of Michigan. Accessed March 06, 2021.
http://hdl.handle.net/2027.42/126529.
MLA Handbook (7th Edition):
Oh, Yoonna. “Constructive logic and layout synthesis.” 2006. Web. 06 Mar 2021.
Vancouver:
Oh Y. Constructive logic and layout synthesis. [Internet] [Doctoral dissertation]. University of Michigan; 2006. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/2027.42/126529.
Council of Science Editors:
Oh Y. Constructive logic and layout synthesis. [Doctoral Dissertation]. University of Michigan; 2006. Available from: http://hdl.handle.net/2027.42/126529
University of Waterloo
30.
Ravishankar, Chirag.
Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs.
Degree: 2012, University of Waterloo
URL: http://hdl.handle.net/10012/6644
► Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times…
(more)
▼ Guarded evaluation is a power reduction technique that involves
identifying sub-circuits (within a larger circuit) whose inputs can be
held constant (guarded) at specific times during circuit operation,
thereby reducing switching activity and lowering dynamic power. The
concept is rooted in the property that under certain conditions, some
signals within digital designs are not "observable" at design
outputs, making the circuitry that generates such signals a candidate
for guarding.
Guarded evaluation has been demonstrated successfully
for custom ASICs; in this work, we apply the technique to FPGAs. In
ASICs, guarded evaluation entails adding additional hardware to the
design, increasing silicon area and cost. Here, we apply the technique
in a way that imposes minimal area overhead by leveraging existing
unused circuitry within the FPGA. The LUT functionality is modified
to incorporate the guards and reduce toggle rates.
The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's
inputs can be held constant without impacting the larger
circuit's functional correctness. We propose a simple solution to
this problem based on discovering gating inputs using "non-inverting paths"
and trimming inputs using "partial non-inverting paths" in the
circuit's AND-Inverter graph representation.
Experimental results show that guarded evaluation can reduce switching activity by
as much as 32% for FPGAs with 6-LUT architectures and 25% for 4-LUT architectures, on
average, and can reduce power consumption in the FPGA interconnect by
29% for 6-LUTs and 27% for 4-LUTs. A clustered architecture with four LUTs to a cluster
and ten LUTs to a cluster produced the best power reduction results.
We implement guarded evaluation at various stages of the FPGA CAD flow and analyze the reductions. We implement
the algorithm as post technology mapping, post packing and post placement optimizations. Guarded Evaluation
as a post technology mapping algorithm inserted the most number of guards and hence achieved the highest activity
and interconnect reduction. However, guarding signals come with a cost of increased fanout and stress on routing
resources. Packing and placement provides the algorithm with additional information of the circuit which is leveraged
to insert high quality guards with minimal impact on routing. Experimental results show that post-packing
and post-placement methods have comparable reductions to post-mapping with considerably lesser impact on the critical
path delay and routability of the circuit.
Subjects/Keywords: Field-programmable gate arrays; Power optimization; low-power design; logic synthesis; technology mapping
Record Details
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Cite
Share »
Record Details
Similar Records
Cite
« Share
❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Ravishankar, C. (2012). Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/6644
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Ravishankar, Chirag. “Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs.” 2012. Thesis, University of Waterloo. Accessed March 06, 2021.
http://hdl.handle.net/10012/6644.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Ravishankar, Chirag. “Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs.” 2012. Web. 06 Mar 2021.
Vancouver:
Ravishankar C. Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs. [Internet] [Thesis]. University of Waterloo; 2012. [cited 2021 Mar 06].
Available from: http://hdl.handle.net/10012/6644.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Ravishankar C. Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs. [Thesis]. University of Waterloo; 2012. Available from: http://hdl.handle.net/10012/6644
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
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Open Access Theses and Dissertations
