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You searched for subject:(Line Associative Registers). Showing records 1 – 3 of 3 total matches.

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University of Kentucky

1. Ponnala, Kalyan. DESIGN AND IMPLEMENTATION OF THE INSTRUCTION SET ARCHITECTURE FOR DATA LARS.

Degree: 2010, University of Kentucky

The ideal memory system assumed by most programmers is one which has high capacity, yet allows any word to be accessed instantaneously. To make the hardware approximate this performance, an increasingly complex memory hierarchy, using caches and techniques like automatic prefetch, has evolved. However, as the gap between processor and memory speeds continues to widen, these programmer-visible mechanisms are becoming inadequate. Part of the recent increase in processor performance has been due to the introduction of programmer/compiler-visible SWAR (SIMD Within A Register) parallel processing on increasingly wide DATA LARs (Line Associative Registers) as a way to both improve data access speed and increase efficiency of SWAR processing. Although the base concept of DATA LARs predates this thesis, this thesis presents the first instruction set architecture specification complete enough to allow construction of a detailed prototype hardware design. This design was implemented and tested using a hardware simulator.

Subjects/Keywords: Line Associative Registers; DATA LARs; SIMD Within a Register (SWAR); Cache Registers (CRegs); Associativity; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ponnala, K. (2010). DESIGN AND IMPLEMENTATION OF THE INSTRUCTION SET ARCHITECTURE FOR DATA LARS. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/gradschool_theses/58

Chicago Manual of Style (16th Edition):

Ponnala, Kalyan. “DESIGN AND IMPLEMENTATION OF THE INSTRUCTION SET ARCHITECTURE FOR DATA LARS.” 2010. Masters Thesis, University of Kentucky. Accessed July 18, 2019. http://uknowledge.uky.edu/gradschool_theses/58.

MLA Handbook (7th Edition):

Ponnala, Kalyan. “DESIGN AND IMPLEMENTATION OF THE INSTRUCTION SET ARCHITECTURE FOR DATA LARS.” 2010. Web. 18 Jul 2019.

Vancouver:

Ponnala K. DESIGN AND IMPLEMENTATION OF THE INSTRUCTION SET ARCHITECTURE FOR DATA LARS. [Internet] [Masters thesis]. University of Kentucky; 2010. [cited 2019 Jul 18]. Available from: http://uknowledge.uky.edu/gradschool_theses/58.

Council of Science Editors:

Ponnala K. DESIGN AND IMPLEMENTATION OF THE INSTRUCTION SET ARCHITECTURE FOR DATA LARS. [Masters Thesis]. University of Kentucky; 2010. Available from: http://uknowledge.uky.edu/gradschool_theses/58


University of Kentucky

2. Sparks, Matthew A. A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE.

Degree: 2013, University of Kentucky

Modern processor architectures suffer from an ever increasing gap between processor and memory performance. The current memory-register model attempts to hide this gap by a system of cache memory. Line Associative Registers(LARs) are proposed as a new system to avoid the memory gap by pre-fetching and associative updating of both instructions and data. This thesis presents a fully LAR-based architecture, targeting a previously developed instruction set architecture. This architecture features an execution pipeline supporting SWAR operations, and a memory system supporting the associative behavior of LARs and lazy writeback to memory.

Subjects/Keywords: Line Associative Registers; Hardware Description Language; Memory Caching; Ambiguous Alias; Computer Arithmetic; Computer and Systems Architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sparks, M. A. (2013). A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/ece_etds/26

Chicago Manual of Style (16th Edition):

Sparks, Matthew A. “A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE.” 2013. Masters Thesis, University of Kentucky. Accessed July 18, 2019. http://uknowledge.uky.edu/ece_etds/26.

MLA Handbook (7th Edition):

Sparks, Matthew A. “A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE.” 2013. Web. 18 Jul 2019.

Vancouver:

Sparks MA. A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE. [Internet] [Masters thesis]. University of Kentucky; 2013. [cited 2019 Jul 18]. Available from: http://uknowledge.uky.edu/ece_etds/26.

Council of Science Editors:

Sparks MA. A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE. [Masters Thesis]. University of Kentucky; 2013. Available from: http://uknowledge.uky.edu/ece_etds/26


University of Kentucky

3. Lim, Nien Yi. SEPARATING INSTRUCTION FETCHES FROM MEMORY ACCESSES : ILAR (INSTRUCTION LINE ASSOCIATIVE REGISTERS).

Degree: 2009, University of Kentucky

Due to the growing mismatch between processor performance and memory latency, many dynamic mechanisms which are “invisible” to the user have been proposed: for example, trace caches and automatic pre-fetch units. However, these dynamic mechanisms have become inadequate due to implicit memory accesses that have become so expensive. On the other hand, compiler-visible mechanisms like SWAR (SIMD Within A Register) and LARs (Line Associative Registers) are potentially more effective at improving data access performance. This thesis investigates applying the same ideas to improve instruction access. ILAR (Instruction LARs) store instructions in wide registers. Instruction blocks are explicitly loaded into ILAR, using block compression to enhance memory bandwidth. The control flow of the program then refers to instructions directly by their position within an ILAR, rather than by lengthy memory addresses. Because instructions are accessed directly from within registers, there is no implicit instruction fetch from memory. This thesis proposes an instruction set architecture for ILAR, investigates a mechanism to load ILAR using the best available block compression algorithm and also develop hardware descriptions for both ILAR and a conventional memory cache model so that performance comparisons could be made on the instruction fetch stage.

Subjects/Keywords: Memory latency|CRegs (Cache Registers)|SWAR (SIMD Within a Register)|LARs (Line Associative Registers)|Searching block compression algorithm using a GA (Genetic algorithm); Electrical and Computer Engineering; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lim, N. Y. (2009). SEPARATING INSTRUCTION FETCHES FROM MEMORY ACCESSES : ILAR (INSTRUCTION LINE ASSOCIATIVE REGISTERS). (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/gradschool_theses/625

Chicago Manual of Style (16th Edition):

Lim, Nien Yi. “SEPARATING INSTRUCTION FETCHES FROM MEMORY ACCESSES : ILAR (INSTRUCTION LINE ASSOCIATIVE REGISTERS).” 2009. Masters Thesis, University of Kentucky. Accessed July 18, 2019. http://uknowledge.uky.edu/gradschool_theses/625.

MLA Handbook (7th Edition):

Lim, Nien Yi. “SEPARATING INSTRUCTION FETCHES FROM MEMORY ACCESSES : ILAR (INSTRUCTION LINE ASSOCIATIVE REGISTERS).” 2009. Web. 18 Jul 2019.

Vancouver:

Lim NY. SEPARATING INSTRUCTION FETCHES FROM MEMORY ACCESSES : ILAR (INSTRUCTION LINE ASSOCIATIVE REGISTERS). [Internet] [Masters thesis]. University of Kentucky; 2009. [cited 2019 Jul 18]. Available from: http://uknowledge.uky.edu/gradschool_theses/625.

Council of Science Editors:

Lim NY. SEPARATING INSTRUCTION FETCHES FROM MEMORY ACCESSES : ILAR (INSTRUCTION LINE ASSOCIATIVE REGISTERS). [Masters Thesis]. University of Kentucky; 2009. Available from: http://uknowledge.uky.edu/gradschool_theses/625

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