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You searched for subject:(Layout design through error aware transistor positioning dual interlocked storage cell LEAP DICE ). Showing records 1 – 30 of 114406 total matches.

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1. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

design through Error-Aware transistor Positioning LFSR Linear Feedback Shift Register LHL… …Resilience CPU Central Processing Unit DAC Design Automation Conference DICE Dual Interlocked… …Storage Cell DIVA Dynamic Implementation Verification Architecture, a faulttolerant CPU… …standards JTAG Joint Test Action Group, develops on-chip instrumentation standards LEAP Layout… …Error Detecting Cores through Low-Cost Modulo-3 Shadow Datapaths” [1], “Hybrid Quick… 

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APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 03, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 03 Mar 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294


Vanderbilt University

2. Amusan, Oluwole Ayodele. Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies.

Degree: PhD, Electrical Engineering, 2009, Vanderbilt University

 Sub-100 nm technologies are more vulnerable than older technologies to single event effects (SEE) due to Moore's Law scaling trend. The increased SEE vulnerability has… (more)

Subjects/Keywords: nodal spacing; single event circuit characterization; soft error cross-section; pulse-widths; guard-bands; Dual Interlocked Cell (DICE) latch; Radiation hardening; Space environment; charge sharing mitigation; heavy-ion; guard-rings; Metal oxide semiconductors Complementary  – Effect of radiation on

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APA (6th Edition):

Amusan, O. A. (2009). Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10577

Chicago Manual of Style (16th Edition):

Amusan, Oluwole Ayodele. “Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies.” 2009. Doctoral Dissertation, Vanderbilt University. Accessed March 03, 2021. http://hdl.handle.net/1803/10577.

MLA Handbook (7th Edition):

Amusan, Oluwole Ayodele. “Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies.” 2009. Web. 03 Mar 2021.

Vancouver:

Amusan OA. Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2009. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/1803/10577.

Council of Science Editors:

Amusan OA. Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies. [Doctoral Dissertation]. Vanderbilt University; 2009. Available from: http://hdl.handle.net/1803/10577


Universidade do Rio Grande do Sul

3. Guex, Jerson Paulo. Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo.

Degree: 2013, Universidade do Rio Grande do Sul

Este trabalho visa explorar técnicas de projeto de células que possibilitem a minimização dos efeitos da variabilidade de processo sobre o comportamento elétrico dos circuitos… (more)

Subjects/Keywords: Microeletrônica; Cell layout; Process variability; Vlsi; Transistores; DFM; Transistor folding; Microelectronics

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APA (6th Edition):

Guex, J. P. (2013). Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/78529

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Guex, Jerson Paulo. “Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo.” 2013. Thesis, Universidade do Rio Grande do Sul. Accessed March 03, 2021. http://hdl.handle.net/10183/78529.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Guex, Jerson Paulo. “Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo.” 2013. Web. 03 Mar 2021.

Vancouver:

Guex JP. Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2013. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/10183/78529.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guex JP. Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo. [Thesis]. Universidade do Rio Grande do Sul; 2013. Available from: http://hdl.handle.net/10183/78529

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

4. Brito, Eliseu Silveira. Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo.

Degree: 2010, Universidade do Rio Grande do Sul

A constante evolução dos sistemas produtivos amplia a importância dada aos projetos de instalações industriais, onde os sistemas celulares possuem uma importância especial, pois tem… (more)

Subjects/Keywords: Automação industrial; Cell layout; Layout industrial; Group technology; Usinagem; Manufacturing automation; Layout design

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APA (6th Edition):

Brito, E. S. (2010). Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/29421

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Brito, Eliseu Silveira. “Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed March 03, 2021. http://hdl.handle.net/10183/29421.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Brito, Eliseu Silveira. “Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo.” 2010. Web. 03 Mar 2021.

Vancouver:

Brito ES. Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/10183/29421.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Brito ES. Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/29421

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

5. Shiyanovskii, Yuriy. Reliability of SRAMs and 3D TSV ICS: Design Protection from Soft Errors and 3D Thermal Modeling.

Degree: PhD, EECS - Computer Engineering, 2012, Case Western Reserve University School of Graduate Studies

  With CMOS technology scaling into deep nanoscale level, reliability issues have emerged as key concerns for SRAM memories. The reliability of SRAM memories is… (more)

Subjects/Keywords: Computer Engineering; Electrical Engineering; Soft Error; SRAMs; Hardening; Reliability; Memory Cell Design; 3D ICs; TSV; Through-Silicon Vias; Thermal Modeling; Thermal Management

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APA (6th Edition):

Shiyanovskii, Y. (2012). Reliability of SRAMs and 3D TSV ICS: Design Protection from Soft Errors and 3D Thermal Modeling. (Doctoral Dissertation). Case Western Reserve University School of Graduate Studies. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1334891947

Chicago Manual of Style (16th Edition):

Shiyanovskii, Yuriy. “Reliability of SRAMs and 3D TSV ICS: Design Protection from Soft Errors and 3D Thermal Modeling.” 2012. Doctoral Dissertation, Case Western Reserve University School of Graduate Studies. Accessed March 03, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=case1334891947.

MLA Handbook (7th Edition):

Shiyanovskii, Yuriy. “Reliability of SRAMs and 3D TSV ICS: Design Protection from Soft Errors and 3D Thermal Modeling.” 2012. Web. 03 Mar 2021.

Vancouver:

Shiyanovskii Y. Reliability of SRAMs and 3D TSV ICS: Design Protection from Soft Errors and 3D Thermal Modeling. [Internet] [Doctoral dissertation]. Case Western Reserve University School of Graduate Studies; 2012. [cited 2021 Mar 03]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1334891947.

Council of Science Editors:

Shiyanovskii Y. Reliability of SRAMs and 3D TSV ICS: Design Protection from Soft Errors and 3D Thermal Modeling. [Doctoral Dissertation]. Case Western Reserve University School of Graduate Studies; 2012. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1334891947

6. -5314-7669. Standard cell optimization and physical design in advanced technology nodes.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin

 Integrated circuits (ICs) are at the heart of modern electronics, which rely heavily on the state-of-the-art semiconductor manufacturing technology. The key to pushing forward semiconductor… (more)

Subjects/Keywords: Standard cell; Physical design; Cell optimization; Integrated circuits; Semiconductor technology; Miniaturization; Unidirectional layout design

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APA (6th Edition):

-5314-7669. (2017). Standard cell optimization and physical design in advanced technology nodes. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/47464

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-5314-7669. “Standard cell optimization and physical design in advanced technology nodes.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed March 03, 2021. http://hdl.handle.net/2152/47464.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-5314-7669. “Standard cell optimization and physical design in advanced technology nodes.” 2017. Web. 03 Mar 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-5314-7669. Standard cell optimization and physical design in advanced technology nodes. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/2152/47464.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-5314-7669. Standard cell optimization and physical design in advanced technology nodes. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/47464

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Delft University of Technology

7. Malagi, Santosh (author). Library Characterization for Cell-Aware Test.

Degree: 2018, Delft University of Technology

Due to their large number of high-precision, defect-prone manufacturing steps, integrated circuits (ICs) are susceptible to manufacturing defects and hence need to undergo electrical tests… (more)

Subjects/Keywords: Cell-Aware Test; Library Characterization; Design for Test

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APA (6th Edition):

Malagi, S. (. (2018). Library Characterization for Cell-Aware Test. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:266ab254-3895-4295-b557-eec87eb9c811

Chicago Manual of Style (16th Edition):

Malagi, Santosh (author). “Library Characterization for Cell-Aware Test.” 2018. Masters Thesis, Delft University of Technology. Accessed March 03, 2021. http://resolver.tudelft.nl/uuid:266ab254-3895-4295-b557-eec87eb9c811.

MLA Handbook (7th Edition):

Malagi, Santosh (author). “Library Characterization for Cell-Aware Test.” 2018. Web. 03 Mar 2021.

Vancouver:

Malagi S(. Library Characterization for Cell-Aware Test. [Internet] [Masters thesis]. Delft University of Technology; 2018. [cited 2021 Mar 03]. Available from: http://resolver.tudelft.nl/uuid:266ab254-3895-4295-b557-eec87eb9c811.

Council of Science Editors:

Malagi S(. Library Characterization for Cell-Aware Test. [Masters Thesis]. Delft University of Technology; 2018. Available from: http://resolver.tudelft.nl/uuid:266ab254-3895-4295-b557-eec87eb9c811


Penn State University

8. Patki, Mayuresh Premanand. A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network.

Degree: 2017, Penn State University

 With several advancements in medical science being carried out over the past few decades, there has been a constant need to process information artificially, the… (more)

Subjects/Keywords: Artificial Intelligence; Artificial Neural Networks; Metal Oxide Semiconductor Implementation Service; Integrated Circuit; CMOS; Very Large Scale Integration; McCulloch and Pitts neuron; Perceptron; Backpropagation Algorithm; Synapses; Gilbert Multiplier Cell; Activation Function Circuit; Floating Gate; Single Transistor Learning Synapse; Post-Synaptic Current; Spike Timing Dependent Plasticity; Long Term Potentiation; Long Term Depression; Static Random Access Memory; Memristor; Mean Square Error; Cadence OrCAD Capture; Cadence PSpice A/D; Electric VLSI Design System; Network Consistency Check; Layout Vs Schematic Check; XOR Classification Problem; MATLAB; Time Domain; Instantaneous Power Dissipation; Loading; Learning Rate; Mixed Signal; System on Chip; Field Programmable Gate Arrays

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APA (6th Edition):

Patki, M. P. (2017). A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/13800mfp5198

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Patki, Mayuresh Premanand. “A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network.” 2017. Thesis, Penn State University. Accessed March 03, 2021. https://submit-etda.libraries.psu.edu/catalog/13800mfp5198.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Patki, Mayuresh Premanand. “A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network.” 2017. Web. 03 Mar 2021.

Vancouver:

Patki MP. A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network. [Internet] [Thesis]. Penn State University; 2017. [cited 2021 Mar 03]. Available from: https://submit-etda.libraries.psu.edu/catalog/13800mfp5198.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Patki MP. A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network. [Thesis]. Penn State University; 2017. Available from: https://submit-etda.libraries.psu.edu/catalog/13800mfp5198

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

9. RANJAN, MUKESH. AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS.

Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati

 A key task in the automated design of analog/RF circuits is circuit sizing, a process that involves assigning numerical values to unknown circuit parameters of… (more)

Subjects/Keywords: Computer Science; Analog Circuit Synthesis; Symbolic Analysis; Layout-Aware; Parasitic-Aware; Analog Design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

RANJAN, M. (2005). AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496

Chicago Manual of Style (16th Edition):

RANJAN, MUKESH. “AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed March 03, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496.

MLA Handbook (7th Edition):

RANJAN, MUKESH. “AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS.” 2005. Web. 03 Mar 2021.

Vancouver:

RANJAN M. AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2021 Mar 03]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496.

Council of Science Editors:

RANJAN M. AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496


Vanderbilt University

10. Kauppila, Jeffrey Scott. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.

Degree: PhD, Electrical Engineering, 2015, Vanderbilt University

 The development of integrated circuits intended for use in transient radiation environments must account for the impact of the environment on the operation of the… (more)

Subjects/Keywords: CAD Tools; Semiconductor Device Modeling; Process Design Kit; Gummel Poon; BSIMSOI; MEXTRAM; Radiation Modeling; TCAD; BSIM4; Bias-Dependent Modeling; Dose Rate Effects; Compact Models; Single Event Effects; Compact Model; BJT; MOSFET; Layout-Aware Modeling; Layout-Aware Analysis; SPICE; Layout; Radiation Effects; Circuit Simulation; Radiation-Enabled Model; Single-Event Transient; Single-Event Upset; Charge Sharing; Computational Modeling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kauppila, J. S. (2015). Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10793

Chicago Manual of Style (16th Edition):

Kauppila, Jeffrey Scott. “Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed March 03, 2021. http://hdl.handle.net/1803/10793.

MLA Handbook (7th Edition):

Kauppila, Jeffrey Scott. “Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.” 2015. Web. 03 Mar 2021.

Vancouver:

Kauppila JS. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/1803/10793.

Council of Science Editors:

Kauppila JS. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/10793

11. Björkman, Hanna. Designing a board game rulebook – It is harder than you would think.

Degree: Faculty of Science & Engineering, 2019, Linköping UniversityLinköping University

  This thesis has explored how to create a board game rulebook, for the board game Curators, in order to facilitate learning the rules as… (more)

Subjects/Keywords: graphic design; board game; tabletop game; rulebook; rule book; instruction manual; layout; typography; research through design; color; gestalt principles; teaching; Other Engineering and Technologies not elsewhere specified; Övrig annan teknik

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APA (6th Edition):

Björkman, H. (2019). Designing a board game rulebook – It is harder than you would think. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-160510

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Björkman, Hanna. “Designing a board game rulebook – It is harder than you would think.” 2019. Thesis, Linköping UniversityLinköping University. Accessed March 03, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-160510.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Björkman, Hanna. “Designing a board game rulebook – It is harder than you would think.” 2019. Web. 03 Mar 2021.

Vancouver:

Björkman H. Designing a board game rulebook – It is harder than you would think. [Internet] [Thesis]. Linköping UniversityLinköping University; 2019. [cited 2021 Mar 03]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-160510.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Björkman H. Designing a board game rulebook – It is harder than you would think. [Thesis]. Linköping UniversityLinköping University; 2019. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-160510

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of South Florida

12. Krishnan, Vyas. Temperature and Interconnect Aware Unified Physical and High Level Synthesis.

Degree: 2008, University of South Florida

 Aggressive scaling of nanoscale CMOS integrated circuits has created significant design challenges arising from increasing power densities, thermal concerns, and rising wire delays. The main… (more)

Subjects/Keywords: behavioral synthesis; power-aware design; thermal analysis; interconnectcentric design; stochastic interconnect estimation; layout-aware synthesis; American Studies; Arts and Humanities

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APA (6th Edition):

Krishnan, V. (2008). Temperature and Interconnect Aware Unified Physical and High Level Synthesis. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/347

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Krishnan, Vyas. “Temperature and Interconnect Aware Unified Physical and High Level Synthesis.” 2008. Thesis, University of South Florida. Accessed March 03, 2021. https://scholarcommons.usf.edu/etd/347.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Krishnan, Vyas. “Temperature and Interconnect Aware Unified Physical and High Level Synthesis.” 2008. Web. 03 Mar 2021.

Vancouver:

Krishnan V. Temperature and Interconnect Aware Unified Physical and High Level Synthesis. [Internet] [Thesis]. University of South Florida; 2008. [cited 2021 Mar 03]. Available from: https://scholarcommons.usf.edu/etd/347.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Krishnan V. Temperature and Interconnect Aware Unified Physical and High Level Synthesis. [Thesis]. University of South Florida; 2008. Available from: https://scholarcommons.usf.edu/etd/347

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. FOLKESSON, JOSEFINE. Butikskommunikation och layout.

Degree: Swedish School of Textiles, 2014, University of Borås

Syftet med detta examensarbete är att med hjälp av empiriskt material och tidigare forskning undersöka hur en butikskedja inom modebranschen använder sin butikslayout och… (more)

Subjects/Keywords: Layout; butikskommunikation; exponering; Design; Design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

FOLKESSON, J. (2014). Butikskommunikation och layout. (Thesis). University of Borås. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-18010

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

FOLKESSON, JOSEFINE. “Butikskommunikation och layout.” 2014. Thesis, University of Borås. Accessed March 03, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-18010.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

FOLKESSON, JOSEFINE. “Butikskommunikation och layout.” 2014. Web. 03 Mar 2021.

Vancouver:

FOLKESSON J. Butikskommunikation och layout. [Internet] [Thesis]. University of Borås; 2014. [cited 2021 Mar 03]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-18010.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

FOLKESSON J. Butikskommunikation och layout. [Thesis]. University of Borås; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-18010

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Otago

14. Galland, William. Changing layout at Cableways - A project that investigates the process invoked-with changing Layout in a small- New Zealand business.

Degree: 2011, University of Otago

 This project is concerned with the process of initiating layout changes in a New Zealand business. The business that is being investigated, Cableways, operates a… (more)

Subjects/Keywords: Cableways; layout; layout primitive; appropriate design

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APA (6th Edition):

Galland, W. (2011). Changing layout at Cableways - A project that investigates the process invoked-with changing Layout in a small- New Zealand business. (Masters Thesis). University of Otago. Retrieved from http://hdl.handle.net/10523/1375

Chicago Manual of Style (16th Edition):

Galland, William. “Changing layout at Cableways - A project that investigates the process invoked-with changing Layout in a small- New Zealand business. ” 2011. Masters Thesis, University of Otago. Accessed March 03, 2021. http://hdl.handle.net/10523/1375.

MLA Handbook (7th Edition):

Galland, William. “Changing layout at Cableways - A project that investigates the process invoked-with changing Layout in a small- New Zealand business. ” 2011. Web. 03 Mar 2021.

Vancouver:

Galland W. Changing layout at Cableways - A project that investigates the process invoked-with changing Layout in a small- New Zealand business. [Internet] [Masters thesis]. University of Otago; 2011. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/10523/1375.

Council of Science Editors:

Galland W. Changing layout at Cableways - A project that investigates the process invoked-with changing Layout in a small- New Zealand business. [Masters Thesis]. University of Otago; 2011. Available from: http://hdl.handle.net/10523/1375


University of Michigan

15. Chang, Kai-hui. Functional design error diagnosis, correction and layout repair of digital circuits.

Degree: PhD, Electrical engineering, 2007, University of Michigan

 The dramatic increase in design complexity of modern circuits challenges our ability to verify their functional correctness. Therefore, circuits are often taped-out with functional errors,… (more)

Subjects/Keywords: Debugging; Design; Digital; Error Correction; Error Diagnosis; Functional; Integrated Circuits; Layout Repair; Verification

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, K. (2007). Functional design error diagnosis, correction and layout repair of digital circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/126892

Chicago Manual of Style (16th Edition):

Chang, Kai-hui. “Functional design error diagnosis, correction and layout repair of digital circuits.” 2007. Doctoral Dissertation, University of Michigan. Accessed March 03, 2021. http://hdl.handle.net/2027.42/126892.

MLA Handbook (7th Edition):

Chang, Kai-hui. “Functional design error diagnosis, correction and layout repair of digital circuits.” 2007. Web. 03 Mar 2021.

Vancouver:

Chang K. Functional design error diagnosis, correction and layout repair of digital circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2007. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/2027.42/126892.

Council of Science Editors:

Chang K. Functional design error diagnosis, correction and layout repair of digital circuits. [Doctoral Dissertation]. University of Michigan; 2007. Available from: http://hdl.handle.net/2027.42/126892


Oklahoma State University

16. De, Kanishka. Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent.

Degree: Electrical Engineering, 2014, Oklahoma State University

 This work presents the design methodologies, considerations and practical implementation techniques of a sub-threshold/ moderate inversion variability aware Transmission Gate based digital cell library. The… (more)

Subjects/Keywords: robust cell library; sub-threshold/ moderate inversion; t-gate and cmos topology; ultra low power; variability aware design; vlsi/ circuit design

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APA (6th Edition):

De, K. (2014). Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/14796

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

De, Kanishka. “Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent.” 2014. Thesis, Oklahoma State University. Accessed March 03, 2021. http://hdl.handle.net/11244/14796.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

De, Kanishka. “Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent.” 2014. Web. 03 Mar 2021.

Vancouver:

De K. Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent. [Internet] [Thesis]. Oklahoma State University; 2014. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/11244/14796.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

De K. Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent. [Thesis]. Oklahoma State University; 2014. Available from: http://hdl.handle.net/11244/14796

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. Tsai, Ming-Yu. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.

Degree: PhD, Computer Science and Engineering, 2009, NSYSU

 The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic… (more)

Subjects/Keywords: 3D Graphics Processors; Arithmetic Units; Standard Cell Library; ASIC Cell-Based Design Flow; Logic Synthesizer; Pass-Transistor-Logic (PTL); CMOS logic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tsai, M. (2009). An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529

Chicago Manual of Style (16th Edition):

Tsai, Ming-Yu. “An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.” 2009. Doctoral Dissertation, NSYSU. Accessed March 03, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529.

MLA Handbook (7th Edition):

Tsai, Ming-Yu. “An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.” 2009. Web. 03 Mar 2021.

Vancouver:

Tsai M. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. [Internet] [Doctoral dissertation]. NSYSU; 2009. [cited 2021 Mar 03]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529.

Council of Science Editors:

Tsai M. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. [Doctoral Dissertation]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529


University of Illinois – Urbana-Champaign

18. Wang, Curtis Yilin. High-speed characterizations of single quantum-well transistor laser.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 The transistor laser (TL) is a unique three-terminal semiconductor laser device that possesses qualities and functionalities that cannot be achieved by diode lasers alone. In… (more)

Subjects/Keywords: Transistor Laser; Bit Error Ration Testing

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APA (6th Edition):

Wang, C. Y. (2015). High-speed characterizations of single quantum-well transistor laser. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89158

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Curtis Yilin. “High-speed characterizations of single quantum-well transistor laser.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed March 03, 2021. http://hdl.handle.net/2142/89158.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Curtis Yilin. “High-speed characterizations of single quantum-well transistor laser.” 2015. Web. 03 Mar 2021.

Vancouver:

Wang CY. High-speed characterizations of single quantum-well transistor laser. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/2142/89158.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang CY. High-speed characterizations of single quantum-well transistor laser. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89158

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Ericson, Jessica. Har den digitala pizzamenyn en genomtänkt stil? : En analys av lågprispizzeriors design av menyer.

Degree: Information Systems, 2020, Dalarna University

Det finns studier som anger rekommendationer för att designa en väl utformad restaurangmeny. Syftet med rapporten är att undersöka om pizzeriapersonal och formgivare designar… (more)

Subjects/Keywords: Branding; brand identity; contrasts; design; gestalt laws; graphic elements; icons; images; layout; pizzeria; positioning; typography; Bilder; dekorelement; design; gestaltlagar; ikoner; kontraster; layout; meny; pizzeria; positionering; typografi; varumärke; varumärkesidentitet.; Information Systems; Systemvetenskap, informationssystem och informatik

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APA (6th Edition):

Ericson, J. (2020). Har den digitala pizzamenyn en genomtänkt stil? : En analys av lågprispizzeriors design av menyer. (Thesis). Dalarna University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:du-34252

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ericson, Jessica. “Har den digitala pizzamenyn en genomtänkt stil? : En analys av lågprispizzeriors design av menyer.” 2020. Thesis, Dalarna University. Accessed March 03, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:du-34252.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ericson, Jessica. “Har den digitala pizzamenyn en genomtänkt stil? : En analys av lågprispizzeriors design av menyer.” 2020. Web. 03 Mar 2021.

Vancouver:

Ericson J. Har den digitala pizzamenyn en genomtänkt stil? : En analys av lågprispizzeriors design av menyer. [Internet] [Thesis]. Dalarna University; 2020. [cited 2021 Mar 03]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:du-34252.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ericson J. Har den digitala pizzamenyn en genomtänkt stil? : En analys av lågprispizzeriors design av menyer. [Thesis]. Dalarna University; 2020. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:du-34252

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Loughborough University

20. Carreira, Joao F. M. Error resilience and concealment techniques for high-efficiency video coding.

Degree: PhD, 2018, Loughborough University

 This thesis investigates the problem of robust coding and error concealment in High Efficiency Video Coding (HEVC). After a review of the current state of… (more)

Subjects/Keywords: HEVC; Error resilience; Error concealment; Reference frame selection; Concealment-aware resilience

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Carreira, J. F. M. (2018). Error resilience and concealment techniques for high-efficiency video coding. (Doctoral Dissertation). Loughborough University. Retrieved from http://hdl.handle.net/2134/36613

Chicago Manual of Style (16th Edition):

Carreira, Joao F M. “Error resilience and concealment techniques for high-efficiency video coding.” 2018. Doctoral Dissertation, Loughborough University. Accessed March 03, 2021. http://hdl.handle.net/2134/36613.

MLA Handbook (7th Edition):

Carreira, Joao F M. “Error resilience and concealment techniques for high-efficiency video coding.” 2018. Web. 03 Mar 2021.

Vancouver:

Carreira JFM. Error resilience and concealment techniques for high-efficiency video coding. [Internet] [Doctoral dissertation]. Loughborough University; 2018. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/2134/36613.

Council of Science Editors:

Carreira JFM. Error resilience and concealment techniques for high-efficiency video coding. [Doctoral Dissertation]. Loughborough University; 2018. Available from: http://hdl.handle.net/2134/36613


NSYSU

21. Hsu, Ting-pi. Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density.

Degree: Master, Electrical Engineering, 2017, NSYSU

 In this thesis, we propose a vertical channel non-classical CMOS (VNCCMOS) with low power dissipation and high integration density. Junctionless transistor and punch through transistor(more)

Subjects/Keywords: CMOS; punch through transistor; junctionless transistor; high integration density; low power dissipation; vertical channel

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APA (6th Edition):

Hsu, T. (2017). Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154234

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Ting-pi. “Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density.” 2017. Thesis, NSYSU. Accessed March 03, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154234.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Ting-pi. “Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density.” 2017. Web. 03 Mar 2021.

Vancouver:

Hsu T. Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Mar 03]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154234.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu T. Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154234

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

22. Svorad, Adam. Audio zesilovač ve třídě D pro laboratorní výuku: Class D audio amplifier for laboratory measurements.

Degree: 2018, Brno University of Technology

 Bachelor’s thesis delves into a field of Class-D audio amplifiers. Keystone part of the work summarizes theoretical knowledge focused on measuring techniques of lowfrequency amplifiers… (more)

Subjects/Keywords: Meranie parametrov audio zosilňovačov; triedy zosilňovačov; zosilňovač v triede D; návrh dolnej priepusti; ochranné obvody proti shoot-through efektu; návrh DPS; Audio amplifier performance measurements; power classes; Class-D amplifier; low-pass filter design; shoot-through protection circuits; PCB layout

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APA (6th Edition):

Svorad, A. (2018). Audio zesilovač ve třídě D pro laboratorní výuku: Class D audio amplifier for laboratory measurements. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/81763

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Svorad, Adam. “Audio zesilovač ve třídě D pro laboratorní výuku: Class D audio amplifier for laboratory measurements.” 2018. Thesis, Brno University of Technology. Accessed March 03, 2021. http://hdl.handle.net/11012/81763.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Svorad, Adam. “Audio zesilovač ve třídě D pro laboratorní výuku: Class D audio amplifier for laboratory measurements.” 2018. Web. 03 Mar 2021.

Vancouver:

Svorad A. Audio zesilovač ve třídě D pro laboratorní výuku: Class D audio amplifier for laboratory measurements. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/11012/81763.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Svorad A. Audio zesilovač ve třídě D pro laboratorní výuku: Class D audio amplifier for laboratory measurements. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/81763

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

23. Diril, Abdulkadir Utku. Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic.

Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech

 Technology scaling trends lead to shrinking of the individual elements like transistors and wires in digital systems. The main driving force behind this is cutting… (more)

Subjects/Keywords: Low-power; Digital design; Dual threshold; Dual supply; Soft error tolerance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Diril, A. U. (2005). Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6929

Chicago Manual of Style (16th Edition):

Diril, Abdulkadir Utku. “Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic.” 2005. Doctoral Dissertation, Georgia Tech. Accessed March 03, 2021. http://hdl.handle.net/1853/6929.

MLA Handbook (7th Edition):

Diril, Abdulkadir Utku. “Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic.” 2005. Web. 03 Mar 2021.

Vancouver:

Diril AU. Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic. [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/1853/6929.

Council of Science Editors:

Diril AU. Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic. [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6929


Linköping University

24. Klevbrink, Anna-Charlotta. Evaluation of Aptivia and a Place and Route tool.

Degree: Electrical Engineering, 2005, Linköping University

  This master thesis tells about Aptivia, what it contains and how i works (inluding a manual). As well as problems with it. It also… (more)

Subjects/Keywords: Aptivia; manual; standard cell; design automation; layout; Electronics; Elektronik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Klevbrink, A. (2005). Evaluation of Aptivia and a Place and Route tool. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3768

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Klevbrink, Anna-Charlotta. “Evaluation of Aptivia and a Place and Route tool.” 2005. Thesis, Linköping University. Accessed March 03, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3768.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Klevbrink, Anna-Charlotta. “Evaluation of Aptivia and a Place and Route tool.” 2005. Web. 03 Mar 2021.

Vancouver:

Klevbrink A. Evaluation of Aptivia and a Place and Route tool. [Internet] [Thesis]. Linköping University; 2005. [cited 2021 Mar 03]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3768.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Klevbrink A. Evaluation of Aptivia and a Place and Route tool. [Thesis]. Linköping University; 2005. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3768

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

25. Chang, Hsu-Kuang. An Improved Scheme for Sensor Alignment Calibration of Ultra Short Baseline Positioning Systems.

Degree: Master, IAMPUT, 2009, NSYSU

 This study proposed a numerical algorithm for estimating the angular misalignments between sensors of an ultra short baseline (USBL) positioning system. The algorithm is based… (more)

Subjects/Keywords: Alignment error; USBL; Iterative scheme; Positioning

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APA (6th Edition):

Chang, H. (2009). An Improved Scheme for Sensor Alignment Calibration of Ultra Short Baseline Positioning Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809109-233755

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Hsu-Kuang. “An Improved Scheme for Sensor Alignment Calibration of Ultra Short Baseline Positioning Systems.” 2009. Thesis, NSYSU. Accessed March 03, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809109-233755.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Hsu-Kuang. “An Improved Scheme for Sensor Alignment Calibration of Ultra Short Baseline Positioning Systems.” 2009. Web. 03 Mar 2021.

Vancouver:

Chang H. An Improved Scheme for Sensor Alignment Calibration of Ultra Short Baseline Positioning Systems. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Mar 03]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809109-233755.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang H. An Improved Scheme for Sensor Alignment Calibration of Ultra Short Baseline Positioning Systems. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809109-233755

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Valadimas, Stefanos. Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες.

Degree: 2016, National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ)

As technology scales down, timing errors are a real concern in high complexity and high frequency integrated circuits. Process, Voltage and Temperature variations lead to… (more)

Subjects/Keywords: εν λειτουργία έλεγχος ορθής λειτουργίας; λάθη χρονισμού; Ανίχνευση λαθών; ανθεκτικότητα σε λάθη χρονισμού; σχεδίαση αξιόπιστων συστημάτων; Διόρθωση λαθών; On-line testing; timing errors; Error detection; timing error tolerance; reliability-aware design; Error correction

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APA (6th Edition):

Valadimas, S. (2016). Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες. (Thesis). National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ). Retrieved from http://hdl.handle.net/10442/hedi/38222

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Valadimas, Stefanos. “Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες.” 2016. Thesis, National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ). Accessed March 03, 2021. http://hdl.handle.net/10442/hedi/38222.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Valadimas, Stefanos. “Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες.” 2016. Web. 03 Mar 2021.

Vancouver:

Valadimas S. Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες. [Internet] [Thesis]. National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ); 2016. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/10442/hedi/38222.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Valadimas S. Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες. [Thesis]. National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ); 2016. Available from: http://hdl.handle.net/10442/hedi/38222

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. ZHENG HUANHUAN. DESIGN AND ANALYSIS OF VISIBLE LIGHT COMMUNICATION AND POSITIONING SYSTEMS.

Degree: 2017, National University of Singapore

Subjects/Keywords: LED arrangement design; visible light communication; error correcting algorithm; positioning error; visible light positioning; asynchronous CDMA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

HUANHUAN, Z. (2017). DESIGN AND ANALYSIS OF VISIBLE LIGHT COMMUNICATION AND POSITIONING SYSTEMS. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/136048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

HUANHUAN, ZHENG. “DESIGN AND ANALYSIS OF VISIBLE LIGHT COMMUNICATION AND POSITIONING SYSTEMS.” 2017. Thesis, National University of Singapore. Accessed March 03, 2021. http://scholarbank.nus.edu.sg/handle/10635/136048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

HUANHUAN, ZHENG. “DESIGN AND ANALYSIS OF VISIBLE LIGHT COMMUNICATION AND POSITIONING SYSTEMS.” 2017. Web. 03 Mar 2021.

Vancouver:

HUANHUAN Z. DESIGN AND ANALYSIS OF VISIBLE LIGHT COMMUNICATION AND POSITIONING SYSTEMS. [Internet] [Thesis]. National University of Singapore; 2017. [cited 2021 Mar 03]. Available from: http://scholarbank.nus.edu.sg/handle/10635/136048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

HUANHUAN Z. DESIGN AND ANALYSIS OF VISIBLE LIGHT COMMUNICATION AND POSITIONING SYSTEMS. [Thesis]. National University of Singapore; 2017. Available from: http://scholarbank.nus.edu.sg/handle/10635/136048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Washington State University

28. [No author]. WHAT DOES THE ARCHITECTURAL CREATIVE LEAP LOOK LIKE THROUGH A CONCEPTUAL DESIGN PHASE IN THE UNDERGRADUATE ARCHITECTURAL DESIGN STUDIO? .

Degree: 2012, Washington State University

 The creative leap is a mental creative moment in which one discovers and illustrates a new design idea, or restructures and develops an old one.… (more)

Subjects/Keywords: Architecture; Design; architectural design education; conceptual design; Creative leap; creativity; design decisions; design knowledge

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

author], [. (2012). WHAT DOES THE ARCHITECTURAL CREATIVE LEAP LOOK LIKE THROUGH A CONCEPTUAL DESIGN PHASE IN THE UNDERGRADUATE ARCHITECTURAL DESIGN STUDIO? . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/4163

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “WHAT DOES THE ARCHITECTURAL CREATIVE LEAP LOOK LIKE THROUGH A CONCEPTUAL DESIGN PHASE IN THE UNDERGRADUATE ARCHITECTURAL DESIGN STUDIO? .” 2012. Thesis, Washington State University. Accessed March 03, 2021. http://hdl.handle.net/2376/4163.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “WHAT DOES THE ARCHITECTURAL CREATIVE LEAP LOOK LIKE THROUGH A CONCEPTUAL DESIGN PHASE IN THE UNDERGRADUATE ARCHITECTURAL DESIGN STUDIO? .” 2012. Web. 03 Mar 2021.

Vancouver:

author] [. WHAT DOES THE ARCHITECTURAL CREATIVE LEAP LOOK LIKE THROUGH A CONCEPTUAL DESIGN PHASE IN THE UNDERGRADUATE ARCHITECTURAL DESIGN STUDIO? . [Internet] [Thesis]. Washington State University; 2012. [cited 2021 Mar 03]. Available from: http://hdl.handle.net/2376/4163.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. WHAT DOES THE ARCHITECTURAL CREATIVE LEAP LOOK LIKE THROUGH A CONCEPTUAL DESIGN PHASE IN THE UNDERGRADUATE ARCHITECTURAL DESIGN STUDIO? . [Thesis]. Washington State University; 2012. Available from: http://hdl.handle.net/2376/4163

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

29. Chang, Yu-Wei. Implementation of the broadband Power Line Communication system.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 Digital home has been mentioned a lot in recent years. We can connect appliances through the internet to provide new services such as home care,… (more)

Subjects/Keywords: block interleaver; quadrature amplitude modulation; Power Line Communication; error correcting code; cell-based design flow

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, Y. (2015). Implementation of the broadband Power Line Communication system. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0309115-161048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Yu-Wei. “Implementation of the broadband Power Line Communication system.” 2015. Thesis, NSYSU. Accessed March 03, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0309115-161048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Yu-Wei. “Implementation of the broadband Power Line Communication system.” 2015. Web. 03 Mar 2021.

Vancouver:

Chang Y. Implementation of the broadband Power Line Communication system. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Mar 03]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0309115-161048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang Y. Implementation of the broadband Power Line Communication system. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0309115-161048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Marzaki, Abderrezak. Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS : Development of innovative manufacturing process techniques and a new MOS transistor architecture.

Degree: Docteur es, Micro et Nanoélectronique, 2013, Aix Marseille Université

La miniaturisation des composants et l’amélioration des performances des circuits intégrés (ICs) sont dues aux progrès liés au procédé de fabrication. Malgré le nombre de… (more)

Subjects/Keywords: Effet de pointe; Mémoire non volatile; Caractérisation morphologique; Caractérisation électrique; Patterning; Transistor à tension de seuil; Modélisation compacte; Conception analogique; Peak effect; Non volatile memory; Morphological characterization; Electrical characterization; Patterning; Dual-Control-Gate Floating-Gate-Transistor (DCG FGT); Compact modeling; Analog design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Marzaki, A. (2013). Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS : Development of innovative manufacturing process techniques and a new MOS transistor architecture. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2013AIXM4768

Chicago Manual of Style (16th Edition):

Marzaki, Abderrezak. “Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS : Development of innovative manufacturing process techniques and a new MOS transistor architecture.” 2013. Doctoral Dissertation, Aix Marseille Université. Accessed March 03, 2021. http://www.theses.fr/2013AIXM4768.

MLA Handbook (7th Edition):

Marzaki, Abderrezak. “Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS : Development of innovative manufacturing process techniques and a new MOS transistor architecture.” 2013. Web. 03 Mar 2021.

Vancouver:

Marzaki A. Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS : Development of innovative manufacturing process techniques and a new MOS transistor architecture. [Internet] [Doctoral dissertation]. Aix Marseille Université 2013. [cited 2021 Mar 03]. Available from: http://www.theses.fr/2013AIXM4768.

Council of Science Editors:

Marzaki A. Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS : Development of innovative manufacturing process techniques and a new MOS transistor architecture. [Doctoral Dissertation]. Aix Marseille Université 2013. Available from: http://www.theses.fr/2013AIXM4768

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