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1.
Campbell, Keith A.
Robust and reliable hardware accelerator design through high-level synthesis.
Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign
URL: http://hdl.handle.net/2142/99294 
► System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety…
(more)
▼ System-on-chip
design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to
design complex, custom hardware that is efficient, but also correct and reliable.
High-level synthesis shows promise to address the problem of complex hardware
design by providing a bridge from the high-productivity software domain to the hardware
design process. Much research has been done on high-level synthesis efficiency optimizations. This dissertation shows that high-level synthesis also has the power to address validation and reliability challenges
through three automated solutions targeting three key stages in the hardware
design and use cycle: pre-silicon debugging, post-silicon validation, and post-deployment
error detection.
Our solution for rapid pre-silicon debugging of accelerator designs is hybrid tracing: comparing a datapath-level trace of hardware execution with a reference software implementation at a fine temporal and spatial granularity to detect logic bugs. An integrated backtrace process delivers source-code meaning to the hardware designer, pinpointing the location of bug activation and providing a strong hint for potential bug fixes. Experimental results show that we are able to detect and aid in localization of logic bugs from both C/C++ specifications as well as the high-level synthesis engine itself.
A variation of this solution tailored for rapid post-silicon validation of accelerator designs is hybrid hashing: inserting signature generation logic in a hardware
design to create a heavily compressed signature stream that captures the internal behavior of the
design at a fine temporal and spatial granularity for comparison with a reference set of signatures generated by high-level simulation to detect bugs. Using hybrid hashing, we demonstrate an improvement in
error detection latency (time elapsed from when a bug is activated to when it manifests as an observable failure) of two orders of magnitude and a threefold improvement in bug coverage compared to traditional post-silicon validation techniques. Hybrid hashing also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. Hybrid hashing incurs less than 10% area overhead for the accelerator it validates with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by hybrid hashing.
Finally, our solution for post-deployment
error detection is modulo-3 shadow datapaths: performing lightweight shadow computations in modulo-3 space for each main computation. We leverage the binding and scheduling…
Advisors/Committee Members: Chen, Deming (advisor), Chen, Deming (Committee Chair), Hwu, Wen-Mei W (committee member), Wong, Martin D F (committee member), Kim, Nam Sung (committee member).
Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency
…design through Error-Aware transistor Positioning
LFSR
Linear Feedback Shift Register
LHL… …Resilience
CPU
Central Processing Unit
DAC
Design Automation Conference
DICE
Dual Interlocked… …Storage Cell
DIVA
Dynamic Implementation Verification Architecture, a faulttolerant CPU… …standards
JTAG
Joint Test Action Group, develops on-chip instrumentation
standards
LEAP
Layout… …Error
Detecting Cores through Low-Cost Modulo-3 Shadow Datapaths” [1], “Hybrid
Quick…
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APA (6th Edition):
Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294
Chicago Manual of Style (16th Edition):
Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 03, 2021.
http://hdl.handle.net/2142/99294.
MLA Handbook (7th Edition):
Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 03 Mar 2021.
Vancouver:
Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/2142/99294.
Council of Science Editors:
Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294
Vanderbilt University
2.
Amusan, Oluwole Ayodele.
Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies.
Degree: PhD, Electrical Engineering, 2009, Vanderbilt University
URL: http://hdl.handle.net/1803/10577
► Sub-100 nm technologies are more vulnerable than older technologies to single event effects (SEE) due to Moore's Law scaling trend. The increased SEE vulnerability has…
(more)
▼ Sub-100 nm technologies are more vulnerable than older technologies to single event effects (SEE) due to Moore's Law scaling trend. The increased SEE vulnerability has been attributed to the decrease in nodal charge for information
storage, reduced nodal separation, and increased switching frequency. The effect of the reduced nodal separation is the increased probability of simultaneous charge collection at several nodes from a single ion-strike (called charge sharing).
Charge sharing is a significant SEE issue because it can render circuit-level hardening techniques ineffective. Conventional SEE radiation-hardened by
design (RHBD) approaches provide excellent protection against single event upsets (SEU) resulting from charge collection occurs on a single node. However, for sub-100 nm technologies, the probability of multiple node charge collection is significant, thwarting RHBD protection. As CMOS processes continue to scale, there is a continued decrease in nodal pitch, but virtually no change in the charge generation radius of the heavy-ion strike. Hence, charge sharing is a troubling reliability roadblock for advanced technologies.
This dissertation introduces and details the charge sharing effect. It examines –
through finite element simulations, focused laser testing, and broadbeam heavy ion experiments – the effects of charge sharing at the 130 nm and 90 nm CMOS technology nodes. Results include quantification of the all-important angle of incidence on device and circuit response. Further, this dissertation examines the effectiveness of several charge sharing mitigation techniques.
The work presented in this dissertation directly impacts the SEE qualification techniques used by the radiation community for sub-100 nm technologies. The mitigation techniques proposed and verified are useful for improving the radiation hardness of advanced technologies, and provide designers with
design guidelines applicable to space-deployed applications.
Advisors/Committee Members: Dr. Mark N. Ellingham (committee member), Dr. Michael L. Alles (committee member), Dr. Arthur F. Witulski (committee member), Dr. Bharat L. Bhuva (committee member), Dr. Lloyd W. Massengill (Committee Chair).
Subjects/Keywords: nodal spacing; single event circuit characterization; soft error cross-section; pulse-widths; guard-bands; Dual Interlocked Cell (DICE) latch; Radiation hardening; Space environment; charge sharing mitigation; heavy-ion; guard-rings; Metal oxide semiconductors Complementary – Effect of radiation on
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APA (6th Edition):
Amusan, O. A. (2009). Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10577
Chicago Manual of Style (16th Edition):
Amusan, Oluwole Ayodele. “Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies.” 2009. Doctoral Dissertation, Vanderbilt University. Accessed March 03, 2021.
http://hdl.handle.net/1803/10577.
MLA Handbook (7th Edition):
Amusan, Oluwole Ayodele. “Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies.” 2009. Web. 03 Mar 2021.
Vancouver:
Amusan OA. Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2009. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/1803/10577.
Council of Science Editors:
Amusan OA. Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies. [Doctoral Dissertation]. Vanderbilt University; 2009. Available from: http://hdl.handle.net/1803/10577
Universidade do Rio Grande do Sul
3.
Guex, Jerson Paulo.
Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo.
Degree: 2013, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/78529
► Este trabalho visa explorar técnicas de projeto de células que possibilitem a minimização dos efeitos da variabilidade de processo sobre o comportamento elétrico dos circuitos…
(more)
▼ Este trabalho visa explorar técnicas de projeto de células que possibilitem a minimização dos efeitos da variabilidade de processo sobre o comportamento elétrico dos circuitos integrados. Para este trabalho foram abordados aspectos de regularidade, principalmente na camada de polisilício. A técnica de folding foi explorada em conjunto com a regularidade como possível metodologia de projeto voltada para a minimização dos efeitos da variabilidade de processo. Leiautes de portas lógicas complexas e básicas foram criadas utilizando tecnologia em 65nm. Os netlists dos leiautes extraídos foram simulados utilizando modelos que refletiam os efeitos da variabilidade sobre os parâmetros tecnológicos mais afetados pela variabilidade de processo. Os parâmetros selecionados para este experimento foram a largura (W) e comprimento (L) do canal do transistor, espessura do óxido de porta (Tox) e a mobilidade (μ0) das cargas. Os dados referentes ao pior caso envolvendo atraso e potência consumida de cada porta foram utilizados como métricas de comparação. Os resultados encontrados demonstram que a utilização da técnica de folding juntamente com aspectos de regularidade tornaram os experimentos menos sensíveis às variações do processos de manufatura de circuitos integrados. Essas reduções de sensibilidade chegaram em algumas situações à 33.22% para as portas básicas e de 28.96% para as portas complexas. A adição de folding e regularidade da camada de polisilício, trazem desvantagens significativas em área e potência consumida de cada porta. Pelos experimentos realizados é possível verificar aumento superior a 100% em área de algumas portas e de até 20.54% de aumento em potência. A união destas duas técnicas pode ser utilizada para tornar, por exemplo, o caminho crítico de um circuito integrado mais robusto quanto as variações de temporização e de potência.
This paper aims to explore for design techniques that allow the minimization of the effects of process variability on the electrical behavior of integrated circuits. To this work were discussed aspects of regularity, especially in poly-silicon layer. The technique of it folding was explored in conjunction with the regularity as possible design methodology aimed to minimizing the effects of process variability. Complex and basic layouts logic gates were built using 65nm technology. The it netlists extracted from layouts of the gates were simulated using models that reflected the effects of variability on the main technological parameters such as W, L, Tx, mu0 of the charges. The worst delay of each port and power consumption parameters were used for comparison in this work. The results show that using the it folding with regularity aspects of the experiments turns the layout gates less sensitive to process variations. These sensitivity reductions reached in some situations to 33.22 % for the basic gates and 28.96 % for the complex gates created. This techniques brings significant disadvantages in size and power consumption. For the experiments you can check increase of over 100% in…
Advisors/Committee Members: Reis, Ricardo Augusto da Luz.
Subjects/Keywords: Microeletrônica; Cell layout; Process variability; Vlsi; Transistores; DFM; Transistor folding; Microelectronics
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APA ·
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APA (6th Edition):
Guex, J. P. (2013). Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/78529
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Guex, Jerson Paulo. “Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo.” 2013. Thesis, Universidade do Rio Grande do Sul. Accessed March 03, 2021.
http://hdl.handle.net/10183/78529.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Guex, Jerson Paulo. “Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo.” 2013. Web. 03 Mar 2021.
Vancouver:
Guex JP. Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2013. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/10183/78529.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Guex JP. Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo. [Thesis]. Universidade do Rio Grande do Sul; 2013. Available from: http://hdl.handle.net/10183/78529
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Universidade do Rio Grande do Sul
4.
Brito, Eliseu Silveira.
Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo.
Degree: 2010, Universidade do Rio Grande do Sul
URL: http://hdl.handle.net/10183/29421
► A constante evolução dos sistemas produtivos amplia a importância dada aos projetos de instalações industriais, onde os sistemas celulares possuem uma importância especial, pois tem…
(more)
▼ A constante evolução dos sistemas produtivos amplia a importância dada aos projetos de instalações industriais, onde os sistemas celulares possuem uma importância especial, pois tem maior tendência de utilização na atualidade pela engenharia industrial. O sistema celular adota conceitos de tecnologia de grupo, permitindo produzir pequenos lotes e ganhar vantagens econômicas semelhantes às obtidas com produção em massa, não perdendo a flexibilidade da produção por processo. Com a evolução da computação, sistemas integrados de apoio à decisão no planejamento e implantação destes projetos foram surgindo e auxiliando para se ter arranjos físicos adequados as novas exigências de produção, mas o custo de aquisição e desenvolvimento de softwares específicos ainda é bastante elevado. Este trabalho apresenta uma solução computacional para o projeto de células através do desenvolvimento de um aplicativo que traduz o resultado de um algoritmo de tecnologia de grupo em opções gráficas de diferentes concepções físicas para o layout da célula, propondo uma função integradora, associando-se uma biblioteca de modelos gráficos de máquinas-ferramenta para representar no chão-de-fábrica diferentes opções de fluxos para o layout. A interface, desenvolvida em Visual Basic, permite tanto o processamento do algoritmo para definição dos grupos de máquinas, baseado em análise de fluxo de produção, quanto a representação no sistema gráfico e interação necessária com banco de dados em padrão Microsoft Access. O modelamento é representado em ambiente gráfico do software Solid Edge, que permite a customização necessária para gerar, de modo automatizado, uma interface para o projeto de layout. Na definição das fronteiras dos agrupamentos, ou seja, na delimitação da célula, utiliza-se uma metodologia que os identifica automaticamente, sendo que na maioria dos trabalhos realizados anteriormente estes não previam rotinas automáticas, ficando geralmente a cargo do usuário esta identificação. O sistema desenvolvido tem aplicação como ferramenta no planejamento e projeto de layout, à medida que lança mão de recursos de uma plataforma gráfica comercial (CAD) para representar de modo automatizado, o resultado de algoritmos que normalmente seriam apenas informações textuais. Este trabalho complementa outras aplicações realizadas anteriormente que limitavam-se às definições de células, sem representá-las graficamente, além de possibilitar a escolha da forma de fluxo a ser assumida pela célula, representando um elemento importante para apoio à decisão a quem esteja projetando ou promovendo melhorias em um ambiente industrial.
The constant evolution of production systems increases the importance given to industrial installation projects where the cellular systems have a special importance because of their strong trend to be used today by industrial engineering. The cellular system adopt concepts of group technology making it possible to produce small batches and gain economic advantages similar to those obtained with mass production without losing…
Advisors/Committee Members: Lorini, Flavio Jose.
Subjects/Keywords: Automação industrial; Cell layout; Layout industrial; Group technology; Usinagem; Manufacturing automation; Layout design
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APA ·
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Manager
APA (6th Edition):
Brito, E. S. (2010). Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/29421
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Brito, Eliseu Silveira. “Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed March 03, 2021.
http://hdl.handle.net/10183/29421.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Brito, Eliseu Silveira. “Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo.” 2010. Web. 03 Mar 2021.
Vancouver:
Brito ES. Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/10183/29421.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Brito ES. Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/29421
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
5.
Shiyanovskii, Yuriy.
Reliability of SRAMs and 3D TSV ICS: Design Protection from
Soft Errors and 3D Thermal Modeling.
Degree: PhD, EECS - Computer Engineering, 2012, Case Western Reserve University School of Graduate Studies
URL: http://rave.ohiolink.edu/etdc/view?acc_num=case1334891947
► With CMOS technology scaling into deep nanoscale level, reliability issues have emerged as key concerns for SRAM memories. The reliability of SRAM memories is…
(more)
▼ With CMOS technology scaling into deep
nanoscale level, reliability issues have emerged as key concerns
for SRAM memories. The reliability of SRAM memories is critical for
the overall reliability of the modern ICs because memories occupy a
large portion of the chip area. SRAM memory susceptibility to soft
errors caused by ionizing particles significantly increases due to
small node capacitance. Further aggressive
technology scaling is reaching its saturation due to limitations
posed by physics on
transistor size reduction. Emerging 3D
through-silicon vias (TSV) chip integration can provide an
alternative solution to satisfy ever-growing demands for packing
density. However, increased heat generation per unit footprint and
poor heat dissipation in 3D stacks can lead to high chip
temperatures, thus thermal management is considered one of the most
critical reliability issues in 3D ICs. This work addresses the most
urgent reliability concerns in conventional SRAM memories caused by
soft errors and in emerging 3D TSV ICs caused by excessive heat
generation, respectively.In this research, a new methodology based
on functional component separation, for the
design of soft
error
tolerant SRAM cells, is presented. The methodology is applied to
develop several novel SRAM
cell designs with improved soft
error
tolerance. Novel hardened SRAM
cell designs using
on-demand protective capacitor circuitry and tri-state inverters
are developed based on the proposed methodology of functional
separation. The developed SRAM designs offer high soft
error
protection level. In addition to soft
error robustness, the
tri-state based SRAM cells demonstrate excellent write performance,
low power consumption, and high read
cell stability, and are
scalable into the deep nanoscale region. A new
3D analytical thermal model is developed to simulate temperature
fields in 3D TSV ICs. The model allows for consideration of
inhomogeneous localized heating sources, heat exchange within the
layer, heat transfer
through external surfaces of the device,
inter-layer heat transfer with possible inhomogeneous TSV
placement, and micro-channel cooling. The model is applied to
analyze the steady state thermal behavior of 3D TSV devices with
inhomogeneous power densities. The model has a high computational
efficiency, and allows simulations to be performed in real
time.
Advisors/Committee Members: Papachristou, Christou (Advisor).
Subjects/Keywords: Computer Engineering; Electrical Engineering; Soft Error; SRAMs; Hardening; Reliability; Memory Cell Design; 3D ICs; TSV; Through-Silicon Vias; Thermal Modeling; Thermal Management
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APA ·
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Manager
APA (6th Edition):
Shiyanovskii, Y. (2012). Reliability of SRAMs and 3D TSV ICS: Design Protection from
Soft Errors and 3D Thermal Modeling. (Doctoral Dissertation). Case Western Reserve University School of Graduate Studies. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1334891947
Chicago Manual of Style (16th Edition):
Shiyanovskii, Yuriy. “Reliability of SRAMs and 3D TSV ICS: Design Protection from
Soft Errors and 3D Thermal Modeling.” 2012. Doctoral Dissertation, Case Western Reserve University School of Graduate Studies. Accessed March 03, 2021.
http://rave.ohiolink.edu/etdc/view?acc_num=case1334891947.
MLA Handbook (7th Edition):
Shiyanovskii, Yuriy. “Reliability of SRAMs and 3D TSV ICS: Design Protection from
Soft Errors and 3D Thermal Modeling.” 2012. Web. 03 Mar 2021.
Vancouver:
Shiyanovskii Y. Reliability of SRAMs and 3D TSV ICS: Design Protection from
Soft Errors and 3D Thermal Modeling. [Internet] [Doctoral dissertation]. Case Western Reserve University School of Graduate Studies; 2012. [cited 2021 Mar 03].
Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1334891947.
Council of Science Editors:
Shiyanovskii Y. Reliability of SRAMs and 3D TSV ICS: Design Protection from
Soft Errors and 3D Thermal Modeling. [Doctoral Dissertation]. Case Western Reserve University School of Graduate Studies; 2012. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1334891947
6.
-5314-7669.
Standard cell optimization and physical design in advanced technology nodes.
Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin
URL: http://hdl.handle.net/2152/47464
► Integrated circuits (ICs) are at the heart of modern electronics, which rely heavily on the state-of-the-art semiconductor manufacturing technology. The key to pushing forward semiconductor…
(more)
▼ Integrated circuits (ICs) are at the heart of modern electronics, which rely heavily on the state-of-the-art semiconductor manufacturing technology. The key to pushing forward semiconductor technology is IC feature-size miniaturization. However, this brings ever-increasing
design complexities and manufacturing challenges to the $340 billion semiconductor industry. The manufacturing of two-dimensional
layout on high-density metal layers depends on complex
design-for-manufacturing techniques and sophisticated empirical optimizations, which introduces huge amounts of turnaround time and yield loss in advanced technology nodes. Our study reveals that unidirectional
layout design can significantly reduce the manufacturing complexities and improve the yield, which is becoming increasingly adopted in semiconductor industry [61, 89]. The lithography printing of unidirectional
layout can be tightly controlled using advanced patterning techniques, such as self-aligned double and quadruple patterning. Despite the manufacturing benefits, unidirectional
layout leads to more restrictive solution space and brings significant impacts on the IC
design automation ow for routing closure. Notably, unidirectional routing limits the standard
cell pin accessibility, which further exacerbates the resource competitions during routing. Moreover, for post-routing optimization, traditional redundant-via insertion has become obsolete under unidirectional routing style, which makes the yield enhancement task extremely challenging. Regardless of complex multiple patterning and
design-for-manufacturing approaches, mask optimization
through resolution enhancement techniques remains as the key strategy to improve the yield of the semiconductor manufacturing processes. Among them, Sub-Resolution Assist Feature (SRAF) generation is a very important method to improve lithographic process windows. Model-based SRAF generation has been widely used to achieve high accuracy but it is time-consuming and hard to obtain consistent SRAFs. This dissertation proposes novel CAD algorithms and methodologies for standard
cell optimization and physical
design in advanced technology nodes, which ultimately reduces the
design cycle and manufacturing cost of IC
design. First, a standard
cell pin access optimization engine is proposed to evaluate the pin accessibility of a given standard
cell library. We further propose novel pin access planning techniques and concurrent pin access optimizations to efficiently resolve the routing resource competitions, which generates much better routing solutions than state-of-the-art, manufacturing-friendly routers. To systematically improve the manufacturing yield in the post-routing stage, a global optimization engine has been introduced for redundant local-loop insertion considering advanced manufacturing constraints. Finally, we propose the first machine learning-based framework for fast yet consistent SRAF generation with the high quality of results.
Advisors/Committee Members: Pan, David Z. (advisor), Cline, Brian (committee member), Orshansky, Michael (committee member), Sun, Nan (committee member), Touba, Nur A. (committee member).
Subjects/Keywords: Standard cell; Physical design; Cell optimization; Integrated circuits; Semiconductor technology; Miniaturization; Unidirectional layout design
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APA ·
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APA (6th Edition):
-5314-7669. (2017). Standard cell optimization and physical design in advanced technology nodes. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/47464
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-5314-7669. “Standard cell optimization and physical design in advanced technology nodes.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed March 03, 2021.
http://hdl.handle.net/2152/47464.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-5314-7669. “Standard cell optimization and physical design in advanced technology nodes.” 2017. Web. 03 Mar 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-5314-7669. Standard cell optimization and physical design in advanced technology nodes. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/2152/47464.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-5314-7669. Standard cell optimization and physical design in advanced technology nodes. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/47464
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Delft University of Technology
7.
Malagi, Santosh (author).
Library Characterization for Cell-Aware Test.
Degree: 2018, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:266ab254-3895-4295-b557-eec87eb9c811
► Due to their large number of high-precision, defect-prone manufacturing steps, integrated circuits (ICs) are susceptible to manufacturing defects and hence need to undergo electrical tests…
(more)
▼ Due to their large number of high-precision, defect-prone manufacturing steps, integrated circuits (ICs) are susceptible to manufacturing defects and hence need to undergo electrical tests to weed out the defective parts and guarantee sufficient outgoing product quality to the customer. A key step in test development for digital logic ICs is automatic test pattern generation (ATPG). Cell-aware test (CAT) is a next-generation test pattern generation approach; its novel feature is that it explicitly addresses cell-internal defects (as opposed to relying on serendipitous coverage by traditional ATPG). CAT consists of two stages - cell-aware library characterization (CA-LC) and cell-aware ATPG. Library characterization uses parasitics-extracted transistor-level netlists to model open and short defects candidates, which are then simulated with an exhaustive set of cell-level test patterns. The results are encoded in the form of defect detection matrices (DDMs). Cell-aware ATPG uses this information to determine a set of test patterns such that, as many as possible cell-internal defects in the circuit are covered. As an industrial standard-cell library contains hundreds of cells, library characterization is a time consuming task. The target defect set must be realistic and complete, but not unnecessarily large. The objective of this thesis is to improve the library characterization stage of the Cadence CAT flow by effectively and efficiently modelling realistic defects, while trying to minimize the time required for characterization. To achieve this, several improvements to the existing flow are proposed. (1) defining a set of customized settings for the parasitics extraction tool for generating transistor-level netlists, which are well-suited for cell-aware defect modelling (2) elimination of potential defects, which were superfluous elements being inserted into the netlist (3) using super-hard defect resistance values for modelling opens and shorts (4) reduction in simulation time by modifying the software flow and, (5) inserting a single short defect between two net pairs to reduce the size of the target defect set. For the 45nm generic library (GPDK045) from Cadence, these modifications resulted in an improvement in test quality by uncovering as many as 1114 false detections and a reduction of 6% in the characterization time. The number of short defects to be simulated reduced by 97.7%. This work was carried out as a part of a joint project on cell-aware test between Cadence (supplier of electronic design automation software), IMEC (research organization), and Eindhoven University of Technology.
Computer Engineering
Advisors/Committee Members: Hamdioui, Said (mentor), van Leuken, Rene (graduation committee), Marinissen, EJ (graduation committee), Delft University of Technology (degree granting institution).
Subjects/Keywords: Cell-Aware Test; Library Characterization; Design for Test
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APA (6th Edition):
Malagi, S. (. (2018). Library Characterization for Cell-Aware Test. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:266ab254-3895-4295-b557-eec87eb9c811
Chicago Manual of Style (16th Edition):
Malagi, Santosh (author). “Library Characterization for Cell-Aware Test.” 2018. Masters Thesis, Delft University of Technology. Accessed March 03, 2021.
http://resolver.tudelft.nl/uuid:266ab254-3895-4295-b557-eec87eb9c811.
MLA Handbook (7th Edition):
Malagi, Santosh (author). “Library Characterization for Cell-Aware Test.” 2018. Web. 03 Mar 2021.
Vancouver:
Malagi S(. Library Characterization for Cell-Aware Test. [Internet] [Masters thesis]. Delft University of Technology; 2018. [cited 2021 Mar 03].
Available from: http://resolver.tudelft.nl/uuid:266ab254-3895-4295-b557-eec87eb9c811.
Council of Science Editors:
Malagi S(. Library Characterization for Cell-Aware Test. [Masters Thesis]. Delft University of Technology; 2018. Available from: http://resolver.tudelft.nl/uuid:266ab254-3895-4295-b557-eec87eb9c811
Penn State University
8.
Patki, Mayuresh Premanand.
A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network.
Degree: 2017, Penn State University
URL: https://submit-etda.libraries.psu.edu/catalog/13800mfp5198
► With several advancements in medical science being carried out over the past few decades, there has been a constant need to process information artificially, the…
(more)
▼ With several advancements in medical science being carried out over the past few decades, there has been a constant need to process information artificially, the way it is processed inside the human body. This inherent attribute of Artificial Intelligence (AI) is achieved in practice using Artificial Neural Networks (ANNs). ANNs have been around since 1943 and used since then for artificial information processing and neural computation.
This thesis focuses on the hardware implementation of an artificial neural network using CMOS technology. The
design is carried out in the analog domain to exploit certain advantages of analog integrated circuit
design, such as, high efficiency, in terms of area and power, and ease of computation. The neural architecture designed is a multilayer feedforward neural network to solve the XOR classification problem, which serves as a benchmark for several complex classification problems that are not linearly separable. Each component circuit of the network, such as the synapse circuit that performs the multiplication operation and the non-linear activation function circuit that acts as squashing function, is designed using MOSFETs operating in the sub-threshold (weak inversion) region.
The schematic designs are carried out using Cadence OrCAD Capture version 16.6 EDA software and simulated using PSPICE version 16.6, an in-built simulation tool within OrCAD capture. The
layout of the individual components and the overall schematic is also done using Electric VLSI
Design software version 9.06 on a 200 nm
design scale. A consistency check is carried out to ensure equivalency of
layout with the schematic, for a potential scope towards chip fabrication using Metal Oxide Semiconductor Implementation Service (MOSIS) foundry. The
layout of the proposed neural architecture is found to occupy an area of 0.065 〖mm〗
2, indicating
design compactness to a moderate level.
Advisors/Committee Members: Seth Wolpert, Thesis Advisor/Co-Advisor, Scott Von Tonningen, Committee Member, Wolfram Bettermann, Committee Member.
Subjects/Keywords: Artificial Intelligence; Artificial Neural Networks; Metal Oxide Semiconductor Implementation Service; Integrated Circuit; CMOS; Very Large Scale Integration; McCulloch and Pitts neuron; Perceptron; Backpropagation Algorithm; Synapses; Gilbert Multiplier Cell; Activation Function Circuit; Floating Gate; Single Transistor Learning Synapse; Post-Synaptic Current; Spike Timing Dependent Plasticity; Long Term Potentiation; Long Term Depression; Static Random Access Memory; Memristor; Mean Square Error; Cadence OrCAD Capture; Cadence PSpice A/D; Electric VLSI Design System; Network Consistency Check; Layout Vs Schematic Check; XOR Classification Problem; MATLAB; Time Domain; Instantaneous Power Dissipation; Loading; Learning Rate; Mixed Signal; System on Chip; Field Programmable Gate Arrays
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APA (6th Edition):
Patki, M. P. (2017). A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/13800mfp5198
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Patki, Mayuresh Premanand. “A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network.” 2017. Thesis, Penn State University. Accessed March 03, 2021.
https://submit-etda.libraries.psu.edu/catalog/13800mfp5198.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Patki, Mayuresh Premanand. “A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network.” 2017. Web. 03 Mar 2021.
Vancouver:
Patki MP. A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network. [Internet] [Thesis]. Penn State University; 2017. [cited 2021 Mar 03].
Available from: https://submit-etda.libraries.psu.edu/catalog/13800mfp5198.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Patki MP. A Low Power and Area Efficient CMOS Implementation of Multilayer Feedforward Artificial Neural Network. [Thesis]. Penn State University; 2017. Available from: https://submit-etda.libraries.psu.edu/catalog/13800mfp5198
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Cincinnati
9.
RANJAN, MUKESH.
AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS
USING SYMBOLIC PERFORMANCE MODELS.
Degree: PhD, Engineering : Computer Science and
Engineering, 2005, University of Cincinnati
URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496
► A key task in the automated design of analog/RF circuits is circuit sizing, a process that involves assigning numerical values to unknown circuit parameters of…
(more)
▼ A key task in the automated
design of analog/RF
circuits is circuit sizing, a process that involves assigning
numerical values to unknown circuit parameters of a fixed topology,
while being subjected to a set of performance constraints. Over the
years, the terms sizing and synthesis have been used
interchangeably, and have become synonymous in the analog domain.
Mature tools for the synthesis of digital circuits are abundant,
but the market for analog synthesis tools is still growing and very
few commercial products exist. Several techniques have been
developed in the past for analog synthesis, ranging from
knowledge-based methods to techniques using numerical simulation. A
frequently used technique involves an iterative stochastic search,
which uses numerical simulations at every probable
design point, in
order to obtain the performance metrics. Expensive computations and
parasitics unawareness of this traditional method necessitates a
scheme which can produce fast
layout aware designs. In this
dissertation a new synthesis methodology, which uses parameterized
layout generators and symbolic performance models (SPMs) inside the
synthesis loop, has been developed to overcome the deficiencies of
the previous circuit sizing method. This
layout-inclusive
(
layout-in-loop) approach uses efficient parameterized procedural
layout generators, obtained using the module specification language
(MSL) system, for speedy
layout instantiation. Fast performance
estimation is achieved by using pre-compiled SPMs, which are
symbolic representation of circuit performances, obtained using
symbolic analysis. The transfer functions of SPMs are stored as
efficient symbolic graphs called element-coefficient diagrams
(ECDs). Techniques to include
layout geometry effects in the SPMs
have also been developed. This method is used for the synthesis of
op-amps and filters. The method proposed above for analog circuits
is then applied to the synthesis of an RF low-noise amplifier
(LNA). This method also uses symbolic performance models (SPMs),
and parameterized
layout generator along with high-frequency
extraction techniques in the synthesis loop. SPMs for noise figure
and distortion parameters are developed using repetitive and weakly
nonlinear symbolic analysis and are stored as pre-compiled ECDs.
Full parasitic extraction is done by using multiple extractors.
Quasi-static extraction is used to obtain the critical parasitic
effects of interconnects and on-chip inductors. Further in the
dissertation, efforts are made to overcome the shortcomings of the
proposed method. The first limitation is the size of circuits that
can be synthesized. It arises because of the limit on the size of
ECD-code that can be compiled by a standard GNU C++ compiler. To
overcome this bottleneck, a new comprehensive method and framework
for exact symbolic analysis of large analog circuits is developed.
The method is based on the concepts of hierarchical circuit
decomposition, subcircuit symbolic analysis and transfer function
synthesis. Node tearing methods have been used…
Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).
Subjects/Keywords: Computer Science; Analog Circuit Synthesis; Symbolic Analysis; Layout-Aware; Parasitic-Aware; Analog Design
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APA (6th Edition):
RANJAN, M. (2005). AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS
USING SYMBOLIC PERFORMANCE MODELS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496
Chicago Manual of Style (16th Edition):
RANJAN, MUKESH. “AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS
USING SYMBOLIC PERFORMANCE MODELS.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed March 03, 2021.
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496.
MLA Handbook (7th Edition):
RANJAN, MUKESH. “AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS
USING SYMBOLIC PERFORMANCE MODELS.” 2005. Web. 03 Mar 2021.
Vancouver:
RANJAN M. AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS
USING SYMBOLIC PERFORMANCE MODELS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2021 Mar 03].
Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496.
Council of Science Editors:
RANJAN M. AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS
USING SYMBOLIC PERFORMANCE MODELS. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496
Vanderbilt University
10.
Kauppila, Jeffrey Scott.
Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.
Degree: PhD, Electrical Engineering, 2015, Vanderbilt University
URL: http://hdl.handle.net/1803/10793
► The development of integrated circuits intended for use in transient radiation environments must account for the impact of the environment on the operation of the…
(more)
▼ The development of integrated circuits intended for use in transient radiation environments must account for the impact of the environment on the operation of the circuit. The
design of integrated circuits is increasingly simulation driven, and increased costs to fabricate designs require engineers to consider radiation effects in the simulation and
design phase to limit fabrication and test cycles required to produce a radiation hardened part. This work advances the historical modeling approaches with bias-dependent and
layout-
aware methods for modeling the dose-rate and single-event effects in advanced technologies.
This research develops a bias-dependent modeling method that accounts for circuit induced shaping of the device-level transient current. Behavioral modeling languages are utilized to eliminate independent current sources and lumped SPICE element models. Dose rate models are developed for multiple dielectrically-isolated processes across technology types, accounting for real-time bias-dependence and
layout geometries in modern integrated circuit processes. Single-event modeling methods are developed to capture the bias-dependent current response observed in recent TCAD simulations. Bulk CMOS and SiGe HBT technology model parameterization for multiple-device charge collection is demonstrated. A new geometry-
aware single-event model for sub-50nm partially-depleted SOI CMOS with an integrated parasitic BJT parameterized by technology and
design parameters is developed. Dose-rate and single-event model simulations compare well to TCAD and test data.
A novel
layout-
aware analysis method is developed, utilizing a hybrid of compact models (for efficiency) and spatially-
aware layout objects (for geometric charge collection accuracy), in an industry standard integrated circuit
design tool flow. The
layout-
aware analysis provides designers with visual feedback about the sensitivity of a
design directly referenced to the circuit
layout.
The methods developed in this research are being actively utilized in radiation-effects research at universities, aerospace and defense corporations, and commercial integrated circuit
design and manufacturing facilities.
Layout-
aware radiation-enabled models using the methodologies developed in this work have been integrated with process
design kits and deployed to the radiation-hardened-by-
design community. This research develops capabilities that provide a path forward to model transient radiation effects in advanced integrated circuit technologies.
Advisors/Committee Members: Ronald D. Schrimpf, Ph.D. (committee member), W. Timothy Holman, Ph.D. (committee member), Bharat L. Bhuva, Ph.D. (committee member), Mark N. Ellingham, Ph.D. (committee member), Lloyd W. Massengill, Ph.D. (Committee Chair).
Subjects/Keywords: CAD Tools; Semiconductor Device Modeling; Process Design Kit; Gummel Poon; BSIMSOI; MEXTRAM; Radiation Modeling; TCAD; BSIM4; Bias-Dependent Modeling; Dose Rate Effects; Compact Models; Single Event Effects; Compact Model; BJT; MOSFET; Layout-Aware Modeling; Layout-Aware Analysis; SPICE; Layout; Radiation Effects; Circuit Simulation; Radiation-Enabled Model; Single-Event Transient; Single-Event Upset; Charge Sharing; Computational Modeling
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APA (6th Edition):
Kauppila, J. S. (2015). Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10793
Chicago Manual of Style (16th Edition):
Kauppila, Jeffrey Scott. “Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed March 03, 2021.
http://hdl.handle.net/1803/10793.
MLA Handbook (7th Edition):
Kauppila, Jeffrey Scott. “Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.” 2015. Web. 03 Mar 2021.
Vancouver:
Kauppila JS. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/1803/10793.
Council of Science Editors:
Kauppila JS. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/10793
11.
Björkman, Hanna.
Designing a board game rulebook It is harder than you would think.
Degree: Faculty of Science & Engineering, 2019, Linköping UniversityLinköping University
URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-160510
► This thesis has explored how to create a board game rulebook, for the board game Curators, in order to facilitate learning the rules as…
(more)
▼ This thesis has explored how to create a board game rulebook, for the board game Curators, in order to facilitate learning the rules as well as reminding players of the rules. This was done via research through design. The design of a rulebook incorporates many parts of design theory, from layout and typography to the use of color, gestalt principles, and images. All these were combined with knowledge about how existing rulebooks convey rules and the way board gamers use rulebooks, gained through the pre-study, in order to create a rulebook for the coming board game Curators. The analysis of this study shows that the resulting rulebook was successful in both teaching the game and helping players look up rules, though improvements could still be made to make it better. It was concluded that the use of many iterations of designing and testing is ideal for creating a rulebook with as few issues as possible.
Subjects/Keywords: graphic design; board game; tabletop game; rulebook; rule book; instruction manual; layout; typography; research through design; color; gestalt principles; teaching; Other Engineering and Technologies not elsewhere specified; Övrig annan teknik
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APA (6th Edition):
Björkman, H. (2019). Designing a board game rulebook It is harder than you would think. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-160510
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Björkman, Hanna. “Designing a board game rulebook It is harder than you would think.” 2019. Thesis, Linköping UniversityLinköping University. Accessed March 03, 2021.
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-160510.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Björkman, Hanna. “Designing a board game rulebook It is harder than you would think.” 2019. Web. 03 Mar 2021.
Vancouver:
Björkman H. Designing a board game rulebook It is harder than you would think. [Internet] [Thesis]. Linköping UniversityLinköping University; 2019. [cited 2021 Mar 03].
Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-160510.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Björkman H. Designing a board game rulebook It is harder than you would think. [Thesis]. Linköping UniversityLinköping University; 2019. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-160510
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of South Florida
12.
Krishnan, Vyas.
Temperature and Interconnect Aware Unified Physical and High Level Synthesis.
Degree: 2008, University of South Florida
URL: https://scholarcommons.usf.edu/etd/347
► Aggressive scaling of nanoscale CMOS integrated circuits has created significant design challenges arising from increasing power densities, thermal concerns, and rising wire delays. The main…
(more)
▼ Aggressive scaling of nanoscale CMOS integrated circuits has created significant design challenges arising from increasing power densities, thermal concerns, and rising wire delays. The main contribution of this dissertation is the development of unified physical and high-level synthesis techniques for the design of ASICs with optimal chip temperatures and interconnect delays.
Thermal issues are becoming a serious problem in high-performance VLSI circuits, adversely impacting performance, reliability, power consumption, and cooling costs. To address this, we present a temperature-aware behavioral synthesis (TABS) framework that combines power minimization with temperature-aware task scheduling, resource binding, and floorplanning. Compared to conventional low-power synthesis methods, our approach is effective in synthesizing circuits with lower chip temperatures and more uniform thermal distributions, with temperature reductions up to 23% when compared to low-power synthesis.
We propose three techniques to address interconnect delays during high-level synthesis: (1) a simulated annealing (SA) based layout-aware high-level synthesis technique for 3-D integrated circuits, that tightly couples the synthesis tasks of resource binding and 3-D floorplanning. The proposed algorithm significantly outperforms a conventional synthesis flow that separates the binding and floorplanning steps, with improvements in the total wirelength by 29% and of the longest wirelength by 21%; (2) a floorplan-aware high-level synthesis technique that uses the topology of multi-terminal nets to improve interconnect delay estimates during resource binding. Experiments show that the use of accurate wire delay estimates during binding can reduce wire delays by as much as 49% in 70nm technology; (3) an iterative high-level design-space exploration engine that uses a priori stochastic wirelength estimates to guide binding decisions during high-level synthesis. The proposed approach offers a significant speed-up during design space exploration when compared to approaches that use traditional place-and-route to evaluate candidate solutions.
Finally, we present a genetic algorithm (GA) based approach for high-level synthesis. We propose novel GA encoding, crossover, and mutation operators for the problem. The quality of the results generated by the GA are superior to those of several other techniques reported in the literature.
Subjects/Keywords: behavioral synthesis; power-aware design; thermal analysis; interconnectcentric design; stochastic interconnect estimation; layout-aware synthesis; American Studies; Arts and Humanities
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APA ·
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APA (6th Edition):
Krishnan, V. (2008). Temperature and Interconnect Aware Unified Physical and High Level Synthesis. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/347
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Krishnan, Vyas. “Temperature and Interconnect Aware Unified Physical and High Level Synthesis.” 2008. Thesis, University of South Florida. Accessed March 03, 2021.
https://scholarcommons.usf.edu/etd/347.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Krishnan, Vyas. “Temperature and Interconnect Aware Unified Physical and High Level Synthesis.” 2008. Web. 03 Mar 2021.
Vancouver:
Krishnan V. Temperature and Interconnect Aware Unified Physical and High Level Synthesis. [Internet] [Thesis]. University of South Florida; 2008. [cited 2021 Mar 03].
Available from: https://scholarcommons.usf.edu/etd/347.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Krishnan V. Temperature and Interconnect Aware Unified Physical and High Level Synthesis. [Thesis]. University of South Florida; 2008. Available from: https://scholarcommons.usf.edu/etd/347
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
13.
FOLKESSON, JOSEFINE.
Butikskommunikation och layout.
Degree: Swedish School of Textiles, 2014, University of Borås
URL: http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-18010
► Syftet med detta examensarbete är att med hjälp av empiriskt material och tidigare forskning undersöka hur en butikskedja inom modebranschen använder sin butikslayout och…
(more)
▼ Syftet med detta examensarbete är att med hjälp av empiriskt material och tidigare forskning undersöka hur en butikskedja inom modebranschen använder sin butikslayout och olika butiksytor för att visuellt kommunicera till sina kunder. För att avgränsa oss gick vi främst in på användandet av ABC-ytor, butikslayout och färgval i butiksexponeringen. Vi valde att basera vår studie på modekedjan Lindex, för att se om teori och verklighet stämmer överens. I uppsatsen förklaras tre teoretiska modeller som beskriver butikskommunikation och vad som fångar kunders uppmärksamhet i butik. Vi beskriver även vilka olika layouter en butik kan använda sig av, vad de olika butiksytorna ska kommunicera, samt olika exponeringsmetoder. Detta länkas sedan samman med vår undersökning vilket ger svar på vår frågeställning. Vår undersökning utgörs av en deltagande observation i tre av Lindex butiker i centrala Göteborg, där vi undersökte hur kunderna betedde sig i butikerna. Vi observerade hur de bemötte de olika butiksytorna och om de följde något specifikt kundvarv. Vi observerade även vilka färger butikerna hade valt att använda sig av i sin visuella butikskommunikation. Genom vår undersökning kom vi fram till att det är viktigt att butiken använder sig av olika stimuli för att väcka kundens intresse. Detta kan man till exempel göra genom att arbeta fram en tilltalande butiksatmosfär där butikens färger och ljussättning har en betydande roll. Vi kom även fram till att det är viktigt för butiken att arbeta med ett styrt kundvarv för att kunderna ska besöka alla ytor i butiken. Utöver ett organiserat kundvarv är det också viktigt att butiken aktivt arbetar med sin exponering på sina A-, B- och C-ytor. Detta för att kunden skall vilja stanna kvar i butiken och vilja utforska alla butikens ytor.
Program: Butikschef, textil och mode
Subjects/Keywords: Layout; butikskommunikation; exponering; Design; Design
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APA (6th Edition):
FOLKESSON, J. (2014). Butikskommunikation och layout. (Thesis). University of Borås. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-18010
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
FOLKESSON, JOSEFINE. “Butikskommunikation och layout.” 2014. Thesis, University of Borås. Accessed March 03, 2021.
http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-18010.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
FOLKESSON, JOSEFINE. “Butikskommunikation och layout.” 2014. Web. 03 Mar 2021.
Vancouver:
FOLKESSON J. Butikskommunikation och layout. [Internet] [Thesis]. University of Borås; 2014. [cited 2021 Mar 03].
Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-18010.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
FOLKESSON J. Butikskommunikation och layout. [Thesis]. University of Borås; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-18010
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Otago
14.
Galland, William.
Changing layout at Cableways - A project that investigates the process invoked-with changing Layout in a small- New Zealand business.
Degree: 2011, University of Otago
URL: http://hdl.handle.net/10523/1375
► This project is concerned with the process of initiating layout changes in a New Zealand business. The business that is being investigated, Cableways, operates a…
(more)
▼ This project is concerned with the process of initiating layout changes in a New Zealand business. The business that is being investigated, Cableways, operates a bar, a bottle store, a bistro and a gaming room. The bar and gaming room are the focus of this report in with regards to layout changes.
The process started with detailed planning and evaluation of the existing setting. A layout primitive was initially constructed that provided an insight into the current layout of the business. A model was then used to facilitate changes in layout. It began with establishing the likely future considerations that will impact on the operation of the business. The physical functions and their needs are determined from the layout primitive. The space requirements of each function are analysed before the relationship between the patrons that use them is discussed.
Using the original layout primitive of Cableways, and the information gathered above, four different designs were constructed. All four provided different scenarios of layout plans, with the aim of improving current layout. They were evaluated on their ability to meet certain requirements, and the most appropriate design was chosen. It is from this process that option three is recommended for the final step of the process, populating the layout.
There are three reasons why option three has been chosen. Firstly it better satisfies the needs of Cableways when compared to the other options. Secondly it meets the three critical aspects of layout decisions suggested in the literature of planning that is strategic, and in unison with the operations strategy. Thirdly the potential benefits to be gained from this option far out weigh the remaining three.
The design of option three (provided in figure 8) needs to be accurately reproduced to represent measurements and scale. From this a feasibility study can be undertaken to determine whether the option is suitable. If such a study does not identify any problems with the design, then it is recommended that construction begin at a time that is most suitable. The resulting changes should lead to a competitive advantage for Cableways.
Subjects/Keywords: Cableways;
layout;
layout primitive;
appropriate design
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APA ·
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MLA ·
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Export
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APA (6th Edition):
Galland, W. (2011). Changing layout at Cableways - A project that investigates the process invoked-with changing Layout in a small- New Zealand business.
(Masters Thesis). University of Otago. Retrieved from http://hdl.handle.net/10523/1375
Chicago Manual of Style (16th Edition):
Galland, William. “Changing layout at Cableways - A project that investigates the process invoked-with changing Layout in a small- New Zealand business.
” 2011. Masters Thesis, University of Otago. Accessed March 03, 2021.
http://hdl.handle.net/10523/1375.
MLA Handbook (7th Edition):
Galland, William. “Changing layout at Cableways - A project that investigates the process invoked-with changing Layout in a small- New Zealand business.
” 2011. Web. 03 Mar 2021.
Vancouver:
Galland W. Changing layout at Cableways - A project that investigates the process invoked-with changing Layout in a small- New Zealand business.
[Internet] [Masters thesis]. University of Otago; 2011. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/10523/1375.
Council of Science Editors:
Galland W. Changing layout at Cableways - A project that investigates the process invoked-with changing Layout in a small- New Zealand business.
[Masters Thesis]. University of Otago; 2011. Available from: http://hdl.handle.net/10523/1375
University of Michigan
15.
Chang, Kai-hui.
Functional design error diagnosis, correction and layout repair of digital circuits.
Degree: PhD, Electrical engineering, 2007, University of Michigan
URL: http://hdl.handle.net/2027.42/126892
► The dramatic increase in design complexity of modern circuits challenges our ability to verify their functional correctness. Therefore, circuits are often taped-out with functional errors,…
(more)
▼ The dramatic increase in
design complexity of modern circuits challenges our ability to verify their functional correctness. Therefore, circuits are often taped-out with functional errors, which may cause critical system failures and huge financial loss. While improvements in verification allow engineers to find more errors, fixing these errors remains a manual and challenging task, consuming valuable engineering resources that could have otherwise been used to improve verification and
design quality. In this dissertation we solve this problem by proposing innovative methods to automate the debugging process throughout the
design flow. We first observe that existing verification tools often focus exclusively on
error detection, without considering the effort required by
error repair. Therefore, they tend to generate tremendously long bug traces, making the debugging process extremely challenging. Hence, our first innovation is a bug trace minimizer that can remove most redundant information from a trace, thus facilitating debugging. To automate the
error repair process itself, we develop a novel framework that uses simulation to abstract the functionality of the circuit, and then rely on bug traces to guide the refinement of the abstraction. To strengthen the framework, we also propose a compact abstraction encoding using simulated values. This innovation not only integrates verification and debugging but also scales much further than existing solutions. We apply this framework to fix bugs both in gate-level and register-transfer-level circuits. However, we note that this solution is not directly applicable to post-silicon debugging because of the highly-restrictive physical constraints at this
design stage which allow only minimal perturbations of the silicon die. To address this challenge, we propose a set of comprehensive physically-
aware algorithms to generate a range of viable netlist and
layout transformations. We then select the most promising transformations according to the physical constraints. Finally, we integrate all these scalable
error-repair techniques into a framework called FogClear. Our empirical evaluation shows that FogClear can repair errors in a broad range of designs, demonstrating its ability to greatly reduce debugging effort, enhance
design quality, and ultimately enable the
design and manufacture of more reliable electronic devices.
Advisors/Committee Members: Markov, Igor L. (advisor), Bertacco, Valeria M. (advisor).
Subjects/Keywords: Debugging; Design; Digital; Error Correction; Error Diagnosis; Functional; Integrated Circuits; Layout Repair; Verification
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APA (6th Edition):
Chang, K. (2007). Functional design error diagnosis, correction and layout repair of digital circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/126892
Chicago Manual of Style (16th Edition):
Chang, Kai-hui. “Functional design error diagnosis, correction and layout repair of digital circuits.” 2007. Doctoral Dissertation, University of Michigan. Accessed March 03, 2021.
http://hdl.handle.net/2027.42/126892.
MLA Handbook (7th Edition):
Chang, Kai-hui. “Functional design error diagnosis, correction and layout repair of digital circuits.” 2007. Web. 03 Mar 2021.
Vancouver:
Chang K. Functional design error diagnosis, correction and layout repair of digital circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2007. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/2027.42/126892.
Council of Science Editors:
Chang K. Functional design error diagnosis, correction and layout repair of digital circuits. [Doctoral Dissertation]. University of Michigan; 2007. Available from: http://hdl.handle.net/2027.42/126892
Oklahoma State University
16.
De, Kanishka.
Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent.
Degree: Electrical Engineering, 2014, Oklahoma State University
URL: http://hdl.handle.net/11244/14796
► This work presents the design methodologies, considerations and practical implementation techniques of a sub-threshold/ moderate inversion variability aware Transmission Gate based digital cell library. The…
(more)
▼ This work presents the
design methodologies, considerations and practical implementation techniques of a sub-threshold/ moderate inversion variability
aware Transmission Gate based digital
cell library. The implementation method of a reduced ASIC
cell library containing minimum number of logic gates sufficient for further front end and back end processing is described. The proposed library targets a reduced implementation time and effort suitable for academic and industrial environment aiming minimum power consumption in battery less devices, portable electronic gadgets or wireless micro sensor networks where computation speed is not of prime concern. To the authors best knowledge, none of the literature till date demonstrates clearly and in a consolidated manner the applicability of T-Gate logic topology as a candidate for ultra-low power applications. Hence, a comparison is presented with equivalent low power CMOS logic gates. Circuit behavior can be significantly impacted due to MOSFET parameter variation. Clear simulation based measurement techniques are presented for measuring concerned parameters like input capacitance, Static Noise Margin(SNM) and IOFF of the T-Gate logic cells and compared with its CMOS equivalent at the same PVT corners. It is observed that the T-Gate shows lower normalized input capacitance than CMOS logic gates. A statistical analysis of logic failure is also presented along with its potential solutions for improvement. As compared to the CMOS gates, the T-Gate logic gates are found to demonstrate slightly narrower distribution of the switching threshold point(VTrip) when performed 200 point Monte Carlo simulation taking process variation and mismatch into account. The CMOS gates demonstrate better static noise margin and hence more robust than T-Gate logic
cell and suitable for lower supply voltage operation. A comparison of IOFF is presented to compare the static behavior of the two topologies. The details of device and gate sizing methodology are described along with necessary references. The library is characterized and abstracted to generate necessary files for further processing. A target system is synthesized and a seven stage ring oscillator is simulated in both topologies and is compared to make conclusion based on the observations. T-Gate logic cells demonstrate better static behavior but outperformed by its CMOS logic equivalent in terms of energy consumed per cycle within the range of VDDD from 400mV to 600mV. T-Gate logic gates are slower than its CMOS counterpart at any VDDD of operation and insignificant improvement is achieved with increasing power supply.
Advisors/Committee Members: Hutchens, Chris (advisor), Johnson, Louis G. (committee member), Latino, Carl D. (committee member).
Subjects/Keywords: robust cell library; sub-threshold/ moderate inversion; t-gate and cmos topology; ultra low power; variability aware design; vlsi/ circuit design
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Export
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Manager
APA (6th Edition):
De, K. (2014). Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/14796
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
De, Kanishka. “Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent.” 2014. Thesis, Oklahoma State University. Accessed March 03, 2021.
http://hdl.handle.net/11244/14796.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
De, Kanishka. “Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent.” 2014. Web. 03 Mar 2021.
Vancouver:
De K. Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent. [Internet] [Thesis]. Oklahoma State University; 2014. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/11244/14796.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
De K. Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent. [Thesis]. Oklahoma State University; 2014. Available from: http://hdl.handle.net/11244/14796
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
17.
Tsai, Ming-Yu.
An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.
Degree: PhD, Computer Science and Engineering, 2009, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529
► The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic…
(more)
▼ The mainstream of current VLSI
design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic circuit
design styles based on pass-
transistor logic (PTL) have been proposed. Compared with CMOS circuits, these PTL-based circuits are claimed to have better results in area, speed, and power in some particular applications, such as adder and multiplier designs. Since most current automatic logic synthesis tools (such as Synopsys
Design Compiler) are based on conventional CMOS standard
cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this dissertation, we develop two novel PTL synthesizers that can efficiently generate PTL-based circuits. One is based on pure PTL cells; the other mixes CMOS and PTL cells in the standard
cell library to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated to
design large SoC systems as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flows employ the popular Synopsys
Design Compiler (DC) to perform logic translation and minimization based on the standard
cell library composed of PTL and CMOS cells, thus, the PTL
design flow can be easily embedded in the standard
cell-based ASIC
design flow. In this dissertation, we also discuss PTL-based designs of some fundamental hardware components. Furthermore, the proposed PTL
cell library is used to synthesize large processor systems in applications of computer arithmetic and 3D graphics.
Advisors/Committee Members: Bin-Da Liu (chair), Tso-Bing Juang (committee member), Shen-Fu Hsiao (committee member), Pei-Yin Chen (chair), Yuan-Sun Chu (chair), Chen-Hao Chang (chair), Yu-Jung Huang (chair).
Subjects/Keywords: 3D Graphics Processors; Arithmetic Units; Standard Cell Library; ASIC Cell-Based Design Flow; Logic Synthesizer; Pass-Transistor-Logic (PTL); CMOS logic
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APA ·
Chicago ·
MLA ·
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CSE |
Export
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Manager
APA (6th Edition):
Tsai, M. (2009). An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529
Chicago Manual of Style (16th Edition):
Tsai, Ming-Yu. “An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.” 2009. Doctoral Dissertation, NSYSU. Accessed March 03, 2021.
http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529.
MLA Handbook (7th Edition):
Tsai, Ming-Yu. “An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.” 2009. Web. 03 Mar 2021.
Vancouver:
Tsai M. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. [Internet] [Doctoral dissertation]. NSYSU; 2009. [cited 2021 Mar 03].
Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529.
Council of Science Editors:
Tsai M. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. [Doctoral Dissertation]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529
University of Illinois – Urbana-Champaign
18.
Wang, Curtis Yilin.
High-speed characterizations of single quantum-well transistor laser.
Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign
URL: http://hdl.handle.net/2142/89158
► The transistor laser (TL) is a unique three-terminal semiconductor laser device that possesses qualities and functionalities that cannot be achieved by diode lasers alone. In…
(more)
▼ The
transistor laser (TL) is a unique three-terminal semiconductor laser device that possesses qualities and functionalities that cannot be achieved by diode lasers alone. In this thesis, the history of development and device structure, as well as the carrier dynamics in the TL will be first presented to provide background discussion. The focus of this thesis will be on the methods of high-speed characterizations on TLs and data of the optical modulation bandwidth, f-3dB, and
error-free data transmission.
Advisors/Committee Members: Feng, Milton (advisor).
Subjects/Keywords: Transistor Laser; Bit Error Ration Testing
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APA (6th Edition):
Wang, C. Y. (2015). High-speed characterizations of single quantum-well transistor laser. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89158
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Wang, Curtis Yilin. “High-speed characterizations of single quantum-well transistor laser.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed March 03, 2021.
http://hdl.handle.net/2142/89158.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Wang, Curtis Yilin. “High-speed characterizations of single quantum-well transistor laser.” 2015. Web. 03 Mar 2021.
Vancouver:
Wang CY. High-speed characterizations of single quantum-well transistor laser. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/2142/89158.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Wang CY. High-speed characterizations of single quantum-well transistor laser. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89158
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
19.
Ericson, Jessica.
Har den digitala pizzamenyn en genomtänkt stil? : En analys av lågprispizzeriors design av menyer.
Degree: Information Systems, 2020, Dalarna University
URL: http://urn.kb.se/resolve?urn=urn:nbn:se:du-34252
► Det finns studier som anger rekommendationer för att designa en väl utformad restaurangmeny. Syftet med rapporten är att undersöka om pizzeriapersonal och formgivare designar…
(more)
▼ Det finns studier som anger rekommendationer för att designa en väl utformad restaurangmeny. Syftet med rapporten är att undersöka om pizzeriapersonal och formgivare designar digitala pizzamenyer genom medvetna val utifrån de designprinciper och designrekommendationer som finns. Undersökningen är ett kvalitativt forskningsarbete där kartläggning har använts som strategi. Datainsamlingsmetoderna som har använts är litteratursökning, visuell innehållsanalys, gruppintervjuer och semistrukturerade intervjuer för att kunna besvara frågeställningarna. Resultaten från undersökningen påvisar bland annat att pizzeriapersonalen anser att deras menydesign inte överensstämmer med varumärket. Personalen och kunderna har även olika uppfattningar om vad varumärkena står för. Trots att pizzeriornas varumärke inte stämmer överens med designen uppfyller menyerna kundernas förväntan. Slutsatserna visar bland annat att det finns gemensamma och särskiljande grafiska element. De flesta lågprispizzerior har inte ett genomtänkt varumärke samt att det inte finns en medvetenhet angående de designprinciper och designrekommendationerna hos pizzeriapersonal eller formgivare.
For the creation of restaurant menus there are studies that show which recommendations you should use to achieve a well-designed menu. The purpose of the study is to investigate whether pizzeria personnel and designers create digital pizza menus consciously from the design recommendations that exists. This study is a qualitative research work and we have used a survey as strategy. Data collection methods that have been used to answer the study questions are literature search, a visual content analysis, group interviews and semi-structured interviews. One result from the interviews showed that the pizzeria personnel thinks that their menu design does not match their brand. The pizzeria personnel and customers have different perceptions about what the brand stands for. The group interviews show that the digital menus live up to customers expectation and their experience of the low-price pizza. The conclusions show that there are common and distinctive graphical elements. Most low-price pizzerias do not have a well thought out branding, although the pizzeria personnel and designers do not have consciousness regarding the design principles and recommendations.
Subjects/Keywords: Branding; brand identity; contrasts; design; gestalt laws; graphic elements; icons; images; layout; pizzeria; positioning; typography; Bilder; dekorelement; design; gestaltlagar; ikoner; kontraster; layout; meny; pizzeria; positionering; typografi; varumärke; varumärkesidentitet.; Information Systems; Systemvetenskap, informationssystem och informatik
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APA (6th Edition):
Ericson, J. (2020). Har den digitala pizzamenyn en genomtänkt stil? : En analys av lågprispizzeriors design av menyer. (Thesis). Dalarna University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:du-34252
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Ericson, Jessica. “Har den digitala pizzamenyn en genomtänkt stil? : En analys av lågprispizzeriors design av menyer.” 2020. Thesis, Dalarna University. Accessed March 03, 2021.
http://urn.kb.se/resolve?urn=urn:nbn:se:du-34252.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Ericson, Jessica. “Har den digitala pizzamenyn en genomtänkt stil? : En analys av lågprispizzeriors design av menyer.” 2020. Web. 03 Mar 2021.
Vancouver:
Ericson J. Har den digitala pizzamenyn en genomtänkt stil? : En analys av lågprispizzeriors design av menyer. [Internet] [Thesis]. Dalarna University; 2020. [cited 2021 Mar 03].
Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:du-34252.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Ericson J. Har den digitala pizzamenyn en genomtänkt stil? : En analys av lågprispizzeriors design av menyer. [Thesis]. Dalarna University; 2020. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:du-34252
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Loughborough University
20.
Carreira, Joao F. M.
Error resilience and concealment techniques for high-efficiency video coding.
Degree: PhD, 2018, Loughborough University
URL: http://hdl.handle.net/2134/36613
► This thesis investigates the problem of robust coding and error concealment in High Efficiency Video Coding (HEVC). After a review of the current state of…
(more)
▼ This thesis investigates the problem of robust coding and error concealment in High Efficiency Video Coding (HEVC). After a review of the current state of the art, a simulation study about error robustness, revealed that the HEVC has weak protection against network losses with significant impact on video quality degradation. Based on this evidence, the first contribution of this work is a new method to reduce the temporal dependencies between motion vectors, by improving the decoded video quality without compromising the compression efficiency. The second contribution of this thesis is a two-stage approach for reducing the mismatch of temporal predictions in case of video streams received with errors or lost data. At the encoding stage, the reference pictures are dynamically distributed based on a constrained Lagrangian rate-distortion optimization to reduce the number of predictions from a single reference. At the streaming stage, a prioritization algorithm, based on spatial dependencies, selects a reduced set of motion vectors to be transmitted, as side information, to reduce mismatched motion predictions at the decoder. The problem of error concealment-aware video coding is also investigated to enhance the overall error robustness. A new approach based on scalable coding and optimally error concealment selection is proposed, where the optimal error concealment modes are found by simulating transmission losses, followed by a saliency-weighted optimisation. Moreover, recovery residual information is encoded using a rate-controlled enhancement layer. Both are transmitted to the decoder to be used in case of data loss. Finally, an adaptive error resilience scheme is proposed to dynamically predict the video stream that achieves the highest decoded quality for a particular loss case. A neural network selects among the various video streams, encoded with different levels of compression efficiency and error protection, based on information from the video signal, the coded stream and the transmission network. Overall, the new robust video coding methods investigated in this thesis yield consistent quality gains in comparison with other existing methods and also the ones implemented in the HEVC reference software. Furthermore, the trade-off between coding efficiency and error robustness is also better in the proposed methods.
Subjects/Keywords: HEVC; Error resilience; Error concealment; Reference frame selection; Concealment-aware resilience
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APA (6th Edition):
Carreira, J. F. M. (2018). Error resilience and concealment techniques for high-efficiency video coding. (Doctoral Dissertation). Loughborough University. Retrieved from http://hdl.handle.net/2134/36613
Chicago Manual of Style (16th Edition):
Carreira, Joao F M. “Error resilience and concealment techniques for high-efficiency video coding.” 2018. Doctoral Dissertation, Loughborough University. Accessed March 03, 2021.
http://hdl.handle.net/2134/36613.
MLA Handbook (7th Edition):
Carreira, Joao F M. “Error resilience and concealment techniques for high-efficiency video coding.” 2018. Web. 03 Mar 2021.
Vancouver:
Carreira JFM. Error resilience and concealment techniques for high-efficiency video coding. [Internet] [Doctoral dissertation]. Loughborough University; 2018. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/2134/36613.
Council of Science Editors:
Carreira JFM. Error resilience and concealment techniques for high-efficiency video coding. [Doctoral Dissertation]. Loughborough University; 2018. Available from: http://hdl.handle.net/2134/36613
NSYSU
21.
Hsu, Ting-pi.
Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density.
Degree: Master, Electrical Engineering, 2017, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154234
► In this thesis, we propose a vertical channel non-classical CMOS (VNCCMOS) with low power dissipation and high integration density. Junctionless transistor and punch through transistor…
(more)
▼ In this thesis, we propose a vertical channel non-classical CMOS (VNCCMOS) with low power dissipation and high integration density. Junctionless
transistor and punch
through transistor replaced conventional NMOS and PMOS respectively in our structure for use in low power supply systems. The operating mechanisms of respective junctionless
transistor (JLMOS) and punch
through transistor (PTMOS) are further analyzed in depth. The threshold voltage (VTH) and the flat-band voltage (VFB) are used in JLMOS and PTMOS respectively.
This VNCCMOS circuit achieves subthreshold swing = 66 mV/dec and 67 mV/dec of Q1 junctionless
transistor and Q2 punch
through transistor respectively. Both transistorsâs ION/IOFF can be close to 104 at power supply VD = 0.3 V. The VNCCMOS obtain low power dissipation (PD) = 2.01 nW. The power delay product of VNCCMOS is better than conventional planar CMOS (CMOS) and planar non-classical CMOS (NCCMOS). The VNCCMOS with vertical channel is good for scaling down. Our structure can reduced the
layout area by 56.5 % compared with conventional CMOS inverter. The VNCCMOS reaches low power dissipation and high integration density.
Advisors/Committee Members: Jyi-Tsong Lin (committee member), Chee-Wee Liu (chair), Jinn-Shyan Wang (chair), Kow-Ming Chang (chair), Feng-Der Chin (chair).
Subjects/Keywords: CMOS; punch through transistor; junctionless transistor; high integration density; low power dissipation; vertical channel
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APA (6th Edition):
Hsu, T. (2017). Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154234
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Hsu, Ting-pi. “Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density.” 2017. Thesis, NSYSU. Accessed March 03, 2021.
http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154234.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Hsu, Ting-pi. “Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density.” 2017. Web. 03 Mar 2021.
Vancouver:
Hsu T. Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Mar 03].
Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154234.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Hsu T. Vertical Channel Non-Classical CMOS with Low Power Dissipation and High Integration Density. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716117-154234
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Brno University of Technology
22.
Svorad, Adam.
Audio zesilovač ve třídě D pro laboratorní výuku: Class D audio amplifier for laboratory measurements.
Degree: 2018, Brno University of Technology
URL: http://hdl.handle.net/11012/81763
► Bachelor’s thesis delves into a field of Class-D audio amplifiers. Keystone part of the work summarizes theoretical knowledge focused on measuring techniques of lowfrequency amplifiers…
(more)
▼ Bachelor’s thesis delves into a field of Class-D audio amplifiers. Keystone part of the work summarizes theoretical knowledge focused on measuring techniques of lowfrequency amplifiers and audio amplifier
design. A deeper insight into building blocks of a general Class-D amplifier is also presented. Gained erudition is applied in the second part, which is devoted to a construction of the device. Exceptional attention is drawn to the
design of robust external driver and sophisticated output analog filter. Blueprints required for a PBC
layout are provided as well as outputs of performance measurements taken of a fabricated prototype.
Advisors/Committee Members: Kratochvíl, Tomáš (advisor), Petržela, Jiří (referee).
Subjects/Keywords: Meranie parametrov audio zosilňovačov; triedy zosilňovačov; zosilňovač v triede D; návrh dolnej priepusti; ochranné obvody proti shoot-through efektu; návrh DPS; Audio amplifier performance measurements; power classes; Class-D amplifier; low-pass filter design; shoot-through protection circuits; PCB layout
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APA ·
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APA (6th Edition):
Svorad, A. (2018). Audio zesilovač ve třídě D pro laboratorní výuku: Class D audio amplifier for laboratory measurements. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/81763
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Svorad, Adam. “Audio zesilovač ve třídě D pro laboratorní výuku: Class D audio amplifier for laboratory measurements.” 2018. Thesis, Brno University of Technology. Accessed March 03, 2021.
http://hdl.handle.net/11012/81763.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Svorad, Adam. “Audio zesilovač ve třídě D pro laboratorní výuku: Class D audio amplifier for laboratory measurements.” 2018. Web. 03 Mar 2021.
Vancouver:
Svorad A. Audio zesilovač ve třídě D pro laboratorní výuku: Class D audio amplifier for laboratory measurements. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/11012/81763.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Svorad A. Audio zesilovač ve třídě D pro laboratorní výuku: Class D audio amplifier for laboratory measurements. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/81763
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Georgia Tech
23.
Diril, Abdulkadir Utku.
Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic.
Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech
URL: http://hdl.handle.net/1853/6929
► Technology scaling trends lead to shrinking of the individual elements like transistors and wires in digital systems. The main driving force behind this is cutting…
(more)
▼ Technology scaling trends lead to shrinking of the individual elements like transistors and wires in digital systems. The main driving force behind this is cutting the cost of the systems while the systems are filled with extra functionalities. This is the reason why a 3 GHz Intel processor now is priced less than what a 50MHz processor was priced 10 years ago. As in most cases, this comes with a price. This price is the complex
design process and problems that stem from the reduction in physical dimensions.
As the transistors became smaller in size and the systems became faster, issues like power consumption, signal integrity, soft
error tolerance, and testing became serious challenges. There is an increasing demand to put CAD tools in the
design flow to address these issues at every step of the
design process. First part of this research investigates circuit level techniques to reduce power consumption in digital systems. In second part, improving soft
error tolerance of digital systems is considered as a trade off problem between power and reliability and a power
aware dynamic soft
error tolerance control strategy is developed.
The objective of this research is to provide CAD tools and circuit
design techniques to optimize power consumption and to increase soft
error tolerance of digital circuits. Multiple supply and threshold voltages are used to reduce power consumption. Variable supply and threshold voltages are used together with variable capacitances to develop a dynamic soft
error tolerance control scheme.
Advisors/Committee Members: Abhijit Chatterjee (Committee Chair), Adit D. Singh (Committee Member), Hsien-Hsin S. Lee (Committee Member), Madhavan Swaminathan (Committee Member), Vijay K. Madisetti (Committee Member).
Subjects/Keywords: Low-power; Digital design; Dual threshold; Dual supply; Soft error tolerance
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Manager
APA (6th Edition):
Diril, A. U. (2005). Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6929
Chicago Manual of Style (16th Edition):
Diril, Abdulkadir Utku. “Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic.” 2005. Doctoral Dissertation, Georgia Tech. Accessed March 03, 2021.
http://hdl.handle.net/1853/6929.
MLA Handbook (7th Edition):
Diril, Abdulkadir Utku. “Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic.” 2005. Web. 03 Mar 2021.
Vancouver:
Diril AU. Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic. [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/1853/6929.
Council of Science Editors:
Diril AU. Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic. [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6929
Linköping University
24.
Klevbrink, Anna-Charlotta.
Evaluation of Aptivia and a Place and Route tool.
Degree: Electrical Engineering, 2005, Linköping University
URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3768
► This master thesis tells about Aptivia, what it contains and how i works (inluding a manual). As well as problems with it. It also…
(more)
▼ This master thesis tells about Aptivia, what it contains and how i works (inluding a manual). As well as problems with it. It also consists of an evaluation of a Place and Route tool, telling the discovered problems with it and ideas for solving them.There is also several different descriptions of the code that implements the Place and Route tool.
Subjects/Keywords: Aptivia; manual; standard cell; design automation; layout; Electronics; Elektronik
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APA (6th Edition):
Klevbrink, A. (2005). Evaluation of Aptivia and a Place and Route tool. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3768
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Klevbrink, Anna-Charlotta. “Evaluation of Aptivia and a Place and Route tool.” 2005. Thesis, Linköping University. Accessed March 03, 2021.
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3768.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Klevbrink, Anna-Charlotta. “Evaluation of Aptivia and a Place and Route tool.” 2005. Web. 03 Mar 2021.
Vancouver:
Klevbrink A. Evaluation of Aptivia and a Place and Route tool. [Internet] [Thesis]. Linköping University; 2005. [cited 2021 Mar 03].
Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3768.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Klevbrink A. Evaluation of Aptivia and a Place and Route tool. [Thesis]. Linköping University; 2005. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3768
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
25.
Chang, Hsu-Kuang.
An Improved Scheme for Sensor Alignment Calibration of Ultra Short Baseline Positioning Systems.
Degree: Master, IAMPUT, 2009, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809109-233755
► This study proposed a numerical algorithm for estimating the angular misalignments between sensors of an ultra short baseline (USBL) positioning system. The algorithm is based…
(more)
▼ This study proposed a numerical algorithm for estimating the angular misalignments between sensors of an ultra short baseline (USBL)
positioning system. The algorithm is based on
positioning a seabed transponder by moving a vessel along a predetermined straight-line path. Under the scheme of straight-line survey, mathematical representations of
positioning error arising from heading, pitch, and roll misalignments were derived, respectively. The effect of each misalignment angle and how the differences can be used to calibrate each misalignment angle in turn are presented. A USBL calibration procedure that takes advantage of the geometry of position errors resulting from angular misalignments is then developed. During the USBL measurement, temporal and spatial variations of sound speed structure in water column are the major
error sources. Therefore, this study used the sound speed profile together with a ray tracing method to correct observations of the USBL measurement. In addition, this study developed a method to compensate the effects of cross-track
error on the estimation of alignment errors, and this makes the proposed algorithm applicable for using a vessel without dynamic
positioning (DP) systems to collect USBL observations. The performance of the algorithm is evaluated
through simulation and field experiment. The simulation and experimental results have demonstrated the effectiveness and robustness of the iterative scheme in finding alignment errors. The proposed algorithm yields a very rapid convergence of the solution series; usually the estimates obtained in the first iteration approximate to true values, and only a few iterations are necessary to achieve fairly accurate solutions.
Advisors/Committee Members: Shiahn-Wern Shyue (chair), Hsin-Hung Chen (committee member), Chau-Chang Wang (chair).
Subjects/Keywords: Alignment error; USBL; Iterative scheme; Positioning
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Manager
APA (6th Edition):
Chang, H. (2009). An Improved Scheme for Sensor Alignment Calibration of Ultra Short Baseline Positioning Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809109-233755
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Chang, Hsu-Kuang. “An Improved Scheme for Sensor Alignment Calibration of Ultra Short Baseline Positioning Systems.” 2009. Thesis, NSYSU. Accessed March 03, 2021.
http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809109-233755.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Chang, Hsu-Kuang. “An Improved Scheme for Sensor Alignment Calibration of Ultra Short Baseline Positioning Systems.” 2009. Web. 03 Mar 2021.
Vancouver:
Chang H. An Improved Scheme for Sensor Alignment Calibration of Ultra Short Baseline Positioning Systems. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Mar 03].
Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809109-233755.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Chang H. An Improved Scheme for Sensor Alignment Calibration of Ultra Short Baseline Positioning Systems. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809109-233755
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
26.
Valadimas, Stefanos.
Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες.
Degree: 2016, National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ)
URL: http://hdl.handle.net/10442/hedi/38222
► As technology scales down, timing errors are a real concern in high complexity and high frequency integrated circuits. Process, Voltage and Temperature variations lead to…
(more)
▼ As technology scales down, timing errors are a real concern in high complexity and high frequency integrated circuits. Process, Voltage and Temperature variations lead to large spreads in delay, at the system level, which undermine circuit’s reliability. Moreover, crosstalk, power supply disturbances and resistive IR-drop or inductance IL-drop affect circuit performance increasing the overall impact of timing errors. In addition, aging mechanisms cause gradual speed degradation of the designs over their service life. In this context, it is evident that timing error tolerance techniques are becoming necessary to provide robustness against timing violations and meet system reliability requirements. This thesis presents three concurrent on-line timing error tolerance techniques which enhance circuit’s reliability. The first technique is applied on pipelines which support off-line scan testing. It provides timing error tolerance by exploiting the existing multiplexer in the scan flip-flops. The second technique utilizes a comparator for timing error detection and an additional memory element for storing the error indication. The correction is succeeded by bit-flipping the data stored in the protected flip-flop. The last enhanced technique is based on a transition detector for detecting the delayed responses and an asynchronous local error correction scheme which has no need of additional memory elements or metastability detectors, as in the earlier proposed solutions. To validate the three techniques, they have been applied in the design of a 32-bit MIPS R2000 pipeline microprocessor. The protected microprocessor with the enhanced technique was fabricated in the 65nm Low Leakage technology of UMC, through the ASIC prototyping program offered by the EUROPRACTICE IC Service. Post-layout simulations of the microprocessor design, FPGA-based emulations and experimental results on the fabricated chip, show that the proposed techniques detect and correct the generated timing errors efficiently with low power consumption and low silicon area overhead.
Η κλιμάκωση της τεχνολογίας καθιστά ιδιαίτερα σημαντική την επίδραση των λαθών χρονισμού στα ολοκληρωμένα κυκλώματα μεγάλης πολυπλοκότητας και υψηλής συχνότητας. Οι διακυμάνσεις της κατασκευαστικής διαδικασίας, της τάσης και της θερμοκρασίας οδηγούν σε μεγάλες αποκλίσεις στις καθυστερήσεις, σε επίπεδο συστήματος, οι οποίες υπονομεύουν την αξιοπιστία των κυκλωμάτων. Επίσης, η αλληλεπίδραση μεταξύ των σημάτων, οι διαταραχές στην τροφοδοσία ισχύος και η αντιστατική/επαγωγική πτώση της τάσης στην τροφοδοσία, επηρεάζουν την απόδοση των συστημάτων, αυξάνοντας την συνολική επίπτωση των λαθών χρονισμού. Επιπρόσθετα, μηχανισμοί γήρανσης προκαλούν σταδιακή μείωση της ταχύτητας των κυκλωμάτων κατά τη διάρκεια της λειτουργίας τους. Υπό αυτές τις συνθήκες, είναι προφανές ότι οι τεχνικές που παρέχουν ανεκτικότητα σε λάθη χρονισμού καθίστανται αναγκαίες καθώς προσφέρουν ανθεκτικότητα έναντι των σφαλμάτων χρονισμού και ικανοποιούν τις προδιαγραφές αξιοπιστίας των συστημάτων. Στo πλαίσιο της…
Subjects/Keywords: εν λειτουργία έλεγχος ορθής λειτουργίας; λάθη χρονισμού; Ανίχνευση λαθών; ανθεκτικότητα σε λάθη χρονισμού; σχεδίαση αξιόπιστων συστημάτων; Διόρθωση λαθών; On-line testing; timing errors; Error detection; timing error tolerance; reliability-aware design; Error correction
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APA (6th Edition):
Valadimas, S. (2016). Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες. (Thesis). National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ). Retrieved from http://hdl.handle.net/10442/hedi/38222
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Valadimas, Stefanos. “Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες.” 2016. Thesis, National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ). Accessed March 03, 2021.
http://hdl.handle.net/10442/hedi/38222.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Valadimas, Stefanos. “Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες.” 2016. Web. 03 Mar 2021.
Vancouver:
Valadimas S. Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες. [Internet] [Thesis]. National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ); 2016. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/10442/hedi/38222.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Valadimas S. Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες. [Thesis]. National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ); 2016. Available from: http://hdl.handle.net/10442/hedi/38222
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
27.
ZHENG HUANHUAN.
DESIGN AND ANALYSIS OF VISIBLE LIGHT COMMUNICATION AND POSITIONING SYSTEMS.
Degree: 2017, National University of Singapore
URL: http://scholarbank.nus.edu.sg/handle/10635/136048
Subjects/Keywords: LED arrangement design; visible light communication; error correcting algorithm; positioning error; visible light positioning; asynchronous CDMA
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APA (6th Edition):
HUANHUAN, Z. (2017). DESIGN AND ANALYSIS OF VISIBLE LIGHT COMMUNICATION AND POSITIONING SYSTEMS. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/136048
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
HUANHUAN, ZHENG. “DESIGN AND ANALYSIS OF VISIBLE LIGHT COMMUNICATION AND POSITIONING SYSTEMS.” 2017. Thesis, National University of Singapore. Accessed March 03, 2021.
http://scholarbank.nus.edu.sg/handle/10635/136048.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
HUANHUAN, ZHENG. “DESIGN AND ANALYSIS OF VISIBLE LIGHT COMMUNICATION AND POSITIONING SYSTEMS.” 2017. Web. 03 Mar 2021.
Vancouver:
HUANHUAN Z. DESIGN AND ANALYSIS OF VISIBLE LIGHT COMMUNICATION AND POSITIONING SYSTEMS. [Internet] [Thesis]. National University of Singapore; 2017. [cited 2021 Mar 03].
Available from: http://scholarbank.nus.edu.sg/handle/10635/136048.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
HUANHUAN Z. DESIGN AND ANALYSIS OF VISIBLE LIGHT COMMUNICATION AND POSITIONING SYSTEMS. [Thesis]. National University of Singapore; 2017. Available from: http://scholarbank.nus.edu.sg/handle/10635/136048
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Washington State University
28.
[No author].
WHAT DOES THE ARCHITECTURAL CREATIVE LEAP LOOK LIKE THROUGH A CONCEPTUAL DESIGN PHASE IN THE UNDERGRADUATE ARCHITECTURAL DESIGN STUDIO?
.
Degree: 2012, Washington State University
URL: http://hdl.handle.net/2376/4163
► The creative leap is a mental creative moment in which one discovers and illustrates a new design idea, or restructures and develops an old one.…
(more)
▼ The creative
leap is a mental creative moment in which one discovers and illustrates a new
design idea, or restructures and develops an old one. It gives birth to the
design continuity and adds fluidity to the
design concept. There are different views about the creative
leap and its holistic view remains unresolved and undiscovered. This research was conducted to answer these related questions: what does the creative
leap look like
through a conceptual
design phase?; what are the factors that might facilitate the creative
leap?; and what are the relationships/interrelationships between these factors? The protocol analysis of 10
design experiments was used mainly to collect two types of data. The first was visual or graphical data (drawing and writing), which was scored by six professional architectural
design instructors with respect to the divergent thinking factors. The verbal data (talking) was transcribed, analyzed, segmented, and coded by using a Limited Commitment Mode (LCM) control strategy to elicit the qualitative and quantitative value for the rest of the factors. The Pearson product-moment correlation coefficient (Pearson r) was computed to assess the degree of association between all the factors. The results from this study show that the creative
leap is a sudden mental insight that comes as a result of structuring the
design knowledge cycle. It arises several times to create a new
design idea or develop an existing one toward a final solution. Further, the total content of creative leaps comprise the final contents of the
design concept. The creative
leap no longer relies on talent or chance alone; it can be taught, learned, and developed by education to enhance
design thinking. Moreover, an increase in creative leaps is associated with increases in each of the following factors: the architectural
design education level, divergent thinking variables, the total number of sub-
design modules, the total number of
design decisions, creativity indicators, lateral thinking approaches, structuring of
design knowledge cycle, the level of expertise,
design proficiency, and the level of
design cognition. Additionally, there is no relationship between the creative
leap and each of the following factors: age, gender, and verbal fluency rate.
Advisors/Committee Members: Wang, David (advisor).
Subjects/Keywords: Architecture;
Design;
architectural design education;
conceptual design;
Creative leap;
creativity;
design decisions;
design knowledge
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APA ·
Chicago ·
MLA ·
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CSE |
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Manager
APA (6th Edition):
author], [. (2012). WHAT DOES THE ARCHITECTURAL CREATIVE LEAP LOOK LIKE THROUGH A CONCEPTUAL DESIGN PHASE IN THE UNDERGRADUATE ARCHITECTURAL DESIGN STUDIO?
. (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/4163
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
author], [No. “WHAT DOES THE ARCHITECTURAL CREATIVE LEAP LOOK LIKE THROUGH A CONCEPTUAL DESIGN PHASE IN THE UNDERGRADUATE ARCHITECTURAL DESIGN STUDIO?
.” 2012. Thesis, Washington State University. Accessed March 03, 2021.
http://hdl.handle.net/2376/4163.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
author], [No. “WHAT DOES THE ARCHITECTURAL CREATIVE LEAP LOOK LIKE THROUGH A CONCEPTUAL DESIGN PHASE IN THE UNDERGRADUATE ARCHITECTURAL DESIGN STUDIO?
.” 2012. Web. 03 Mar 2021.
Vancouver:
author] [. WHAT DOES THE ARCHITECTURAL CREATIVE LEAP LOOK LIKE THROUGH A CONCEPTUAL DESIGN PHASE IN THE UNDERGRADUATE ARCHITECTURAL DESIGN STUDIO?
. [Internet] [Thesis]. Washington State University; 2012. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/2376/4163.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
author] [. WHAT DOES THE ARCHITECTURAL CREATIVE LEAP LOOK LIKE THROUGH A CONCEPTUAL DESIGN PHASE IN THE UNDERGRADUATE ARCHITECTURAL DESIGN STUDIO?
. [Thesis]. Washington State University; 2012. Available from: http://hdl.handle.net/2376/4163
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
NSYSU
29.
Chang, Yu-Wei.
Implementation of the broadband Power Line Communication system.
Degree: Master, Computer Science and Engineering, 2015, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0309115-161048
► Digital home has been mentioned a lot in recent years. We can connect appliances through the internet to provide new services such as home care,…
(more)
▼ Digital home has been mentioned a lot in recent years. We can connect appliances
through the internet to provide new services such as home care, digital entertainment, power management, and home safety, etc. Power Line Communication plays an important role in it. Power Line Communication uses the existing wires to transmit data, so there is no need to put extra wires. This thesis uses
cell-based
design flow to implement the broadband Power Line Communication system. The transmitter includes scrambler, convolutional encoder, block interleaver, quadrature amplitude modulator, and add cyclic prefix. The receiver includes remove cyclic prefix, quadrature amplitude demodulator, block deinterleaver, convolutional decoder, and descrambler. The experiment result shows that under different noisy channel, this
design still has
error correction ability. When signal to noise ratio is 0dB, bit
error rate is 0.457. When signal to noise ratio is 10dB, bit
error rate is 0.0001. This thesis uses TSMC 90nm process. The total area is 94188 um2, the power dissipation is 8.85mW.
Advisors/Committee Members: Tong-Yu Hsieh (chair), Ko-Chi Kuo (committee member), Shiann-Rong Kuang (chair), Katherine Shu-Min Li (chair).
Subjects/Keywords: block interleaver; quadrature amplitude modulation; Power Line Communication; error correcting code; cell-based design flow
Record Details
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Record Details
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❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Chang, Y. (2015). Implementation of the broadband Power Line Communication system. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0309115-161048
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Chang, Yu-Wei. “Implementation of the broadband Power Line Communication system.” 2015. Thesis, NSYSU. Accessed March 03, 2021.
http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0309115-161048.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Chang, Yu-Wei. “Implementation of the broadband Power Line Communication system.” 2015. Web. 03 Mar 2021.
Vancouver:
Chang Y. Implementation of the broadband Power Line Communication system. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Mar 03].
Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0309115-161048.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Chang Y. Implementation of the broadband Power Line Communication system. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0309115-161048
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
30.
Marzaki, Abderrezak.
Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS : Development of innovative manufacturing process techniques and a new MOS transistor architecture.
Degree: Docteur es, Micro et Nanoélectronique, 2013, Aix Marseille Université
URL: http://www.theses.fr/2013AIXM4768
► La miniaturisation des composants et l’amélioration des performances des circuits intégrés (ICs) sont dues aux progrès liés au procédé de fabrication. Malgré le nombre de…
(more)
▼ La miniaturisation des composants et l’amélioration des performances des circuits intégrés (ICs) sont dues aux progrès liés au procédé de fabrication. Malgré le nombre de technologie existante, la technologie CMOS est la plus utilisée. Dans le cadre du développement de la technologie CMOS 90nm à double niveau de poly, des recherches sur l’introduction de techniques innovantes de procédé de fabrication et d’une nouvelle architecture de transistor MOS à tension de seuil ajustable ont été menées dans le but d’améliorer les performances des ICs. Une première étude sur l’implémentation des effets de pointe dans les ICs, en particulier pour les mémoires non volatiles est entreprise. Un nouveau procédé de fabrication permettant d’obtenir des pointes dans un matériau est proposé. Il est démontré le gain en courant tunnel obtenu sur une structure pointue par rapport à une structure plane. Une seconde étude est orientée sur le développement d’une nouvelle technique de « patterning ». Les techniques de « patterning » permettent de réduire les dimensions de la photolithographie sans utiliser de masque ayant des dimensions agressives. Les avantages de cette nouvelle technique aux niveaux de sa mise en œuvre et de la suppression des problèmes d’alignement sont présentés. Une dernière étude sur le développement d’un transistor à tension de seuil ajustable est développée. Il est démontré l’avantage de ce composant par rapport aux autres composants à tension de seuil ajustable. La réalisation du modèle et des premières simulations électriques de circuit élémentaire à base de se composant sont présentés. L’amélioration de certaines performances des circuits élémentaire est démontrée.
The component miniaturization and the circuit performance improvement are due to the progress related to the manufacturing process. Despite the number of existing technology, the CMOS technology is the most used. In the 90nm CMOS technology development, with a double poly-silicon level, the research on the introduction of innovative manufacturing process techniques and a new architecture of MOS transistor with an adjustable threshold voltage are carried out to improve the integrated circuit performances. A first study, on the peak effect implementation in the integrated circuits, particularly in the non-volatile memories is undertaken. A new process to obtain a peak effect in a material is proposed. It is shown the tunnel current gain obtained on a peak structure compared with a planar structure. A second study is focused on the development of a new patterning technique. The patterning techniques allow to reduce the photolithography dimensions without using an aggressive mask. The advantages of this new technique in terms of its implementation and the suppression of alignment problems are presented. A last study on the development of a MOS transistor with an adjustable threshold voltage is developed. It is shown the advantage of this component relative to the other components with an adjustable threshold voltage. The model implementation and the first…
Advisors/Committee Members: Bouchakour, Rachid (thesis director).
Subjects/Keywords: Effet de pointe; Mémoire non volatile; Caractérisation morphologique; Caractérisation électrique; Patterning; Transistor à tension de seuil; Modélisation compacte; Conception analogique; Peak effect; Non volatile memory; Morphological characterization; Electrical characterization; Patterning; Dual-Control-Gate Floating-Gate-Transistor (DCG FGT); Compact modeling; Analog design
Record Details
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Cite
Share »
Record Details
Similar Records
Cite
« Share
❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Marzaki, A. (2013). Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS : Development of innovative manufacturing process techniques and a new MOS transistor architecture. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2013AIXM4768
Chicago Manual of Style (16th Edition):
Marzaki, Abderrezak. “Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS : Development of innovative manufacturing process techniques and a new MOS transistor architecture.” 2013. Doctoral Dissertation, Aix Marseille Université. Accessed March 03, 2021.
http://www.theses.fr/2013AIXM4768.
MLA Handbook (7th Edition):
Marzaki, Abderrezak. “Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS : Development of innovative manufacturing process techniques and a new MOS transistor architecture.” 2013. Web. 03 Mar 2021.
Vancouver:
Marzaki A. Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS : Development of innovative manufacturing process techniques and a new MOS transistor architecture. [Internet] [Doctoral dissertation]. Aix Marseille Université 2013. [cited 2021 Mar 03].
Available from: http://www.theses.fr/2013AIXM4768.
Council of Science Editors:
Marzaki A. Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS : Development of innovative manufacturing process techniques and a new MOS transistor architecture. [Doctoral Dissertation]. Aix Marseille Université 2013. Available from: http://www.theses.fr/2013AIXM4768
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Open Access Theses and Dissertations
