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You searched for subject:(Layout Generation). Showing records 1 – 15 of 15 total matches.

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KTH

1. Stange, Yuri. Visualization of Code Flow.

Degree: Computer Science and Communication (CSC), 2015, KTH

Visual representation of Control Flow Graphs (CFG) is a feature available in many tools, such as decompilers. These tools often rely on graph drawing… (more)

Subjects/Keywords: Control Flow Graphs; Sugiyama Framework; Graph Layout Generation; Computer Sciences; Datavetenskap (datalogi)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Stange, Y. (2015). Visualization of Code Flow. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-162108

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Stange, Yuri. “Visualization of Code Flow.” 2015. Thesis, KTH. Accessed January 20, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-162108.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Stange, Yuri. “Visualization of Code Flow.” 2015. Web. 20 Jan 2021.

Vancouver:

Stange Y. Visualization of Code Flow. [Internet] [Thesis]. KTH; 2015. [cited 2021 Jan 20]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-162108.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Stange Y. Visualization of Code Flow. [Thesis]. KTH; 2015. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-162108

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

2. Tong, X. (author). 170-GHz Power Amplifier in 0.13-μm SiGe BiCMOS.

Degree: 2020, Delft University of Technology

In recent years, the demand for the wireless connectivity is increasing and leads to the research into the above 100GHz design. Developments have been made… (more)

Subjects/Keywords: 170-GHz power amplifier; SiGe BiCMOS; cascode amplifier; Ocean script design flow; Skillcode layout generation

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APA (6th Edition):

Tong, X. (. (2020). 170-GHz Power Amplifier in 0.13-μm SiGe BiCMOS. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:3dd46dba-d6d7-47b5-ba88-c9b1c248ac71

Chicago Manual of Style (16th Edition):

Tong, X (author). “170-GHz Power Amplifier in 0.13-μm SiGe BiCMOS.” 2020. Masters Thesis, Delft University of Technology. Accessed January 20, 2021. http://resolver.tudelft.nl/uuid:3dd46dba-d6d7-47b5-ba88-c9b1c248ac71.

MLA Handbook (7th Edition):

Tong, X (author). “170-GHz Power Amplifier in 0.13-μm SiGe BiCMOS.” 2020. Web. 20 Jan 2021.

Vancouver:

Tong X(. 170-GHz Power Amplifier in 0.13-μm SiGe BiCMOS. [Internet] [Masters thesis]. Delft University of Technology; 2020. [cited 2021 Jan 20]. Available from: http://resolver.tudelft.nl/uuid:3dd46dba-d6d7-47b5-ba88-c9b1c248ac71.

Council of Science Editors:

Tong X(. 170-GHz Power Amplifier in 0.13-μm SiGe BiCMOS. [Masters Thesis]. Delft University of Technology; 2020. Available from: http://resolver.tudelft.nl/uuid:3dd46dba-d6d7-47b5-ba88-c9b1c248ac71


Linköping University

3. Tsirepli, Ismini. A Cadence layout wrapper for MATLAB.

Degree: Electrical Engineering, 2006, Linköping University

  In this thesis, the focus is on creating a wrapper between MATLAB and the Cadence Virtuoso design environment. The central idea is to use… (more)

Subjects/Keywords: SKILL; MATLAB; wrapper; layout generation,; Electronics; Elektronik

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APA (6th Edition):

Tsirepli, I. (2006). A Cadence layout wrapper for MATLAB. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6916

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsirepli, Ismini. “A Cadence layout wrapper for MATLAB.” 2006. Thesis, Linköping University. Accessed January 20, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6916.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsirepli, Ismini. “A Cadence layout wrapper for MATLAB.” 2006. Web. 20 Jan 2021.

Vancouver:

Tsirepli I. A Cadence layout wrapper for MATLAB. [Internet] [Thesis]. Linköping University; 2006. [cited 2021 Jan 20]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6916.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsirepli I. A Cadence layout wrapper for MATLAB. [Thesis]. Linköping University; 2006. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6916

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Western Ontario

4. de Vlugt, Bradley J. Modern Optimization Algorithms and Applications: Architectural Layout Generation and Parallel Linear Programming.

Degree: 2015, University of Western Ontario

 This thesis examines two topics from the field of computational optimization; architectural layout generation and parallel linear programming. The first topic, a modern problem in… (more)

Subjects/Keywords: Procedural Layout Generation; Linear Programming; Simplex Algorithm; Parallel Computing; Genetic Algorithm; Optimization; Other Electrical and Computer Engineering

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APA (6th Edition):

de Vlugt, B. J. (2015). Modern Optimization Algorithms and Applications: Architectural Layout Generation and Parallel Linear Programming. (Thesis). University of Western Ontario. Retrieved from https://ir.lib.uwo.ca/etd/3208

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

de Vlugt, Bradley J. “Modern Optimization Algorithms and Applications: Architectural Layout Generation and Parallel Linear Programming.” 2015. Thesis, University of Western Ontario. Accessed January 20, 2021. https://ir.lib.uwo.ca/etd/3208.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

de Vlugt, Bradley J. “Modern Optimization Algorithms and Applications: Architectural Layout Generation and Parallel Linear Programming.” 2015. Web. 20 Jan 2021.

Vancouver:

de Vlugt BJ. Modern Optimization Algorithms and Applications: Architectural Layout Generation and Parallel Linear Programming. [Internet] [Thesis]. University of Western Ontario; 2015. [cited 2021 Jan 20]. Available from: https://ir.lib.uwo.ca/etd/3208.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

de Vlugt BJ. Modern Optimization Algorithms and Applications: Architectural Layout Generation and Parallel Linear Programming. [Thesis]. University of Western Ontario; 2015. Available from: https://ir.lib.uwo.ca/etd/3208

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

5. SAMPATH, HEMANTH KUMAR. A MODULE GENERATION ENVIRONMENT FOR MIXED-SIGNAL CIRCUITS.

Degree: MS, Engineering : Computer Engineering, 2003, University of Cincinnati

 Mixed-Signal systems have resulted from the integration of analog and digital systems on the same chip. In mixed-signal systems, the performance depends on the quality… (more)

Subjects/Keywords: Module Generation; Mixed-Signal; Analog; Design Automation; Layout

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

SAMPATH, H. K. (2003). A MODULE GENERATION ENVIRONMENT FOR MIXED-SIGNAL CIRCUITS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1052321882

Chicago Manual of Style (16th Edition):

SAMPATH, HEMANTH KUMAR. “A MODULE GENERATION ENVIRONMENT FOR MIXED-SIGNAL CIRCUITS.” 2003. Masters Thesis, University of Cincinnati. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1052321882.

MLA Handbook (7th Edition):

SAMPATH, HEMANTH KUMAR. “A MODULE GENERATION ENVIRONMENT FOR MIXED-SIGNAL CIRCUITS.” 2003. Web. 20 Jan 2021.

Vancouver:

SAMPATH HK. A MODULE GENERATION ENVIRONMENT FOR MIXED-SIGNAL CIRCUITS. [Internet] [Masters thesis]. University of Cincinnati; 2003. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1052321882.

Council of Science Editors:

SAMPATH HK. A MODULE GENERATION ENVIRONMENT FOR MIXED-SIGNAL CIRCUITS. [Masters Thesis]. University of Cincinnati; 2003. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1052321882


Universidade do Rio Grande do Sul

6. Lazzari, Cristiano. Automatic layout generation of static CMOS circuits targeting delay and power.

Degree: 2003, Universidade do Rio Grande do Sul

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in… (more)

Subjects/Keywords: Microeletrônica; Automatic layout generation; Static CMOS logic gates; Layout : Circuitos integrados; Power and timing optimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lazzari, C. (2003). Automatic layout generation of static CMOS circuits targeting delay and power. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/5690

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lazzari, Cristiano. “Automatic layout generation of static CMOS circuits targeting delay and power.” 2003. Thesis, Universidade do Rio Grande do Sul. Accessed January 20, 2021. http://hdl.handle.net/10183/5690.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lazzari, Cristiano. “Automatic layout generation of static CMOS circuits targeting delay and power.” 2003. Web. 20 Jan 2021.

Vancouver:

Lazzari C. Automatic layout generation of static CMOS circuits targeting delay and power. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2003. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10183/5690.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lazzari C. Automatic layout generation of static CMOS circuits targeting delay and power. [Thesis]. Universidade do Rio Grande do Sul; 2003. Available from: http://hdl.handle.net/10183/5690

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

7. Lazzari, Cristiano. Transistor level automatic generation of radiation-hardened circuits.

Degree: 2007, Universidade do Rio Grande do Sul

Tecnologias submicrônicas (DSM) têm inserido novos desafios ao projeto de circuitos devido a redução de geometrias, redução na tensão de alimentação, aumento da freqüência e… (more)

Subjects/Keywords: Transistor level automatic layout generation; Microeletrônica; Cmos; Transistor sizing; Layout : Circuitos integrados; Low leakage; Radiation-hardened circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lazzari, C. (2007). Transistor level automatic generation of radiation-hardened circuits. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/15506

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lazzari, Cristiano. “Transistor level automatic generation of radiation-hardened circuits.” 2007. Thesis, Universidade do Rio Grande do Sul. Accessed January 20, 2021. http://hdl.handle.net/10183/15506.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lazzari, Cristiano. “Transistor level automatic generation of radiation-hardened circuits.” 2007. Web. 20 Jan 2021.

Vancouver:

Lazzari C. Transistor level automatic generation of radiation-hardened circuits. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2007. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10183/15506.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lazzari C. Transistor level automatic generation of radiation-hardened circuits. [Thesis]. Universidade do Rio Grande do Sul; 2007. Available from: http://hdl.handle.net/10183/15506

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

8. Ziesemer Junior, Adriel Mota. Geração automática de partes operativas de circuitos VLSI.

Degree: 2007, Universidade do Rio Grande do Sul

Tanto nos circuitos integrados para processamento de sinais digitais quanto em microprocessadores, a parte operativa é o núcleo onde a computação dos dados é realizada.… (more)

Subjects/Keywords: Automatic generation; Microeletrônica; Layout; Cmos; Vlsi; Datapath; CMOS cells; CAD; Microelectronic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ziesemer Junior, A. M. (2007). Geração automática de partes operativas de circuitos VLSI. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/15530

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ziesemer Junior, Adriel Mota. “Geração automática de partes operativas de circuitos VLSI.” 2007. Thesis, Universidade do Rio Grande do Sul. Accessed January 20, 2021. http://hdl.handle.net/10183/15530.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ziesemer Junior, Adriel Mota. “Geração automática de partes operativas de circuitos VLSI.” 2007. Web. 20 Jan 2021.

Vancouver:

Ziesemer Junior AM. Geração automática de partes operativas de circuitos VLSI. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2007. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10183/15530.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ziesemer Junior AM. Geração automática de partes operativas de circuitos VLSI. [Thesis]. Universidade do Rio Grande do Sul; 2007. Available from: http://hdl.handle.net/10183/15530

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

9. Tutenel, T. Semantic Game Worlds.

Degree: 2012, Delft University of Technology

 The visual quality of game worlds increased massively in the last three decades. However, the closer game worlds depict reality, the more noticeable it is… (more)

Subjects/Keywords: semantic game worlds; declarative modeling; procedural content generation; semantic layout solving

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APA (6th Edition):

Tutenel, T. (2012). Semantic Game Worlds. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b ; urn:NBN:nl:ui:24-uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b ; urn:NBN:nl:ui:24-uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b ; http://resolver.tudelft.nl/uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b

Chicago Manual of Style (16th Edition):

Tutenel, T. “Semantic Game Worlds.” 2012. Doctoral Dissertation, Delft University of Technology. Accessed January 20, 2021. http://resolver.tudelft.nl/uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b ; urn:NBN:nl:ui:24-uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b ; urn:NBN:nl:ui:24-uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b ; http://resolver.tudelft.nl/uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b.

MLA Handbook (7th Edition):

Tutenel, T. “Semantic Game Worlds.” 2012. Web. 20 Jan 2021.

Vancouver:

Tutenel T. Semantic Game Worlds. [Internet] [Doctoral dissertation]. Delft University of Technology; 2012. [cited 2021 Jan 20]. Available from: http://resolver.tudelft.nl/uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b ; urn:NBN:nl:ui:24-uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b ; urn:NBN:nl:ui:24-uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b ; http://resolver.tudelft.nl/uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b.

Council of Science Editors:

Tutenel T. Semantic Game Worlds. [Doctoral Dissertation]. Delft University of Technology; 2012. Available from: http://resolver.tudelft.nl/uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b ; urn:NBN:nl:ui:24-uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b ; urn:NBN:nl:ui:24-uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b ; http://resolver.tudelft.nl/uuid:0b688fb4-2fe7-4b7c-92c5-7fbcb682466b


Universidade do Rio Grande do Sul

10. Santos, Cristiano Lopes dos. Verificação e otimização de atraso durante a síntese física de circuitos integrados CMOS.

Degree: 2005, Universidade do Rio Grande do Sul

Este trabalho propõe um método de otimização de atraso, através de dimensionamento de transistores, o qual faz parte de um fluxo automático de síntese física… (more)

Subjects/Keywords: Critical delay optimization; Microeletrônica; Transistor sizing; Cmos; Timing analysis; Timing-driven physical synthesis; Layout generation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Santos, C. L. d. (2005). Verificação e otimização de atraso durante a síntese física de circuitos integrados CMOS. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/17785

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Santos, Cristiano Lopes dos. “Verificação e otimização de atraso durante a síntese física de circuitos integrados CMOS.” 2005. Thesis, Universidade do Rio Grande do Sul. Accessed January 20, 2021. http://hdl.handle.net/10183/17785.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Santos, Cristiano Lopes dos. “Verificação e otimização de atraso durante a síntese física de circuitos integrados CMOS.” 2005. Web. 20 Jan 2021.

Vancouver:

Santos CLd. Verificação e otimização de atraso durante a síntese física de circuitos integrados CMOS. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2005. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10183/17785.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Santos CLd. Verificação e otimização de atraso durante a síntese física de circuitos integrados CMOS. [Thesis]. Universidade do Rio Grande do Sul; 2005. Available from: http://hdl.handle.net/10183/17785

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

11. Abumurad, Abdulrahman. An Automated Framework for Flash ADC Design and Analysis.

Degree: 2020, Penn State University

 Threshold Inverter Quantizer (TIQ) Flash Analog to Digital Converters (ADCs) are good candidates for System-on-Chip applications because they can be designed using the digital CMOS… (more)

Subjects/Keywords: TIQ Comparators; Flash ADC; ADC Design Automation; Low-noise ADCs; Quality Flash ADCs; Circuit Layout Generation; Comparator Thresholds selection; Flash ADC and Process-Temperature-Voltage Variation; High-Precision Flash ADCs; Signal Switching Noise in Flash ADCs; Circuit Design Automation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Abumurad, A. (2020). An Automated Framework for Flash ADC Design and Analysis. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/17761aka133

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Abumurad, Abdulrahman. “An Automated Framework for Flash ADC Design and Analysis.” 2020. Thesis, Penn State University. Accessed January 20, 2021. https://submit-etda.libraries.psu.edu/catalog/17761aka133.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Abumurad, Abdulrahman. “An Automated Framework for Flash ADC Design and Analysis.” 2020. Web. 20 Jan 2021.

Vancouver:

Abumurad A. An Automated Framework for Flash ADC Design and Analysis. [Internet] [Thesis]. Penn State University; 2020. [cited 2021 Jan 20]. Available from: https://submit-etda.libraries.psu.edu/catalog/17761aka133.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Abumurad A. An Automated Framework for Flash ADC Design and Analysis. [Thesis]. Penn State University; 2020. Available from: https://submit-etda.libraries.psu.edu/catalog/17761aka133

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Pompeu Fabra

12. Bahrehmand, Arash. A Computational model for generating and analysing architectural layouts in virtual environments.

Degree: Departament de Tecnologies de la Informació i les Comunicacions, 2016, Universitat Pompeu Fabra

 El diseño de las disposiciones interiores es uno de los elementos más comunes de los proyectos de gráficos por ordenador y de inmersión (por ejemplo,… (more)

Subjects/Keywords: Design; Interactive layout planning; Genetic algorithm; Computational metric; Procedural generation; 3D visualization of layouts; Diseño; Planificación diseño interactiva; Algoritmo genético; Computacional métrico; Generación por procedimientos; La visualización en 3D de diseños; 62

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bahrehmand, A. (2016). A Computational model for generating and analysing architectural layouts in virtual environments. (Thesis). Universitat Pompeu Fabra. Retrieved from http://hdl.handle.net/10803/395174

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bahrehmand, Arash. “A Computational model for generating and analysing architectural layouts in virtual environments.” 2016. Thesis, Universitat Pompeu Fabra. Accessed January 20, 2021. http://hdl.handle.net/10803/395174.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bahrehmand, Arash. “A Computational model for generating and analysing architectural layouts in virtual environments.” 2016. Web. 20 Jan 2021.

Vancouver:

Bahrehmand A. A Computational model for generating and analysing architectural layouts in virtual environments. [Internet] [Thesis]. Universitat Pompeu Fabra; 2016. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/10803/395174.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bahrehmand A. A Computational model for generating and analysing architectural layouts in virtual environments. [Thesis]. Universitat Pompeu Fabra; 2016. Available from: http://hdl.handle.net/10803/395174

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Melbourne

13. MARSHALL, ROBERT. Improving the efficiency and capabilities of document structuring.

Degree: 2007, University of Melbourne

 Natural language generation (NLG), the problem of creating human-readable documents by computer, is one of the major fields of research in computational linguistics The task… (more)

Subjects/Keywords: natural language generation; NLG; natural language processing; computational linguistics; document structuresummarization; document layout; constraint programming

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

MARSHALL, R. (2007). Improving the efficiency and capabilities of document structuring. (Masters Thesis). University of Melbourne. Retrieved from http://hdl.handle.net/11343/39295

Chicago Manual of Style (16th Edition):

MARSHALL, ROBERT. “Improving the efficiency and capabilities of document structuring.” 2007. Masters Thesis, University of Melbourne. Accessed January 20, 2021. http://hdl.handle.net/11343/39295.

MLA Handbook (7th Edition):

MARSHALL, ROBERT. “Improving the efficiency and capabilities of document structuring.” 2007. Web. 20 Jan 2021.

Vancouver:

MARSHALL R. Improving the efficiency and capabilities of document structuring. [Internet] [Masters thesis]. University of Melbourne; 2007. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/11343/39295.

Council of Science Editors:

MARSHALL R. Improving the efficiency and capabilities of document structuring. [Masters Thesis]. University of Melbourne; 2007. Available from: http://hdl.handle.net/11343/39295


University of Cincinnati

14. VIJAY, VIKAS. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS.

Degree: MS, Engineering : Computer Engineering, 2004, University of Cincinnati

 This thesis presents automated techniques for synthesis of high performance RF circuits. The top-down methodology developed encompasses all stages of RF design from circuit sizing,… (more)

Subjects/Keywords: Radio Frequency; Synthesis; Optimization; Automation; Layout Generation; RF; Analog; High Frequency; Module Generation; C++; SKILL; Extraction; Performance Analysis; Circuit Sizing; Radio Receiver; LNA; Mixer; VCO; Phase Frequency Detector

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APA (6th Edition):

VIJAY, V. (2004). A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283

Chicago Manual of Style (16th Edition):

VIJAY, VIKAS. “A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS.” 2004. Masters Thesis, University of Cincinnati. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.

MLA Handbook (7th Edition):

VIJAY, VIKAS. “A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS.” 2004. Web. 20 Jan 2021.

Vancouver:

VIJAY V. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. [Internet] [Masters thesis]. University of Cincinnati; 2004. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.

Council of Science Editors:

VIJAY V. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. [Masters Thesis]. University of Cincinnati; 2004. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283

15. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…standards JTAG Joint Test Action Group, develops on-chip instrumentation standards LEAP Layout… …signature generation logic into a fabricated hardware design to create a heavily compressed… …variables to capture and enabling the sharing of expensive signature generation logic. In Chapter… …generation of these units. We show that the use of these new functional units reduces shadow… …inserts multiplexers at this stage to facilitate such sharing. 6. RTL Generation: The engine… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 20, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 20 Jan 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

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