subject:(LDPC)

1. Mahdi, Ahmed. Αρχιτεκτονική και υλοποίηση κωδικοποιητών VLSI για κώδικες LDPC.

Degree: 2010, University of Patras

URL: http://nemertes.lis.upatras.gr/jspui/handle/10889/4280

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Η διπλωματική εργασία επικεντρώνεται στη μελέτη της κωδικοποίησης για κώδικες LDPC. Στα πλαίσιά της, θα μελετηθούν τα προβλήματα και η πολυπλοκότητα κωδικοποίησης συναρτήσει του μήκους… (more)

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Η διπλωματική εργασία επικεντρώνεται στη μελέτη της κωδικοποίησης για κώδικες LDPC. Στα πλαίσιά της, θα μελετηθούν τα προβλήματα και η πολυπλοκότητα κωδικοποίησης συναρτήσει του μήκους της κωδικής λέξης. Έμφαση θα δοθεί σε εφαρμογές με μεγάλο μήκος κωδικής λέξης όπως εκείνες που χρησιμοποιούνται σε νέες τηλεπικοινωνιακές εφαρμογές, όπως δορυφορικό Digital Video Broadcast (DVB) DVB-S2, IEEE 802.3an (10GBASE-T) και IEEE 802.16(WiMAX). Σε τέτοιες εφαρμογές όπου η κωδική λέξη μπορεί να έχει μήκος αρκετά μεγαλύτερο των 1000 bits, η πολυπλοκότητα κωδικοποίησης είναι σημαντική. Αυτό συμβαίνει διότι απαιτούνται μεγάλες σε μέγεθος μνήμες για την αποθήκευση του Πίνακα Έλεγχου Ισοτιμίας (Parity-check Matrix H), πολύ μεγάλη χρονική επεξεργαστική πολυπλοκότητα O(n²) αλλά και πολλά επεξεργαστικά στοιχεία τάξης Ο(n²). Ο σκοπός λοιπόν είναι να μελετηθούν οι αλγόριθμοι κωδικοποίησης και να μελετηθεί πώς μπορεί να αξιοποιηθεί η αραιότητα του Πίνακα Έλεγχου Ισοτιμίας έτσι ώστε να επιτευχθεί κατά το δυνατόν γραμμική πολυπλοκότητα O(n) κωδικοποίησης. Στη συνέχεια, αφού αναπτυχθεί η κατάλληλη μέθοδος κωδικοποίησης, θα ακολουθήσει η μελέτη και ο σχεδιασμός μίας βέλτιστης VLSI αρχιτεκτονικής για την υλοποίηση σε υλικό του LDPC κωδικοποιητή, ώστε να ικανοποιεί και άλλα πρακτικά κριτήρια, με έμφαση στη μείωση της καθυστέρησης και της απαιτούμενης επιφάνειας. Θα αναπτυχθεί επίσης μια κατάλληλη αρχιτεκτονική για διάφορους βαθμούς παραλληλίας του κωδικοποιητή.

An LDPC code is a linear block code specified by a very sparse parity check matrix (PCM). LDPC codes are usually represented by a bi-partite graph in which a variable node corresponds to a ’coded bit’ or a PCM column, and a check node corresponds to a parity check equation or a PCM row. There is an edge between each pair of nodes if there is a ’one’ in the corresponding PCM entry. In a general analysis an (n, k) LDPC code has k information bits and n coded bits with code rate r = k/n. An important issue in the implementation of LDPC-code based forward error correction systems is the encoding of LDPC codes. Generally, LDPC codes cannot have the simple encoding structures based on of shift registers as in the case of convolutional, turbo codes, or cyclic block codes. However, general LDPC codes do not fall in this category. Except QC-cyclic LDPC codes, most efficient LDPC codes, especially irregular LDPC codes are hard to encode with the idea of shift registers. A straightforward way is to derive a systematic generator matrix from a PCM, and then to encode LDPC code systematically with the generator matrix. This can work for every LDPC code in theory, but practically it is a very bad idea because it has high complexity, as the generator matrix derived from parity-check matrix is not sparse contrasted to the PCM. Generator matrix can be very dense matrix. The objective is to utilize the sparseness to achieve LDPC encoding in linear time. This Master’s thesis presents a flexible encoder architecture using QC-cyclic LDPC codes and efficient two-step encoding algorithm in…

Advisors/Committee Members: Παλιουράς, Βασίλειος, Μπίρμπας, Αλέξιος, Μπερμπιρίδης, Κωνσταντίνος, Παλιουράς, Βασίλειος.

Subjects/Keywords: Κωδικοποιητές; Κώδικες LDPC; 005.72; Encoders; LDPC codes

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APA (6^th Edition):

Mahdi, A. (2010). Αρχιτεκτονική και υλοποίηση κωδικοποιητών VLSI για κώδικες LDPC. (Masters Thesis). University of Patras. Retrieved from http://nemertes.lis.upatras.gr/jspui/handle/10889/4280

Chicago Manual of Style (16^th Edition):

Mahdi, Ahmed. “Αρχιτεκτονική και υλοποίηση κωδικοποιητών VLSI για κώδικες LDPC.” 2010. Masters Thesis, University of Patras. Accessed June 19, 2019. http://nemertes.lis.upatras.gr/jspui/handle/10889/4280.

MLA Handbook (7^th Edition):

Mahdi, Ahmed. “Αρχιτεκτονική και υλοποίηση κωδικοποιητών VLSI για κώδικες LDPC.” 2010. Web. 19 Jun 2019.

Vancouver:

Mahdi A. Αρχιτεκτονική και υλοποίηση κωδικοποιητών VLSI για κώδικες LDPC. [Internet] [Masters thesis]. University of Patras; 2010. [cited 2019 Jun 19]. Available from: http://nemertes.lis.upatras.gr/jspui/handle/10889/4280.

Council of Science Editors:

Mahdi A. Αρχιτεκτονική και υλοποίηση κωδικοποιητών VLSI για κώδικες LDPC. [Masters Thesis]. University of Patras; 2010. Available from: http://nemertes.lis.upatras.gr/jspui/handle/10889/4280

University of Alberta

2. Zhang, Shuai. Controlling the Error Floors of the Low-Density Parity-Check Codes.

Degree: PhD, Department of Electrical and Computer Engineering, 2012, University of Alberta

URL: https://era.library.ualberta.ca/files/5425kb98q

► The goal of error control coding is to encode information in such a way, that in the event that errors occur during transmission over a… (more)

▼ The goal of error control coding is to encode information in such a way, that in the event that errors occur during transmission over a noisy communication channel or during storage in an unreliable memory, the receiver can correct the errors and recover the original transmitted information. Low-density parity-check (LDPC) codes are a kind of high performance linear block code, which are already used in many recent communication systems. Information rates guaranteed by these codes approach the theoretical Shannon capacity limit. In addition, LDPC codes are now widely used in practice and included in many communication standards. Therefore study of these codes is very important and practical approaches to their design and decoding techniques are of great interest. There exist very good decoding algorithms for LDPC codes with respect to different channel models. However, LDPC codes suffer from the infamous error floor problem at high signal-to-noise ratios. This problem is attributed to the trapping sets by Richardson. It is shown that the dominant trapping sets of regular LDPC codes, so called absorption sets, undergo a two-phase dynamic behavior in the iterative message-passing decoding algorithm. We present a linear dynamic model for the iteration behavior of these sets. It can be seen that they undergo an initial geometric growth phase which stabilizes in a final bit-flipping behavior where the algorithm reaches a fixed point. Our analysis is shown to lead to very accurate numerical calculations of the error floor bit error rates down to error rates that are inaccessible by simulation. The topologies of the dominant absorption sets of two example codes, the IEEE 802.3an [2048,1723] regular (6,32) LDPC code and the Tanner [155,64,20] regular (3,5) LDPC code, are identified and tabulated by using topological features in combination with search algorithms, respectively. To make our analysis more complete, we provide more solid evidence showing that trapping sets are equivalent to absorption sets. In other words, we argue that absorption sets characterize all failure mechanisms. Some insights from our linear analysis can be borrowed to approach this problem. Another insight that this formula provides to us is the means to reduce the error floor, which is another important part of what we hoped to achieve by developing the formula in the first place. By allowing the log-likelihood ratios (LLRs) utilized by the message-passing decoding to grow bigger in precision length, the absorption sets as a trouble-causing structure will be successfully corrected. Therefore, the absorption sets, generically born with the code design, will no longer threaten the error correcting performance as long as the messages have enough room and time to grow. This translates to greater LLR clipping thresholds and more iterations, both of which are preset at the decoder. However, the actual settings are dependent on how much the subgraph of the dominant absorption set resembles that of a non-zero minimum-weight codeword, therefore the settings…

Subjects/Keywords: LDPC; Error Floor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhang, S. (2012). Controlling the Error Floors of the Low-Density Parity-Check Codes. (Doctoral Dissertation). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/5425kb98q

Chicago Manual of Style (16^th Edition):

Zhang, Shuai. “Controlling the Error Floors of the Low-Density Parity-Check Codes.” 2012. Doctoral Dissertation, University of Alberta. Accessed June 19, 2019. https://era.library.ualberta.ca/files/5425kb98q.

MLA Handbook (7^th Edition):

Zhang, Shuai. “Controlling the Error Floors of the Low-Density Parity-Check Codes.” 2012. Web. 19 Jun 2019.

Vancouver:

Zhang S. Controlling the Error Floors of the Low-Density Parity-Check Codes. [Internet] [Doctoral dissertation]. University of Alberta; 2012. [cited 2019 Jun 19]. Available from: https://era.library.ualberta.ca/files/5425kb98q.

Council of Science Editors:

Zhang S. Controlling the Error Floors of the Low-Density Parity-Check Codes. [Doctoral Dissertation]. University of Alberta; 2012. Available from: https://era.library.ualberta.ca/files/5425kb98q

Texas A&M University

3. Wang, Weihuang. Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.

Degree: 2009, Texas A&M University

URL: http://hdl.handle.net/1969.1/ETD-TAMU-2504

► This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading channels… (more)

Subjects/Keywords: VLSI; LDPC; low power

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APA (6^th Edition):

Wang, W. (2009). Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2504

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wang, Weihuang. “Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.” 2009. Thesis, Texas A&M University. Accessed June 19, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2504.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wang, Weihuang. “Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.” 2009. Web. 19 Jun 2019.

Vancouver:

Wang W. Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2504.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang W. Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2504

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Georgia Tech

4. Dihidar, Souvik. Applications of Low Density Parity Check Codes for Wiretap Channels and Congestion Localization in Networks.

Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech

URL: http://hdl.handle.net/1853/13969

► Error control coding in some form is present in virtually every communication system today. Recently, Low Density Parity Check (LDPC) codes have been proposed along… (more)

▼ Error control coding in some form is present in virtually every communication system today. Recently, Low Density Parity Check (LDPC) codes have been proposed along with a simple iterative decoding algorithm. These codes have been demonstrated to perform very close to the Shannon Limit. The simplicity of LDPC codes have also led to many interesting asymptotic and finite-length properties of these codes. The techniques for designing good LDPC codes over a wide variety of channels have been studied. LDPC codes are being used in a wide variety of applications, such as fading channels, Orthogonal Frequency Division Multiplexing (OFDM) systems, source compression etc. This proposal investigates the use of LDPC codes in wiretap channel systems such as quantum key distribution and for congestion localization in large networks. Quantum Key Distribution (QKD) is secure key exchange method where the two legitimate parties first transmit information over a quantum channel, which can be eavesdropped on by the eavesdropper. The QKD system can be modeled as a special case of an wiretap channel system. An wiretap chanel system is a broadcast system, where the sender has to send a message to a legitimate party over a main channel. The wiretapper also receives the message through another channel called the wiretap channel. The sender has to code the transmitted message in such a way so that the legitimate party is able to recover the message without errors, whereas the wiretapper essentially has no information about the message. As we will see, the encoder for such a system is stochastic as opposed to a deterministic encoder in error correction coding. In this research, we propose a coding scheme using LDPC codes for such systems. Congestion in a network occurs when some nodes receive more traffic than they can process. It leads to dropping packets and thus lowering the throughput. On the contrary, if other nodes in the network are aware of the congested nodes, new packets can be dynamically routed through less congested routes. We developed a congestion detection mechanism wherein a few high priority probe packets are routed through the network. A central entity collects the contents of all the probe packets and estimates the state (congested or not) of every node in the network. One important parameter of congeston localization schemes is scalability, i.e. how the number of measurements scales with the size of network as the size of the network grows. We have shown that it is possible to do congestion detection using our scheme for a properly designed network with the number of measurements required growing linearly with the size of the network. Advisors/Committee Members: Steven W. McLaughlin (Committee Chair), Chuanyi Ji (Committee Member), Faramarz Fekri (Committee Member), Xingxing Yu (Committee Member), Yorai Wardi (Committee Member).

Subjects/Keywords: LDPC; Wiretap

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Dihidar, S. (2006). Applications of Low Density Parity Check Codes for Wiretap Channels and Congestion Localization in Networks. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/13969

Chicago Manual of Style (16^th Edition):

Dihidar, Souvik. “Applications of Low Density Parity Check Codes for Wiretap Channels and Congestion Localization in Networks.” 2006. Doctoral Dissertation, Georgia Tech. Accessed June 19, 2019. http://hdl.handle.net/1853/13969.

MLA Handbook (7^th Edition):

Dihidar, Souvik. “Applications of Low Density Parity Check Codes for Wiretap Channels and Congestion Localization in Networks.” 2006. Web. 19 Jun 2019.

Vancouver:

Dihidar S. Applications of Low Density Parity Check Codes for Wiretap Channels and Congestion Localization in Networks. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/1853/13969.

Council of Science Editors:

Dihidar S. Applications of Low Density Parity Check Codes for Wiretap Channels and Congestion Localization in Networks. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/13969

Queens University

5. Alnabulsi, Basel. LDPC-OFDM: Channel Estimation and Power considerations .

Degree: Electrical and Computer Engineering, 2013, Queens University

URL: http://hdl.handle.net/1974/7981

► Small cells are low-powered radio access nodes that operate in licensed and unlicensed spectrum that have a range of 10 meters to 200 meters, compared… (more)

▼ Small cells are low-powered radio access nodes that operate in licensed and unlicensed spectrum that have a range of 10 meters to 200 meters, compared to a mobile macrocell which might have a range of a few kilometres. This dissertation proposes algorithms for the enhancement of small cells installed in high speed rails. The thesis addresses two main points: the link between the small cell and the base station, and the link between the end-users and the small cell. The channel between the small cell and the base station is a fast fading channel due to the mobility of the high speed rail. The first part of the thesis proposes methods to enhance the link between the small cell and the base station using Low-Density Parity-Check codes (LDPC) for fast fading channels. The proposed uses nonuniform reconstruction methods based on the soft output log-likelihood ratio (LLR) provided by the LDPC decoder. The LLRs provide information about the location of the symbols with high probability of being correct. The grid formed under the assumption of a correlated Rayleigh channel affecting the transmitted data is highly nonuniform. Reconstruction of the channel under such assumptions is highly unstable. A signal-to-noise- ratio dependent regularization method is implemented to enhance the performance under imperfect Doppler spread estimation. The second part of the thesis proposes algorithms for the link between the end-user and the small cell. Since power efficiency is a major factor for end-users employing battery powered devices, we propose a Linear Programming (LP) algorithm for signal shaping to minimize the average transmitted power. The other problem the thesis addresses is the minimization of Peak-to-Average Power-Ratio (PAPR) of Orthogonal Frequency Division Multiplexing (OFDM) signals. The PAPR is minimized using a set of phase shifts for the constituting subcarriers of the OFDM signal. The set of phase shifts is determined using a LP approach that minimizes the complexity when the block length is high. A real-time implementation of some of the algorithms is carried out using the TMS320C6713 Texas Instruments board. The results for fixed-point versus floating-point implementation is shown for a different number of precision bits.

Subjects/Keywords: LDPC; OFDM; PAPR; Nonuniform Interpolation

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APA (6^th Edition):

Alnabulsi, B. (2013). LDPC-OFDM: Channel Estimation and Power considerations . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/7981

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Alnabulsi, Basel. “LDPC-OFDM: Channel Estimation and Power considerations .” 2013. Thesis, Queens University. Accessed June 19, 2019. http://hdl.handle.net/1974/7981.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Alnabulsi, Basel. “LDPC-OFDM: Channel Estimation and Power considerations .” 2013. Web. 19 Jun 2019.

Vancouver:

Alnabulsi B. LDPC-OFDM: Channel Estimation and Power considerations . [Internet] [Thesis]. Queens University; 2013. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/1974/7981.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alnabulsi B. LDPC-OFDM: Channel Estimation and Power considerations . [Thesis]. Queens University; 2013. Available from: http://hdl.handle.net/1974/7981

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Louisiana State University

6. Xia, Tian. Blind LDPC encoder identification.

Degree: MSEE, Electrical and Computer Engineering, 2013, Louisiana State University

URL: etd-11182013-115645 ; https://digitalcommons.lsu.edu/gradschool_theses/3323

► Nowadays, adaptive modulation and coding (AMC) techniques can facilitate flexible strategies subject to dynamic channel quality. The AMC transceivers select the most suitable coding and… (more)

Subjects/Keywords: LDPC codes; blind identification

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Xia, T. (2013). Blind LDPC encoder identification. (Masters Thesis). Louisiana State University. Retrieved from etd-11182013-115645 ; https://digitalcommons.lsu.edu/gradschool_theses/3323

Chicago Manual of Style (16^th Edition):

Xia, Tian. “Blind LDPC encoder identification.” 2013. Masters Thesis, Louisiana State University. Accessed June 19, 2019. etd-11182013-115645 ; https://digitalcommons.lsu.edu/gradschool_theses/3323.

MLA Handbook (7^th Edition):

Xia, Tian. “Blind LDPC encoder identification.” 2013. Web. 19 Jun 2019.

Vancouver:

Xia T. Blind LDPC encoder identification. [Internet] [Masters thesis]. Louisiana State University; 2013. [cited 2019 Jun 19]. Available from: etd-11182013-115645 ; https://digitalcommons.lsu.edu/gradschool_theses/3323.

Council of Science Editors:

Xia T. Blind LDPC encoder identification. [Masters Thesis]. Louisiana State University; 2013. Available from: etd-11182013-115645 ; https://digitalcommons.lsu.edu/gradschool_theses/3323

University of Saskatchewan

7. Loi, Kung Chi Cinnati. Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2).

Degree: 2010, University of Saskatchewan

URL: http://hdl.handle.net/10388/etd-09222010-120119

► In recent years, LDPC codes are gaining a lot of attention among researchers. Its near-Shannon performance combined with its highly parallel architecture and lesser complexity… (more)

Subjects/Keywords: FPGA; DVB-S2; LDPC

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APA (6^th Edition):

Loi, K. C. C. (2010). Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2). (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/etd-09222010-120119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Loi, Kung Chi Cinnati. “Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2).” 2010. Thesis, University of Saskatchewan. Accessed June 19, 2019. http://hdl.handle.net/10388/etd-09222010-120119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Loi, Kung Chi Cinnati. “Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2).” 2010. Web. 19 Jun 2019.

Vancouver:

Loi KCC. Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2). [Internet] [Thesis]. University of Saskatchewan; 2010. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/10388/etd-09222010-120119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Loi KCC. Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2). [Thesis]. University of Saskatchewan; 2010. Available from: http://hdl.handle.net/10388/etd-09222010-120119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Waterloo

8. Li, Si-Yun. Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder.

Degree: 2012, University of Waterloo

URL: http://hdl.handle.net/10012/6962

► In this thesis, we present an FPGA implementation of parallel-node low-density-parity-check convolutional-code (PN-LDPC-CC) encoder and decoder. A 2.4 Gbit/s rate-1/2 (3, 6) PN-LDPC-CC encoder and… (more)

Subjects/Keywords: LDPC; FPGA; Convolutional Codes; FEC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Li, S. (2012). Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/6962

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Li, Si-Yun. “Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder.” 2012. Thesis, University of Waterloo. Accessed June 19, 2019. http://hdl.handle.net/10012/6962.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Li, Si-Yun. “Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder.” 2012. Web. 19 Jun 2019.

Vancouver:

Li S. Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder. [Internet] [Thesis]. University of Waterloo; 2012. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/10012/6962.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li S. Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder. [Thesis]. University of Waterloo; 2012. Available from: http://hdl.handle.net/10012/6962

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Arizona

9. Sun, Xiaole. Secure and Reliable Communications over Free-space Optical Channels .

Degree: 2019, University of Arizona

URL: http://hdl.handle.net/10150/631902

► Free-space optical (FSO) communication provides a promising alternative solution to the traditional radio frequency (RF) communications. Compared to the RF technology, there are many advantages… (more)

▼ Free-space optical (FSO) communication provides a promising alternative solution to the traditional radio frequency (RF) communications. Compared to the RF technology, there are many advantages of FSO communications, such as ultra-high bandwidth, license-free spectrum, low inter-channel interference, and energy-efficient transmission. The potential applications for FSO communication include the last-one-mile access link from the fiber-based backbone network, low earth orbit (LEO) satellite communications, high-altitude base station platforms or vehicles, deep-space communications, and in-building automation connections. As the FSO technology becomes mature and increasingly involved, the security and reliability requirements of such applications also become crucial. Regarding the security issues, although the FSO communication is inherently more secure than the RF counterpart due to high directivity of its line-of-sight (LOS) link, it can still suffer from optical wire-tapping attack. There are many different application schemes that an eavesdropper can still probe the FSO link. Traditionally, to protect the communication, many works have been done on encryption layer and upper network layer, such as computationally intensive cryptographic algorithms and message exchanging protocols. In recent years, physical-layer security (PLS) has been getting more attentions as it provides an extra layer of security against eavesdropping. The PLS schemes, in general can be categorized into two main categories: classical PLS and quantum key distribution (QKD) protocols. The classical PLS is based on the information theoretic security analysis, while the QKD security is guaranteed by the quantum mechanics laws. Both techniques have been studied for FSO channels. In the first half of this dissertation, we study the PLS in a LOS FSO channel using orbital angular momentum (OAM) multiplexing and show that higher secrecy capacity can be achieved using OAM multiplexing technology in the presence of atmospheric turbulence effects. Then, we proposed an adaptation scheme for QKD system over FSO channel with different QKD protocols, i.e. BB84 and decoy state protocols. By adapting the source brightness based on the channel condition, we optimized the secret key rate (SKR) of the QKD system. Furthermore, we proposed a multiple spatial modes-based QKD system with backpropagation method to increase the total SKR through parallel channels. Regarding the reliability of an optical communication system as well as information reconciliation for both PLS and QKD schemes, the forward error correction (FEC) becomes an essential technique to enable high-speed transmission. The FEC with low-density parity-check (LDPC) codes has been studied for decades from LDPC block codes to the most recent spatially-coupled (SC) LDPC codes. For FSO communications, due to the time-varying nature of FSO channels, the capability of rate adaptation is important to achieve a consistent reliable transmission. In the second half of this dissertation, we proposed unified… Advisors/Committee Members: Djordjevic, Ivan B (advisor), Bilgin, Ali (committeemember), Kilper, Daniel (committeemember).

Subjects/Keywords: FPGA; FSO; LDPC; QKD

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APA (6^th Edition):

Sun, X. (2019). Secure and Reliable Communications over Free-space Optical Channels . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/631902

Chicago Manual of Style (16^th Edition):

Sun, Xiaole. “Secure and Reliable Communications over Free-space Optical Channels .” 2019. Doctoral Dissertation, University of Arizona. Accessed June 19, 2019. http://hdl.handle.net/10150/631902.

MLA Handbook (7^th Edition):

Sun, Xiaole. “Secure and Reliable Communications over Free-space Optical Channels .” 2019. Web. 19 Jun 2019.

Vancouver:

Sun X. Secure and Reliable Communications over Free-space Optical Channels . [Internet] [Doctoral dissertation]. University of Arizona; 2019. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/10150/631902.

Council of Science Editors:

Sun X. Secure and Reliable Communications over Free-space Optical Channels . [Doctoral Dissertation]. University of Arizona; 2019. Available from: http://hdl.handle.net/10150/631902

10. Bhutto, Tarique Inayat. Root LDPC Codes for Non Ergodic Transmission Channels.

Degree: 2011, , School of Engineering

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5938

►

4 ABSTRACT Tremendous amount of research has been conducted in modern coding theory in the past few years and much of the work has… (more)

Subjects/Keywords: Non-Binary Root LDPC codes; LDPC codes; Binary-Root LDPC codes; Signal Processing; Signalbehandling; Computer Sciences; Datavetenskap (datalogi); Telecommunications; Telekommunikation

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APA (6^th Edition):

Bhutto, T. I. (2011). Root LDPC Codes for Non Ergodic Transmission Channels. (Thesis). , School of Engineering. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5938

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Bhutto, Tarique Inayat. “Root LDPC Codes for Non Ergodic Transmission Channels.” 2011. Thesis, , School of Engineering. Accessed June 19, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5938.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Bhutto, Tarique Inayat. “Root LDPC Codes for Non Ergodic Transmission Channels.” 2011. Web. 19 Jun 2019.

Vancouver:

Bhutto TI. Root LDPC Codes for Non Ergodic Transmission Channels. [Internet] [Thesis]. , School of Engineering; 2011. [cited 2019 Jun 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5938.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bhutto TI. Root LDPC Codes for Non Ergodic Transmission Channels. [Thesis]. , School of Engineering; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5938

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Kansas State University

11. Kopparthi, Sunitha. Flexible encoder and decoder designs for low-density parity-check codes.

Degree: PhD, Department of Electrical and Computer Engineering, 2010, Kansas State University

URL: http://hdl.handle.net/2097/4190

► Future technologies such as cognitive radio require flexible and reliable hardware architectures that can be easily configured and adapted to varying coding parameters. The objective… (more)

▼ Future technologies such as cognitive radio require flexible and reliable hardware architectures that can be easily configured and adapted to varying coding parameters. The objective of this work is to develop a flexible hardware encoder and decoder for low-density parity-check (LDPC) codes. The design methodologies used for the implementation of a LDPC encoder and decoder are flexible in terms of parity-check matrix, code rate and code length. All these designs are implemented on a programmable chip and tested. Encoder implementations of LDPC codes are optimized for area due to their high complexity. Such designs usually have relatively low data rate. Two new encoder designs are developed that achieve much higher data rates of up to 844 Mbps while requiring more area for implementation. Using structured LDPC codes decreases the encoding complexity and provides design flexibility. The architecture for an encoder is presented that adheres to the structured LDPC codes defined in the IEEE 802.16e standard. A single encoder design is also developed that accommodates different code lengths and code rates and does not require re-synthesis of the design in order to change the encoding parameters. The flexible encoder design for structured LDPC codes is also implemented on a custom chip. The maximum coded data rate of the structured encoder is up to 844 Mbps and for a given code rate its value is independent of the code length. An LDPC decoder is designed and its design methodology is generic. It is applicable to both structured and any randomly generated LDPC codes. The coded data rate of the decoder increases with the increase in the code length. The number of decoding iterations used for the decoding process plays an important role in determining the decoder performance and latency. This design validates the estimated codeword after every iteration and stops the decoding process when the correct codeword is estimated which saves power consumption. For a given parity-check matrix and signal-to-noise ratio, a procedure to find an optimum value of the maximum number of decoding iterations is presented that considers the affects of power, delay, and error performance. Advisors/Committee Members: Don M. Gruenbacher.

Subjects/Keywords: Flexible LDPC encoder; IEEE 802.16e LDPC codes; Flexible LDPC decoder; Hardware Architecture; Engineering, Electronics and Electrical (0544)

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APA (6^th Edition):

Kopparthi, S. (2010). Flexible encoder and decoder designs for low-density parity-check codes. (Doctoral Dissertation). Kansas State University. Retrieved from http://hdl.handle.net/2097/4190

Chicago Manual of Style (16^th Edition):

Kopparthi, Sunitha. “Flexible encoder and decoder designs for low-density parity-check codes.” 2010. Doctoral Dissertation, Kansas State University. Accessed June 19, 2019. http://hdl.handle.net/2097/4190.

MLA Handbook (7^th Edition):

Kopparthi, Sunitha. “Flexible encoder and decoder designs for low-density parity-check codes.” 2010. Web. 19 Jun 2019.

Vancouver:

Kopparthi S. Flexible encoder and decoder designs for low-density parity-check codes. [Internet] [Doctoral dissertation]. Kansas State University; 2010. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/2097/4190.

Council of Science Editors:

Kopparthi S. Flexible encoder and decoder designs for low-density parity-check codes. [Doctoral Dissertation]. Kansas State University; 2010. Available from: http://hdl.handle.net/2097/4190

University of Alberta

12. Zheng, Chao. Design and Decoding LDPC Codes With Low Complexity.

Degree: MS, Department of Electrical and Computer Engineering, 2012, University of Alberta

URL: https://era.library.ualberta.ca/files/2v23vt80m

► This thesis presents low complexity design and decoding schemes for low density parity check (LDPC) codes. First, we consider the iterative decoding of LDPC codes… (more)

Subjects/Keywords: iterative decoding; universal codes; LLR; LDPC codes

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APA (6^th Edition):

Zheng, C. (2012). Design and Decoding LDPC Codes With Low Complexity. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/2v23vt80m

Chicago Manual of Style (16^th Edition):

Zheng, Chao. “Design and Decoding LDPC Codes With Low Complexity.” 2012. Masters Thesis, University of Alberta. Accessed June 19, 2019. https://era.library.ualberta.ca/files/2v23vt80m.

MLA Handbook (7^th Edition):

Zheng, Chao. “Design and Decoding LDPC Codes With Low Complexity.” 2012. Web. 19 Jun 2019.

Vancouver:

Zheng C. Design and Decoding LDPC Codes With Low Complexity. [Internet] [Masters thesis]. University of Alberta; 2012. [cited 2019 Jun 19]. Available from: https://era.library.ualberta.ca/files/2v23vt80m.

Council of Science Editors:

Zheng C. Design and Decoding LDPC Codes With Low Complexity. [Masters Thesis]. University of Alberta; 2012. Available from: https://era.library.ualberta.ca/files/2v23vt80m

University of Alberta

13. Maier, Andrew J. Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications.

Degree: MS, Department of Electrical and Computer Engineering, 2016, University of Alberta

URL: https://era.library.ualberta.ca/files/cjd472w72q

► Open Computing Language (OpenCL) is a high-level language that allows developers to produce portable software for heterogeneous parallel computing platforms. OpenCL is available for a… (more)

Subjects/Keywords: OpenCL; LDPC; FPGA; Heterogeneous Programming; Parallel Programming

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APA (6^th Edition):

Maier, A. J. (2016). Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/cjd472w72q

Chicago Manual of Style (16^th Edition):

Maier, Andrew J. “Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications.” 2016. Masters Thesis, University of Alberta. Accessed June 19, 2019. https://era.library.ualberta.ca/files/cjd472w72q.

MLA Handbook (7^th Edition):

Maier, Andrew J. “Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications.” 2016. Web. 19 Jun 2019.

Vancouver:

Maier AJ. Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications. [Internet] [Masters thesis]. University of Alberta; 2016. [cited 2019 Jun 19]. Available from: https://era.library.ualberta.ca/files/cjd472w72q.

Council of Science Editors:

Maier AJ. Design and Optimization of Decoders for Low-Denisty Parity Check Codes Synthesized from the OpenCL Specifications. [Masters Thesis]. University of Alberta; 2016. Available from: https://era.library.ualberta.ca/files/cjd472w72q

University of Edinburgh

14. Khan, Zahid. Optimization of advanced telecommunication algorithms from power and performance perspective.

Degree: 2011, University of Edinburgh

URL: http://hdl.handle.net/1842/5784

► This thesis investigates optimization of advanced telecommunication algorithms from power and performance perspectives. The algorithms chosen are MIMO and LDPC. MIMO is implemented in custom… (more)

▼ This thesis investigates optimization of advanced telecommunication algorithms from power and performance perspectives. The algorithms chosen are MIMO and LDPC. MIMO is implemented in custom ASIC for power optimization and LDPC is implemented on dynamically reconfigurable fabric for both power and performance optimization. Both MIMO and LDPC are considered computational bottlenecks of current and future wireless standards such as IEEE 802.11n for Wi-Fi and IEEE 802.16 for WiMax applications. Optimization of these algorithms is carried out separately. The thesis is organized implicitly in two parts. The first part presents selection and analysis of the VBLAST receiver used in MIMO wireless system from custom ASIC perspective and identifies those processing elements that consume larger area as well as power due to complex signal processing. The thesis models a scalable VBLAST architecture based on MMSE nulling criteria assuming block rayleigh flat fading channel. After identifying the major area and power consuming blocks, it proposes low power and area efficient VLSI architectures for the three building blocks of VBLAST namely Pseudo Inverse, Sorting and NULLing & Cancellation modules assuming a 4x4 MIMO system. The thesis applies dynamic power management, algebraic transformation (strength reduction), resource sharing, clock gating, algorithmic modification, operation substitution, redundant arithmetic and bus encoding as the low power techniques applied at different levels of design abstraction ranging from system to architecture, to reduce power consumption. It also presents novel architectures not only for the constituent blocks but also for the whole receiver. It builds the low power VBLAST receiver for single carrier and provides its area, power and performance figures. It then investigates into the practicality and feasibility of VBLAST into an OFDM environment. It provides estimated data with respect to silicon real estate and throughput from which conclusion can easily be drawn about the feasibility of VBLAST in a multi carrier environment. The second part of the thesis presents novel architectures for the real time adaptive LDPC encoder and decoder as specified in IEEE 802.16E standard for WiMax application. It also presents optimizations of encoder as well as decoder on RICA (Reconfigurable Instruction Cell Architecture). It has searched an optimized way of storing the H matrices that reduces the memory by 20 times. It uses Loop unrolling to distribute the instructions spatially depending upon the available resources to execute them concurrently to as much as possible. The parallel memory banks and distributed registers inside RICA allow good reduction in memory access time. This together with hardware pipelining provides substantial potential for optimizing algorithms from power and performance perspectives. The thesis also suggests ways of improvements inside RICA architecture.

Subjects/Keywords: 621.382; MIMO; LDPC; low power; VBLAST

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APA (6^th Edition):

Khan, Z. (2011). Optimization of advanced telecommunication algorithms from power and performance perspective. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/5784

Chicago Manual of Style (16^th Edition):

Khan, Zahid. “Optimization of advanced telecommunication algorithms from power and performance perspective.” 2011. Doctoral Dissertation, University of Edinburgh. Accessed June 19, 2019. http://hdl.handle.net/1842/5784.

MLA Handbook (7^th Edition):

Khan, Zahid. “Optimization of advanced telecommunication algorithms from power and performance perspective.” 2011. Web. 19 Jun 2019.

Vancouver:

Khan Z. Optimization of advanced telecommunication algorithms from power and performance perspective. [Internet] [Doctoral dissertation]. University of Edinburgh; 2011. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/1842/5784.

Council of Science Editors:

Khan Z. Optimization of advanced telecommunication algorithms from power and performance perspective. [Doctoral Dissertation]. University of Edinburgh; 2011. Available from: http://hdl.handle.net/1842/5784

15. 尾澤, 章弘. ギャップの大きなLDPC符号に対するRichardson符号化法の効率改善 : Improving the complexity of richardson's encoding algorithm for LDPC codes with large gap; ギャップノオオキナ LDPC フゴウニタイスル Richardson フゴウカホウノコウリツカイゼン.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

URL: http://hdl.handle.net/10061/1211

Subjects/Keywords: LDPC符号

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APA (6^th Edition):

尾澤, �. (n.d.). ギャップの大きなLDPC符号に対するRichardson符号化法の効率改善 : Improving the complexity of richardson's encoding algorithm for LDPC codes with large gap; ギャップノオオキナ LDPC フゴウニタイスル Richardson フゴウカホウノコウリツカイゼン. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/1211

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

尾澤, 章弘. “ギャップの大きなLDPC符号に対するRichardson符号化法の効率改善 : Improving the complexity of richardson's encoding algorithm for LDPC codes with large gap; ギャップノオオキナ LDPC フゴウニタイスル Richardson フゴウカホウノコウリツカイゼン.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed June 19, 2019. http://hdl.handle.net/10061/1211.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

尾澤, 章弘. “ギャップの大きなLDPC符号に対するRichardson符号化法の効率改善 : Improving the complexity of richardson's encoding algorithm for LDPC codes with large gap; ギャップノオオキナ LDPC フゴウニタイスル Richardson フゴウカホウノコウリツカイゼン.” Web. 19 Jun 2019.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

尾澤 �. ギャップの大きなLDPC符号に対するRichardson符号化法の効率改善 : Improving the complexity of richardson's encoding algorithm for LDPC codes with large gap; ギャップノオオキナ LDPC フゴウニタイスル Richardson フゴウカホウノコウリツカイゼン. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2019 Jun 19]. Available from: http://hdl.handle.net/10061/1211.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

尾澤 �. ギャップの大きなLDPC符号に対するRichardson符号化法の効率改善 : Improving the complexity of richardson's encoding algorithm for LDPC codes with large gap; ギャップノオオキナ LDPC フゴウニタイスル Richardson フゴウカホウノコウリツカイゼン. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/1211

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Georgia Tech

16. Du, Jianxuan. Layered Space-Time Structure for MIMO-OFDM Systems.

Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech

URL: http://hdl.handle.net/1853/7204

► The low complexity of layered processing makes the layered structure a promising candidate for MIMO systems with a large number of transmit antennas and higher… (more)

▼ The low complexity of layered processing makes the layered structure a promising candidate for MIMO systems with a large number of transmit antennas and higher order modulation. For broadband systems, orthogonal frequency division multiplexing (OFDM) appears promising for its immunity against delay spread. In addition, OFDM is especially suitable for frequency selective MIMO systems since the introduction of orthogonal subcarriers makes system design and implementation as simple as those for flat fading channels. Therefore, the combination of layered structure with OFDM is a promising technique for high-speed wireless data transmission. The proposed research is focused on the layered structure for MIMO-OFDM systems, where several techniques are proposed for performance enhancement, namely, channel estimation based on subspace tracking, parallel detection of group-wise space-time codes by predictive soft interference cancellation, quasi-block diagonal low-density parity-check codes (LDPC) coding and statistical data rate allocation for layered systems. For MIMO-OFDM systems, rank reduction by some linear transform matrix is necessary for channel estimation. In the proposed research, we propose a channel estimation algorithm for MIMO-OFDM systems, which uses the optimum low-rank channel approximation obtained by tracking the frequency autocorrelation matrix of the channel response. Then parallel detection algorithm is proposed for a modified layered system with group-wise space-time coding, where the structure of particular component space-time code trellises is exploited using partial information from the Viterbi decoder of the simultaneously decoded interfering component codes. Next we incorporate the layered structure with LDPC to develop a quasi-block diagonal LDPC space-time structure. The lower triangular structure of the parity check matrix introduces correlation between layers. Each layer, as a part of the whole codeword, can be decoded while taking information from other undetected layers to improve the decoding performance. In the end, a modified layered structure is proposed where the layer detection order is fixed and the data rate for each layer is allocated based on the detection order and channel statistics. With Gaussian approximation of layer capacities, we derive the optimum data rate allocation. Advisors/Committee Members: Douglas Williams (Committee Chair), Doron Lubinsky (Committee Member), Greg Durgin (Committee Member), Mary Ann Ingram (Committee Member), Ye (Geoffrey) Li (Committee Member).

Subjects/Keywords: LDPC; OFDM; MIMO

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APA (6^th Edition):

Du, J. (2005). Layered Space-Time Structure for MIMO-OFDM Systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/7204

Chicago Manual of Style (16^th Edition):

Du, Jianxuan. “Layered Space-Time Structure for MIMO-OFDM Systems.” 2005. Doctoral Dissertation, Georgia Tech. Accessed June 19, 2019. http://hdl.handle.net/1853/7204.

MLA Handbook (7^th Edition):

Du, Jianxuan. “Layered Space-Time Structure for MIMO-OFDM Systems.” 2005. Web. 19 Jun 2019.

Vancouver:

Du J. Layered Space-Time Structure for MIMO-OFDM Systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/1853/7204.

Council of Science Editors:

Du J. Layered Space-Time Structure for MIMO-OFDM Systems. [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/7204

UCLA

17. Vakilinia, Kasra. Coding Schemes to Approach Capacity in Short Blocklength with Feedback and LDPC Coding for Flash Memory.

Degree: Electrical Engineering, 2016, UCLA

URL: http://www.escholarship.org/uc/item/08f672rf

► This dissertation mainly focuses on two different branches of coding theory and its applications:1) coding to approach capacity in short blocklengths using feedback and 2)… (more)

▼ This dissertation mainly focuses on two different branches of coding theory and its applications:1) coding to approach capacity in short blocklengths using feedback and 2) LDPC coding for Flash memory systems. In the first area, we study the benefits that feedback with incremental redundancy can provide to increase the maximum achievable rate in communication systems, using carefully designed adaptive non-binary LDPC codes. We show how to achieve over 90% of the idealized throughput of rate-compatible sphere-packing with maximum-likelihood decoding (RCSP-ML) for average blocklengths of 150-450 bits. This is important because it illustrates that feedback greatly reduces the number of transmitted symbols required to achieve near-capacity performance.We then extend these ideas to feedback systems where the number of incremental transmissions is limited. In order to optimize the blocklengths for each incremental transmission we formulate an integer optimization problem involving an approximation based on the inverse-Gaussian p.d.f., the distribution of the blocklength required for successful decoding. The brute-force approach to solve this computationally complex optimization problem quickly becomes infeasible. In order to solve this problem efficiently, we introduce sequential differential optimization (SDO) algorithm that has only linear complexity to identify optimal incremental transmission lengths. The results obtained from SDO are negligibly different from the exponentially complex exhaustive-search solution. By using the optimized incremental transmission lengths (with an average blocklength of less than 500 bits), non-binary LDPC codes achieve a throughput greater than 90% of the capacity with atwo-phase scheme. Furthermore, we extend these ideas to the case of using cyclic redundancy checks (CRC). With CRC, even better performance in the blocklength range of about 500 bits is obtainable. The overhead associated with a CRC prevents great performance in short blocklength regime (fewer than 400 bits). We also extend these ideas to systems with larger constellations operating at a higher signal-to-noise ratio (SNR).Another incremental transmission coding scheme studied in this dissertation focuses on de- sign and use of rate-compatible protograph-based raptor-like (PBRL) LDPC codes with various blocklengths and rates that can be used in feedback systems over additive-white Gaussian noise (AWGN) channels. The codes proposed in this work use X-OR operations and density evolution to produce additional degree-one parity bits providing extensive rate compatibility. The protographs are also carefully lifted to avoid undesirable graphical structures such as problematic stopping sets. For a target frame error rate of 10−5, at each rate the k = 1032 and k = 16384 code families perform within 1 dB and 0.4 dB, respectively, of both the Gallager bound and the normal approximation. The k = 16384 code family outperforms the best known standardized code family, the AR4JA and longer DVB-S2 codes.We extend the ideas in design of…

Subjects/Keywords: Electrical engineering; Feedback; Flash Memory; LDPC Coding

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APA (6^th Edition):

Vakilinia, K. (2016). Coding Schemes to Approach Capacity in Short Blocklength with Feedback and LDPC Coding for Flash Memory. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/08f672rf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Vakilinia, Kasra. “Coding Schemes to Approach Capacity in Short Blocklength with Feedback and LDPC Coding for Flash Memory.” 2016. Thesis, UCLA. Accessed June 19, 2019. http://www.escholarship.org/uc/item/08f672rf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Vakilinia, Kasra. “Coding Schemes to Approach Capacity in Short Blocklength with Feedback and LDPC Coding for Flash Memory.” 2016. Web. 19 Jun 2019.

Vancouver:

Vakilinia K. Coding Schemes to Approach Capacity in Short Blocklength with Feedback and LDPC Coding for Flash Memory. [Internet] [Thesis]. UCLA; 2016. [cited 2019 Jun 19]. Available from: http://www.escholarship.org/uc/item/08f672rf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vakilinia K. Coding Schemes to Approach Capacity in Short Blocklength with Feedback and LDPC Coding for Flash Memory. [Thesis]. UCLA; 2016. Available from: http://www.escholarship.org/uc/item/08f672rf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Texas – Austin

18. Regulapati, Varsha. Error correction codes in NAND flash memory.

Degree: Electrical and Computer Engineering, 2015, University of Texas – Austin

URL: http://hdl.handle.net/2152/33302

► Error Correction Codes (ECC) are used in NAND Flash memories to detect and correct bit-errors. With shrinking technology nodes and increased memory complexity, bit error… (more)

Subjects/Keywords: Error correction codes; NAND flash memory; LDPC

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APA (6^th Edition):

Regulapati, V. (2015). Error correction codes in NAND flash memory. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/33302

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Regulapati, Varsha. “Error correction codes in NAND flash memory.” 2015. Thesis, University of Texas – Austin. Accessed June 19, 2019. http://hdl.handle.net/2152/33302.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Regulapati, Varsha. “Error correction codes in NAND flash memory.” 2015. Web. 19 Jun 2019.

Vancouver:

Regulapati V. Error correction codes in NAND flash memory. [Internet] [Thesis]. University of Texas – Austin; 2015. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/2152/33302.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Regulapati V. Error correction codes in NAND flash memory. [Thesis]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/33302

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Minnesota

19. Kim, Sangmin. Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes.

Degree: PhD, Electrical Engineering, 2010, University of Minnesota

URL: http://purl.umn.edu/96825

► This thesis proposes efficient algorithm and architecture aspects for binary and nonbinary low- density parity-check (LDPC) codes by developing optimal quantization approaches, decoding algorithms, decoding… (more)

Subjects/Keywords: Architecture; Decoding; LDPC; VLSI; Electrical Engineering

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APA (6^th Edition):

Kim, S. (2010). Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/96825

Chicago Manual of Style (16^th Edition):

Kim, Sangmin. “Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes.” 2010. Doctoral Dissertation, University of Minnesota. Accessed June 19, 2019. http://purl.umn.edu/96825.

MLA Handbook (7^th Edition):

Kim, Sangmin. “Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes.” 2010. Web. 19 Jun 2019.

Vancouver:

Kim S. Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes. [Internet] [Doctoral dissertation]. University of Minnesota; 2010. [cited 2019 Jun 19]. Available from: http://purl.umn.edu/96825.

Council of Science Editors:

Kim S. Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes. [Doctoral Dissertation]. University of Minnesota; 2010. Available from: http://purl.umn.edu/96825

University of Newcastle

20. Brown, Raymond. Design of low-density parity-check Codes for multiple-input multiple-output wireless systems.

Degree: LDPC, 2009, University of Newcastle

URL: http://hdl.handle.net/1959.13/41187

►

Masters Research - Masters of Engineering

Mobile telephony, wireless networks and wireless telemetry systems have gone from simple single-input single-output wireless architectures with low data… (more)

▼

Masters Research - Masters of Engineering

Mobile telephony, wireless networks and wireless telemetry systems have gone from simple single-input single-output wireless architectures with low data transmission rates to complex systems employing multiple antennas and forward error correction algorithms capable of high data transmission rates over wireless channels. Claude Shannon provided the fundamental capacity limits for a communications system and it can be shown that the capacity for a single-input single-output systems is limited in it’s capability to provide for modern wireless applications. The introduction of multiple-input multiple-output systems employing multiple antenna elements and orthogonal coding structures proved beneficial and could provide the capacities required for modern wireless applications. This thesis begins with an introduction and overview of space-time coding and the codes of Tarokh, Jafarkhani and Alamouti. Further, this thesis provides an introduction and overview to the family of forward error correction codes known as low-density parity-check (LDPC) codes. LDPC codes, when employed over Gaussian channels, provide near-Shannon limit performance and the question is posed as to their suitability for a wireless multiple-input multiple-output system employing multiple antennas and space-time coding. This question is answered by the use and demonstration of LDPC codes as outer codes to a MIMO system employing space-time block codes and a modified maximum-likelihood decoder. By modifying the space-time block-code decoder to provide a soft-information output, iterative decoders such as the sum-product algorithm can be employed to provide significant performance gains over a Rayleigh flat-fading channel. Further the use of design tools such as EXIT charts can then be used to design codes. The key to allowing the use of EXIT charts is the observation that a MIMO system employing orthogonal transmissions in a Rayleigh flat-fading channel is the equivalent to a SISO channel employing Nakagami-m fading coefficients. The seemingly complex MIMO system can now be analyzed in the form of a simpler SISO equivalent allowing the use of techniques such as EXIT charts to be employed in order to design codes with known and predictable performance haracteristics. This thesis demonstrates this technique and shows by example the performance gains that can be achieved for MIMO systems and opens some further questions for future research.

Advisors/Committee Members: University of Newcastle. Faculty of Engineering and Built Environment, School of Electrical Engineering and Computer Science.

Subjects/Keywords: MIMO; STBC; LDPC; EXIT Charts; FEC

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APA (6^th Edition):

Brown, R. (2009). Design of low-density parity-check Codes for multiple-input multiple-output wireless systems. (Masters Thesis). University of Newcastle. Retrieved from http://hdl.handle.net/1959.13/41187

Chicago Manual of Style (16^th Edition):

Brown, Raymond. “Design of low-density parity-check Codes for multiple-input multiple-output wireless systems.” 2009. Masters Thesis, University of Newcastle. Accessed June 19, 2019. http://hdl.handle.net/1959.13/41187.

MLA Handbook (7^th Edition):

Brown, Raymond. “Design of low-density parity-check Codes for multiple-input multiple-output wireless systems.” 2009. Web. 19 Jun 2019.

Vancouver:

Brown R. Design of low-density parity-check Codes for multiple-input multiple-output wireless systems. [Internet] [Masters thesis]. University of Newcastle; 2009. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/1959.13/41187.

Council of Science Editors:

Brown R. Design of low-density parity-check Codes for multiple-input multiple-output wireless systems. [Masters Thesis]. University of Newcastle; 2009. Available from: http://hdl.handle.net/1959.13/41187

Universitat Politècnica de València

21. Angarita Preciado, Fabián Enrique. Diseño de decodificadores de altas prestaciones para código LDPC .

Degree: 2013, Universitat Politècnica de València

URL: http://hdl.handle.net/10251/31646

► En esta tesis se han investigado los algoritmos de decodificación para códigos de comprobación de paridad de baja densidad (LDPC) y las arquitecturas para la… (more)

▼ En esta tesis se han investigado los algoritmos de decodificación para códigos de comprobación de paridad de baja densidad (LDPC) y las arquitecturas para la implementación hardware de éstos. El trabajo realizado se centra en los algoritmos del tipo de intercambio de mensajes para códigos estructurados los cuales se incluyen en varios estándares de comunicaciones. Inicialmente se han evaluado las prestaciones de los algoritmos existentes Sum-product, Min-Sum y las principales variantes de este último (Min-Sum con escalado y Min-Sum con offset). Además, se ha realizado un análisis de precisión finita utilizando los códigos LDPC de los estándares IEEE 802.3an, IEEE 802.11n e IEEE 802.16e. Posteriormente se han propuesto dos algoritmos basados en el algoritmo Min-Sum, denominados Min-Sum entero y Min-Sum modificado con corrección. La complejidad de éstos es menor que las de los algoritmos estudiados anteriormente y además permiten una implementación hardware eficiente. Por otra parte, se han estudiado diferentes métodos de actualización de los algoritmos de decodificación: por inundación, por capas horizontales (layered) y por capas verticales (shuffled), y se ha propuesto un nuevo método por capas verticales entrelazadas (x-shuffled) que consigue mejorar la tasa de decodificación. Tras el estudio algorítmico, se han realizado implementaciones hardwar} con diferentes arquitecturas para los algoritmos y métodos de actualización evaluados y propuestos. En la mayoría de algoritmos implementados se requiere el cálculo de los dos primeros mínimos, por lo que inicialmente se realiza un estudio de las arquitecturas hardware para realizar este cálculo y se ha propuesto una nueva arquitectura de menor complejidad. En segundo lugar se ha realizado una comparación de las prestaciones hardware de los diferentes algoritmos con las arquitecturas de referencia: completamente paralela y parcialmente paralela basada en memorias. También se han propuesto dos arquitecturas enfocadas a la alta velocidad, la cuales se implementan con el algoritmo Sum-Product. La primera es una modificación de la arquitectura Sliced Message-Passing que consigue una reducción en el área de la implementación, y la segunda, es una arquitectura específica para el método de actualización propuesto x-shuffled que alcanza tasas de decodificación muy altas. Finalmente, se han implementado los algoritmos propuestos con la arquitectura layered obteniendo implementaciones hardware eficientes con baja área y muy alta tasa de decodificación. Estas últimas consiguen un ratio entre tasa de decodificación y área mejor que las implementaciones existentes en la literatura. Por último, se ha evaluado el comportamiento de los algoritmos de decodificación estudiados en la zona de baja tasa de error, donde las prestaciones se suelen degradar debido a la aparición de un suelo de error. Para ello se ha implementado un simulador hardware usando dispositivos FPGA. La tasa de datos alcanzada con el simulador hardware diseñado es superior a la de otros simuladores documentados… Advisors/Committee Members: Almenar Terré, Vicenç (advisor), Valls Coquillat, Javier (advisor).

Subjects/Keywords: Corrección de errores; Decodificación; Códigos LDPC; VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Angarita Preciado, F. E. (2013). Diseño de decodificadores de altas prestaciones para código LDPC . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/31646

Chicago Manual of Style (16^th Edition):

Angarita Preciado, Fabián Enrique. “Diseño de decodificadores de altas prestaciones para código LDPC .” 2013. Doctoral Dissertation, Universitat Politècnica de València. Accessed June 19, 2019. http://hdl.handle.net/10251/31646.

MLA Handbook (7^th Edition):

Angarita Preciado, Fabián Enrique. “Diseño de decodificadores de altas prestaciones para código LDPC .” 2013. Web. 19 Jun 2019.

Vancouver:

Angarita Preciado FE. Diseño de decodificadores de altas prestaciones para código LDPC . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2013. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/10251/31646.

Council of Science Editors:

Angarita Preciado FE. Diseño de decodificadores de altas prestaciones para código LDPC . [Doctoral Dissertation]. Universitat Politècnica de València; 2013. Available from: http://hdl.handle.net/10251/31646

22. Růžička Lukáš. Návrhový systém pro implementaci a analýzu vlastností LDPC kódu .

Degree: 2014, Czech University of Technology

URL: http://hdl.handle.net/10467/24271

► Low-denstiy parity-check (LDPC, Řídké paritu kontrolující) kódy jsou v těchto dnech celkem populární. Mají dobrý výkon, který je blízko Shannovýmu limitu a mohou být s… (more)

▼ Low-denstiy parity-check (LDPC, Řídké paritu kontrolující) kódy jsou v těchto dnech celkem populární. Mají dobrý výkon, který je blízko Shannovýmu limitu a mohou být s výbornými vysledky využity v satelitní komunikaci. V této práci uvádíme základní nástroje pro práci s nimi. Hlavně ukazujeme způsob, jak generovat pseudo náhodné řidké kontrolní matice H, které definují kód. Dále popisujeme dvě metody algebraické tvorby matice H. V další částí je repeat-accumulate (RA) LDPC kód, který jednodušeji kóduje zdrojová data na kódová slova. Zkoumali jsme také chyby opravující dekódování pro přenesené zprávy přes AWGN kanál, hlavně dekódování s Sum-product algoritmem (SPA), který je hlavně použit s informacemi v podobě log-likelihood ratio (LLR). Dále jsme také ukázali dvě metody pro analýzu kvalit kódů s Bit-error rate (BER) testem a Extrinsic information transfer (EXIT) grafem. V poslední části porovnáváme některé speciální případy kódů pro ukázání rozdílů pro různé parametry. Všechny metody jsou implementovány do MATLABových kódů.; Low-density parity-check (LDPC) codes have become quite popular these days. They have good performance which is close to Shannon limits and can be used in satellite communication with excellent results. This thesis presents elementary tools for work with them. Mainly we show how to generate pseudo-random sparse parity-check matrix H, which define code. We also describe two methods to make algebraically constructed matrix H. Next there is repeat-accumulate (RA) LDPC code which can encode source data to codeword more easily. Further we examine error-correcting decoding for transferred messages through AWGN channel especially with Sum-product algorithm (SPA), which is mainly used with log-likelihood ratio (LLR) information. Then we also present two methods for analyzing qualities of code with Bit-error rate (BER) test and Extrinsic information transfer (EXIT) charts. In the last part we compared some special cases of codes to show differences for various parameters. All methods are implemented in MATLAB codes. Advisors/Committee Members: Sýkora Jan (advisor).

Subjects/Keywords: LDPC; řídké matice; pseudo náhodné matice; AWGN kanál; RA LDPC; SPA dekódování; BER; EXIT graf

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lukáš, R. (2014). Návrhový systém pro implementaci a analýzu vlastností LDPC kódu . (Thesis). Czech University of Technology. Retrieved from http://hdl.handle.net/10467/24271

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lukáš, Růžička. “Návrhový systém pro implementaci a analýzu vlastností LDPC kódu .” 2014. Thesis, Czech University of Technology. Accessed June 19, 2019. http://hdl.handle.net/10467/24271.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lukáš, Růžička. “Návrhový systém pro implementaci a analýzu vlastností LDPC kódu .” 2014. Web. 19 Jun 2019.

Vancouver:

Lukáš R. Návrhový systém pro implementaci a analýzu vlastností LDPC kódu . [Internet] [Thesis]. Czech University of Technology; 2014. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/10467/24271.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lukáš R. Návrhový systém pro implementaci a analýzu vlastností LDPC kódu . [Thesis]. Czech University of Technology; 2014. Available from: http://hdl.handle.net/10467/24271

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. Le Trung, Khoa. Nouvelle approche pour une implémentation matérielle à faible complexité du décodeur PGDBF : New direction on Low complexity implementation of Probabilisitic Gradient Descent Bit Flipping.

Degree: Docteur es, STIC - Cergy, 2017, Cergy-Pontoise

URL: http://www.theses.fr/2017CERG0902

► L’algorithme de basculement de bits à descente de gradient probabiliste (Probabilistic Gradient Descent Bit Flipping :PGDBF) est récemment introduit comme un nouveau type de décodeur… (more)

▼ L’algorithme de basculement de bits à descente de gradient probabiliste (Probabilistic Gradient Descent Bit Flipping :PGDBF) est récemment introduit comme un nouveau type de décodeur de décision forte pour le code de contrôle de parité à faible densité (Low Density Parity Check : LDPC) appliqué au canal symétrique binaire. En suivant précisément les étapes de décodage du décodeur déterministe Gradient Descent Bit-Flipping (GDBF), le PGDBF intègre en plus la perturbation aléatoire dans l'opération de basculement des Nœuds de Variables (VNs) et produit ainsi une performance de décodage exceptionnelle qui est meilleure que tous les décodeurs à basculement des bits (BF : Bit Flipping) connus dans la littérature, et qui approche les performances du décodeur de décision souple. Nous proposons dans cette thèse plusieurs implémentations matérielles du PGDBF, ainsi qu'une analyse théorique de sa capacité de correction d'erreurs. Avec une analyse de chaîne de Markov du décodeur, nous montrons qu’en raison de l'incorporation de la perturbation aléatoire dans le traitement des VNs, le PGDBF s'échappe des états de piégeage qui empêchent sa convergence. De plus, avec la nouvelle méthode d'analyse proposée, la performance du PGDBF peut être prédite et formulée par une équation de taux de trames erronées en fonction du nombre des itérations, pour un motif d'erreur donné. L'analyse fournit également des explications claires sur plusieurs phénomènes de PGDBF tels que le gain de re-décodage (ou de redémarrage) sur un motif d'erreur reçu. La problématique de l’implémentation matérielle du PGDBF est également abordée dans cette thèse. L’implémentation classique du décodeur PGDBF, dans laquelle un générateur de signal probabiliste est ajouté au-dessus du GDBF, est introduite avec une augmentation inévitable de la complexité du décodeur. Plusieurs procédés de génération de signaux probabilistes sont introduits pour minimiser le surcoût matériel du PGDBF. Ces méthodes sont motivées par l'analyse statistique qui révèle les caractéristiques critiques de la séquence aléatoire binaire requise pour obtenir une bonne performance de décodage et suggérer les directions possibles de simplification. Les résultats de synthèse montrent que le PGDBF déployé avec notre méthode de génération des signaux aléatoires n’a besoin qu’une très faible complexité supplémentaire par rapport au GDBF tout en gardant les mêmes performances qu’un décodeur PGDBF théorique. Une implémentation matérielle intéressante et particulière du PGDBF sur les codes LDPC quasicyclique (QC-LPDC) est proposée dans la dernière partie de la thèse. En exploitant la structure du QCLPDC, une nouvelle architecture pour implémenter le PGDBF est proposée sous le nom d'architecture à décalage des Nœuds de Variables (VNSA : Variable-Node Shift Architecture). En implémentant le PGDBF par VNSA, nous montrons que la complexité matérielle du décodeur est même inférieure à celle du GDBF déterministe tout en préservant la performance de décodage aussi élevée que celle fournie par un PGDBF théorique.… Advisors/Committee Members: Declercq, David (thesis director), Ghaffari, Fakhreddine (thesis director).

Subjects/Keywords: LDPC codec; Tolérants aux erreurs; Arithmétique imprécis; LDPC codec; Fault tolerant; Imprecise arithmetic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Le Trung, K. (2017). Nouvelle approche pour une implémentation matérielle à faible complexité du décodeur PGDBF : New direction on Low complexity implementation of Probabilisitic Gradient Descent Bit Flipping. (Doctoral Dissertation). Cergy-Pontoise. Retrieved from http://www.theses.fr/2017CERG0902

Chicago Manual of Style (16^th Edition):

Le Trung, Khoa. “Nouvelle approche pour une implémentation matérielle à faible complexité du décodeur PGDBF : New direction on Low complexity implementation of Probabilisitic Gradient Descent Bit Flipping.” 2017. Doctoral Dissertation, Cergy-Pontoise. Accessed June 19, 2019. http://www.theses.fr/2017CERG0902.

MLA Handbook (7^th Edition):

Le Trung, Khoa. “Nouvelle approche pour une implémentation matérielle à faible complexité du décodeur PGDBF : New direction on Low complexity implementation of Probabilisitic Gradient Descent Bit Flipping.” 2017. Web. 19 Jun 2019.

Vancouver:

Le Trung K. Nouvelle approche pour une implémentation matérielle à faible complexité du décodeur PGDBF : New direction on Low complexity implementation of Probabilisitic Gradient Descent Bit Flipping. [Internet] [Doctoral dissertation]. Cergy-Pontoise; 2017. [cited 2019 Jun 19]. Available from: http://www.theses.fr/2017CERG0902.

Council of Science Editors:

Le Trung K. Nouvelle approche pour une implémentation matérielle à faible complexité du décodeur PGDBF : New direction on Low complexity implementation of Probabilisitic Gradient Descent Bit Flipping. [Doctoral Dissertation]. Cergy-Pontoise; 2017. Available from: http://www.theses.fr/2017CERG0902

24. Γκίκα, Ζαχαρούλα. Διόρθωση λαθών με τη χρήση κωδίκων RS-LDPC.

Degree: 2012, University of Patras

URL: http://hdl.handle.net/10889/6037

► Σήμερα, σε όλα σχεδόν τα τηλεπικοινωνιακά συστήματα τα οποία προορίζονται για αποστολή δεδομένων σε υψηλούς ρυθμούς, έχουν υιοθετηθεί κώδικες διόρθωσης λαθών για την αύξηση της… (more)

▼ Σήμερα, σε όλα σχεδόν τα τηλεπικοινωνιακά συστήματα τα οποία προορίζονται για αποστολή δεδομένων σε υψηλούς ρυθμούς, έχουν υιοθετηθεί κώδικες διόρθωσης λαθών για την αύξηση της αξιοπιστίας τους και τη μείωση της απαιτούμενης ισχύος εκπομπής τους. Οι κώδικες αυτοί δίνουν τη δυνατότητα ανίχνευσης και διόρθωσης των λαθών που μπορεί να δημιουργήσει το μέσο μετάδοσης (κανάλι) σε κάποιο τμήμα πληροφορίας που μεταφέρεται μέσω του τηλεπικοινωνιακού δικτύου. Μία κατηγορία τέτοιων κωδίκων, και μάλιστα με εξαιρετικές επιδόσεις, είναι η οικογένεια των LDPC (Low Density Parity Check) κωδίκων. Πρόκειται για γραμμικούς μπλοκ κώδικες, με απόδοση πολύ κοντά στο όριο Shannon. Στην παρούσα διπλωματική μελετώνται οι κώδικες LDPC και σχετικές αρχιτεκτονικές υλικού. Oι κώδικες LDPC χρησιμοποιούνται όλο και περισσότερο σε εφαρμογές που απαιτούν αξιόπιστη και υψηλής απόδοσης μετάδοση, υπό την παρουσία ισχυρού θορύβου. Η κατασκευή τους στηρίζεται στη χρήση πινάκων ελέγχου ισοτιμίας χαμηλής πυκνότητας, ενώ η αποκωδικοποίηση εκτελείται με τη χρήση επαναληπτικών αλγορίθμων. Σε υψηλά επίπεδα θορύβου παρουσιάζουν πολύ καλή διορθωτική ικανότητα, αλλά υστερούν σε χαμηλότερα επίπεδα θορύβου, όπου υποφέρουν από το φαινόμενο του error floor. Στη συγκεκριμένη εργασία μελετάται εκτενώς μία αλγεβρική μέθοδος για την κατασκευή regular LDPC κωδίκων που βασίζεται σε κώδικες Reed-Solomon με δύο σύμβολα πληροφορίας. Η μέθοδος αυτή μας επιτρέπει την κατασκευή ενός πίνακα ελέγχου ισοτιμίας Η για τον κώδικα LDPC, όπου το διάγραμμα Tanner που του αντιστοιχεί δεν περιέχει κύκλους μήκους 4 (ελάχιστο μήκος κύκλου 6). Οι κύκλοι μικρού μήκους στο διάγραμμα Tanner «εγκλωβίζουν» τον αποκωδικοποιητή σε καταστάσεις που δεν μπορεί να ανιχνεύσει και να διορθώσει τα λάθη που δημιουργήθηκαν στη μετάδοση. Έτσι χρησιμοποιώντας την παραπάνω μέθοδο μπορούμε να κατασκευάσουμε απλούς σε δομή κώδικες, που σε συνδυασμό με τους επαναληπτικούς αλγορίθμους αποκωδικοποίησης οδηγούν σε αποκωδικοποιητές με εξαιρετικές διορθωτικές ικανότητες και εμφάνιση error floor σε πολύ χαμηλές τιμές του BER. Ακόμα, αυτού του τύπου οι πίνακες ισοτιμίας επιβάλλουν μία συγκεκριμένη δομή για το γεννήτορα πίνακα G που χρησιμοποιείται για την κωδικοποίηση. Για το λόγο αυτό μελετάται επίσης ο τρόπος για να κατασκευάσουμε ένα συστηματικό πίνακα G, ο οποίος απλουστεύει κατά πολύ τη διαδικασία της κωδικοποίησης. Όλες οι παραπάνω διαδικασίες εφαρμόζονται για την κατασκευή του κώδικα (2048,1723) RS-LDPC. Πρόκειται για έναν κώδικα ρυθμού 0,84 που χρησιμοποιείται από το πρότυπο 802.3an της IEEE για το 10GBASE-T Ethernet και παρουσιάζει ιδιαίτερο ενδιαφέρον λόγω των επιδόσεών του. Για τον κώδικα αυτό προτείνεται σχεδίαση για τον κωδικοποιητή και τον αποκωδικοποιητή καθώς και για όλα τα εξωτερικά κυκλώματα που απαιτούνται ώστε να δημιουργηθεί ένα ολοκληρωμένο σύστημα αποστολής, λήψης και διόρθωσης δεδομένων. Έχοντας όλο το υπόβαθρο για την κατασκευή ενός RS-LDPC συστήματος κωδικοποίησης-αποκωδικοποίησης, υλοποιήσαμε τη σχεδίαση του συστήματος σε κώδικα VHDL ενώ εκτελέστηκαν οι απαραίτητες εξομοιώσεις (Modelsim).… Advisors/Committee Members: Παλιουράς, Βασίλειος, Gkika, Zacharoula, Μπίρμπας, Αλέξιος, Μπερμπερίδης, Κωνσταντίνος.

Subjects/Keywords: Κώδικες RS-LDPC; Διόρθωση λαθών; 621.382 1; RS-LDPC codes; Error correction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Γκίκα, �. (2012). Διόρθωση λαθών με τη χρήση κωδίκων RS-LDPC. (Masters Thesis). University of Patras. Retrieved from http://hdl.handle.net/10889/6037

Chicago Manual of Style (16^th Edition):

Γκίκα, Ζαχαρούλα. “Διόρθωση λαθών με τη χρήση κωδίκων RS-LDPC.” 2012. Masters Thesis, University of Patras. Accessed June 19, 2019. http://hdl.handle.net/10889/6037.

MLA Handbook (7^th Edition):

Γκίκα, Ζαχαρούλα. “Διόρθωση λαθών με τη χρήση κωδίκων RS-LDPC.” 2012. Web. 19 Jun 2019.

Vancouver:

Γκίκα �. Διόρθωση λαθών με τη χρήση κωδίκων RS-LDPC. [Internet] [Masters thesis]. University of Patras; 2012. [cited 2019 Jun 19]. Available from: http://hdl.handle.net/10889/6037.

Council of Science Editors:

Γκίκα �. Διόρθωση λαθών με τη χρήση κωδίκων RS-LDPC. [Masters Thesis]. University of Patras; 2012. Available from: http://hdl.handle.net/10889/6037

25. Planjery, Shiva Kumar. Iterative decoding beyond belief propagation for low-density parity-check codes : Décodage itératif pour les codes LDPC au-delà de la propagation de croyances.

Degree: Docteur es, STIC (sciences et technologies de l'information et de la communication) - Cergy, 2012, Cergy-Pontoise; University of Arizona

URL: http://www.theses.fr/2012CERG0618

► Les codes Low-Density Parity-Check (LDPC) sont au coeur de larecherche des codes correcteurs d'erreurs en raison de leur excellenteperformance de décodage en utilisant un algorithme… (more)

▼ Les codes Low-Density Parity-Check (LDPC) sont au coeur de larecherche des codes correcteurs d'erreurs en raison de leur excellenteperformance de décodage en utilisant un algorithme de décodageitératif de type propagation de croyances (Belief Propagation - BP).Cet algorithme utilise la représentation graphique d'un code, ditgraphe de Tanner, et calcule les fonctions marginales sur le graphe.Même si l'inférence calculée n'est exacte que sur un graphe acyclique(arbre), l'algorithme BP estime de manière très proche les marginalessur les graphes cycliques, et les codes LDPC peuvent asymptotiquementapprocher la capacité de Shannon avec cet algorithme.Cependant, sur des codes de longueurs finies dont la représentationgraphique contient des cycles, l'algorithme BP est sous-optimal etdonne lieu à l'apparition du phénomène dit de plancher d'erreur. Leplancher d'erreur se manifeste par la dégradation soudaine de la pentedu taux d'erreur dans la zone de fort rapport signal à bruit où lesstructures néfastes au décodage sont connues en termes de TrappingSets présents dans le graphe de Tanner du code, entraînant un échec dudécodage. De plus, les effets de la quantification introduite parl'implémentation en hardware de l'algorithme BP peuvent amplifier ceproblème de plancher d'erreur.Dans cette thèse nous introduisons un nouveau paradigme pour ledécodage itératif à précision finie des codes LDPC sur le canalbinaire symétrique. Ces nouveaux décodeurs, appelés décodeursitératifs à alphabet fini (Finite Alphabet Iterative Decoders – FAID)pour préciser que les messages appartiennent à un alphabet fini, sontcapables de surpasser l'algorithme BP dans la région du plancherd'erreur. Les messages échangés par les FAID ne sont pas desprobabilités ou vraisemblances quantifiées, et les fonctions de miseà jour des noeuds de variable ne copient en rien le décodage par BP cequi contraste avec les décodeurs BP quantifiés traditionnels. Eneffet, les fonctions de mise à jour sont de simples tables de véritéconçues pour assurer une plus grande capacité de correction d'erreuren utilisant la connaissance de topologies potentiellement néfastes audécodage présentes dans un code donné. Nous montrons que sur demultiples codes ayant un poids colonne de trois, il existe des FAIDutilisant 3 bits de précision pouvant surpasser l'algorithme BP(implémenté en précision flottante) dans la zone de plancher d'erreursans aucun compromis dans la latence de décodage. C'est pourquoi lesFAID obtiennent des performances supérieures comparées au BP avecseulement une fraction de sa complexité.Par ailleurs, nous proposons dans cette thèse une décimation amélioréedes FAID pour les codes LDPC dans le traitement de la mise à jour desnoeuds de variable. La décimation implique de fixer certains bits ducode à une valeur particulière pendant le décodage et peut réduire demanière significative le nombre d'itérations requises pour corriger uncertain nombre d'erreurs fixé tout en maintenant de bonnesperformances d'un FAID, le rendant plus à même d'être analysé. Nousillustrons cette… Advisors/Committee Members: Declercq, David (thesis director), Vasic, Bane (thesis director).

Subjects/Keywords: Ldpc; Propagation de croyances; Trapping sets; Décodage itératif; Ldpc; Belief propagation; Trapping sets

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Planjery, S. K. (2012). Iterative decoding beyond belief propagation for low-density parity-check codes : Décodage itératif pour les codes LDPC au-delà de la propagation de croyances. (Doctoral Dissertation). Cergy-Pontoise; University of Arizona. Retrieved from http://www.theses.fr/2012CERG0618

Chicago Manual of Style (16^th Edition):

Planjery, Shiva Kumar. “Iterative decoding beyond belief propagation for low-density parity-check codes : Décodage itératif pour les codes LDPC au-delà de la propagation de croyances.” 2012. Doctoral Dissertation, Cergy-Pontoise; University of Arizona. Accessed June 19, 2019. http://www.theses.fr/2012CERG0618.

MLA Handbook (7^th Edition):

Planjery, Shiva Kumar. “Iterative decoding beyond belief propagation for low-density parity-check codes : Décodage itératif pour les codes LDPC au-delà de la propagation de croyances.” 2012. Web. 19 Jun 2019.

Vancouver:

Planjery SK. Iterative decoding beyond belief propagation for low-density parity-check codes : Décodage itératif pour les codes LDPC au-delà de la propagation de croyances. [Internet] [Doctoral dissertation]. Cergy-Pontoise; University of Arizona; 2012. [cited 2019 Jun 19]. Available from: http://www.theses.fr/2012CERG0618.

Council of Science Editors:

Planjery SK. Iterative decoding beyond belief propagation for low-density parity-check codes : Décodage itératif pour les codes LDPC au-delà de la propagation de croyances. [Doctoral Dissertation]. Cergy-Pontoise; University of Arizona; 2012. Available from: http://www.theses.fr/2012CERG0618

26. Ben Maad, Hassen. Optimisation des stratégies de décodage des codes LDPC dans les environnements impulsifs : application aux réseaux de capteurs et ad hoc : LDPC strategy decoding optimization in impulsive environments : sensors and ad hoc networks application.

Degree: Docteur es, Génie informatique, automatique et traitement du signal, 2011, Reims

URL: http://www.theses.fr/2011REIMS023

►

L’objectif de cette thèse est d’étudier le comportement des codes LDPC dans un environnement où l’interférence générée par un réseau n’est pas de nature gaussienne… (more)

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L’objectif de cette thèse est d’étudier le comportement des codes LDPC dans un environnement où l’interférence générée par un réseau n’est pas de nature gaussienne mais présente un caractère impulsif. Un premier constat rapide montre que sans précaution, les performances de ces codes se dégradent très significativement. Nous étudions tout d’abord les différentes solutions possibles pour modéliser les bruits impulsifs. Dans le cas des interférences d’accès multiples qui apparaissent dans les réseaux ad hoc et les réseaux de capteurs, il nous semble approprié de choisir les distributions alpha-stables. Généralisation de la gaussienne, stables par convolution, elles peuvent être validées théoriquement dans plusieurs situations.Nous déterminons alors la capacité de l’environnement α-stable et montrons par une approche asymptotique que les codes LDPC dans cet environnement sont bons mais qu’une simple opération linéaire à l’entrée du décodeur ne permet pas d’obtenir de bonnes performances. Nous avons donc proposé différentes façons de calculer la vraisemblance en entrée du décodeur. L’approche optimale est très complexe à mettre en oeuvre. Nous avons étudié plusieurs approches différentes et en particulier le clipping dont nous avons cherché les paramètres optimaux.

The goal of this PhD is to study the performance of LDPC codes in an environment where interference, generated by the network, has not a Gaussian nature but presents an impulsive behavior.A rapid study shows that, if we do not take care, the codes’ performance significantly degrades.In a first step, we study different approaches for impulsive noise modeling. In the case of multiple access interference that disturb communications in ad hoc or sensor networks, the choice of alpha-stable distributions is appropriate. They generalize Gaussian distributions, are stable by convolution and can be theoretically justified in several contexts.We then determine the capacity if the α-stable environment and show using an asymptotic method that LDPC codes in such an environment are efficient but that a simple linear operation on the received samples at the decoder input does not allow to obtain the expected good performance. Consequently we propose several methods to obtain the likelihood ratio necessary at the decoder input. The optimal solution is highly complex to implement. We have studied several other approaches and especially the clipping for which we proposed several approaches to determine the optimal parameters.

Advisors/Committee Members: Gellé, Guillaume (thesis director).

Subjects/Keywords: Distributions alpha-stables; Codes LDPC; Bruit impulsif; Alpha-stable distributions; LDPC codes; Impulsive noise

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ben Maad, H. (2011). Optimisation des stratégies de décodage des codes LDPC dans les environnements impulsifs : application aux réseaux de capteurs et ad hoc : LDPC strategy decoding optimization in impulsive environments : sensors and ad hoc networks application. (Doctoral Dissertation). Reims. Retrieved from http://www.theses.fr/2011REIMS023

Chicago Manual of Style (16^th Edition):

Ben Maad, Hassen. “Optimisation des stratégies de décodage des codes LDPC dans les environnements impulsifs : application aux réseaux de capteurs et ad hoc : LDPC strategy decoding optimization in impulsive environments : sensors and ad hoc networks application.” 2011. Doctoral Dissertation, Reims. Accessed June 19, 2019. http://www.theses.fr/2011REIMS023.

MLA Handbook (7^th Edition):

Ben Maad, Hassen. “Optimisation des stratégies de décodage des codes LDPC dans les environnements impulsifs : application aux réseaux de capteurs et ad hoc : LDPC strategy decoding optimization in impulsive environments : sensors and ad hoc networks application.” 2011. Web. 19 Jun 2019.

Vancouver:

Ben Maad H. Optimisation des stratégies de décodage des codes LDPC dans les environnements impulsifs : application aux réseaux de capteurs et ad hoc : LDPC strategy decoding optimization in impulsive environments : sensors and ad hoc networks application. [Internet] [Doctoral dissertation]. Reims; 2011. [cited 2019 Jun 19]. Available from: http://www.theses.fr/2011REIMS023.

Council of Science Editors:

Ben Maad H. Optimisation des stratégies de décodage des codes LDPC dans les environnements impulsifs : application aux réseaux de capteurs et ad hoc : LDPC strategy decoding optimization in impulsive environments : sensors and ad hoc networks application. [Doctoral Dissertation]. Reims; 2011. Available from: http://www.theses.fr/2011REIMS023

Utah State University

27. Tithi, Tasnuva Tarannum. Error-Floors of the 802.3an LDPC Code for Noise Assisted Decoding.

Degree: PhD, Electrical and Computer Engineering, 2019, Utah State University

URL: https://digitalcommons.usu.edu/etd/7465

► In digital communication, information is sent as bits, which is corrupted by the noise present in wired/wireless medium known as the channel. The Low… (more)

Subjects/Keywords: LDPC code; Error Correction Code; Stochastic Decoding; LDPC Error Floors; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tithi, T. T. (2019). Error-Floors of the 802.3an LDPC Code for Noise Assisted Decoding. (Doctoral Dissertation). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/7465

Chicago Manual of Style (16^th Edition):

Tithi, Tasnuva Tarannum. “Error-Floors of the 802.3an LDPC Code for Noise Assisted Decoding.” 2019. Doctoral Dissertation, Utah State University. Accessed June 19, 2019. https://digitalcommons.usu.edu/etd/7465.

MLA Handbook (7^th Edition):

Tithi, Tasnuva Tarannum. “Error-Floors of the 802.3an LDPC Code for Noise Assisted Decoding.” 2019. Web. 19 Jun 2019.

Vancouver:

Tithi TT. Error-Floors of the 802.3an LDPC Code for Noise Assisted Decoding. [Internet] [Doctoral dissertation]. Utah State University; 2019. [cited 2019 Jun 19]. Available from: https://digitalcommons.usu.edu/etd/7465.

Council of Science Editors:

Tithi TT. Error-Floors of the 802.3an LDPC Code for Noise Assisted Decoding. [Doctoral Dissertation]. Utah State University; 2019. Available from: https://digitalcommons.usu.edu/etd/7465

28. Shams, Bilal. Les Codes LDPC non-binaires de nouvelle génération : Development of new generation non-binary LDPC error correcting codes.

Degree: Docteur es, STIC (sciences et technologies de l'information et de la communication), 2010, Cergy-Pontoise

URL: http://www.theses.fr/2010CERG0525

►

Dans cette thèse, nous présentons nos travaux dans le domaine de l'algorithme de décodage non-binaire pour les classes générales de codes LDPC non-binaires. Les Low-Density… (more)

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Dans cette thèse, nous présentons nos travaux dans le domaine de l'algorithme de décodage non-binaire pour les classes générales de codes LDPC non-binaires. Les Low-Density Parity-Check (LDPC) codes ont été initialement présentés par Gallager en 1963, et après quelques avancées théoriques fondamentales, ils ont été pris en compte dans les normes comme le DVB-S2, WI-MAX, DSL, W-LAN etc. Plus tard, Les codes LDPC non-binaires (NB-LDPC) ont été proposés dans la littérature, et ont montré de meilleures performances lorsque la taille du code est petite ou lorsqu'il est utilisé sur des canaux non-binaires. Toutefois, les avantages de l'utilisation des codes LDPC non-binaires entrainent une complexité de décodage fortement accrue. Pour un code défini dans GF (q), la complexité est de l'ordre O(q²). De même, la mémoire nécessaire pour stocker les messages est d'ordre O(q). Par conséquent, l'implémentation d'un décodeur LDPC-définie sur un ordre q> 64 devient pratiquement impossible.L'objectif principal de la thèse est de développer des algorithmes a complexité réduite, pour les codes LDPC non-binaires qui démontrent un rendement excellent et qui soient implémentable. Pour optimiser les performances de décodage, non seulement l'algorithme de décodage est important, mais aussi la structure du code joue un rôle important. Avec cet objectif à l'esprit, une nouvelle famille de codes appelés codes cluster-NB-LDPC a été élaboré et des améliorations spécifiques du décodeur NB pour les codes de cluster-NB-LDPC ont été proposés. Notre principal résultat est que nous étions en mesure de proposer des décodeurs de codes cluster-NB-LDPC avec une complexité réduite par rapport à décodeurs d'habitude pour les codes LDPC-NB sur les corps de Galois, sans aucune perte de performance en matière de la capacité de correction d'erreur.

In this thesis we present our work in the domain of non-binary decoding algorithm for general classes of non-binary LDPC codes. Low-Density Parity-Check (LDPC) codes were originally presented by Gallager in 1963, and after some fundamental theoretical advancements, they were considered in standards like DVB-S2, WI-MAX, DSL, W-LAN etc. Later on, non-binary LDPC (NB-LDPC)codes were proposed in the litterature, and showed better performance for small lengths or when used on non-binary channels. However, the advantages of using NB-LDPC codes comes with the consequence of an heavily increased decoding complexity. For a code defined in GF(q), the complexity is of the order O(q²). Similarly, the memory required for storing messages is of order O(q). Consequently, the implementation of an LDPC-decoder defined over a field order q > 64 becomes practically impossible.The main objective of the thesis is to develop reduced complexity algorithms for non-binary LDPC codes that exhibit excellent performance and is practically im-plementable. For better decoding performance, not only the decoding algorithm is important, but also the structure of the code plays an important role. With this goal in mind, a new family of codes…

Advisors/Committee Members: Declercq, David (thesis director).

Subjects/Keywords: Codes LDPC non-binaires; Corps fini de Galois; Codes LDPC defini sur les groups fini; Cluster LDPC codes; Les algorithmes de decodage; Codes de correction des erreurs; Non-binary LDPC codes; Finite Galois gields; LDPC defined over finite groups; Cluster LDPC codes; Decoding algorithms; Error correcting codes

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Shams, B. (2010). Les Codes LDPC non-binaires de nouvelle génération : Development of new generation non-binary LDPC error correcting codes. (Doctoral Dissertation). Cergy-Pontoise. Retrieved from http://www.theses.fr/2010CERG0525

Chicago Manual of Style (16^th Edition):

Shams, Bilal. “Les Codes LDPC non-binaires de nouvelle génération : Development of new generation non-binary LDPC error correcting codes.” 2010. Doctoral Dissertation, Cergy-Pontoise. Accessed June 19, 2019. http://www.theses.fr/2010CERG0525.

MLA Handbook (7^th Edition):

Shams, Bilal. “Les Codes LDPC non-binaires de nouvelle génération : Development of new generation non-binary LDPC error correcting codes.” 2010. Web. 19 Jun 2019.

Vancouver:

Shams B. Les Codes LDPC non-binaires de nouvelle génération : Development of new generation non-binary LDPC error correcting codes. [Internet] [Doctoral dissertation]. Cergy-Pontoise; 2010. [cited 2019 Jun 19]. Available from: http://www.theses.fr/2010CERG0525.

Council of Science Editors:

Shams B. Les Codes LDPC non-binaires de nouvelle génération : Development of new generation non-binary LDPC error correcting codes. [Doctoral Dissertation]. Cergy-Pontoise; 2010. Available from: http://www.theses.fr/2010CERG0525

29. Li, Ao. Performances des codes correcteurs d’erreur LDPC appliqués au lien Fronthaul optique haut-débit pour l’architecture C-RAN du réseau 5G : conception et implantation sur FPGA : Modeling and simulation of high speed optical transmission and forward error correction design and implementation using FPGA.

Degree: Docteur es, Electronique des Hautes Fréquences, Photonique et Systèmes, 2017, Limoges

URL: http://www.theses.fr/2017LIMO0110

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De nos jours, l’architecture du réseau mobile est en pleine évolution pour assurer la montée en débit entre les Centraux (CO) (réseaux coeurs) et différents… (more)

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De nos jours, l’architecture du réseau mobile est en pleine évolution pour assurer la montée en débit entre les Centraux (CO) (réseaux coeurs) et différents terminaux comme les mobiles, ordinateurs, tablettes afin de satisfaire les utilisateurs. Pour faire face à ces défis du futur, le réseau C-RAN (Cloud ou Centralized-RAN) est connu comme une solution de la 5G. Dans le contexte C-RAN, toutes les BBUs (Base Band Units) sont centralisées dans le CO, seules les RRH (Remote Radio Head) restent situées à la tête de la station de base (BS). Un nouveau segment entre les BBUs et RRHs apparait nommé « fronthaul ». Il est basé sur des transmissions D-ROF (digital radio-overfiber) et transporte le signal radio numérique à un débit binaire élevé en utilisant le protocole CPRI (Common Public Radio Interface). En prenant en compte le CAPEX et l’OPEX, le projet ANR LAMPION a proposé la technologie RSOA (Reflective Semiconductor Optical Amplifier) auto alimenté afin de rendre la solution plus flexible et s’affranchir d’émetteurs/récepteurs colorés dans le cadre de transmission WDM-PON (Wavelength Division Multiplexing Passive Optical Network). Néanmoins, il est nécessaire d’ajouter un FEC (forward error corrector) dans la transmission pour assurer la qualité de service. Donc l’objectif de cette thèse est de trouver le FEC le plus adéquat à appliquer dans le contexte C-RAN. Nos travaux se sont focalisés sur l’utilisation de codes LDPC, choisis après comparaisons des performances avec les autres types de codes. Nous avons précisé les paramètres (rendement du code, taille de la matrice, cycle, etc.) nécessaires pour les codes LDPC afin d'obtenir les meilleures performances. Les algorithmes LDPC à décisions dures ont été choisis après considération du compromis entre complexités de circuit et performance. Parmi ces algorithmes à décision dures, le GDBF (gradient descent bit-flipping) était la meilleure solution. La prise en compte d’un CAN 2-Bit dans le canal nous a amené à proposer une variante : le BWGDBF (Balanced weighted GDBF). Des optimisations ont également été faites en regard de la convergence de l'algorithme et de la latence. Enfin, nous avons réussi à implémenter notre propre algorithme sur le FPGA Spartan 6 xc6slx16. Plusieurs méthodes ont été proposées pour atteindre une latence de 5 μs souhaitée dans le contexte C-RAN. Cette thèse a été soutenue par le projet ANR LAMPION (Lambada-based Access and Metropolitan Passive Optical networks).

Nowadays, the architecture of the mobile network is in full evolution to ensure the increase in terms of bit rate between the Central (CO) (core networks) and various terminals such as mobiles, computers, tablets in order to satisfy the users. To address these challenges of the future, the C-RAN (Cloud or Centralized-RAN) network is known as a 5G solution. In the C-RAN context, all BBUs (Base Band Units) are centralized in the CO, only the RRH (Remote Radio Head) remain at the head of the base station (BS). A new segment between BBUs and RRHs appears called "fronthaul". It is based on…

Advisors/Committee Members: Aupetit-Berthelemot, Christelle (thesis director), Meghdadi Neyshabouri, Vahid (thesis director), Cances, Jean-Pierre (thesis director).

Subjects/Keywords: Codes correcteurs d’erreur,; C-RAN; LDPC; Fronthaul optique; Forward error code; C-RAN; LDPC; Optical Fronthaul; 621.382 2

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Li, A. (2017). Performances des codes correcteurs d’erreur LDPC appliqués au lien Fronthaul optique haut-débit pour l’architecture C-RAN du réseau 5G : conception et implantation sur FPGA : Modeling and simulation of high speed optical transmission and forward error correction design and implementation using FPGA. (Doctoral Dissertation). Limoges. Retrieved from http://www.theses.fr/2017LIMO0110

Chicago Manual of Style (16^th Edition):

Li, Ao. “Performances des codes correcteurs d’erreur LDPC appliqués au lien Fronthaul optique haut-débit pour l’architecture C-RAN du réseau 5G : conception et implantation sur FPGA : Modeling and simulation of high speed optical transmission and forward error correction design and implementation using FPGA.” 2017. Doctoral Dissertation, Limoges. Accessed June 19, 2019. http://www.theses.fr/2017LIMO0110.

MLA Handbook (7^th Edition):

Li, Ao. “Performances des codes correcteurs d’erreur LDPC appliqués au lien Fronthaul optique haut-débit pour l’architecture C-RAN du réseau 5G : conception et implantation sur FPGA : Modeling and simulation of high speed optical transmission and forward error correction design and implementation using FPGA.” 2017. Web. 19 Jun 2019.

Vancouver:

Li A. Performances des codes correcteurs d’erreur LDPC appliqués au lien Fronthaul optique haut-débit pour l’architecture C-RAN du réseau 5G : conception et implantation sur FPGA : Modeling and simulation of high speed optical transmission and forward error correction design and implementation using FPGA. [Internet] [Doctoral dissertation]. Limoges; 2017. [cited 2019 Jun 19]. Available from: http://www.theses.fr/2017LIMO0110.

Council of Science Editors:

Li A. Performances des codes correcteurs d’erreur LDPC appliqués au lien Fronthaul optique haut-débit pour l’architecture C-RAN du réseau 5G : conception et implantation sur FPGA : Modeling and simulation of high speed optical transmission and forward error correction design and implementation using FPGA. [Doctoral Dissertation]. Limoges; 2017. Available from: http://www.theses.fr/2017LIMO0110

30. Nguyen Ly, Thien Truong. Mise en oeuvre matérielle de décodeurs LDPC haut débit, en exploitant la robustesse du décodage par passage de messages aux imprécisions de calcul : Efficient Hardware Implementations of LDPC Decoders, through Exploiting Impreciseness in Message-Passing Decoding Algorithms.

Degree: Docteur es, Génie électrique et électronique - Cergy, 2017, Cergy-Pontoise

URL: http://www.theses.fr/2017CERG0904

► Les codes correcteurs d'erreurs sont une composante essentielle de tout système de communication, capables d’assurer le transport fiable de l’information sur un canal de communication… (more)

▼ Les codes correcteurs d'erreurs sont une composante essentielle de tout système de communication, capables d’assurer le transport fiable de l’information sur un canal de communication bruité. Les systèmes de communication de nouvelle génération devront faire face à une demande sans cesse croissante en termes de débit binaire, pouvant aller de 1 à plusieurs centaines de gigabits par seconde. Dans ce contexte, les codes LDPC (pour Low-Density Parity-Check, en anglais), sont reconnus comme une des solutions les mieux adaptées, en raison de la possibilité de paralléliser massivement leurs algorithmes de décodage et les architectures matérielles associées. Cependant, si l’utilisation d’architectures massivement parallèles permet en effet d’atteindre des débits très élevés, cette solution entraine également une augmentation significative du coût matériel.L’objectif de cette thèse est de proposer des implémentations matérielles de décodeurs LDPC très haut débit, en exploitant la robustesse des algorithmes de décodage par passage de messages aux imprécisions de calcul. L’intégration dans le décodage itératif de mécanismes de calcul imprécis, s’accompagne du développement de nouvelles approches d’optimisation du design en termes de coût, débit et capacité de correction.Pour ce faire, nous avons considéré l’optimisation conjointe de (i) le bloc de quantification qui fournit l'information à précision finie au décodeur, et (ii) les unités de traitement imprécis des données, pour la mise à jour des messages échangés pendant de processus de décodage. Ainsi, nous avons tout d’abord proposé un quantificateur à faible complexité, qui peut être optimisé par évolution de densité en fonction du code LDPC utilisé et capable d’approcher de très près les performances d’un quantificateur optimal. Le quantificateur proposé a été en outre optimisé et utilisé pour chacun des décodeurs imprécis proposés ensuite dans cette thèse.Nous avons ensuite proposé, analysé et implémenté plusieurs décodeurs LDPC imprécis. Les deux premiers décodeurs sont des versions imprécises du décodeur « Offset Min-Sum » (OMS) : la surestimation des messages des nœuds de contrôle est d’abord compensée par un simple effacement du bit de poids faible (« Partially OMS »), ensuite le coût matériel est d’avantage réduit en supprimant un signal spécifique (« Imprecise Partially OMS »). Les résultats d’implémentation sur cible FPGA montrent une réduction importante du coût matériel, tout en assurant une performance de décodage très proche du OMS, malgré l'imprécision introduite dans les unités de traitement.Nous avions ensuite introduit les décodeurs à alphabet fini non-surjectifs (NS-FAIDs, pour « Non-Surjective Finite Alphabet Iterative Decoders », en anglais), qui étendent le concept d’« imprécision » au bloc mémoire du décodeur LDPC. Les décodeurs NS-FAIDs ont été optimisés par évolution de densité pour des codes LDPC réguliers et irréguliers. Les résultats d'optimisation révèlent différents compromis possibles entre la performance de décodage et l'efficacité de la mise… Advisors/Committee Members: Declercq, David (thesis director).

Subjects/Keywords: Ldpc; Imprécisions; D'optimisation de coût; Haut débit; NS-FAIDs; Ldpc; Impreciseness; Cost-Effective; High-Throughput; NS-FAIDs

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Nguyen Ly, T. T. (2017). Mise en oeuvre matérielle de décodeurs LDPC haut débit, en exploitant la robustesse du décodage par passage de messages aux imprécisions de calcul : Efficient Hardware Implementations of LDPC Decoders, through Exploiting Impreciseness in Message-Passing Decoding Algorithms. (Doctoral Dissertation). Cergy-Pontoise. Retrieved from http://www.theses.fr/2017CERG0904

Chicago Manual of Style (16^th Edition):

Nguyen Ly, Thien Truong. “Mise en oeuvre matérielle de décodeurs LDPC haut débit, en exploitant la robustesse du décodage par passage de messages aux imprécisions de calcul : Efficient Hardware Implementations of LDPC Decoders, through Exploiting Impreciseness in Message-Passing Decoding Algorithms.” 2017. Doctoral Dissertation, Cergy-Pontoise. Accessed June 19, 2019. http://www.theses.fr/2017CERG0904.

MLA Handbook (7^th Edition):

Nguyen Ly, Thien Truong. “Mise en oeuvre matérielle de décodeurs LDPC haut débit, en exploitant la robustesse du décodage par passage de messages aux imprécisions de calcul : Efficient Hardware Implementations of LDPC Decoders, through Exploiting Impreciseness in Message-Passing Decoding Algorithms.” 2017. Web. 19 Jun 2019.

Vancouver:

Nguyen Ly TT. Mise en oeuvre matérielle de décodeurs LDPC haut débit, en exploitant la robustesse du décodage par passage de messages aux imprécisions de calcul : Efficient Hardware Implementations of LDPC Decoders, through Exploiting Impreciseness in Message-Passing Decoding Algorithms. [Internet] [Doctoral dissertation]. Cergy-Pontoise; 2017. [cited 2019 Jun 19]. Available from: http://www.theses.fr/2017CERG0904.

Council of Science Editors:

Nguyen Ly TT. Mise en oeuvre matérielle de décodeurs LDPC haut débit, en exploitant la robustesse du décodage par passage de messages aux imprécisions de calcul : Efficient Hardware Implementations of LDPC Decoders, through Exploiting Impreciseness in Message-Passing Decoding Algorithms. [Doctoral Dissertation]. Cergy-Pontoise; 2017. Available from: http://www.theses.fr/2017CERG0904

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