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You searched for subject:(JTAG). Showing records 1 – 30 of 50 total matches.

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NSYSU

1. Hou, Shao-Chieh. Integration of C Source Level Debugging and HW Tracing and Monitoring.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 With the increasing of manufacture and software design technology, embedded system now become more and more complex, time-to-market also become more short. For integrated a… (more)

Subjects/Keywords: Debugger; JTAG; Co-Debugging

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hou, S. (2014). Integration of C Source Level Debugging and HW Tracing and Monitoring. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-115349

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hou, Shao-Chieh. “Integration of C Source Level Debugging and HW Tracing and Monitoring.” 2014. Thesis, NSYSU. Accessed January 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-115349.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hou, Shao-Chieh. “Integration of C Source Level Debugging and HW Tracing and Monitoring.” 2014. Web. 22 Jan 2021.

Vancouver:

Hou S. Integration of C Source Level Debugging and HW Tracing and Monitoring. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Jan 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-115349.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hou S. Integration of C Source Level Debugging and HW Tracing and Monitoring. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-115349

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Debrecen

2. Egri, Sándor. Nagy komplexitású PCB vizsgálata Boundary Scan technológiával .

Degree: DE – TEK – Természettudományi és Technológiai Kar – Fizikai Intézet, 2011, University of Debrecen

Értekezés egy kommunikációs eszköz gyártásközi tesztjének lehetséges módjáról és annak megvalósítása. Advisors/Committee Members: Misák, Sándor (advisor).

Subjects/Keywords: JTAG; Boundary scan; PCB; PCB

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Egri, S. (2011). Nagy komplexitású PCB vizsgálata Boundary Scan technológiával . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/118917

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Egri, Sándor. “Nagy komplexitású PCB vizsgálata Boundary Scan technológiával .” 2011. Thesis, University of Debrecen. Accessed January 22, 2021. http://hdl.handle.net/2437/118917.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Egri, Sándor. “Nagy komplexitású PCB vizsgálata Boundary Scan technológiával .” 2011. Web. 22 Jan 2021.

Vancouver:

Egri S. Nagy komplexitású PCB vizsgálata Boundary Scan technológiával . [Internet] [Thesis]. University of Debrecen; 2011. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2437/118917.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Egri S. Nagy komplexitású PCB vizsgálata Boundary Scan technológiával . [Thesis]. University of Debrecen; 2011. Available from: http://hdl.handle.net/2437/118917

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

3. Sedlář, Jan. Programátor obvodů FPGA: FPGA programmer.

Degree: 2019, Brno University of Technology

 The work deals with the analysis of the realization of FPGA programmers. Its aim is to create a functional programmer. The proposal aims to minimize… (more)

Subjects/Keywords: FPGA; FTDI; JTAG; SVF; Programátor; FPGA; FTDI; JTAG; SVF Programmer

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sedlář, J. (2019). Programátor obvodů FPGA: FPGA programmer. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/61682

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sedlář, Jan. “Programátor obvodů FPGA: FPGA programmer.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/61682.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sedlář, Jan. “Programátor obvodů FPGA: FPGA programmer.” 2019. Web. 22 Jan 2021.

Vancouver:

Sedlář J. Programátor obvodů FPGA: FPGA programmer. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/61682.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sedlář J. Programátor obvodů FPGA: FPGA programmer. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/61682

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

4. Jonsson, Simon. Development of Test Equipment Based On Boundary Scan to Analyze Camera Systems for the Car Industry.

Degree: Integrated Circuits and Systems, 2016, Linköping University

  Testing a PCB assembly can be very time consuming due to its complexity andcompactness. Tests are desired to be consistent and test coverage should… (more)

Subjects/Keywords: JTAG; Boundary Scan; test coverage; troubleshooting

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jonsson, S. (2016). Development of Test Equipment Based On Boundary Scan to Analyze Camera Systems for the Car Industry. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129218

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jonsson, Simon. “Development of Test Equipment Based On Boundary Scan to Analyze Camera Systems for the Car Industry.” 2016. Thesis, Linköping University. Accessed January 22, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129218.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jonsson, Simon. “Development of Test Equipment Based On Boundary Scan to Analyze Camera Systems for the Car Industry.” 2016. Web. 22 Jan 2021.

Vancouver:

Jonsson S. Development of Test Equipment Based On Boundary Scan to Analyze Camera Systems for the Car Industry. [Internet] [Thesis]. Linköping University; 2016. [cited 2021 Jan 22]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129218.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jonsson S. Development of Test Equipment Based On Boundary Scan to Analyze Camera Systems for the Car Industry. [Thesis]. Linköping University; 2016. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129218

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

5. Sedlář, Jan. Testování SRAM pamětí s využitím MBIST: SRAM memories testing with utilization of memory built-in-self-test.

Degree: 2019, Brno University of Technology

 The project deals with the testing of SRAM memories using method MBIST with the utilisation of sofware tool Tessent Memory BIST. The main purpose is… (more)

Subjects/Keywords: SRAM; Tessent; MBIST; Test paměti; JTAG; Čip; SRAM; Tessent; MBIST; Memory test; JTAG; Chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sedlář, J. (2019). Testování SRAM pamětí s využitím MBIST: SRAM memories testing with utilization of memory built-in-self-test. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/80934

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sedlář, Jan. “Testování SRAM pamětí s využitím MBIST: SRAM memories testing with utilization of memory built-in-self-test.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/80934.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sedlář, Jan. “Testování SRAM pamětí s využitím MBIST: SRAM memories testing with utilization of memory built-in-self-test.” 2019. Web. 22 Jan 2021.

Vancouver:

Sedlář J. Testování SRAM pamětí s využitím MBIST: SRAM memories testing with utilization of memory built-in-self-test. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/80934.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sedlář J. Testování SRAM pamětí s využitím MBIST: SRAM memories testing with utilization of memory built-in-self-test. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/80934

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

6. Dostál, František. Vývojový kit s AVR procesorem: Developmental kit width AVR microcontrollers.

Degree: 2019, Brno University of Technology

 The topic of my bachelor´s thesis is the implementation of development kit with AVR ATmega16 processor and creation a simple program to verify the functionality… (more)

Subjects/Keywords: ATmega16; mikroprocesor; ADXL330; vývojový kit; programátor; JTAG; ATmega16; microprocessor; ADXL330; development kit; programmer; JTAG

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dostál, F. (2019). Vývojový kit s AVR procesorem: Developmental kit width AVR microcontrollers. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/8933

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dostál, František. “Vývojový kit s AVR procesorem: Developmental kit width AVR microcontrollers.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/8933.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dostál, František. “Vývojový kit s AVR procesorem: Developmental kit width AVR microcontrollers.” 2019. Web. 22 Jan 2021.

Vancouver:

Dostál F. Vývojový kit s AVR procesorem: Developmental kit width AVR microcontrollers. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/8933.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dostál F. Vývojový kit s AVR procesorem: Developmental kit width AVR microcontrollers. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/8933

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

7. Petrilak, Michal. Programování obvodů PLD pomocí mikroprocesorů: Programming of PLD devices using microprocessors.

Degree: 2019, Brno University of Technology

 This work is focused on configuring of Xiling's FPGA devices by embedded microcontroller. Several methods of configuration are described and the most suitable method is… (more)

Subjects/Keywords: FPGA; CPLD; JTAG; mikrokontrolér; konfigurace PLD; FPGA; CPLD; JTAG; microcontroller; PLD configuration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Petrilak, M. (2019). Programování obvodů PLD pomocí mikroprocesorů: Programming of PLD devices using microprocessors. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/2804

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Petrilak, Michal. “Programování obvodů PLD pomocí mikroprocesorů: Programming of PLD devices using microprocessors.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/2804.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Petrilak, Michal. “Programování obvodů PLD pomocí mikroprocesorů: Programming of PLD devices using microprocessors.” 2019. Web. 22 Jan 2021.

Vancouver:

Petrilak M. Programování obvodů PLD pomocí mikroprocesorů: Programming of PLD devices using microprocessors. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/2804.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Petrilak M. Programování obvodů PLD pomocí mikroprocesorů: Programming of PLD devices using microprocessors. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/2804

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

8. Hrbáček, Radek. Generátor ladicího nástroje na čipu: On-Chip Debugger Generator.

Degree: 2019, Brno University of Technology

 This bachelor's thesis deals with the design and implementation of an on-chip debugger and its connection to the hardware generated using software tools developed as a… (more)

Subjects/Keywords: ladění kódu; JTAG; Nexus 5001; Lissom; VHDL; vestavěný systém; debugging; JTAG; Nexus 5001; Lissom; VHDL; embedded system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hrbáček, R. (2019). Generátor ladicího nástroje na čipu: On-Chip Debugger Generator. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/55716

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hrbáček, Radek. “Generátor ladicího nástroje na čipu: On-Chip Debugger Generator.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/55716.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hrbáček, Radek. “Generátor ladicího nástroje na čipu: On-Chip Debugger Generator.” 2019. Web. 22 Jan 2021.

Vancouver:

Hrbáček R. Generátor ladicího nástroje na čipu: On-Chip Debugger Generator. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/55716.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hrbáček R. Generátor ladicího nástroje na čipu: On-Chip Debugger Generator. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/55716

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

9. Svoboda, Stanislav. Laboratorní přípravek pro demonstraci programovatelných logických obvodů: Laboratory Kit for Programmable Logic Demonstration.

Degree: 2019, Brno University of Technology

 This bachelor’s project deals with solutions of laboratory kit for teaching of work with CPLD curcuits which are made by company ALTERA. It is also… (more)

Subjects/Keywords: Přípravek pro výuku; ALTERA; CPLD; EPM7064; napájecí zdroj; JTAG.; Laboratory kit; ALTERA; CPLD; EPM7064; power supply unit; JTAG.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Svoboda, S. (2019). Laboratorní přípravek pro demonstraci programovatelných logických obvodů: Laboratory Kit for Programmable Logic Demonstration. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/14121

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Svoboda, Stanislav. “Laboratorní přípravek pro demonstraci programovatelných logických obvodů: Laboratory Kit for Programmable Logic Demonstration.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/14121.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Svoboda, Stanislav. “Laboratorní přípravek pro demonstraci programovatelných logických obvodů: Laboratory Kit for Programmable Logic Demonstration.” 2019. Web. 22 Jan 2021.

Vancouver:

Svoboda S. Laboratorní přípravek pro demonstraci programovatelných logických obvodů: Laboratory Kit for Programmable Logic Demonstration. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/14121.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Svoboda S. Laboratorní přípravek pro demonstraci programovatelných logických obvodů: Laboratory Kit for Programmable Logic Demonstration. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/14121

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

10. Gajdošík, Petr. Laboratorní přípravek pro experimentální práci s obvody CoolRunner: Laboratory kit for experimental work with CoolRunner devices.

Degree: 2019, Brno University of Technology

 This bachelor´s thesis deals with the programming of the CPLD device from the CoolRunner.II family, made by Xilinx company, through the use of USB bus.… (more)

Subjects/Keywords: CPLD; CoolRunner II; USB; laboratorní přípravek; JTAG; VHDL.; CPLD; CoolRunner II; USB; laboratory kit; JTAG; VHDL.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gajdošík, P. (2019). Laboratorní přípravek pro experimentální práci s obvody CoolRunner: Laboratory kit for experimental work with CoolRunner devices. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/16449

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gajdošík, Petr. “Laboratorní přípravek pro experimentální práci s obvody CoolRunner: Laboratory kit for experimental work with CoolRunner devices.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/16449.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gajdošík, Petr. “Laboratorní přípravek pro experimentální práci s obvody CoolRunner: Laboratory kit for experimental work with CoolRunner devices.” 2019. Web. 22 Jan 2021.

Vancouver:

Gajdošík P. Laboratorní přípravek pro experimentální práci s obvody CoolRunner: Laboratory kit for experimental work with CoolRunner devices. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/16449.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gajdošík P. Laboratorní přípravek pro experimentální práci s obvody CoolRunner: Laboratory kit for experimental work with CoolRunner devices. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/16449

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

11. Gryžboň, Jan. Průmyslový programátor mikrokontrolérů AVR Atmel: Industrial programmer Atmel AVR microcontrollers.

Degree: 2019, Brno University of Technology

 The aim of this thesis is to design and implement an industrial programmer AVR microcontrollers from Atmel. The first section provides the theoretical knowledge of… (more)

Subjects/Keywords: AVR; Atmel; programátor; metody programování; ISP; JTAG; PWM; Eagle; Atmel; AVR; programmer; programming methods; ISP; JTAG; PWM; Eagle

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gryžboň, J. (2019). Průmyslový programátor mikrokontrolérů AVR Atmel: Industrial programmer Atmel AVR microcontrollers. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/32909

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gryžboň, Jan. “Průmyslový programátor mikrokontrolérů AVR Atmel: Industrial programmer Atmel AVR microcontrollers.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/32909.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gryžboň, Jan. “Průmyslový programátor mikrokontrolérů AVR Atmel: Industrial programmer Atmel AVR microcontrollers.” 2019. Web. 22 Jan 2021.

Vancouver:

Gryžboň J. Průmyslový programátor mikrokontrolérů AVR Atmel: Industrial programmer Atmel AVR microcontrollers. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/32909.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gryžboň J. Průmyslový programátor mikrokontrolérů AVR Atmel: Industrial programmer Atmel AVR microcontrollers. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/32909

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

12. Gajdošík, Petr. Laboratorní přípravek pro vývoj aplikací obvodů CPLD firmy Altera: Laboratory kit for design work with Altera CPLD devices.

Degree: 2019, Brno University of Technology

 In this thesis I aim at a design of the laboratory kit and study ways how to programme CPLD devices made by Altera company. The… (more)

Subjects/Keywords: Laboratorní přípravek; CPLD; Altera; JTAG; VHDL; QUARTUS II.; Laboratory kit; CPLD; Altera; JTAG; VHDL; QUARTUS II.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gajdošík, P. (2019). Laboratorní přípravek pro vývoj aplikací obvodů CPLD firmy Altera: Laboratory kit for design work with Altera CPLD devices. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/11375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gajdošík, Petr. “Laboratorní přípravek pro vývoj aplikací obvodů CPLD firmy Altera: Laboratory kit for design work with Altera CPLD devices.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/11375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gajdošík, Petr. “Laboratorní přípravek pro vývoj aplikací obvodů CPLD firmy Altera: Laboratory kit for design work with Altera CPLD devices.” 2019. Web. 22 Jan 2021.

Vancouver:

Gajdošík P. Laboratorní přípravek pro vývoj aplikací obvodů CPLD firmy Altera: Laboratory kit for design work with Altera CPLD devices. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/11375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gajdošík P. Laboratorní přípravek pro vývoj aplikací obvodů CPLD firmy Altera: Laboratory kit for design work with Altera CPLD devices. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/11375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

13. Mavuram, Sushmitha. Design of an Efficient Design for Test (DFT) Architecture and it's Verification Using Universal Verification Methodology.

Degree: MS, Computer Engineering, 2019, Rochester Institute of Technology

  The complexity of the circuit design has been significantly increased from 1980’s till date, and until 80’s, due to less complexity and technology node… (more)

Subjects/Keywords: Integrated circuits; Integrated circuit testing; Testability features; MBIST; LBIST; JTAG

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mavuram, S. (2019). Design of an Efficient Design for Test (DFT) Architecture and it's Verification Using Universal Verification Methodology. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10326

Chicago Manual of Style (16th Edition):

Mavuram, Sushmitha. “Design of an Efficient Design for Test (DFT) Architecture and it's Verification Using Universal Verification Methodology.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed January 22, 2021. https://scholarworks.rit.edu/theses/10326.

MLA Handbook (7th Edition):

Mavuram, Sushmitha. “Design of an Efficient Design for Test (DFT) Architecture and it's Verification Using Universal Verification Methodology.” 2019. Web. 22 Jan 2021.

Vancouver:

Mavuram S. Design of an Efficient Design for Test (DFT) Architecture and it's Verification Using Universal Verification Methodology. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2021 Jan 22]. Available from: https://scholarworks.rit.edu/theses/10326.

Council of Science Editors:

Mavuram S. Design of an Efficient Design for Test (DFT) Architecture and it's Verification Using Universal Verification Methodology. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10326


Siauliai University

14. Vismantas, Tomas. JTAG sąsaja programuojamuose elektroniniuose prietaisuose.

Degree: Master, Electronics and Electrical Engineering, 2005, Siauliai University

 This master‘s final paper describes JTAG (boundary scan) interface in which discuss IEEE standart 1149.1 circuit model and the main TAP (Test Access Port) controllers… (more)

Subjects/Keywords: Programmable logic; Programuojama logika; JTAG

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vismantas, Tomas. (2005). JTAG sąsaja programuojamuose elektroniniuose prietaisuose. (Masters Thesis). Siauliai University. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2005~D_20050615_150741-49753 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

Vismantas, Tomas. “JTAG sąsaja programuojamuose elektroniniuose prietaisuose.” 2005. Masters Thesis, Siauliai University. Accessed January 22, 2021. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2005~D_20050615_150741-49753 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

Vismantas, Tomas. “JTAG sąsaja programuojamuose elektroniniuose prietaisuose.” 2005. Web. 22 Jan 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Vismantas, Tomas. JTAG sąsaja programuojamuose elektroniniuose prietaisuose. [Internet] [Masters thesis]. Siauliai University; 2005. [cited 2021 Jan 22]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2005~D_20050615_150741-49753 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

Vismantas, Tomas. JTAG sąsaja programuojamuose elektroniniuose prietaisuose. [Masters Thesis]. Siauliai University; 2005. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2005~D_20050615_150741-49753 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

15. Sousa, Valentim Peixoto de. Acesso remoto via infra-estrutura de teste IEEE1149.1 a dispositivos lógicos programáveis.

Degree: 2011, Instituto Politécnico do Porto

Actualmente verifica-se que a complexidade dos sistemas informáticos tem vindo a aumentar, fazendo parte das nossas ferramentas diárias de trabalho a utilização de sistemas informáticos… (more)

Subjects/Keywords: OpenWrt; JTAG; Laboratórios remotos; Pseudo-terminais; Remote laboratories; Pseudo-terminal

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sousa, V. P. d. (2011). Acesso remoto via infra-estrutura de teste IEEE1149.1 a dispositivos lógicos programáveis. (Thesis). Instituto Politécnico do Porto. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/2723

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sousa, Valentim Peixoto de. “Acesso remoto via infra-estrutura de teste IEEE1149.1 a dispositivos lógicos programáveis.” 2011. Thesis, Instituto Politécnico do Porto. Accessed January 22, 2021. http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/2723.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sousa, Valentim Peixoto de. “Acesso remoto via infra-estrutura de teste IEEE1149.1 a dispositivos lógicos programáveis.” 2011. Web. 22 Jan 2021.

Vancouver:

Sousa VPd. Acesso remoto via infra-estrutura de teste IEEE1149.1 a dispositivos lógicos programáveis. [Internet] [Thesis]. Instituto Politécnico do Porto; 2011. [cited 2021 Jan 22]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/2723.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sousa VPd. Acesso remoto via infra-estrutura de teste IEEE1149.1 a dispositivos lógicos programáveis. [Thesis]. Instituto Politécnico do Porto; 2011. Available from: http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/2723

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

16. Berggren, Erik. Testverktyg för JTAG Boundary Scan.

Degree: Computer Engineering, 2017, Linköping University

  Ett projekt har genomförts i python för att läsa och analysera nätlistor från eCAD programmet Altium. Projektet är en prototyp till en mjukvara som… (more)

Subjects/Keywords: boundary scan; jtag; atpg; testsystem; testdesign; Computer Engineering; Datorteknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Berggren, E. (2017). Testverktyg för JTAG Boundary Scan. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-135785

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Berggren, Erik. “Testverktyg för JTAG Boundary Scan.” 2017. Thesis, Linköping University. Accessed January 22, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-135785.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Berggren, Erik. “Testverktyg för JTAG Boundary Scan.” 2017. Web. 22 Jan 2021.

Vancouver:

Berggren E. Testverktyg för JTAG Boundary Scan. [Internet] [Thesis]. Linköping University; 2017. [cited 2021 Jan 22]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-135785.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Berggren E. Testverktyg för JTAG Boundary Scan. [Thesis]. Linköping University; 2017. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-135785

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

17. Michl, Kamil. Ladění software v Codasip Studiu pomocí JTAG rozhraní simulovaném v RTL simulátoru: Software Debugging in Codasip Studio Using JTAG Interface Simulated in RTL Simulator.

Degree: 2018, Brno University of Technology

 This thesis is dealing with an option to connect the RTL simulation of a processor with a software debugger. Acording to my design, the communication… (more)

Subjects/Keywords: JTAG rozhraní; RTL simulace; VPI rozhraní; Nexus rozhraní; Codasip; Questa Advanced Simulator; JTAG interface; RTL simulation; VPI interface; Nexus interface; Codasip; Questa Advanced Simulator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Michl, K. (2018). Ladění software v Codasip Studiu pomocí JTAG rozhraní simulovaném v RTL simulátoru: Software Debugging in Codasip Studio Using JTAG Interface Simulated in RTL Simulator. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/69844

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Michl, Kamil. “Ladění software v Codasip Studiu pomocí JTAG rozhraní simulovaném v RTL simulátoru: Software Debugging in Codasip Studio Using JTAG Interface Simulated in RTL Simulator.” 2018. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/69844.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Michl, Kamil. “Ladění software v Codasip Studiu pomocí JTAG rozhraní simulovaném v RTL simulátoru: Software Debugging in Codasip Studio Using JTAG Interface Simulated in RTL Simulator.” 2018. Web. 22 Jan 2021.

Vancouver:

Michl K. Ladění software v Codasip Studiu pomocí JTAG rozhraní simulovaném v RTL simulátoru: Software Debugging in Codasip Studio Using JTAG Interface Simulated in RTL Simulator. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/69844.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Michl K. Ladění software v Codasip Studiu pomocí JTAG rozhraní simulovaném v RTL simulátoru: Software Debugging in Codasip Studio Using JTAG Interface Simulated in RTL Simulator. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/69844

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

18. Laurinc, Pavel. Připojení paměťové karty SD k mikrokontroléru: Connecting SD Memory Card to Microcontroller.

Degree: 2019, Brno University of Technology

 Author concerns with SD memory cards and microcontroller Atmel ATmega128. He describes their architecture, features, properties and technology used in devices. He is mentioning principle… (more)

Subjects/Keywords: Paměťová karta; SD; MMC; mikrokontrolér; Atmel; AVR; ATmega128; SPI; CPRM; systém souborů; FAT; fragmentace; JTAG.; Memory card; SD; MMC; microcontroller; Atmel; AVR; ATmega128; SPI; CPRM; file system; FAT; fragmentation; JTAG.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Laurinc, P. (2019). Připojení paměťové karty SD k mikrokontroléru: Connecting SD Memory Card to Microcontroller. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/53972

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Laurinc, Pavel. “Připojení paměťové karty SD k mikrokontroléru: Connecting SD Memory Card to Microcontroller.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/53972.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Laurinc, Pavel. “Připojení paměťové karty SD k mikrokontroléru: Connecting SD Memory Card to Microcontroller.” 2019. Web. 22 Jan 2021.

Vancouver:

Laurinc P. Připojení paměťové karty SD k mikrokontroléru: Connecting SD Memory Card to Microcontroller. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/53972.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Laurinc P. Připojení paměťové karty SD k mikrokontroléru: Connecting SD Memory Card to Microcontroller. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/53972

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

19. Matula, Rastislav. Dotykové ovládání přístroje pomocí kapacitních senzorových obvodů: Device control based on touch-sensitive capacitance-sensing circuits.

Degree: 2019, Brno University of Technology

 The primary objective of this master’s thesis is to discuss a design and development of proximity touch control panel, which contains two simulated buttons and… (more)

Subjects/Keywords: Dotykové kapacitní senzory; MPR083; MPR084; USB JTAG Programátor; PCD8544; ATmega16; sériové rozhraní I2C.; Proximity touch capacitive sensors; MPR083; MPR084; USB JTAG Programmer; PCD8544; ATmega16; I2C serial interface.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Matula, R. (2019). Dotykové ovládání přístroje pomocí kapacitních senzorových obvodů: Device control based on touch-sensitive capacitance-sensing circuits. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/11144

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Matula, Rastislav. “Dotykové ovládání přístroje pomocí kapacitních senzorových obvodů: Device control based on touch-sensitive capacitance-sensing circuits.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/11144.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Matula, Rastislav. “Dotykové ovládání přístroje pomocí kapacitních senzorových obvodů: Device control based on touch-sensitive capacitance-sensing circuits.” 2019. Web. 22 Jan 2021.

Vancouver:

Matula R. Dotykové ovládání přístroje pomocí kapacitních senzorových obvodů: Device control based on touch-sensitive capacitance-sensing circuits. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/11144.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Matula R. Dotykové ovládání přístroje pomocí kapacitních senzorových obvodů: Device control based on touch-sensitive capacitance-sensing circuits. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/11144

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

20. Vaško, Jiří. Řídicí systém tvářecího stroje: Forming Machine Control System.

Degree: 2018, Brno University of Technology

 This master thesis deals with the implementation of the control system for the forming machine used in producing of confectionery forms. The introductory part describes… (more)

Subjects/Keywords: automat; tvarovací stroj; ARM; Cortex M3; C#/.net; JTAG; SD karta; FAT32; automat; forming machine; ARM; Cortex M3; C#/.NET; JTAG; SD card; FAT32

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vaško, J. (2018). Řídicí systém tvářecího stroje: Forming Machine Control System. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/17602

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vaško, Jiří. “Řídicí systém tvářecího stroje: Forming Machine Control System.” 2018. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/17602.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vaško, Jiří. “Řídicí systém tvářecího stroje: Forming Machine Control System.” 2018. Web. 22 Jan 2021.

Vancouver:

Vaško J. Řídicí systém tvářecího stroje: Forming Machine Control System. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/17602.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vaško J. Řídicí systém tvářecího stroje: Forming Machine Control System. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/17602

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

21. Rébl, Miroslav. Algoritmy zpracování obrazu v osmibitových procesorech: Image processing algorithms in eight-bit microcontroller.

Degree: 2019, Brno University of Technology

 The aim of master thesis was to investigate a simple camera and processor Atmel AVR unit implementation. Thesis describes how to get image from C3088… (more)

Subjects/Keywords: C3088; OV6620; digitální kamera; mikroprocesor; ATmega; AVR; I2C; JTAG; zpracování obrazu; C3088; OV6620; digital camera; microprocessor; ATmega; AVR; I2C; JTAG; image processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rébl, M. (2019). Algoritmy zpracování obrazu v osmibitových procesorech: Image processing algorithms in eight-bit microcontroller. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/7150

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rébl, Miroslav. “Algoritmy zpracování obrazu v osmibitových procesorech: Image processing algorithms in eight-bit microcontroller.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/7150.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rébl, Miroslav. “Algoritmy zpracování obrazu v osmibitových procesorech: Image processing algorithms in eight-bit microcontroller.” 2019. Web. 22 Jan 2021.

Vancouver:

Rébl M. Algoritmy zpracování obrazu v osmibitových procesorech: Image processing algorithms in eight-bit microcontroller. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/7150.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rébl M. Algoritmy zpracování obrazu v osmibitových procesorech: Image processing algorithms in eight-bit microcontroller. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/7150

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

22. Procházka, Matěj. Řízení modelu protokolem CAN: Control of a model with CAN protocol.

Degree: 2019, Brno University of Technology

 This thesis focuses in the importance of technical text on the CAN protocol, the design of communication with robotic chassis. The first part contains general… (more)

Subjects/Keywords: ARM; Cortex-M3; CAN; software; hardware; CooCox; JTAG; recesivní; dominantní; inicializace; ovladač; rámec; identifikátor; Mbed; ARM; Cortex-M3; CAN; software; hardware; CooCox; JTAG; recessive; dominant; initialization; control; frame identifier; mbed.

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APA (6th Edition):

Procházka, M. (2019). Řízení modelu protokolem CAN: Control of a model with CAN protocol. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/71586

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Procházka, Matěj. “Řízení modelu protokolem CAN: Control of a model with CAN protocol.” 2019. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/71586.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Procházka, Matěj. “Řízení modelu protokolem CAN: Control of a model with CAN protocol.” 2019. Web. 22 Jan 2021.

Vancouver:

Procházka M. Řízení modelu protokolem CAN: Control of a model with CAN protocol. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/71586.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Procházka M. Řízení modelu protokolem CAN: Control of a model with CAN protocol. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/71586

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

23. Huang, Shih-tung. Hardware/software co-verification for processor-OpenOCD integration.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 We usually use RVDS [18] (RealView Development Suite) and MUlTI-ICE (protocol converter) as ARM program debug environment by controlling ICE module for controlling CPU. But… (more)

Subjects/Keywords: OpenOCD (Open On-Chip Debugger); GNU Debugger; Co-verification; EICE (Embedded In-Circuit Emulator); JTAG

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APA (6th Edition):

Huang, S. (2013). Hardware/software co-verification for processor-OpenOCD integration. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Shih-tung. “Hardware/software co-verification for processor-OpenOCD integration.” 2013. Thesis, NSYSU. Accessed January 22, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Shih-tung. “Hardware/software co-verification for processor-OpenOCD integration.” 2013. Web. 22 Jan 2021.

Vancouver:

Huang S. Hardware/software co-verification for processor-OpenOCD integration. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Jan 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang S. Hardware/software co-verification for processor-OpenOCD integration. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Couto, André Carvalho de Azevedo Silva. Desenvolvimento de um Controlador de Boundary Scan (Ieee 1149.1).

Degree: 2014, Instituto Politécnico do Porto

Mestrado em Engenharia Electrotécnica e de Computadores - Área de Especialização em Automação e Sistemas

O Boundary Scan consiste numa infra-estrutura de teste por varrimento… (more)

Subjects/Keywords: Boundary Scan; JTAG; IEEE 1149.1; Serial Vector Format; Teste e Depuração; Debugging

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Couto, A. C. d. A. S. (2014). Desenvolvimento de um Controlador de Boundary Scan (Ieee 1149.1). (Thesis). Instituto Politécnico do Porto. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/5590

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Couto, André Carvalho de Azevedo Silva. “Desenvolvimento de um Controlador de Boundary Scan (Ieee 1149.1).” 2014. Thesis, Instituto Politécnico do Porto. Accessed January 22, 2021. http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/5590.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Couto, André Carvalho de Azevedo Silva. “Desenvolvimento de um Controlador de Boundary Scan (Ieee 1149.1).” 2014. Web. 22 Jan 2021.

Vancouver:

Couto ACdAS. Desenvolvimento de um Controlador de Boundary Scan (Ieee 1149.1). [Internet] [Thesis]. Instituto Politécnico do Porto; 2014. [cited 2021 Jan 22]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/5590.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Couto ACdAS. Desenvolvimento de um Controlador de Boundary Scan (Ieee 1149.1). [Thesis]. Instituto Politécnico do Porto; 2014. Available from: http://www.rcaap.pt/detail.jsp?id=oai:recipp.ipp.pt:10400.22/5590

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. 永田, 和生; ナガタ, カズオ. ネットワークを利用したFPGA遠隔再構成システムに関する研究 : ネットワーク オ リヨウ シタ FPGA エンカク サイコウセイ システム ニ カンスル ケンキュウ.

Degree: Kumamoto University / 熊本大学

本研究ではネットワークを介してFPGA内部の回路再構成を行うFPGA遠隔再構成システムの開発を行う。このシステムによって、膨大な数に上る出荷済みの機器や、人の立入りが困難な場所にある機器に対しても回路動作の変更が可能となる。また、本システムには遠隔操作によってFPGA実装回路の動作検証を行う手法として、リモート・ロジックアナライザとBIST(Built-In Self Test)[6]を装備する。併せて、データベースを用いた自動再構成機構を開発し、その動作について検証・考察し、実践的なアプリケーションの実装と評価を通じてその効果を確認する。

Subjects/Keywords: リコンフィギャラブルコンピューティング; RLD; IEEE; JTAG; リモート・ロジックアナライザ; BIST

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

永田, 和生; ナガタ, . (n.d.). ネットワークを利用したFPGA遠隔再構成システムに関する研究 : ネットワーク オ リヨウ シタ FPGA エンカク サイコウセイ システム ニ カンスル ケンキュウ. (Thesis). Kumamoto University / 熊本大学. Retrieved from http://hdl.handle.net/2298/11060

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

永田, 和生; ナガタ, カズオ. “ネットワークを利用したFPGA遠隔再構成システムに関する研究 : ネットワーク オ リヨウ シタ FPGA エンカク サイコウセイ システム ニ カンスル ケンキュウ.” Thesis, Kumamoto University / 熊本大学. Accessed January 22, 2021. http://hdl.handle.net/2298/11060.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

永田, 和生; ナガタ, カズオ. “ネットワークを利用したFPGA遠隔再構成システムに関する研究 : ネットワーク オ リヨウ シタ FPGA エンカク サイコウセイ システム ニ カンスル ケンキュウ.” Web. 22 Jan 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

永田, 和生; ナガタ . ネットワークを利用したFPGA遠隔再構成システムに関する研究 : ネットワーク オ リヨウ シタ FPGA エンカク サイコウセイ システム ニ カンスル ケンキュウ. [Internet] [Thesis]. Kumamoto University / 熊本大学; [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2298/11060.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

永田, 和生; ナガタ . ネットワークを利用したFPGA遠隔再構成システムに関する研究 : ネットワーク オ リヨウ シタ FPGA エンカク サイコウセイ システム ニ カンスル ケンキュウ. [Thesis]. Kumamoto University / 熊本大学; Available from: http://hdl.handle.net/2298/11060

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Linköping University

26. Baig, Aijaz. Embedded boundary scan for test & debug.

Degree: Computer and Information Science, 2009, Linköping University

  The boundary scan standard which has been in existence since the early nineties is widely used to test printed circuit boards (PCB). It is… (more)

Subjects/Keywords: boundary scan; JTAG; embedded; test; Electronics; Elektronik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Baig, A. (2009). Embedded boundary scan for test & debug. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19368

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Baig, Aijaz. “Embedded boundary scan for test & debug.” 2009. Thesis, Linköping University. Accessed January 22, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19368.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Baig, Aijaz. “Embedded boundary scan for test & debug.” 2009. Web. 22 Jan 2021.

Vancouver:

Baig A. Embedded boundary scan for test & debug. [Internet] [Thesis]. Linköping University; 2009. [cited 2021 Jan 22]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19368.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Baig A. Embedded boundary scan for test & debug. [Thesis]. Linköping University; 2009. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19368

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Cabral, Carlos Javier. Design and implementation of an IEEE 1149.7-compliant cJTAG Controller for Debug and Trace Probe.

Degree: MSin Engineering, Electrical and Computer Engineering, 2012, University of Texas – Austin

 Debugging and testing today's complex processors and embedded systems provides many challenges. A Debug and Trace Probe with a standard interface to Target Systems (TS)… (more)

Subjects/Keywords: IEEE 1149.7; cJTAG; JTAG; IEEE 1149.1

…Command Register Definition for RAW JTAG . . . . . . . . . Command Register Definition for SEND… …various interfaces and trace mechanisms, the focus of the cJTAG Controller is the serial JTAG… …can be seen in Figure X. The IEEE 1149.7 Compliant JTAG Controller (cJTAG Controller… …Debug and Trace Hardware Probe and the Target System (TS) connected to the JTAG… …that improves upon the IEEE 1149.1 standard, commonly referred to as JTAG (Joint Test… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cabral, C. J. (2012). Design and implementation of an IEEE 1149.7-compliant cJTAG Controller for Debug and Trace Probe. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/19988

Chicago Manual of Style (16th Edition):

Cabral, Carlos Javier. “Design and implementation of an IEEE 1149.7-compliant cJTAG Controller for Debug and Trace Probe.” 2012. Masters Thesis, University of Texas – Austin. Accessed January 22, 2021. http://hdl.handle.net/2152/19988.

MLA Handbook (7th Edition):

Cabral, Carlos Javier. “Design and implementation of an IEEE 1149.7-compliant cJTAG Controller for Debug and Trace Probe.” 2012. Web. 22 Jan 2021.

Vancouver:

Cabral CJ. Design and implementation of an IEEE 1149.7-compliant cJTAG Controller for Debug and Trace Probe. [Internet] [Masters thesis]. University of Texas – Austin; 2012. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2152/19988.

Council of Science Editors:

Cabral CJ. Design and implementation of an IEEE 1149.7-compliant cJTAG Controller for Debug and Trace Probe. [Masters Thesis]. University of Texas – Austin; 2012. Available from: http://hdl.handle.net/2152/19988

28. Byström, Henrik. Kostnadseffektiv enhet för fjärrövervakning av inbyggda system.

Degree: 2013, , Faculty of Technology and Society (TS)

Företag kan ha produktionsanläggningar på ett antal olika platser runt om i världen. Den industriella utrustningen som används i anläggningarna innehåller ofta någon form… (more)

Subjects/Keywords: Kostnadseffektiv; Inbyggda system; Fjärrövervakning; Raspberry Pi; Arduino; Kommunikationssystem; RS-232; JTAG; GPIO; Engineering and Technology; Teknik och teknologier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Byström, H. (2013). Kostnadseffektiv enhet för fjärrövervakning av inbyggda system. (Thesis). , Faculty of Technology and Society (TS). Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-20467

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Byström, Henrik. “Kostnadseffektiv enhet för fjärrövervakning av inbyggda system.” 2013. Thesis, , Faculty of Technology and Society (TS). Accessed January 22, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-20467.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Byström, Henrik. “Kostnadseffektiv enhet för fjärrövervakning av inbyggda system.” 2013. Web. 22 Jan 2021.

Vancouver:

Byström H. Kostnadseffektiv enhet för fjärrövervakning av inbyggda system. [Internet] [Thesis]. , Faculty of Technology and Society (TS); 2013. [cited 2021 Jan 22]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-20467.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Byström H. Kostnadseffektiv enhet för fjärrövervakning av inbyggda system. [Thesis]. , Faculty of Technology and Society (TS); 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-20467

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


KTH

29. Bergman, Robin. Utvärdering av JTAG Boundary scan som testmetod vid temperaturchocker.

Degree: Sustainable production development, 2020, KTH

Rapporten beskriver ett examensarbete som har genomförts hos Scania R&D. Målet har varit att testa om det är möjligt att använda JTAG för kontroll… (more)

Subjects/Keywords: jtag boundary scan; temperature shock cycle; iso 26262; ball grid array; pcb; embedded system; cpu; cpld; mcu; JTAG boundary scan; temperaturchock; temperaturchockscykler; ISO 26262; ball grid array; pcb; inbyggda system; cpu; cpld; mcu; Engineering and Technology; Teknik och teknologier

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APA (6th Edition):

Bergman, R. (2020). Utvärdering av JTAG Boundary scan som testmetod vid temperaturchocker. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-280322

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bergman, Robin. “Utvärdering av JTAG Boundary scan som testmetod vid temperaturchocker.” 2020. Thesis, KTH. Accessed January 22, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-280322.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bergman, Robin. “Utvärdering av JTAG Boundary scan som testmetod vid temperaturchocker.” 2020. Web. 22 Jan 2021.

Vancouver:

Bergman R. Utvärdering av JTAG Boundary scan som testmetod vid temperaturchocker. [Internet] [Thesis]. KTH; 2020. [cited 2021 Jan 22]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-280322.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bergman R. Utvärdering av JTAG Boundary scan som testmetod vid temperaturchocker. [Thesis]. KTH; 2020. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-280322

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

30. Bartek, Lukáš. Univerzální programátor obvodů s rozhraním JTAG: Versatile Programmer of Components with JTAG Interface.

Degree: 2018, Brno University of Technology

 This master's thesis deals with designing and implementation of universal programmer with JTAG interface. The project consists of a hardware and software part. Theoretical part… (more)

Subjects/Keywords: ARM; bitstream; FPGA; FTDI; FT2232; hraniční test; IEEE 1149.1; JTAG; MPSSE; OpenOCD; paměť flash; paměť NAND; SVF; USB; ARM; bitstream; boundary scan; flash memory; FPGA; FTDI; FT2232; IEEE 1149.1; JTAG; MPSSE; NAND memory; OpenOCD; SVF; USB

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bartek, L. (2018). Univerzální programátor obvodů s rozhraním JTAG: Versatile Programmer of Components with JTAG Interface. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bartek, Lukáš. “Univerzální programátor obvodů s rozhraním JTAG: Versatile Programmer of Components with JTAG Interface.” 2018. Thesis, Brno University of Technology. Accessed January 22, 2021. http://hdl.handle.net/11012/54219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bartek, Lukáš. “Univerzální programátor obvodů s rozhraním JTAG: Versatile Programmer of Components with JTAG Interface.” 2018. Web. 22 Jan 2021.

Vancouver:

Bartek L. Univerzální programátor obvodů s rozhraním JTAG: Versatile Programmer of Components with JTAG Interface. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/11012/54219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bartek L. Univerzální programátor obvodů s rozhraním JTAG: Versatile Programmer of Components with JTAG Interface. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/54219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2]

.