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You searched for subject:(Interconnect). Showing records 1 – 30 of 205 total matches.

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University of New South Wales

1. Chen, Ge. Computer bus interconnect coding and optimisation.

Degree: Electrical Engineering & Telecommunications, 2012, University of New South Wales

 Interconnects become a major bottleneck for deep sub-micron technologies. Interconnect design plays an important role in optimizing the performance of the interconnect in the modern… (more)

Subjects/Keywords: Interconnect; Bus Optimisation

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APA (6th Edition):

Chen, G. (2012). Computer bus interconnect coding and optimisation. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/51624

Chicago Manual of Style (16th Edition):

Chen, Ge. “Computer bus interconnect coding and optimisation.” 2012. Doctoral Dissertation, University of New South Wales. Accessed February 21, 2018. http://handle.unsw.edu.au/1959.4/51624.

MLA Handbook (7th Edition):

Chen, Ge. “Computer bus interconnect coding and optimisation.” 2012. Web. 21 Feb 2018.

Vancouver:

Chen G. Computer bus interconnect coding and optimisation. [Internet] [Doctoral dissertation]. University of New South Wales; 2012. [cited 2018 Feb 21]. Available from: http://handle.unsw.edu.au/1959.4/51624.

Council of Science Editors:

Chen G. Computer bus interconnect coding and optimisation. [Doctoral Dissertation]. University of New South Wales; 2012. Available from: http://handle.unsw.edu.au/1959.4/51624


Anna University

2. Anithar. Design implementation and Performance evaluation of network On chip communication link router;.

Degree: Design implementation and Performance evaluation of network On chip communication link router, 2015, Anna University

In today s mobile and communication world Router plays a newlinesignificant role to select classify and forward the data from source node to newlinedestination node… (more)

Subjects/Keywords: Fixed routing scheme; Interconnect infrastructure

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APA (6th Edition):

Anithar. (2015). Design implementation and Performance evaluation of network On chip communication link router;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/39833

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Anithar. “Design implementation and Performance evaluation of network On chip communication link router;.” 2015. Thesis, Anna University. Accessed February 21, 2018. http://shodhganga.inflibnet.ac.in/handle/10603/39833.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Anithar. “Design implementation and Performance evaluation of network On chip communication link router;.” 2015. Web. 21 Feb 2018.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Anithar. Design implementation and Performance evaluation of network On chip communication link router;. [Internet] [Thesis]. Anna University; 2015. [cited 2018 Feb 21]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39833.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Anithar. Design implementation and Performance evaluation of network On chip communication link router;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39833

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

3. Adongo, Mchael O. Automated multiagent-based interoperator billing and payment system (ambibpsy) .

Degree: 2012, University of Nairobi

 Different operators offering telecommunication services cannot operate in isolation. They have to depend on each other in order to provide all inclusive telecommunication services to… (more)

Subjects/Keywords: AMBIBPSY system; operators; interconnect services

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APA (6th Edition):

Adongo, M. O. (2012). Automated multiagent-based interoperator billing and payment system (ambibpsy) . (Thesis). University of Nairobi. Retrieved from http://erepository.uonbi.ac.ke:8080/xmlui/handle/123456789/10157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Adongo, Mchael O. “Automated multiagent-based interoperator billing and payment system (ambibpsy) .” 2012. Thesis, University of Nairobi. Accessed February 21, 2018. http://erepository.uonbi.ac.ke:8080/xmlui/handle/123456789/10157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Adongo, Mchael O. “Automated multiagent-based interoperator billing and payment system (ambibpsy) .” 2012. Web. 21 Feb 2018.

Vancouver:

Adongo MO. Automated multiagent-based interoperator billing and payment system (ambibpsy) . [Internet] [Thesis]. University of Nairobi; 2012. [cited 2018 Feb 21]. Available from: http://erepository.uonbi.ac.ke:8080/xmlui/handle/123456789/10157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Adongo MO. Automated multiagent-based interoperator billing and payment system (ambibpsy) . [Thesis]. University of Nairobi; 2012. Available from: http://erepository.uonbi.ac.ke:8080/xmlui/handle/123456789/10157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

4. Hu, Jianchen. Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System.

Degree: MS, Electrical Engineering, 2009, North Carolina State University

 As the complexity of SoC design grows, the traditional register transfer level (RTL) centric design flow cannot meet the time to market. In that case,… (more)

Subjects/Keywords: interconnect; TLM; Network-on-chip

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APA (6th Edition):

Hu, J. (2009). Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hu, Jianchen. “Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System.” 2009. Thesis, North Carolina State University. Accessed February 21, 2018. http://www.lib.ncsu.edu/resolver/1840.16/1617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hu, Jianchen. “Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System.” 2009. Web. 21 Feb 2018.

Vancouver:

Hu J. Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System. [Internet] [Thesis]. North Carolina State University; 2009. [cited 2018 Feb 21]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hu J. Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System. [Thesis]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Wright State University

5. Katpally, Kaushik Reddy. Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect.

Degree: MSEgr, Electrical Engineering, 2014, Wright State University

 A System-on-a-Chip (SoC) has millions of transistors connected by wires or so called Interconnects. As CMOS technologies scale down, SoC becomes more complex and denser.… (more)

Subjects/Keywords: Engineering; Electrical Engineering; Interconnect Delay

…Uniformly Spaced Interconnect Specifications 16 6. Non-Uniformly Spaced Interconnect… …Specifications 16 7. Non-Uniformly Spaced Interconnect Output Simulation 17 8. Uniformly Spaced… …Interconnect Output Simulation 17 9. (a). Original Booster: Propagation Delay, Rise Time and Fall… …increases. 3. The reliability of the circuits increases. Interconnect delay has been negligible… …significant. In an Interconnect, 1. wire resistance is proportional to its length. 2. wire… 

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APA (6th Edition):

Katpally, K. R. (2014). Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1422056732

Chicago Manual of Style (16th Edition):

Katpally, Kaushik Reddy. “Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect.” 2014. Masters Thesis, Wright State University. Accessed February 21, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=wright1422056732.

MLA Handbook (7th Edition):

Katpally, Kaushik Reddy. “Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect.” 2014. Web. 21 Feb 2018.

Vancouver:

Katpally KR. Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect. [Internet] [Masters thesis]. Wright State University; 2014. [cited 2018 Feb 21]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1422056732.

Council of Science Editors:

Katpally KR. Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect. [Masters Thesis]. Wright State University; 2014. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1422056732


Delft University of Technology

6. Carisey, Y.C.P. Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles:.

Degree: 2014, Delft University of Technology

 Nowadays, the demand for enhanced performance and reliability in micro and nano systems is growing, especially for fine pitch wafer level integration. Due to reliability… (more)

Subjects/Keywords: interconnect; nanoparticle; sintering; stencil printing

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APA (6th Edition):

Carisey, Y. C. P. (2014). Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:1b9a667d-40c6-4743-8466-6d4614505ada

Chicago Manual of Style (16th Edition):

Carisey, Y C P. “Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles:.” 2014. Masters Thesis, Delft University of Technology. Accessed February 21, 2018. http://resolver.tudelft.nl/uuid:1b9a667d-40c6-4743-8466-6d4614505ada.

MLA Handbook (7th Edition):

Carisey, Y C P. “Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles:.” 2014. Web. 21 Feb 2018.

Vancouver:

Carisey YCP. Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles:. [Internet] [Masters thesis]. Delft University of Technology; 2014. [cited 2018 Feb 21]. Available from: http://resolver.tudelft.nl/uuid:1b9a667d-40c6-4743-8466-6d4614505ada.

Council of Science Editors:

Carisey YCP. Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles:. [Masters Thesis]. Delft University of Technology; 2014. Available from: http://resolver.tudelft.nl/uuid:1b9a667d-40c6-4743-8466-6d4614505ada


Delft University of Technology

7. Kukreja, R.S. Modeling and performance analysis of a high bandwidth, low power ring interconnect:.

Degree: 2015, Delft University of Technology

 As technology is improving and the performance of a single core has reached its peak performance, Multicore Systems on Chip have emerged as the trend… (more)

Subjects/Keywords: Interconnect; Network on Chip; Ring

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APA (6th Edition):

Kukreja, R. S. (2015). Modeling and performance analysis of a high bandwidth, low power ring interconnect:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:c2831f45-8cc5-4e14-8065-c98d54665d7e

Chicago Manual of Style (16th Edition):

Kukreja, R S. “Modeling and performance analysis of a high bandwidth, low power ring interconnect:.” 2015. Masters Thesis, Delft University of Technology. Accessed February 21, 2018. http://resolver.tudelft.nl/uuid:c2831f45-8cc5-4e14-8065-c98d54665d7e.

MLA Handbook (7th Edition):

Kukreja, R S. “Modeling and performance analysis of a high bandwidth, low power ring interconnect:.” 2015. Web. 21 Feb 2018.

Vancouver:

Kukreja RS. Modeling and performance analysis of a high bandwidth, low power ring interconnect:. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2018 Feb 21]. Available from: http://resolver.tudelft.nl/uuid:c2831f45-8cc5-4e14-8065-c98d54665d7e.

Council of Science Editors:

Kukreja RS. Modeling and performance analysis of a high bandwidth, low power ring interconnect:. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:c2831f45-8cc5-4e14-8065-c98d54665d7e


University of Toronto

8. Sharifymoghaddam, Sayeh. Low-swing Signaling for FPGA Interconnect Power Reduction.

Degree: 2015, University of Toronto

FPGAs are widely used in digital circuits implementation because of their lower non-recurring engineering cost and shorter time-to-market in comparison with ASICs. However, there are… (more)

Subjects/Keywords: FPGA; Interconnect; low-swing signaling; Power; 0544

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APA (6th Edition):

Sharifymoghaddam, S. (2015). Low-swing Signaling for FPGA Interconnect Power Reduction. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/72600

Chicago Manual of Style (16th Edition):

Sharifymoghaddam, Sayeh. “Low-swing Signaling for FPGA Interconnect Power Reduction.” 2015. Masters Thesis, University of Toronto. Accessed February 21, 2018. http://hdl.handle.net/1807/72600.

MLA Handbook (7th Edition):

Sharifymoghaddam, Sayeh. “Low-swing Signaling for FPGA Interconnect Power Reduction.” 2015. Web. 21 Feb 2018.

Vancouver:

Sharifymoghaddam S. Low-swing Signaling for FPGA Interconnect Power Reduction. [Internet] [Masters thesis]. University of Toronto; 2015. [cited 2018 Feb 21]. Available from: http://hdl.handle.net/1807/72600.

Council of Science Editors:

Sharifymoghaddam S. Low-swing Signaling for FPGA Interconnect Power Reduction. [Masters Thesis]. University of Toronto; 2015. Available from: http://hdl.handle.net/1807/72600


University of Toronto

9. Petelin, Oleg. CAD Tools and Architectures for Improved FPGA Interconnect.

Degree: 2016, University of Toronto

The FPGA routing architecture consists of routing wires and programmable switches which together account for a significant fraction of the fabric delay and area, making… (more)

Subjects/Keywords: Architectures; CAD Tools; FPGA; Interconnect; Metrics; 0464

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APA (6th Edition):

Petelin, O. (2016). CAD Tools and Architectures for Improved FPGA Interconnect. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/75854

Chicago Manual of Style (16th Edition):

Petelin, Oleg. “CAD Tools and Architectures for Improved FPGA Interconnect.” 2016. Masters Thesis, University of Toronto. Accessed February 21, 2018. http://hdl.handle.net/1807/75854.

MLA Handbook (7th Edition):

Petelin, Oleg. “CAD Tools and Architectures for Improved FPGA Interconnect.” 2016. Web. 21 Feb 2018.

Vancouver:

Petelin O. CAD Tools and Architectures for Improved FPGA Interconnect. [Internet] [Masters thesis]. University of Toronto; 2016. [cited 2018 Feb 21]. Available from: http://hdl.handle.net/1807/75854.

Council of Science Editors:

Petelin O. CAD Tools and Architectures for Improved FPGA Interconnect. [Masters Thesis]. University of Toronto; 2016. Available from: http://hdl.handle.net/1807/75854


Texas A&M University

10. Yi, Yang. Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages.

Degree: 2011, Texas A&M University

Interconnect modeling plays an important role in design and verification of VLSI circuits and packages. For low frequency circuits, great advances for parasitic resistance and… (more)

Subjects/Keywords: Interconnect Modeling; Boundary Element Method; Inductance; Impedance.

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APA (6th Edition):

Yi, Y. (2011). Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-2912

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yi, Yang. “Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages.” 2011. Thesis, Texas A&M University. Accessed February 21, 2018. http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-2912.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yi, Yang. “Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages.” 2011. Web. 21 Feb 2018.

Vancouver:

Yi Y. Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages. [Internet] [Thesis]. Texas A&M University; 2011. [cited 2018 Feb 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-2912.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yi Y. Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages. [Thesis]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-2912

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Ye, Xiaoji. Fast high-order variation-aware IC interconnect analysis.

Degree: 2009, Texas A&M University

 Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in… (more)

Subjects/Keywords: Interconnect; variation

…64 ix LIST OF TABLES TABLE Page I Variational interconnect analysis results: fixed… …input slew (50ps) . . . 36 II Variational interconnect analysis results: w/ input… …37 Variational interconnect delays/slews of RC circuits driven by an inverter: inverter… …interconnect delays/slews of RC circuits driven by a two-input NAND: NAND gate input slew (30ps… …distribution for a near-end node. . . . . . . . . . 31 10 PDF of the interconnect delay… 

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7

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APA (6th Edition):

Ye, X. (2009). Fast high-order variation-aware IC interconnect analysis. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1431

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ye, Xiaoji. “Fast high-order variation-aware IC interconnect analysis.” 2009. Thesis, Texas A&M University. Accessed February 21, 2018. http://hdl.handle.net/1969.1/ETD-TAMU-1431.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ye, Xiaoji. “Fast high-order variation-aware IC interconnect analysis.” 2009. Web. 21 Feb 2018.

Vancouver:

Ye X. Fast high-order variation-aware IC interconnect analysis. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2018 Feb 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1431.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ye X. Fast high-order variation-aware IC interconnect analysis. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1431

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

12. Bharadwaj, Vedula Venkata. Scaling address translation in multi-core architectures using low-latency interconnects.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 Modern systems employ structures known as Translation Lookaside Buffers(TLB) to accelerate the address translation mechanism. As workloads use ever-increasing memory footprints, TLBs are becoming critical… (more)

Subjects/Keywords: TLB; NUTRA; SMART; Interconnect; Distributed; NUCA

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APA (6th Edition):

Bharadwaj, V. V. (2017). Scaling address translation in multi-core architectures using low-latency interconnects. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59300

Chicago Manual of Style (16th Edition):

Bharadwaj, Vedula Venkata. “Scaling address translation in multi-core architectures using low-latency interconnects.” 2017. Masters Thesis, Georgia Tech. Accessed February 21, 2018. http://hdl.handle.net/1853/59300.

MLA Handbook (7th Edition):

Bharadwaj, Vedula Venkata. “Scaling address translation in multi-core architectures using low-latency interconnects.” 2017. Web. 21 Feb 2018.

Vancouver:

Bharadwaj VV. Scaling address translation in multi-core architectures using low-latency interconnects. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2018 Feb 21]. Available from: http://hdl.handle.net/1853/59300.

Council of Science Editors:

Bharadwaj VV. Scaling address translation in multi-core architectures using low-latency interconnects. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59300


Georgia Tech

13. Chen, Wei. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.

Degree: PhD, Mechanical Engineering, 2015, Georgia Tech

 Free-standing off-chip interconnects have high in-plane and out-of-plane compliance and are being pursued in academia and industry to reduce die stresses and to enhance interconnect(more)

Subjects/Keywords: Compliant interconnect; Microelectronic packaging; Packaging reliability

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APA (6th Edition):

Chen, W. (2015). Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55550

Chicago Manual of Style (16th Edition):

Chen, Wei. “Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.” 2015. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2018. http://hdl.handle.net/1853/55550.

MLA Handbook (7th Edition):

Chen, Wei. “Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.” 2015. Web. 21 Feb 2018.

Vancouver:

Chen W. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2018 Feb 21]. Available from: http://hdl.handle.net/1853/55550.

Council of Science Editors:

Chen W. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/55550


University of Cincinnati

14. Liu, Jianxun. Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects.

Degree: PhD, Engineering and Applied Science: Computer Science and Engineering, 2011, University of Cincinnati

 As technology approaches deep sub-micron and clock frequency approaches Giga Hertz, the signal integrity problem of high-speed interconnects is becoming a more and more serious… (more)

Subjects/Keywords: Computer Engineering; Interconnect Testing; Pseudo-Exhaustive Testing; PE-BIST; Signal Integrity; SoC; High Speed Interconnect

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APA (6th Edition):

Liu, J. (2011). Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248

Chicago Manual of Style (16th Edition):

Liu, Jianxun. “Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects.” 2011. Doctoral Dissertation, University of Cincinnati. Accessed February 21, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248.

MLA Handbook (7th Edition):

Liu, Jianxun. “Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects.” 2011. Web. 21 Feb 2018.

Vancouver:

Liu J. Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects. [Internet] [Doctoral dissertation]. University of Cincinnati; 2011. [cited 2018 Feb 21]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248.

Council of Science Editors:

Liu J. Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects. [Doctoral Dissertation]. University of Cincinnati; 2011. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248

15. Guidoni, Luca. Design and testing of an orthogonal LCP interconnect for RF applications in high vibration environments.

Degree: MS, Aerospace Engineering, 2016, Georgia Tech

 A new design is presented for a wideband orthogonal interconnect between two perpendicular printed wiring boards, employing novel geometries and materials to minimize stress under… (more)

Subjects/Keywords: Orthogonal interconnect; RF interconnect; Fatigue

…with Quadratic Interpolation 27 Figure 17: 3D Von Mises Stress Distribution in Interconnect… …Stress Distribution in Interconnect with Aspect Ratio of 0.5 Under 8 mil Total Applied… …Displacement 28 Figure 19: Stackup of Layers Composing the LCP Interconnect Cross-Section 30 Figure… …Distribution vs. Curvilinear Co-Ordinate for 2D Plane Stress Revised Interconnect Model due to 8 mil… …Technique (B) Installed Springs Using Wraparound Technique 51 Figure 39: Interconnect… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Guidoni, L. (2016). Design and testing of an orthogonal LCP interconnect for RF applications in high vibration environments. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54950

Chicago Manual of Style (16th Edition):

Guidoni, Luca. “Design and testing of an orthogonal LCP interconnect for RF applications in high vibration environments.” 2016. Masters Thesis, Georgia Tech. Accessed February 21, 2018. http://hdl.handle.net/1853/54950.

MLA Handbook (7th Edition):

Guidoni, Luca. “Design and testing of an orthogonal LCP interconnect for RF applications in high vibration environments.” 2016. Web. 21 Feb 2018.

Vancouver:

Guidoni L. Design and testing of an orthogonal LCP interconnect for RF applications in high vibration environments. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2018 Feb 21]. Available from: http://hdl.handle.net/1853/54950.

Council of Science Editors:

Guidoni L. Design and testing of an orthogonal LCP interconnect for RF applications in high vibration environments. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/54950


UCLA

16. Jangam, SivaChandra. Simple Universal Parallel Interface (SuperCHIPS) Protocol for High Performance Heterogenous System Integration.

Degree: Electrical Engineering, 2017, UCLA

 This thesis presents the Simple Universal Parallel intERface (SuperCHIPS) protocol for high interconnect density heterogeneous system integration. This is enabled by fine pitch interconnects and… (more)

Subjects/Keywords: Electrical engineering; Engineering; Fine Pitch Interconnect; Silicon Interconnect Fabric; SuperCHIPS; Thermal Compression Bonding

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APA (6th Edition):

Jangam, S. (2017). Simple Universal Parallel Interface (SuperCHIPS) Protocol for High Performance Heterogenous System Integration. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/3m28s0xf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jangam, SivaChandra. “Simple Universal Parallel Interface (SuperCHIPS) Protocol for High Performance Heterogenous System Integration.” 2017. Thesis, UCLA. Accessed February 21, 2018. http://www.escholarship.org/uc/item/3m28s0xf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jangam, SivaChandra. “Simple Universal Parallel Interface (SuperCHIPS) Protocol for High Performance Heterogenous System Integration.” 2017. Web. 21 Feb 2018.

Vancouver:

Jangam S. Simple Universal Parallel Interface (SuperCHIPS) Protocol for High Performance Heterogenous System Integration. [Internet] [Thesis]. UCLA; 2017. [cited 2018 Feb 21]. Available from: http://www.escholarship.org/uc/item/3m28s0xf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jangam S. Simple Universal Parallel Interface (SuperCHIPS) Protocol for High Performance Heterogenous System Integration. [Thesis]. UCLA; 2017. Available from: http://www.escholarship.org/uc/item/3m28s0xf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of South Florida

17. Krishnan, Vyas. Temperature and interconnect aware unified physical and high level synthesis.

Degree: 2008, University of South Florida

 Aggressive scaling of nanoscale CMOS integrated circuits has created significant design challenges arising from increasing power densities, thermal concerns, and rising wire delays. The main… (more)

Subjects/Keywords: Behavioral synthesis; Power-aware design; Thermal analysis; Interconnect-centric design; Stochastic interconnect estimation; American Studies; Arts and Humanities

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APA (6th Edition):

Krishnan, V. (2008). Temperature and interconnect aware unified physical and high level synthesis. (Thesis). University of South Florida. Retrieved from http://scholarcommons.usf.edu/etd/347

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Krishnan, Vyas. “Temperature and interconnect aware unified physical and high level synthesis.” 2008. Thesis, University of South Florida. Accessed February 21, 2018. http://scholarcommons.usf.edu/etd/347.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Krishnan, Vyas. “Temperature and interconnect aware unified physical and high level synthesis.” 2008. Web. 21 Feb 2018.

Vancouver:

Krishnan V. Temperature and interconnect aware unified physical and high level synthesis. [Internet] [Thesis]. University of South Florida; 2008. [cited 2018 Feb 21]. Available from: http://scholarcommons.usf.edu/etd/347.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Krishnan V. Temperature and interconnect aware unified physical and high level synthesis. [Thesis]. University of South Florida; 2008. Available from: http://scholarcommons.usf.edu/etd/347

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Sousa, Cláwsio Rogério Cruz de. Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS .

Degree: 2014, Universidade do Rio Grande do Norte

 Doped lanthanum chromite ( LaCrO3 ) has been the most common material used as interconnect in solid oxide fuel cells for high temperature ( SOFC-HT… (more)

Subjects/Keywords: Termo-mecânica. Interconector cerâmico. Interconector metálico. Cromita de lantânio. PaCOS; Thermo-mechanical. Metallic interconnect. Ceramic interconnect. Lanthanum chromite. SOFC

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APA (6th Edition):

Sousa, C. R. C. d. (2014). Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/12864

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sousa, Cláwsio Rogério Cruz de. “Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS .” 2014. Thesis, Universidade do Rio Grande do Norte. Accessed February 21, 2018. http://repositorio.ufrn.br/handle/123456789/12864.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sousa, Cláwsio Rogério Cruz de. “Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS .” 2014. Web. 21 Feb 2018.

Vancouver:

Sousa CRCd. Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2014. [cited 2018 Feb 21]. Available from: http://repositorio.ufrn.br/handle/123456789/12864.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sousa CRCd. Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS . [Thesis]. Universidade do Rio Grande do Norte; 2014. Available from: http://repositorio.ufrn.br/handle/123456789/12864

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Rochester

19. Hu, Jianyun (1981 - ). Energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects.

Degree: PhD, 2013, University of Rochester

 Recently with the increasing demand for high-speed communications, wideband systems have becomes one of the major research focuses for both academia and industry. While wide… (more)

Subjects/Keywords: Integrated circuit design; On-chip interconnect; Optical interconnect; Transceiver design; Ultra-wideband impulse radio; Wideband and high-speed; CMOS

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APA (6th Edition):

Hu, J. (. -. ). (2013). Energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/26451

Chicago Manual of Style (16th Edition):

Hu, Jianyun (1981 - ). “Energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects.” 2013. Doctoral Dissertation, University of Rochester. Accessed February 21, 2018. http://hdl.handle.net/1802/26451.

MLA Handbook (7th Edition):

Hu, Jianyun (1981 - ). “Energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects.” 2013. Web. 21 Feb 2018.

Vancouver:

Hu J(-). Energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects. [Internet] [Doctoral dissertation]. University of Rochester; 2013. [cited 2018 Feb 21]. Available from: http://hdl.handle.net/1802/26451.

Council of Science Editors:

Hu J(-). Energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects. [Doctoral Dissertation]. University of Rochester; 2013. Available from: http://hdl.handle.net/1802/26451

20. Sousa, Cláwsio Rogério Cruz de. Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS .

Degree: 2014, Universidade do Rio Grande do Norte

 Doped lanthanum chromite ( LaCrO3 ) has been the most common material used as interconnect in solid oxide fuel cells for high temperature ( SOFC-HT… (more)

Subjects/Keywords: Termo-mecânica. Interconector cerâmico. Interconector metálico. Cromita de lantânio. PaCOS; Thermo-mechanical. Metallic interconnect. Ceramic interconnect. Lanthanum chromite. SOFC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sousa, C. R. C. d. (2014). Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS . (Doctoral Dissertation). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/12864

Chicago Manual of Style (16th Edition):

Sousa, Cláwsio Rogério Cruz de. “Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS .” 2014. Doctoral Dissertation, Universidade do Rio Grande do Norte. Accessed February 21, 2018. http://repositorio.ufrn.br/handle/123456789/12864.

MLA Handbook (7th Edition):

Sousa, Cláwsio Rogério Cruz de. “Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS .” 2014. Web. 21 Feb 2018.

Vancouver:

Sousa CRCd. Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS . [Internet] [Doctoral dissertation]. Universidade do Rio Grande do Norte; 2014. [cited 2018 Feb 21]. Available from: http://repositorio.ufrn.br/handle/123456789/12864.

Council of Science Editors:

Sousa CRCd. Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS . [Doctoral Dissertation]. Universidade do Rio Grande do Norte; 2014. Available from: http://repositorio.ufrn.br/handle/123456789/12864

21. Qureshi, Rayyan Ali. FFTS based RFI monitoring for Onsala Space Observatory.

Degree: 2010, Chalmers University of Technology

 The quality of radio astronomical scientific data can be greatly affected by radio frequency interference (RFI). With the increasing demand for wireless communications, the RFI… (more)

Subjects/Keywords: Radio Frequency Interference; Spectral Kurtosis; Interconnect Break-out-Board

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APA (6th Edition):

Qureshi, R. A. (2010). FFTS based RFI monitoring for Onsala Space Observatory. (Thesis). Chalmers University of Technology. Retrieved from http://studentarbeten.chalmers.se/publication/129974-ffts-based-rfi-monitoring-for-onsala-space-observatory

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Qureshi, Rayyan Ali. “FFTS based RFI monitoring for Onsala Space Observatory.” 2010. Thesis, Chalmers University of Technology. Accessed February 21, 2018. http://studentarbeten.chalmers.se/publication/129974-ffts-based-rfi-monitoring-for-onsala-space-observatory.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Qureshi, Rayyan Ali. “FFTS based RFI monitoring for Onsala Space Observatory.” 2010. Web. 21 Feb 2018.

Vancouver:

Qureshi RA. FFTS based RFI monitoring for Onsala Space Observatory. [Internet] [Thesis]. Chalmers University of Technology; 2010. [cited 2018 Feb 21]. Available from: http://studentarbeten.chalmers.se/publication/129974-ffts-based-rfi-monitoring-for-onsala-space-observatory.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Qureshi RA. FFTS based RFI monitoring for Onsala Space Observatory. [Thesis]. Chalmers University of Technology; 2010. Available from: http://studentarbeten.chalmers.se/publication/129974-ffts-based-rfi-monitoring-for-onsala-space-observatory

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Notre Dame

22. David Kopp. Microwave Performance and Fabrication Of Quilt Packaging, a Novel Chip-To-Chip Interconnect Technology.

Degree: PhD, Electrical Engineering, 2014, University of Notre Dame

  Microelectronics packaging forms the link between the nanometer scale transistors on a chip and the micrometer or millimeter scale interconnects that provide electrical connections… (more)

Subjects/Keywords: high frequency; scattering parameters; microwave; interconnect; quilt packaging; packaging

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APA (6th Edition):

Kopp, D. (2014). Microwave Performance and Fabrication Of Quilt Packaging, a Novel Chip-To-Chip Interconnect Technology. (Doctoral Dissertation). University of Notre Dame. Retrieved from https://curate.nd.edu/show/pc289g57846

Chicago Manual of Style (16th Edition):

Kopp, David. “Microwave Performance and Fabrication Of Quilt Packaging, a Novel Chip-To-Chip Interconnect Technology.” 2014. Doctoral Dissertation, University of Notre Dame. Accessed February 21, 2018. https://curate.nd.edu/show/pc289g57846.

MLA Handbook (7th Edition):

Kopp, David. “Microwave Performance and Fabrication Of Quilt Packaging, a Novel Chip-To-Chip Interconnect Technology.” 2014. Web. 21 Feb 2018.

Vancouver:

Kopp D. Microwave Performance and Fabrication Of Quilt Packaging, a Novel Chip-To-Chip Interconnect Technology. [Internet] [Doctoral dissertation]. University of Notre Dame; 2014. [cited 2018 Feb 21]. Available from: https://curate.nd.edu/show/pc289g57846.

Council of Science Editors:

Kopp D. Microwave Performance and Fabrication Of Quilt Packaging, a Novel Chip-To-Chip Interconnect Technology. [Doctoral Dissertation]. University of Notre Dame; 2014. Available from: https://curate.nd.edu/show/pc289g57846


University of Florida

23. Li, Zhongqi. On the Exploration of Next-Generation Interconnect Design for Chip Multi-Processors.

Degree: Electrical and Computer Engineering, 2012, University of Florida

 With the emergence of multi- and many-core processors, the required bandwidth to support effective on-chip communication is expected to grow rapidly. According to ITRS, conventional… (more)

Subjects/Keywords: architecture  – interconnect  – noc  – photonic  – processor; Electrical and Computer Engineering

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APA (6th Edition):

Li, Z. (2012). On the Exploration of Next-Generation Interconnect Design for Chip Multi-Processors. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0044835

Chicago Manual of Style (16th Edition):

Li, Zhongqi. “On the Exploration of Next-Generation Interconnect Design for Chip Multi-Processors.” 2012. Doctoral Dissertation, University of Florida. Accessed February 21, 2018. http://ufdc.ufl.edu/UFE0044835.

MLA Handbook (7th Edition):

Li, Zhongqi. “On the Exploration of Next-Generation Interconnect Design for Chip Multi-Processors.” 2012. Web. 21 Feb 2018.

Vancouver:

Li Z. On the Exploration of Next-Generation Interconnect Design for Chip Multi-Processors. [Internet] [Doctoral dissertation]. University of Florida; 2012. [cited 2018 Feb 21]. Available from: http://ufdc.ufl.edu/UFE0044835.

Council of Science Editors:

Li Z. On the Exploration of Next-Generation Interconnect Design for Chip Multi-Processors. [Doctoral Dissertation]. University of Florida; 2012. Available from: http://ufdc.ufl.edu/UFE0044835


Rochester Institute of Technology

24. Coddington, James David. Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures.

Degree: MS, Computer Engineering, 2015, Rochester Institute of Technology

  With the increased complexity and continual scaling of integrated circuit performance, multi-core chips with dozens, hundreds, even thousands of parallel computing units require high… (more)

Subjects/Keywords: 3D IC; Architecture; Energy; Interconnect; Network-on-chip; Performance

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APA (6th Edition):

Coddington, J. D. (2015). Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures. (Masters Thesis). Rochester Institute of Technology. Retrieved from http://scholarworks.rit.edu/theses/8588

Chicago Manual of Style (16th Edition):

Coddington, James David. “Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures.” 2015. Masters Thesis, Rochester Institute of Technology. Accessed February 21, 2018. http://scholarworks.rit.edu/theses/8588.

MLA Handbook (7th Edition):

Coddington, James David. “Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures.” 2015. Web. 21 Feb 2018.

Vancouver:

Coddington JD. Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures. [Internet] [Masters thesis]. Rochester Institute of Technology; 2015. [cited 2018 Feb 21]. Available from: http://scholarworks.rit.edu/theses/8588.

Council of Science Editors:

Coddington JD. Performance and Energy Trade-offs for 3D IC NoC Interconnects and Architectures. [Masters Thesis]. Rochester Institute of Technology; 2015. Available from: http://scholarworks.rit.edu/theses/8588

25. Liu, Xiaobin. ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY.

Degree: 2015, University of Massachusetts

  With the rapid growth in consumer electronics, people expect thin, smart and powerful devices, e.g. Google Glass and other wearable devices. However, as portable… (more)

Subjects/Keywords: CGRA; MRAM; time-scheduled interconnect; Computer and Systems Architecture; Hardware Systems

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APA (6th Edition):

Liu, X. (2015). ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY. (Thesis). University of Massachusetts. Retrieved from http://scholarworks.umass.edu/masters_theses_2/159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Xiaobin. “ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY.” 2015. Thesis, University of Massachusetts. Accessed February 21, 2018. http://scholarworks.umass.edu/masters_theses_2/159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Xiaobin. “ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY.” 2015. Web. 21 Feb 2018.

Vancouver:

Liu X. ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY. [Internet] [Thesis]. University of Massachusetts; 2015. [cited 2018 Feb 21]. Available from: http://scholarworks.umass.edu/masters_theses_2/159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu X. ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY. [Thesis]. University of Massachusetts; 2015. Available from: http://scholarworks.umass.edu/masters_theses_2/159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

26. HAWK, CHRISTOPHER J. DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY.

Degree: MS, Engineering : Computer Engineering, 2004, University of Cincinnati

 Without a doubt semiconductor technology is advancing at an amazing pace. While traditional analog and digital circuits remain the primary focus, future applications are likely… (more)

Subjects/Keywords: FPGA; programmable interconnect; switch blocks

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APA (6th Edition):

HAWK, C. J. (2004). DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1076114416

Chicago Manual of Style (16th Edition):

HAWK, CHRISTOPHER J. “DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY.” 2004. Masters Thesis, University of Cincinnati. Accessed February 21, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1076114416.

MLA Handbook (7th Edition):

HAWK, CHRISTOPHER J. “DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY.” 2004. Web. 21 Feb 2018.

Vancouver:

HAWK CJ. DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY. [Internet] [Masters thesis]. University of Cincinnati; 2004. [cited 2018 Feb 21]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1076114416.

Council of Science Editors:

HAWK CJ. DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY. [Masters Thesis]. University of Cincinnati; 2004. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1076114416

27. Almer, Oscar Erik Gabriel. Automated application-specific optimisation of interconnects in multi-core systems.

Degree: 2012, University of Edinburgh

 In embedded computer systems there are often tasks, implemented as stand-alone devices, that are both application-specific and compute intensive. A recurring problem in this area… (more)

Subjects/Keywords: interconnect; wkNN; random forest

…4.2 Dynamic energy vs Runtime, showing interconnect frequency distribution. Lower is better… …designs like to regularize the interconnect as a network of components, usually referring to the… …interconnect as a network-on-chip (NOC). Whether the connections between blocks in a SOC… …are thought of as a NOC or an interconnect is irrelevant from a larger perspective; both… …terms will be used in this thesis. A classic approach to designing the interconnect of an SOC… 

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APA (6th Edition):

Almer, O. E. G. (2012). Automated application-specific optimisation of interconnects in multi-core systems. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/7622

Chicago Manual of Style (16th Edition):

Almer, Oscar Erik Gabriel. “Automated application-specific optimisation of interconnects in multi-core systems.” 2012. Doctoral Dissertation, University of Edinburgh. Accessed February 21, 2018. http://hdl.handle.net/1842/7622.

MLA Handbook (7th Edition):

Almer, Oscar Erik Gabriel. “Automated application-specific optimisation of interconnects in multi-core systems.” 2012. Web. 21 Feb 2018.

Vancouver:

Almer OEG. Automated application-specific optimisation of interconnects in multi-core systems. [Internet] [Doctoral dissertation]. University of Edinburgh; 2012. [cited 2018 Feb 21]. Available from: http://hdl.handle.net/1842/7622.

Council of Science Editors:

Almer OEG. Automated application-specific optimisation of interconnects in multi-core systems. [Doctoral Dissertation]. University of Edinburgh; 2012. Available from: http://hdl.handle.net/1842/7622


University of Rochester

28. Carpenter, Aaron (1983 - ). The design and use of high-speed transmission line links for global on-chip communication.

Degree: PhD, 2012, University of Rochester

 As transistors approach the limits of traditional scaling, computer architects can no longer rely on the increase in density and core frequency to improve the… (more)

Subjects/Keywords: Interconnect; Chip multiprocessor; On-chip-network; On-chip communication; Transmission lines

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Carpenter, A. (. -. ). (2012). The design and use of high-speed transmission line links for global on-chip communication. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/21272

Chicago Manual of Style (16th Edition):

Carpenter, Aaron (1983 - ). “The design and use of high-speed transmission line links for global on-chip communication.” 2012. Doctoral Dissertation, University of Rochester. Accessed February 21, 2018. http://hdl.handle.net/1802/21272.

MLA Handbook (7th Edition):

Carpenter, Aaron (1983 - ). “The design and use of high-speed transmission line links for global on-chip communication.” 2012. Web. 21 Feb 2018.

Vancouver:

Carpenter A(-). The design and use of high-speed transmission line links for global on-chip communication. [Internet] [Doctoral dissertation]. University of Rochester; 2012. [cited 2018 Feb 21]. Available from: http://hdl.handle.net/1802/21272.

Council of Science Editors:

Carpenter A(-). The design and use of high-speed transmission line links for global on-chip communication. [Doctoral Dissertation]. University of Rochester; 2012. Available from: http://hdl.handle.net/1802/21272


NSYSU

29. Lei, Kin-fong. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.

Degree: Master, Electrical Engineering, 2010, NSYSU

 In the multi-core systems, the data transfer between cores becomes a major challenge. The on-chip interconnect networks should be low latency, high throughput, scalability, better… (more)

Subjects/Keywords: On-Chip Interconnect Networks; Asynchronous Ring Bus; Multi-Core Systems

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APA (6th Edition):

Lei, K. (2010). Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lei, Kin-fong. “Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.” 2010. Thesis, NSYSU. Accessed February 21, 2018. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lei, Kin-fong. “Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.” 2010. Web. 21 Feb 2018.

Vancouver:

Lei K. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. [Internet] [Thesis]. NSYSU; 2010. [cited 2018 Feb 21]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lei K. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Virginia

30. Huang, Yu. Circuit Design for FPGAs in Sub-Threshold Ultra-Low Power Systems.

Degree: MS, 2015, University of Virginia

 Field programmable gate arrays (FPGAs) are one of the most promising programmable devices in the era of ubiquitous computing. With low power systems limited by… (more)

Subjects/Keywords: FPGA interconnect; sub-threshold; low power system; level converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, Y. (2015). Circuit Design for FPGAs in Sub-Threshold Ultra-Low Power Systems. (Doctoral Dissertation). University of Virginia. Retrieved from http://libra.virginia.edu/catalog/libra-oa:9443

Chicago Manual of Style (16th Edition):

Huang, Yu. “Circuit Design for FPGAs in Sub-Threshold Ultra-Low Power Systems.” 2015. Doctoral Dissertation, University of Virginia. Accessed February 21, 2018. http://libra.virginia.edu/catalog/libra-oa:9443.

MLA Handbook (7th Edition):

Huang, Yu. “Circuit Design for FPGAs in Sub-Threshold Ultra-Low Power Systems.” 2015. Web. 21 Feb 2018.

Vancouver:

Huang Y. Circuit Design for FPGAs in Sub-Threshold Ultra-Low Power Systems. [Internet] [Doctoral dissertation]. University of Virginia; 2015. [cited 2018 Feb 21]. Available from: http://libra.virginia.edu/catalog/libra-oa:9443.

Council of Science Editors:

Huang Y. Circuit Design for FPGAs in Sub-Threshold Ultra-Low Power Systems. [Doctoral Dissertation]. University of Virginia; 2015. Available from: http://libra.virginia.edu/catalog/libra-oa:9443

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