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You searched for subject:(Interconnect). Showing records 1 – 30 of 238 total matches.

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University of New South Wales

1. Chen, Ge. Computer bus interconnect coding and optimisation.

Degree: Electrical Engineering & Telecommunications, 2012, University of New South Wales

 Interconnects become a major bottleneck for deep sub-micron technologies. Interconnect design plays an important role in optimizing the performance of the interconnect in the modern… (more)

Subjects/Keywords: Interconnect; Bus Optimisation

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APA (6th Edition):

Chen, G. (2012). Computer bus interconnect coding and optimisation. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/51624 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10291/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Chen, Ge. “Computer bus interconnect coding and optimisation.” 2012. Doctoral Dissertation, University of New South Wales. Accessed October 01, 2020. http://handle.unsw.edu.au/1959.4/51624 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10291/SOURCE02?view=true.

MLA Handbook (7th Edition):

Chen, Ge. “Computer bus interconnect coding and optimisation.” 2012. Web. 01 Oct 2020.

Vancouver:

Chen G. Computer bus interconnect coding and optimisation. [Internet] [Doctoral dissertation]. University of New South Wales; 2012. [cited 2020 Oct 01]. Available from: http://handle.unsw.edu.au/1959.4/51624 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10291/SOURCE02?view=true.

Council of Science Editors:

Chen G. Computer bus interconnect coding and optimisation. [Doctoral Dissertation]. University of New South Wales; 2012. Available from: http://handle.unsw.edu.au/1959.4/51624 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10291/SOURCE02?view=true


Georgia Tech

2. Wahby, William. Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 Three-dimensional integration, in which integrated circuits (ICs) are stacked directly atop one another to reduce interconnect length, is an attractive method for achieving continued performance… (more)

Subjects/Keywords: 3DIC; Interconnect; Thermal

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APA (6th Edition):

Wahby, W. (2018). Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61184

Chicago Manual of Style (16th Edition):

Wahby, William. “Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits.” 2018. Doctoral Dissertation, Georgia Tech. Accessed October 01, 2020. http://hdl.handle.net/1853/61184.

MLA Handbook (7th Edition):

Wahby, William. “Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits.” 2018. Web. 01 Oct 2020.

Vancouver:

Wahby W. Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1853/61184.

Council of Science Editors:

Wahby W. Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/61184


Wright State University

3. Katpally, Kaushik Reddy. Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect.

Degree: MSEgr, Electrical Engineering, 2014, Wright State University

 A System-on-a-Chip (SoC) has millions of transistors connected by wires or so called Interconnects. As CMOS technologies scale down, SoC becomes more complex and denser.… (more)

Subjects/Keywords: Engineering; Electrical Engineering; Interconnect Delay

…Uniformly Spaced Interconnect Specifications 16 6. Non-Uniformly Spaced Interconnect… …Specifications 16 7. Non-Uniformly Spaced Interconnect Output Simulation 17 8. Uniformly Spaced… …Interconnect Output Simulation 17 9. (a). Original Booster: Propagation Delay, Rise Time and Fall… …increases. 3. The reliability of the circuits increases. Interconnect delay has been negligible… …significant. In an Interconnect, 1. wire resistance is proportional to its length. 2. wire… 

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APA (6th Edition):

Katpally, K. R. (2014). Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1422056732

Chicago Manual of Style (16th Edition):

Katpally, Kaushik Reddy. “Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect.” 2014. Masters Thesis, Wright State University. Accessed October 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1422056732.

MLA Handbook (7th Edition):

Katpally, Kaushik Reddy. “Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect.” 2014. Web. 01 Oct 2020.

Vancouver:

Katpally KR. Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect. [Internet] [Masters thesis]. Wright State University; 2014. [cited 2020 Oct 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1422056732.

Council of Science Editors:

Katpally KR. Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect. [Masters Thesis]. Wright State University; 2014. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1422056732


Anna University

4. Anithar. Design implementation and Performance evaluation of network On chip communication link router;.

Degree: Design implementation and Performance evaluation of network On chip communication link router, 2015, Anna University

In today s mobile and communication world Router plays a newlinesignificant role to select classify and forward the data from source node to newlinedestination node… (more)

Subjects/Keywords: Fixed routing scheme; Interconnect infrastructure

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APA (6th Edition):

Anithar. (2015). Design implementation and Performance evaluation of network On chip communication link router;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/39833

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Anithar. “Design implementation and Performance evaluation of network On chip communication link router;.” 2015. Thesis, Anna University. Accessed October 01, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/39833.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Anithar. “Design implementation and Performance evaluation of network On chip communication link router;.” 2015. Web. 01 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Anithar. Design implementation and Performance evaluation of network On chip communication link router;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Oct 01]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39833.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Anithar. Design implementation and Performance evaluation of network On chip communication link router;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39833

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

5. Hu, Jianchen. Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System.

Degree: MS, Electrical Engineering, 2009, North Carolina State University

 As the complexity of SoC design grows, the traditional register transfer level (RTL) centric design flow cannot meet the time to market. In that case,… (more)

Subjects/Keywords: interconnect; TLM; Network-on-chip

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APA (6th Edition):

Hu, J. (2009). Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hu, Jianchen. “Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System.” 2009. Thesis, North Carolina State University. Accessed October 01, 2020. http://www.lib.ncsu.edu/resolver/1840.16/1617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hu, Jianchen. “Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System.” 2009. Web. 01 Oct 2020.

Vancouver:

Hu J. Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System. [Internet] [Thesis]. North Carolina State University; 2009. [cited 2020 Oct 01]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hu J. Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System. [Thesis]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Nairobi

6. Adongo, Mchael O. Automated multiagent-based interoperator billing and payment system (ambibpsy) .

Degree: 2012, University of Nairobi

 Different operators offering telecommunication services cannot operate in isolation. They have to depend on each other in order to provide all inclusive telecommunication services to… (more)

Subjects/Keywords: AMBIBPSY system; operators; interconnect services

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APA (6th Edition):

Adongo, M. O. (2012). Automated multiagent-based interoperator billing and payment system (ambibpsy) . (Thesis). University of Nairobi. Retrieved from http://erepository.uonbi.ac.ke:8080/xmlui/handle/123456789/10157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Adongo, Mchael O. “Automated multiagent-based interoperator billing and payment system (ambibpsy) .” 2012. Thesis, University of Nairobi. Accessed October 01, 2020. http://erepository.uonbi.ac.ke:8080/xmlui/handle/123456789/10157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Adongo, Mchael O. “Automated multiagent-based interoperator billing and payment system (ambibpsy) .” 2012. Web. 01 Oct 2020.

Vancouver:

Adongo MO. Automated multiagent-based interoperator billing and payment system (ambibpsy) . [Internet] [Thesis]. University of Nairobi; 2012. [cited 2020 Oct 01]. Available from: http://erepository.uonbi.ac.ke:8080/xmlui/handle/123456789/10157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Adongo MO. Automated multiagent-based interoperator billing and payment system (ambibpsy) . [Thesis]. University of Nairobi; 2012. Available from: http://erepository.uonbi.ac.ke:8080/xmlui/handle/123456789/10157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

7. Carisey, Y.C.P. (author). Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles.

Degree: 2014, Delft University of Technology

Nowadays, the demand for enhanced performance and reliability in micro and nano systems is growing, especially for fine pitch wafer level integration. Due to reliability… (more)

Subjects/Keywords: interconnect; nanoparticle; sintering; stencil printing

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APA (6th Edition):

Carisey, Y. C. P. (. (2014). Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:1b9a667d-40c6-4743-8466-6d4614505ada

Chicago Manual of Style (16th Edition):

Carisey, Y C P (author). “Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles.” 2014. Masters Thesis, Delft University of Technology. Accessed October 01, 2020. http://resolver.tudelft.nl/uuid:1b9a667d-40c6-4743-8466-6d4614505ada.

MLA Handbook (7th Edition):

Carisey, Y C P (author). “Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles.” 2014. Web. 01 Oct 2020.

Vancouver:

Carisey YCP(. Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles. [Internet] [Masters thesis]. Delft University of Technology; 2014. [cited 2020 Oct 01]. Available from: http://resolver.tudelft.nl/uuid:1b9a667d-40c6-4743-8466-6d4614505ada.

Council of Science Editors:

Carisey YCP(. Low temperature fine pitch vertical wafer level interconnection using copper nanoparticles. [Masters Thesis]. Delft University of Technology; 2014. Available from: http://resolver.tudelft.nl/uuid:1b9a667d-40c6-4743-8466-6d4614505ada

8. Ying, Min. A Soft-Body Interconnect For Self-Reconfigurable Modular Robots.

Degree: MS, 2014, Worcester Polytechnic Institute

 Disaster support and recovery generally involve highly irregular and dangerous environments. Modular robots are a salient solution to support search and rescue efforts but are… (more)

Subjects/Keywords: soft-body material; interconnect mechanism

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APA (6th Edition):

Ying, M. (2014). A Soft-Body Interconnect For Self-Reconfigurable Modular Robots. (Thesis). Worcester Polytechnic Institute. Retrieved from etd-042114-134817 ; https://digitalcommons.wpi.edu/etd-theses/234

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ying, Min. “A Soft-Body Interconnect For Self-Reconfigurable Modular Robots.” 2014. Thesis, Worcester Polytechnic Institute. Accessed October 01, 2020. etd-042114-134817 ; https://digitalcommons.wpi.edu/etd-theses/234.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ying, Min. “A Soft-Body Interconnect For Self-Reconfigurable Modular Robots.” 2014. Web. 01 Oct 2020.

Vancouver:

Ying M. A Soft-Body Interconnect For Self-Reconfigurable Modular Robots. [Internet] [Thesis]. Worcester Polytechnic Institute; 2014. [cited 2020 Oct 01]. Available from: etd-042114-134817 ; https://digitalcommons.wpi.edu/etd-theses/234.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ying M. A Soft-Body Interconnect For Self-Reconfigurable Modular Robots. [Thesis]. Worcester Polytechnic Institute; 2014. Available from: etd-042114-134817 ; https://digitalcommons.wpi.edu/etd-theses/234

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

9. Yi, Yang. Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages.

Degree: PhD, Electrical Engineering, 2011, Texas A&M University

Interconnect modeling plays an important role in design and verification of VLSI circuits and packages. For low frequency circuits, great advances for parasitic resistance and… (more)

Subjects/Keywords: Interconnect Modeling; Boundary Element Method; Inductance; Impedance.

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APA (6th Edition):

Yi, Y. (2011). Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-2912

Chicago Manual of Style (16th Edition):

Yi, Yang. “Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages.” 2011. Doctoral Dissertation, Texas A&M University. Accessed October 01, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-2912.

MLA Handbook (7th Edition):

Yi, Yang. “Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages.” 2011. Web. 01 Oct 2020.

Vancouver:

Yi Y. Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages. [Internet] [Doctoral dissertation]. Texas A&M University; 2011. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-2912.

Council of Science Editors:

Yi Y. Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages. [Doctoral Dissertation]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-2912


University of Toronto

10. Sharifymoghaddam, Sayeh. Low-swing Signaling for FPGA Interconnect Power Reduction.

Degree: 2015, University of Toronto

FPGAs are widely used in digital circuits implementation because of their lower non-recurring engineering cost and shorter time-to-market in comparison with ASICs. However, there are… (more)

Subjects/Keywords: FPGA; Interconnect; low-swing signaling; Power; 0544

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APA (6th Edition):

Sharifymoghaddam, S. (2015). Low-swing Signaling for FPGA Interconnect Power Reduction. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/72600

Chicago Manual of Style (16th Edition):

Sharifymoghaddam, Sayeh. “Low-swing Signaling for FPGA Interconnect Power Reduction.” 2015. Masters Thesis, University of Toronto. Accessed October 01, 2020. http://hdl.handle.net/1807/72600.

MLA Handbook (7th Edition):

Sharifymoghaddam, Sayeh. “Low-swing Signaling for FPGA Interconnect Power Reduction.” 2015. Web. 01 Oct 2020.

Vancouver:

Sharifymoghaddam S. Low-swing Signaling for FPGA Interconnect Power Reduction. [Internet] [Masters thesis]. University of Toronto; 2015. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1807/72600.

Council of Science Editors:

Sharifymoghaddam S. Low-swing Signaling for FPGA Interconnect Power Reduction. [Masters Thesis]. University of Toronto; 2015. Available from: http://hdl.handle.net/1807/72600


University of Toronto

11. Petelin, Oleg. CAD Tools and Architectures for Improved FPGA Interconnect.

Degree: 2016, University of Toronto

The FPGA routing architecture consists of routing wires and programmable switches which together account for a significant fraction of the fabric delay and area, making… (more)

Subjects/Keywords: Architectures; CAD Tools; FPGA; Interconnect; Metrics; 0464

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APA (6th Edition):

Petelin, O. (2016). CAD Tools and Architectures for Improved FPGA Interconnect. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/75854

Chicago Manual of Style (16th Edition):

Petelin, Oleg. “CAD Tools and Architectures for Improved FPGA Interconnect.” 2016. Masters Thesis, University of Toronto. Accessed October 01, 2020. http://hdl.handle.net/1807/75854.

MLA Handbook (7th Edition):

Petelin, Oleg. “CAD Tools and Architectures for Improved FPGA Interconnect.” 2016. Web. 01 Oct 2020.

Vancouver:

Petelin O. CAD Tools and Architectures for Improved FPGA Interconnect. [Internet] [Masters thesis]. University of Toronto; 2016. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1807/75854.

Council of Science Editors:

Petelin O. CAD Tools and Architectures for Improved FPGA Interconnect. [Masters Thesis]. University of Toronto; 2016. Available from: http://hdl.handle.net/1807/75854


University of Toronto

12. Rodionov, Alexandr. Automated Interconnect Synthesis and Optimization for FPGAs.

Degree: PhD, 2019, University of Toronto

 One of the key challenges for the FPGA industry going forward is to make the task of designing hardware easier. A significant portion of that… (more)

Subjects/Keywords: Automation; CAD; FPGA; HLS; Interconnect; NoC; 0464

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APA (6th Edition):

Rodionov, A. (2019). Automated Interconnect Synthesis and Optimization for FPGAs. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/97619

Chicago Manual of Style (16th Edition):

Rodionov, Alexandr. “Automated Interconnect Synthesis and Optimization for FPGAs.” 2019. Doctoral Dissertation, University of Toronto. Accessed October 01, 2020. http://hdl.handle.net/1807/97619.

MLA Handbook (7th Edition):

Rodionov, Alexandr. “Automated Interconnect Synthesis and Optimization for FPGAs.” 2019. Web. 01 Oct 2020.

Vancouver:

Rodionov A. Automated Interconnect Synthesis and Optimization for FPGAs. [Internet] [Doctoral dissertation]. University of Toronto; 2019. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1807/97619.

Council of Science Editors:

Rodionov A. Automated Interconnect Synthesis and Optimization for FPGAs. [Doctoral Dissertation]. University of Toronto; 2019. Available from: http://hdl.handle.net/1807/97619


Georgia Tech

13. Bharadwaj, Vedula Venkata. Scaling address translation in multi-core architectures using low-latency interconnects.

Degree: MS, Electrical and Computer Engineering, 2017, Georgia Tech

 Modern systems employ structures known as Translation Lookaside Buffers(TLB) to accelerate the address translation mechanism. As workloads use ever-increasing memory footprints, TLBs are becoming critical… (more)

Subjects/Keywords: TLB; NUTRA; SMART; Interconnect; Distributed; NUCA

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APA (6th Edition):

Bharadwaj, V. V. (2017). Scaling address translation in multi-core architectures using low-latency interconnects. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59300

Chicago Manual of Style (16th Edition):

Bharadwaj, Vedula Venkata. “Scaling address translation in multi-core architectures using low-latency interconnects.” 2017. Masters Thesis, Georgia Tech. Accessed October 01, 2020. http://hdl.handle.net/1853/59300.

MLA Handbook (7th Edition):

Bharadwaj, Vedula Venkata. “Scaling address translation in multi-core architectures using low-latency interconnects.” 2017. Web. 01 Oct 2020.

Vancouver:

Bharadwaj VV. Scaling address translation in multi-core architectures using low-latency interconnects. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1853/59300.

Council of Science Editors:

Bharadwaj VV. Scaling address translation in multi-core architectures using low-latency interconnects. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59300


Georgia Tech

14. Chen, Wei. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.

Degree: PhD, Mechanical Engineering, 2015, Georgia Tech

 Free-standing off-chip interconnects have high in-plane and out-of-plane compliance and are being pursued in academia and industry to reduce die stresses and to enhance interconnect(more)

Subjects/Keywords: Compliant interconnect; Microelectronic packaging; Packaging reliability

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APA (6th Edition):

Chen, W. (2015). Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55550

Chicago Manual of Style (16th Edition):

Chen, Wei. “Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.” 2015. Doctoral Dissertation, Georgia Tech. Accessed October 01, 2020. http://hdl.handle.net/1853/55550.

MLA Handbook (7th Edition):

Chen, Wei. “Design, fabrication, and reliability study of second-level compliant microelectronic interconnects.” 2015. Web. 01 Oct 2020.

Vancouver:

Chen W. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1853/55550.

Council of Science Editors:

Chen W. Design, fabrication, and reliability study of second-level compliant microelectronic interconnects. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/55550


Louisiana State University

15. Mohsin, K M. Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect.

Degree: PhD, Electrical and Electronics, 2017, Louisiana State University

  This work studies various emerging reduced dimensional materials for very large-scale integration (VLSI) interconnects. The prime motivation of this work is to find an… (more)

Subjects/Keywords: VLSI; Interconnect; Graphene; CNT; Nanomaterials; DFT

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APA (6th Edition):

Mohsin, K. M. (2017). Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect. (Doctoral Dissertation). Louisiana State University. Retrieved from https://digitalcommons.lsu.edu/gradschool_dissertations/4168

Chicago Manual of Style (16th Edition):

Mohsin, K M. “Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect.” 2017. Doctoral Dissertation, Louisiana State University. Accessed October 01, 2020. https://digitalcommons.lsu.edu/gradschool_dissertations/4168.

MLA Handbook (7th Edition):

Mohsin, K M. “Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect.” 2017. Web. 01 Oct 2020.

Vancouver:

Mohsin KM. Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect. [Internet] [Doctoral dissertation]. Louisiana State University; 2017. [cited 2020 Oct 01]. Available from: https://digitalcommons.lsu.edu/gradschool_dissertations/4168.

Council of Science Editors:

Mohsin KM. Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect. [Doctoral Dissertation]. Louisiana State University; 2017. Available from: https://digitalcommons.lsu.edu/gradschool_dissertations/4168

16. Ye, Xiaoji. Fast high-order variation-aware IC interconnect analysis.

Degree: MS, Computer Engineering, 2009, Texas A&M University

 Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in… (more)

Subjects/Keywords: Interconnect; variation

…64 ix LIST OF TABLES TABLE Page I Variational interconnect analysis results: fixed… …input slew (50ps) . . . 36 II Variational interconnect analysis results: w/ input… …37 Variational interconnect delays/slews of RC circuits driven by an inverter: inverter… …interconnect delays/slews of RC circuits driven by a two-input NAND: NAND gate input slew (30ps… …distribution for a near-end node. . . . . . . . . . 31 10 PDF of the interconnect delay… 

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7

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APA (6th Edition):

Ye, X. (2009). Fast high-order variation-aware IC interconnect analysis. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1431

Chicago Manual of Style (16th Edition):

Ye, Xiaoji. “Fast high-order variation-aware IC interconnect analysis.” 2009. Masters Thesis, Texas A&M University. Accessed October 01, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-1431.

MLA Handbook (7th Edition):

Ye, Xiaoji. “Fast high-order variation-aware IC interconnect analysis.” 2009. Web. 01 Oct 2020.

Vancouver:

Ye X. Fast high-order variation-aware IC interconnect analysis. [Internet] [Masters thesis]. Texas A&M University; 2009. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1431.

Council of Science Editors:

Ye X. Fast high-order variation-aware IC interconnect analysis. [Masters Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1431


University of Cincinnati

17. Liu, Jianxun. Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects.

Degree: PhD, Engineering and Applied Science: Computer Science and Engineering, 2011, University of Cincinnati

 As technology approaches deep sub-micron and clock frequency approaches Giga Hertz, the signal integrity problem of high-speed interconnects is becoming a more and more serious… (more)

Subjects/Keywords: Computer Engineering; Interconnect Testing; Pseudo-Exhaustive Testing; PE-BIST; Signal Integrity; SoC; High Speed Interconnect

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APA (6th Edition):

Liu, J. (2011). Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248

Chicago Manual of Style (16th Edition):

Liu, Jianxun. “Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects.” 2011. Doctoral Dissertation, University of Cincinnati. Accessed October 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248.

MLA Handbook (7th Edition):

Liu, Jianxun. “Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects.” 2011. Web. 01 Oct 2020.

Vancouver:

Liu J. Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects. [Internet] [Doctoral dissertation]. University of Cincinnati; 2011. [cited 2020 Oct 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248.

Council of Science Editors:

Liu J. Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects. [Doctoral Dissertation]. University of Cincinnati; 2011. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248

18. Guidoni, Luca. Design and testing of an orthogonal LCP interconnect for RF applications in high vibration environments.

Degree: MS, Aerospace Engineering, 2016, Georgia Tech

 A new design is presented for a wideband orthogonal interconnect between two perpendicular printed wiring boards, employing novel geometries and materials to minimize stress under… (more)

Subjects/Keywords: Orthogonal interconnect; RF interconnect; Fatigue

…with Quadratic Interpolation 27 Figure 17: 3D Von Mises Stress Distribution in Interconnect… …Stress Distribution in Interconnect with Aspect Ratio of 0.5 Under 8 mil Total Applied… …Displacement 28 Figure 19: Stackup of Layers Composing the LCP Interconnect Cross-Section 30 Figure… …Distribution vs. Curvilinear Co-Ordinate for 2D Plane Stress Revised Interconnect Model due to 8 mil… …Technique (B) Installed Springs Using Wraparound Technique 51 Figure 39: Interconnect… 

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APA (6th Edition):

Guidoni, L. (2016). Design and testing of an orthogonal LCP interconnect for RF applications in high vibration environments. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/54950

Chicago Manual of Style (16th Edition):

Guidoni, Luca. “Design and testing of an orthogonal LCP interconnect for RF applications in high vibration environments.” 2016. Masters Thesis, Georgia Tech. Accessed October 01, 2020. http://hdl.handle.net/1853/54950.

MLA Handbook (7th Edition):

Guidoni, Luca. “Design and testing of an orthogonal LCP interconnect for RF applications in high vibration environments.” 2016. Web. 01 Oct 2020.

Vancouver:

Guidoni L. Design and testing of an orthogonal LCP interconnect for RF applications in high vibration environments. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1853/54950.

Council of Science Editors:

Guidoni L. Design and testing of an orthogonal LCP interconnect for RF applications in high vibration environments. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/54950


Universidade do Rio Grande do Norte

19. Sousa, Cláwsio Rogério Cruz de. Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS .

Degree: 2014, Universidade do Rio Grande do Norte

 Doped lanthanum chromite ( LaCrO3 ) has been the most common material used as interconnect in solid oxide fuel cells for high temperature ( SOFC-HT… (more)

Subjects/Keywords: Termo-mecânica. Interconector cerâmico. Interconector metálico. Cromita de lantânio. PaCOS; Thermo-mechanical. Metallic interconnect. Ceramic interconnect. Lanthanum chromite. SOFC

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APA (6th Edition):

Sousa, C. R. C. d. (2014). Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/12864

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sousa, Cláwsio Rogério Cruz de. “Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS .” 2014. Thesis, Universidade do Rio Grande do Norte. Accessed October 01, 2020. http://repositorio.ufrn.br/handle/123456789/12864.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sousa, Cláwsio Rogério Cruz de. “Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS .” 2014. Web. 01 Oct 2020.

Vancouver:

Sousa CRCd. Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2014. [cited 2020 Oct 01]. Available from: http://repositorio.ufrn.br/handle/123456789/12864.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sousa CRCd. Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS . [Thesis]. Universidade do Rio Grande do Norte; 2014. Available from: http://repositorio.ufrn.br/handle/123456789/12864

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Rochester

20. Hu, Jianyun (1981 - ). Energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects.

Degree: PhD, 2013, University of Rochester

 Recently with the increasing demand for high-speed communications, wideband systems have becomes one of the major research focuses for both academia and industry. While wide… (more)

Subjects/Keywords: Integrated circuit design; On-chip interconnect; Optical interconnect; Transceiver design; Ultra-wideband impulse radio; Wideband and high-speed; CMOS

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APA (6th Edition):

Hu, J. (. -. ). (2013). Energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/26451

Chicago Manual of Style (16th Edition):

Hu, Jianyun (1981 - ). “Energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects.” 2013. Doctoral Dissertation, University of Rochester. Accessed October 01, 2020. http://hdl.handle.net/1802/26451.

MLA Handbook (7th Edition):

Hu, Jianyun (1981 - ). “Energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects.” 2013. Web. 01 Oct 2020.

Vancouver:

Hu J(-). Energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects. [Internet] [Doctoral dissertation]. University of Rochester; 2013. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1802/26451.

Council of Science Editors:

Hu J(-). Energy-efficient, wideband transceiver architectures and circuits for high-speed communications and interconnects. [Doctoral Dissertation]. University of Rochester; 2013. Available from: http://hdl.handle.net/1802/26451


Universidade do Rio Grande do Norte

21. Sousa, Cláwsio Rogério Cruz de. Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS .

Degree: 2014, Universidade do Rio Grande do Norte

 Doped lanthanum chromite ( LaCrO3 ) has been the most common material used as interconnect in solid oxide fuel cells for high temperature ( SOFC-HT… (more)

Subjects/Keywords: Termo-mecânica. Interconector cerâmico. Interconector metálico. Cromita de lantânio. PaCOS; Thermo-mechanical. Metallic interconnect. Ceramic interconnect. Lanthanum chromite. SOFC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sousa, C. R. C. d. (2014). Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS . (Doctoral Dissertation). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/12864

Chicago Manual of Style (16th Edition):

Sousa, Cláwsio Rogério Cruz de. “Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS .” 2014. Doctoral Dissertation, Universidade do Rio Grande do Norte. Accessed October 01, 2020. http://repositorio.ufrn.br/handle/123456789/12864.

MLA Handbook (7th Edition):

Sousa, Cláwsio Rogério Cruz de. “Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS .” 2014. Web. 01 Oct 2020.

Vancouver:

Sousa CRCd. Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS . [Internet] [Doctoral dissertation]. Universidade do Rio Grande do Norte; 2014. [cited 2020 Oct 01]. Available from: http://repositorio.ufrn.br/handle/123456789/12864.

Council of Science Editors:

Sousa CRCd. Estudo termo-mecânico de interconector metálico recoberto com filme de La0,8Ca0,2CrO3 e de interconector cerâmico de La0,8Sr0,2Cr0,92Co0,08O3 para PaCOS . [Doctoral Dissertation]. Universidade do Rio Grande do Norte; 2014. Available from: http://repositorio.ufrn.br/handle/123456789/12864


Texas A&M University

22. Jain, Tushar Naveen Kumar. Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips.

Degree: MS, Computer Engineering, 2011, Texas A&M University

 Dr. Paul V. Gratz Network-on-Chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI design,… (more)

Subjects/Keywords: NoC; Mesochronous clocking; GALS; asynchronous interconnect; on-chip networks

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APA (6th Edition):

Jain, T. N. K. (2011). Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8457

Chicago Manual of Style (16th Edition):

Jain, Tushar Naveen Kumar. “Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips.” 2011. Masters Thesis, Texas A&M University. Accessed October 01, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8457.

MLA Handbook (7th Edition):

Jain, Tushar Naveen Kumar. “Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips.” 2011. Web. 01 Oct 2020.

Vancouver:

Jain TNK. Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips. [Internet] [Masters thesis]. Texas A&M University; 2011. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8457.

Council of Science Editors:

Jain TNK. Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips. [Masters Thesis]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8457


McMaster University

23. WANG, YADI. Structure and Electrical Conductivity of Mn-based Spinels Used as Solid Oxide Fuel Cell Interconnect Coatings.

Degree: MASc, 2013, McMaster University

At solid oxide fuel cell (SOFC) operating temperatures (650oC – 800oC), the chromia scale growth on the interconnect surface and chromium poisoning of cathode can… (more)

Subjects/Keywords: SOFC; Interconnect; Coating; Spinel; Electrical conductivity; Ceramic Materials; Ceramic Materials

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APA (6th Edition):

WANG, Y. (2013). Structure and Electrical Conductivity of Mn-based Spinels Used as Solid Oxide Fuel Cell Interconnect Coatings. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/13354

Chicago Manual of Style (16th Edition):

WANG, YADI. “Structure and Electrical Conductivity of Mn-based Spinels Used as Solid Oxide Fuel Cell Interconnect Coatings.” 2013. Masters Thesis, McMaster University. Accessed October 01, 2020. http://hdl.handle.net/11375/13354.

MLA Handbook (7th Edition):

WANG, YADI. “Structure and Electrical Conductivity of Mn-based Spinels Used as Solid Oxide Fuel Cell Interconnect Coatings.” 2013. Web. 01 Oct 2020.

Vancouver:

WANG Y. Structure and Electrical Conductivity of Mn-based Spinels Used as Solid Oxide Fuel Cell Interconnect Coatings. [Internet] [Masters thesis]. McMaster University; 2013. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/11375/13354.

Council of Science Editors:

WANG Y. Structure and Electrical Conductivity of Mn-based Spinels Used as Solid Oxide Fuel Cell Interconnect Coatings. [Masters Thesis]. McMaster University; 2013. Available from: http://hdl.handle.net/11375/13354


Penn State University

24. Li, Lin. DESIGNING ENERGY-EFFICIENT AND RELIABLE CACHES AND INTERCONNECTS.

Degree: 2008, Penn State University

 The minimum feature size of VLSI technology has shrunk exponentially in the past three decades and this trend is expected to continue in the near… (more)

Subjects/Keywords: Energy-Efficiency; Reliability; Cache; Interconnect

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APA (6th Edition):

Li, L. (2008). DESIGNING ENERGY-EFFICIENT AND RELIABLE CACHES AND INTERCONNECTS. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/6754

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Lin. “DESIGNING ENERGY-EFFICIENT AND RELIABLE CACHES AND INTERCONNECTS.” 2008. Thesis, Penn State University. Accessed October 01, 2020. https://submit-etda.libraries.psu.edu/catalog/6754.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Lin. “DESIGNING ENERGY-EFFICIENT AND RELIABLE CACHES AND INTERCONNECTS.” 2008. Web. 01 Oct 2020.

Vancouver:

Li L. DESIGNING ENERGY-EFFICIENT AND RELIABLE CACHES AND INTERCONNECTS. [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Oct 01]. Available from: https://submit-etda.libraries.psu.edu/catalog/6754.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li L. DESIGNING ENERGY-EFFICIENT AND RELIABLE CACHES AND INTERCONNECTS. [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/6754

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

25. Garg, Tushar. HopliteBuf FPGA Network-on-Chip: Architecture and Analysis.

Degree: 2019, University of Waterloo

 We can prove occupancy bounds of stall-free FIFOs used in deflection-free, low-cost, and high-speed FPGA overlay Network-on-chips (NoCs). In our work, we build on top… (more)

Subjects/Keywords: network-on-chip; fpga; programmable-interconnect; unidirectional-torus; reconfigurable-computing

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APA (6th Edition):

Garg, T. (2019). HopliteBuf FPGA Network-on-Chip: Architecture and Analysis. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/14543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Garg, Tushar. “HopliteBuf FPGA Network-on-Chip: Architecture and Analysis.” 2019. Thesis, University of Waterloo. Accessed October 01, 2020. http://hdl.handle.net/10012/14543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Garg, Tushar. “HopliteBuf FPGA Network-on-Chip: Architecture and Analysis.” 2019. Web. 01 Oct 2020.

Vancouver:

Garg T. HopliteBuf FPGA Network-on-Chip: Architecture and Analysis. [Internet] [Thesis]. University of Waterloo; 2019. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/10012/14543.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Garg T. HopliteBuf FPGA Network-on-Chip: Architecture and Analysis. [Thesis]. University of Waterloo; 2019. Available from: http://hdl.handle.net/10012/14543

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

26. Peng, Yuantao. Low-Power Repeater Insertion for Global Interconnects.

Degree: PhD, Electrical Engineering, 2006, North Carolina State University

 Repeater insertion is one of the most widely used techniques to reduce the signal propagation delay on global interconnects. The number of repeaters inserted into… (more)

Subjects/Keywords: Low-Power; Interconnect; Repeater

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APA (6th Edition):

Peng, Y. (2006). Low-Power Repeater Insertion for Global Interconnects. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/3499

Chicago Manual of Style (16th Edition):

Peng, Yuantao. “Low-Power Repeater Insertion for Global Interconnects.” 2006. Doctoral Dissertation, North Carolina State University. Accessed October 01, 2020. http://www.lib.ncsu.edu/resolver/1840.16/3499.

MLA Handbook (7th Edition):

Peng, Yuantao. “Low-Power Repeater Insertion for Global Interconnects.” 2006. Web. 01 Oct 2020.

Vancouver:

Peng Y. Low-Power Repeater Insertion for Global Interconnects. [Internet] [Doctoral dissertation]. North Carolina State University; 2006. [cited 2020 Oct 01]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3499.

Council of Science Editors:

Peng Y. Low-Power Repeater Insertion for Global Interconnects. [Doctoral Dissertation]. North Carolina State University; 2006. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3499


North Carolina State University

27. Kim, Taemin. Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs.

Degree: PhD, Computer Engineering, 2009, North Carolina State University

 Optimization techniques during high level synthesis procedure are often preferred since design decisions at early stages of a design flow are believed to have a… (more)

Subjects/Keywords: High Level Synthesis; Global Interconnect; VLSI CAD; Optimization; Algorithm

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APA (6th Edition):

Kim, T. (2009). Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/4109

Chicago Manual of Style (16th Edition):

Kim, Taemin. “Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs.” 2009. Doctoral Dissertation, North Carolina State University. Accessed October 01, 2020. http://www.lib.ncsu.edu/resolver/1840.16/4109.

MLA Handbook (7th Edition):

Kim, Taemin. “Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs.” 2009. Web. 01 Oct 2020.

Vancouver:

Kim T. Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs. [Internet] [Doctoral dissertation]. North Carolina State University; 2009. [cited 2020 Oct 01]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4109.

Council of Science Editors:

Kim T. Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs. [Doctoral Dissertation]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4109


University of Rochester

28. Carpenter, Aaron (1983 - ). The design and use of high-speed transmission line links for global on-chip communication.

Degree: PhD, 2012, University of Rochester

 As transistors approach the limits of traditional scaling, computer architects can no longer rely on the increase in density and core frequency to improve the… (more)

Subjects/Keywords: Interconnect; Chip multiprocessor; On-chip-network; On-chip communication; Transmission lines

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APA (6th Edition):

Carpenter, A. (. -. ). (2012). The design and use of high-speed transmission line links for global on-chip communication. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/21272

Chicago Manual of Style (16th Edition):

Carpenter, Aaron (1983 - ). “The design and use of high-speed transmission line links for global on-chip communication.” 2012. Doctoral Dissertation, University of Rochester. Accessed October 01, 2020. http://hdl.handle.net/1802/21272.

MLA Handbook (7th Edition):

Carpenter, Aaron (1983 - ). “The design and use of high-speed transmission line links for global on-chip communication.” 2012. Web. 01 Oct 2020.

Vancouver:

Carpenter A(-). The design and use of high-speed transmission line links for global on-chip communication. [Internet] [Doctoral dissertation]. University of Rochester; 2012. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1802/21272.

Council of Science Editors:

Carpenter A(-). The design and use of high-speed transmission line links for global on-chip communication. [Doctoral Dissertation]. University of Rochester; 2012. Available from: http://hdl.handle.net/1802/21272


University of California – San Diego

29. Fang, Cheng-Yi. On-Chip Integrated Nano-Scale Light Sources and Switches for Optical Interconnect.

Degree: Materials Science and Engineering, 2019, University of California – San Diego

 The rapidly growing global internet traffic requires ever faster data transfer within computer networks. Photonic integrated circuits can pave the way to accelerated signal transmission… (more)

Subjects/Keywords: Optics; Materials Science; Applied physics; Optical Interconnect; Semiconductor laser; silicon photonics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fang, C. (2019). On-Chip Integrated Nano-Scale Light Sources and Switches for Optical Interconnect. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/23m805w0

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fang, Cheng-Yi. “On-Chip Integrated Nano-Scale Light Sources and Switches for Optical Interconnect.” 2019. Thesis, University of California – San Diego. Accessed October 01, 2020. http://www.escholarship.org/uc/item/23m805w0.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fang, Cheng-Yi. “On-Chip Integrated Nano-Scale Light Sources and Switches for Optical Interconnect.” 2019. Web. 01 Oct 2020.

Vancouver:

Fang C. On-Chip Integrated Nano-Scale Light Sources and Switches for Optical Interconnect. [Internet] [Thesis]. University of California – San Diego; 2019. [cited 2020 Oct 01]. Available from: http://www.escholarship.org/uc/item/23m805w0.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fang C. On-Chip Integrated Nano-Scale Light Sources and Switches for Optical Interconnect. [Thesis]. University of California – San Diego; 2019. Available from: http://www.escholarship.org/uc/item/23m805w0

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

30. Yasotharan, Sanjesh. A Microfluidic Platform for the Automated Multimodal Assessment of Small Artery Structure and Function.

Degree: 2012, University of Toronto

In this thesis, I present a microfluidic platform that enables automated image-based assessment of biological structure and function. My work focuses on assessing intact resistance… (more)

Subjects/Keywords: Microfluidics; Resistance Artery; Automation; World to chip interconnect; 0548; 0541

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yasotharan, S. (2012). A Microfluidic Platform for the Automated Multimodal Assessment of Small Artery Structure and Function. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/32504

Chicago Manual of Style (16th Edition):

Yasotharan, Sanjesh. “A Microfluidic Platform for the Automated Multimodal Assessment of Small Artery Structure and Function.” 2012. Masters Thesis, University of Toronto. Accessed October 01, 2020. http://hdl.handle.net/1807/32504.

MLA Handbook (7th Edition):

Yasotharan, Sanjesh. “A Microfluidic Platform for the Automated Multimodal Assessment of Small Artery Structure and Function.” 2012. Web. 01 Oct 2020.

Vancouver:

Yasotharan S. A Microfluidic Platform for the Automated Multimodal Assessment of Small Artery Structure and Function. [Internet] [Masters thesis]. University of Toronto; 2012. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1807/32504.

Council of Science Editors:

Yasotharan S. A Microfluidic Platform for the Automated Multimodal Assessment of Small Artery Structure and Function. [Masters Thesis]. University of Toronto; 2012. Available from: http://hdl.handle.net/1807/32504

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