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You searched for subject:(Integrated circuits). Showing records 1 – 30 of 1764 total matches.

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University of Utah

1. Lodder, Michael Alan. Biologically motivated predictions for dynamic power in VLSI circuits.

Degree: MS;, Electrical & Computer Engineering;, 2008, University of Utah

 As Very Large Scale Integrated (VLSI) circuits continue to shrink in size and increase in complexity, device design is increasingly power constrained. Currently, engineers must… (more)

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

Lodder, M. A. (2008). Biologically motivated predictions for dynamic power in VLSI circuits. (Masters Thesis). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1552/rec/158

Chicago Manual of Style (16th Edition):

Lodder, Michael Alan. “Biologically motivated predictions for dynamic power in VLSI circuits.” 2008. Masters Thesis, University of Utah. Accessed May 07, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1552/rec/158.

MLA Handbook (7th Edition):

Lodder, Michael Alan. “Biologically motivated predictions for dynamic power in VLSI circuits.” 2008. Web. 07 May 2021.

Vancouver:

Lodder MA. Biologically motivated predictions for dynamic power in VLSI circuits. [Internet] [Masters thesis]. University of Utah; 2008. [cited 2021 May 07]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1552/rec/158.

Council of Science Editors:

Lodder MA. Biologically motivated predictions for dynamic power in VLSI circuits. [Masters Thesis]. University of Utah; 2008. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1552/rec/158

2. Boggs, Ryan. An electro-optical simulation methodology for the analysis of single-event radiation effects in photonic devices.

Degree: 2019, University of Tennessee – Chattanooga

 Photonic integrated circuits (PICs) are devices that transmit and perform operations on optical signals. PICs offer significant benefits compared to conventional electronics, including increased data… (more)

Subjects/Keywords: Integrated optics; Integrated circuits; Photonics

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APA (6th Edition):

Boggs, R. (2019). An electro-optical simulation methodology for the analysis of single-event radiation effects in photonic devices. (Masters Thesis). University of Tennessee – Chattanooga. Retrieved from https://scholar.utc.edu/theses/619

Chicago Manual of Style (16th Edition):

Boggs, Ryan. “An electro-optical simulation methodology for the analysis of single-event radiation effects in photonic devices.” 2019. Masters Thesis, University of Tennessee – Chattanooga. Accessed May 07, 2021. https://scholar.utc.edu/theses/619.

MLA Handbook (7th Edition):

Boggs, Ryan. “An electro-optical simulation methodology for the analysis of single-event radiation effects in photonic devices.” 2019. Web. 07 May 2021.

Vancouver:

Boggs R. An electro-optical simulation methodology for the analysis of single-event radiation effects in photonic devices. [Internet] [Masters thesis]. University of Tennessee – Chattanooga; 2019. [cited 2021 May 07]. Available from: https://scholar.utc.edu/theses/619.

Council of Science Editors:

Boggs R. An electro-optical simulation methodology for the analysis of single-event radiation effects in photonic devices. [Masters Thesis]. University of Tennessee – Chattanooga; 2019. Available from: https://scholar.utc.edu/theses/619


University of Johannesburg

3. Lacquet, Beatrys Margaretha. Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets.

Degree: 2014, University of Johannesburg

M.Ing. (Electrical & Electronic Engineering Science)

Please refer to full text to view abstract

Subjects/Keywords: Integrated circuits; Semiconductors

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APA (6th Edition):

Lacquet, B. M. (2014). Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets. (Thesis). University of Johannesburg. Retrieved from http://hdl.handle.net/10210/12197

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lacquet, Beatrys Margaretha. “Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets.” 2014. Thesis, University of Johannesburg. Accessed May 07, 2021. http://hdl.handle.net/10210/12197.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lacquet, Beatrys Margaretha. “Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets.” 2014. Web. 07 May 2021.

Vancouver:

Lacquet BM. Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets. [Internet] [Thesis]. University of Johannesburg; 2014. [cited 2021 May 07]. Available from: http://hdl.handle.net/10210/12197.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lacquet BM. Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets. [Thesis]. University of Johannesburg; 2014. Available from: http://hdl.handle.net/10210/12197

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Queens University

4. He, Shan. Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis .

Degree: Electrical and Computer Engineering, 2011, Queens University

 Analog circuits that operate with low voltage supply headroom generally suffer from poor linearity performance, poor noise performance, etc. However, with the aggressive scaling of… (more)

Subjects/Keywords: Linearity ; Integrated Circuits

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APA (6th Edition):

He, S. (2011). Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/6746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

He, Shan. “Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis .” 2011. Thesis, Queens University. Accessed May 07, 2021. http://hdl.handle.net/1974/6746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

He, Shan. “Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis .” 2011. Web. 07 May 2021.

Vancouver:

He S. Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis . [Internet] [Thesis]. Queens University; 2011. [cited 2021 May 07]. Available from: http://hdl.handle.net/1974/6746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

He S. Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis . [Thesis]. Queens University; 2011. Available from: http://hdl.handle.net/1974/6746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Latrobe University

5. Radfar, Mohsen. Method to address performance decline due to process, voltage, and temperature variations in integrated circuits.

Degree: PhD, 2013, Latrobe University

Thesis (Ph.D.) - La Trobe University, 2013

Submission note: "A thesis submitted in total fulfilment of the requirements for the degree of Doctor of Philosophy… (more)

Subjects/Keywords: Integrated circuits.; Integrated circuits  – Design and construction.; Low voltage integrated circuits.

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APA (6th Edition):

Radfar, M. (2013). Method to address performance decline due to process, voltage, and temperature variations in integrated circuits. (Doctoral Dissertation). Latrobe University. Retrieved from http://hdl.handle.net/1959.9/513567

Chicago Manual of Style (16th Edition):

Radfar, Mohsen. “Method to address performance decline due to process, voltage, and temperature variations in integrated circuits.” 2013. Doctoral Dissertation, Latrobe University. Accessed May 07, 2021. http://hdl.handle.net/1959.9/513567.

MLA Handbook (7th Edition):

Radfar, Mohsen. “Method to address performance decline due to process, voltage, and temperature variations in integrated circuits.” 2013. Web. 07 May 2021.

Vancouver:

Radfar M. Method to address performance decline due to process, voltage, and temperature variations in integrated circuits. [Internet] [Doctoral dissertation]. Latrobe University; 2013. [cited 2021 May 07]. Available from: http://hdl.handle.net/1959.9/513567.

Council of Science Editors:

Radfar M. Method to address performance decline due to process, voltage, and temperature variations in integrated circuits. [Doctoral Dissertation]. Latrobe University; 2013. Available from: http://hdl.handle.net/1959.9/513567


Ryerson University

6. Al-Obaidy, Furat. IC testing using thermal image based on intelligent classification methods.

Degree: 2016, Ryerson University

 The goal of this thesis is to propose an algorithm which would can locate the defect IC on the PCB during their manufacturing phase based… (more)

Subjects/Keywords: Integrated circuits  – Thermal properties  – Testing  – Thermographic methods; Integrated circuits  – Testing; Integrated circuits  – Fault tolerance; Integrated circuits; Printed circuits  – Testing; Printed circuits

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APA (6th Edition):

Al-Obaidy, F. (2016). IC testing using thermal image based on intelligent classification methods. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A5822

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Al-Obaidy, Furat. “IC testing using thermal image based on intelligent classification methods.” 2016. Thesis, Ryerson University. Accessed May 07, 2021. https://digital.library.ryerson.ca/islandora/object/RULA%3A5822.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Al-Obaidy, Furat. “IC testing using thermal image based on intelligent classification methods.” 2016. Web. 07 May 2021.

Vancouver:

Al-Obaidy F. IC testing using thermal image based on intelligent classification methods. [Internet] [Thesis]. Ryerson University; 2016. [cited 2021 May 07]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5822.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Al-Obaidy F. IC testing using thermal image based on intelligent classification methods. [Thesis]. Ryerson University; 2016. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5822

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

7. Patwary, Md. Ataur R. Low-power dynamic CMOS circuits in high-performance memory arrays.

Degree: PhD, Electrical and Computer Engineering, 2009, Oregon State University

 Dynamic CMOS circuits are commonly used in high-performance memory arrays to implement wide-NOR logic functions for their read and search operations. This is because dynamic… (more)

Subjects/Keywords: Dynamic circuits; Low voltage integrated circuits

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APA (6th Edition):

Patwary, M. A. R. (2009). Low-power dynamic CMOS circuits in high-performance memory arrays. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/10906

Chicago Manual of Style (16th Edition):

Patwary, Md Ataur R. “Low-power dynamic CMOS circuits in high-performance memory arrays.” 2009. Doctoral Dissertation, Oregon State University. Accessed May 07, 2021. http://hdl.handle.net/1957/10906.

MLA Handbook (7th Edition):

Patwary, Md Ataur R. “Low-power dynamic CMOS circuits in high-performance memory arrays.” 2009. Web. 07 May 2021.

Vancouver:

Patwary MAR. Low-power dynamic CMOS circuits in high-performance memory arrays. [Internet] [Doctoral dissertation]. Oregon State University; 2009. [cited 2021 May 07]. Available from: http://hdl.handle.net/1957/10906.

Council of Science Editors:

Patwary MAR. Low-power dynamic CMOS circuits in high-performance memory arrays. [Doctoral Dissertation]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/10906


Oregon State University

8. Jacob, Michael E. Ultra low capacitance RFIC probe.

Degree: MS, Electrical and Computer Engineering, 2009, Oregon State University

 In Radio Frequency Integrated Circuits (RFIC) or high frequency digital ICs, there is a demand to probe the internal nodes for testing. The ultra low… (more)

Subjects/Keywords: Radio frequency integrated circuits  – Testing

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APA (6th Edition):

Jacob, M. E. (2009). Ultra low capacitance RFIC probe. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/11868

Chicago Manual of Style (16th Edition):

Jacob, Michael E. “Ultra low capacitance RFIC probe.” 2009. Masters Thesis, Oregon State University. Accessed May 07, 2021. http://hdl.handle.net/1957/11868.

MLA Handbook (7th Edition):

Jacob, Michael E. “Ultra low capacitance RFIC probe.” 2009. Web. 07 May 2021.

Vancouver:

Jacob ME. Ultra low capacitance RFIC probe. [Internet] [Masters thesis]. Oregon State University; 2009. [cited 2021 May 07]. Available from: http://hdl.handle.net/1957/11868.

Council of Science Editors:

Jacob ME. Ultra low capacitance RFIC probe. [Masters Thesis]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/11868


Rochester Institute of Technology

9. Ting, Goodwin. An Integrated BiCMOS driver chip for medium power applications.

Degree: Electrical Engineering, 1991, Rochester Institute of Technology

 The development of an integrated driver circuit intended for medium power switching applications is presented. The device contains, on one chip, CMOS digital control logic… (more)

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

Ting, G. (1991). An Integrated BiCMOS driver chip for medium power applications. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/5569

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ting, Goodwin. “An Integrated BiCMOS driver chip for medium power applications.” 1991. Thesis, Rochester Institute of Technology. Accessed May 07, 2021. https://scholarworks.rit.edu/theses/5569.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ting, Goodwin. “An Integrated BiCMOS driver chip for medium power applications.” 1991. Web. 07 May 2021.

Vancouver:

Ting G. An Integrated BiCMOS driver chip for medium power applications. [Internet] [Thesis]. Rochester Institute of Technology; 1991. [cited 2021 May 07]. Available from: https://scholarworks.rit.edu/theses/5569.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ting G. An Integrated BiCMOS driver chip for medium power applications. [Thesis]. Rochester Institute of Technology; 1991. Available from: https://scholarworks.rit.edu/theses/5569

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

10. Price, David T. N-Well CMOS process integration.

Degree: Electrical Engineering, 1992, Rochester Institute of Technology

 The predominant integrated circuit fabrication technologies used for VLSI devices are CMOS, and BiCMOS. The goal of this work was to develop a CMOS process… (more)

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

Price, D. T. (1992). N-Well CMOS process integration. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/5574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Price, David T. “N-Well CMOS process integration.” 1992. Thesis, Rochester Institute of Technology. Accessed May 07, 2021. https://scholarworks.rit.edu/theses/5574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Price, David T. “N-Well CMOS process integration.” 1992. Web. 07 May 2021.

Vancouver:

Price DT. N-Well CMOS process integration. [Internet] [Thesis]. Rochester Institute of Technology; 1992. [cited 2021 May 07]. Available from: https://scholarworks.rit.edu/theses/5574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Price DT. N-Well CMOS process integration. [Thesis]. Rochester Institute of Technology; 1992. Available from: https://scholarworks.rit.edu/theses/5574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

11. Fasang, Patrick Pad, 1941-. Design of a mini-computer controlled digital integrated circuit tester.

Degree: PhD, Electrical and Computer Engineering, 1973, Oregon State University

 The purpose of the thesis is to design, construct, program, and test an automatic integrated circuit test system. The class of integrated circuits tested was… (more)

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

Fasang, Patrick Pad, 1. (1973). Design of a mini-computer controlled digital integrated circuit tester. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/46097

Chicago Manual of Style (16th Edition):

Fasang, Patrick Pad, 1941-. “Design of a mini-computer controlled digital integrated circuit tester.” 1973. Doctoral Dissertation, Oregon State University. Accessed May 07, 2021. http://hdl.handle.net/1957/46097.

MLA Handbook (7th Edition):

Fasang, Patrick Pad, 1941-. “Design of a mini-computer controlled digital integrated circuit tester.” 1973. Web. 07 May 2021.

Vancouver:

Fasang, Patrick Pad 1. Design of a mini-computer controlled digital integrated circuit tester. [Internet] [Doctoral dissertation]. Oregon State University; 1973. [cited 2021 May 07]. Available from: http://hdl.handle.net/1957/46097.

Council of Science Editors:

Fasang, Patrick Pad 1. Design of a mini-computer controlled digital integrated circuit tester. [Doctoral Dissertation]. Oregon State University; 1973. Available from: http://hdl.handle.net/1957/46097


Oregon State University

12. Kazmi, Saeed A. Integrated injection logic alarm system.

Degree: MS, Electrical Engineering, 1976, Oregon State University

 The object of this work was to design and fabricate an integrated circuit using Integrated Injection Logic. Integrated Injection Logic (I[superscript 2] L) is a… (more)

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

Kazmi, S. A. (1976). Integrated injection logic alarm system. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/43395

Chicago Manual of Style (16th Edition):

Kazmi, Saeed A. “Integrated injection logic alarm system.” 1976. Masters Thesis, Oregon State University. Accessed May 07, 2021. http://hdl.handle.net/1957/43395.

MLA Handbook (7th Edition):

Kazmi, Saeed A. “Integrated injection logic alarm system.” 1976. Web. 07 May 2021.

Vancouver:

Kazmi SA. Integrated injection logic alarm system. [Internet] [Masters thesis]. Oregon State University; 1976. [cited 2021 May 07]. Available from: http://hdl.handle.net/1957/43395.

Council of Science Editors:

Kazmi SA. Integrated injection logic alarm system. [Masters Thesis]. Oregon State University; 1976. Available from: http://hdl.handle.net/1957/43395


Cornell University

13. Lee, Wooram. Nonlinear Circuits For Signal Generation And Processing In Cmos.

Degree: PhD, Electrical Engineering, 2012, Cornell University

 As Moore's law predicted, transistor scaling has continued unabated for more than half a century, resulting in significant improvement in speed, efficiency, and integration level.… (more)

Subjects/Keywords: Integrated Circuits; Nonlinear; cmos

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APA (6th Edition):

Lee, W. (2012). Nonlinear Circuits For Signal Generation And Processing In Cmos. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/31174

Chicago Manual of Style (16th Edition):

Lee, Wooram. “Nonlinear Circuits For Signal Generation And Processing In Cmos.” 2012. Doctoral Dissertation, Cornell University. Accessed May 07, 2021. http://hdl.handle.net/1813/31174.

MLA Handbook (7th Edition):

Lee, Wooram. “Nonlinear Circuits For Signal Generation And Processing In Cmos.” 2012. Web. 07 May 2021.

Vancouver:

Lee W. Nonlinear Circuits For Signal Generation And Processing In Cmos. [Internet] [Doctoral dissertation]. Cornell University; 2012. [cited 2021 May 07]. Available from: http://hdl.handle.net/1813/31174.

Council of Science Editors:

Lee W. Nonlinear Circuits For Signal Generation And Processing In Cmos. [Doctoral Dissertation]. Cornell University; 2012. Available from: http://hdl.handle.net/1813/31174


Texas A&M University

14. Carreon Bautista, Salvador. Power Management Circuits for Energy Harvesting Applications.

Degree: PhD, Electrical Engineering, 2015, Texas A&M University

 Energy harvesting is the process of converting ambient available energy into usable electrical energy. Multiple types of sources are can be used to harness environmental… (more)

Subjects/Keywords: Energy Harvesting; Integrated Circuits

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APA (6th Edition):

Carreon Bautista, S. (2015). Power Management Circuits for Energy Harvesting Applications. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/161667

Chicago Manual of Style (16th Edition):

Carreon Bautista, Salvador. “Power Management Circuits for Energy Harvesting Applications.” 2015. Doctoral Dissertation, Texas A&M University. Accessed May 07, 2021. http://hdl.handle.net/1969.1/161667.

MLA Handbook (7th Edition):

Carreon Bautista, Salvador. “Power Management Circuits for Energy Harvesting Applications.” 2015. Web. 07 May 2021.

Vancouver:

Carreon Bautista S. Power Management Circuits for Energy Harvesting Applications. [Internet] [Doctoral dissertation]. Texas A&M University; 2015. [cited 2021 May 07]. Available from: http://hdl.handle.net/1969.1/161667.

Council of Science Editors:

Carreon Bautista S. Power Management Circuits for Energy Harvesting Applications. [Doctoral Dissertation]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/161667


Oregon State University

15. Young, David Y. W. Current-feedthrough cancellation technique for current-mode T/H circuits: Clock-feedthrough cancellation technique for current-mode T/H circuits.

Degree: MS, Electrical and Computer Engineering, 1991, Oregon State University

 In this paper, an analysis of the clock-feedthrough effects in switched-current (SI)' circuits will be presented. The clock-feedthrough effects caused by the non-ideal characteristic of… (more)

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

Young, D. Y. W. (1991). Current-feedthrough cancellation technique for current-mode T/H circuits: Clock-feedthrough cancellation technique for current-mode T/H circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37409

Chicago Manual of Style (16th Edition):

Young, David Y W. “Current-feedthrough cancellation technique for current-mode T/H circuits: Clock-feedthrough cancellation technique for current-mode T/H circuits.” 1991. Masters Thesis, Oregon State University. Accessed May 07, 2021. http://hdl.handle.net/1957/37409.

MLA Handbook (7th Edition):

Young, David Y W. “Current-feedthrough cancellation technique for current-mode T/H circuits: Clock-feedthrough cancellation technique for current-mode T/H circuits.” 1991. Web. 07 May 2021.

Vancouver:

Young DYW. Current-feedthrough cancellation technique for current-mode T/H circuits: Clock-feedthrough cancellation technique for current-mode T/H circuits. [Internet] [Masters thesis]. Oregon State University; 1991. [cited 2021 May 07]. Available from: http://hdl.handle.net/1957/37409.

Council of Science Editors:

Young DYW. Current-feedthrough cancellation technique for current-mode T/H circuits: Clock-feedthrough cancellation technique for current-mode T/H circuits. [Masters Thesis]. Oregon State University; 1991. Available from: http://hdl.handle.net/1957/37409


University of Delaware

16. Yang, Yisu. Toward non-reciprocal chip-scale silicon photonics.

Degree: D.Eng., University of Delaware, Department of Electrical and Computer Engineering, 2015, University of Delaware

 A critical problem in modern photonics is the optical isolation. An optical isolator allows light to pass through in one direction but blocks it in… (more)

Subjects/Keywords: Photonics.; Silicon.; Integrated circuits.

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APA (6th Edition):

Yang, Y. (2015). Toward non-reciprocal chip-scale silicon photonics. (Doctoral Dissertation). University of Delaware. Retrieved from http://udspace.udel.edu/handle/19716/17422

Chicago Manual of Style (16th Edition):

Yang, Yisu. “Toward non-reciprocal chip-scale silicon photonics.” 2015. Doctoral Dissertation, University of Delaware. Accessed May 07, 2021. http://udspace.udel.edu/handle/19716/17422.

MLA Handbook (7th Edition):

Yang, Yisu. “Toward non-reciprocal chip-scale silicon photonics.” 2015. Web. 07 May 2021.

Vancouver:

Yang Y. Toward non-reciprocal chip-scale silicon photonics. [Internet] [Doctoral dissertation]. University of Delaware; 2015. [cited 2021 May 07]. Available from: http://udspace.udel.edu/handle/19716/17422.

Council of Science Editors:

Yang Y. Toward non-reciprocal chip-scale silicon photonics. [Doctoral Dissertation]. University of Delaware; 2015. Available from: http://udspace.udel.edu/handle/19716/17422


Columbia University

17. Kim, Seongjong. Variation-Tolerant and Voltage-Scalable Integrated Circuits Design.

Degree: 2016, Columbia University

 Ultra-low-voltage (ULV) operation where the supply voltage of the digital computing hardware is scaled down to the level near or below transistor threshold voltage (e.g.… (more)

Subjects/Keywords: Integrated circuits – Design and construction; Electrical engineering; Digital integrated circuits; Digital integrated circuits – Design and construction; Integrated circuits

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APA (6th Edition):

Kim, S. (2016). Variation-Tolerant and Voltage-Scalable Integrated Circuits Design. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D8TM7BPF

Chicago Manual of Style (16th Edition):

Kim, Seongjong. “Variation-Tolerant and Voltage-Scalable Integrated Circuits Design.” 2016. Doctoral Dissertation, Columbia University. Accessed May 07, 2021. https://doi.org/10.7916/D8TM7BPF.

MLA Handbook (7th Edition):

Kim, Seongjong. “Variation-Tolerant and Voltage-Scalable Integrated Circuits Design.” 2016. Web. 07 May 2021.

Vancouver:

Kim S. Variation-Tolerant and Voltage-Scalable Integrated Circuits Design. [Internet] [Doctoral dissertation]. Columbia University; 2016. [cited 2021 May 07]. Available from: https://doi.org/10.7916/D8TM7BPF.

Council of Science Editors:

Kim S. Variation-Tolerant and Voltage-Scalable Integrated Circuits Design. [Doctoral Dissertation]. Columbia University; 2016. Available from: https://doi.org/10.7916/D8TM7BPF

18. Pourbakhsh, Seyed Alireza. Dummy TSV-Based Timing Optimization for 3D On-Chip Memory.

Degree: 2016, North Dakota State University

 Design and fabrication of three-dimensional (3D) ICs is one the newest and hottest trends in semiconductor manufacturing industry. In 3D ICs, multiple 2D silicon dies… (more)

Subjects/Keywords: Three-dimensional integrated circuits.

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APA (6th Edition):

Pourbakhsh, S. A. (2016). Dummy TSV-Based Timing Optimization for 3D On-Chip Memory. (Thesis). North Dakota State University. Retrieved from http://hdl.handle.net/10365/29093

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pourbakhsh, Seyed Alireza. “Dummy TSV-Based Timing Optimization for 3D On-Chip Memory.” 2016. Thesis, North Dakota State University. Accessed May 07, 2021. http://hdl.handle.net/10365/29093.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pourbakhsh, Seyed Alireza. “Dummy TSV-Based Timing Optimization for 3D On-Chip Memory.” 2016. Web. 07 May 2021.

Vancouver:

Pourbakhsh SA. Dummy TSV-Based Timing Optimization for 3D On-Chip Memory. [Internet] [Thesis]. North Dakota State University; 2016. [cited 2021 May 07]. Available from: http://hdl.handle.net/10365/29093.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pourbakhsh SA. Dummy TSV-Based Timing Optimization for 3D On-Chip Memory. [Thesis]. North Dakota State University; 2016. Available from: http://hdl.handle.net/10365/29093

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Michigan State University

19. Huang, Chi-Jung. Compact non-quasi-static MOSFET device model.

Degree: MS, Department of Electrical Engineering and System Science, 1988, Michigan State University

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

Huang, C. (1988). Compact non-quasi-static MOSFET device model. (Masters Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:20222

Chicago Manual of Style (16th Edition):

Huang, Chi-Jung. “Compact non-quasi-static MOSFET device model.” 1988. Masters Thesis, Michigan State University. Accessed May 07, 2021. http://etd.lib.msu.edu/islandora/object/etd:20222.

MLA Handbook (7th Edition):

Huang, Chi-Jung. “Compact non-quasi-static MOSFET device model.” 1988. Web. 07 May 2021.

Vancouver:

Huang C. Compact non-quasi-static MOSFET device model. [Internet] [Masters thesis]. Michigan State University; 1988. [cited 2021 May 07]. Available from: http://etd.lib.msu.edu/islandora/object/etd:20222.

Council of Science Editors:

Huang C. Compact non-quasi-static MOSFET device model. [Masters Thesis]. Michigan State University; 1988. Available from: http://etd.lib.msu.edu/islandora/object/etd:20222


University of Toronto

20. Sun, Xiao. Augmented Low Index Guiding and Hybrid Plasmonic Waveguides: Properties and Applications for On-chip Polarization Management.

Degree: PhD, 2018, University of Toronto

 In recent years, photonic integrated circuits (PICs) have attracted much interest. To achieve a compact size, most recent devices are based on the high index… (more)

Subjects/Keywords: Photonics Integrated Circuits; 0752

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APA (6th Edition):

Sun, X. (2018). Augmented Low Index Guiding and Hybrid Plasmonic Waveguides: Properties and Applications for On-chip Polarization Management. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/89675

Chicago Manual of Style (16th Edition):

Sun, Xiao. “Augmented Low Index Guiding and Hybrid Plasmonic Waveguides: Properties and Applications for On-chip Polarization Management.” 2018. Doctoral Dissertation, University of Toronto. Accessed May 07, 2021. http://hdl.handle.net/1807/89675.

MLA Handbook (7th Edition):

Sun, Xiao. “Augmented Low Index Guiding and Hybrid Plasmonic Waveguides: Properties and Applications for On-chip Polarization Management.” 2018. Web. 07 May 2021.

Vancouver:

Sun X. Augmented Low Index Guiding and Hybrid Plasmonic Waveguides: Properties and Applications for On-chip Polarization Management. [Internet] [Doctoral dissertation]. University of Toronto; 2018. [cited 2021 May 07]. Available from: http://hdl.handle.net/1807/89675.

Council of Science Editors:

Sun X. Augmented Low Index Guiding and Hybrid Plasmonic Waveguides: Properties and Applications for On-chip Polarization Management. [Doctoral Dissertation]. University of Toronto; 2018. Available from: http://hdl.handle.net/1807/89675


Texas Tech University

21. Karmokolias, Constantine. Optimal design of the fabrication parameters of integrated circuits.

Degree: Electrical and Computer Engineering, 1975, Texas Tech University

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

Karmokolias, C. (1975). Optimal design of the fabrication parameters of integrated circuits. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/16206

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Karmokolias, Constantine. “Optimal design of the fabrication parameters of integrated circuits.” 1975. Thesis, Texas Tech University. Accessed May 07, 2021. http://hdl.handle.net/2346/16206.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Karmokolias, Constantine. “Optimal design of the fabrication parameters of integrated circuits.” 1975. Web. 07 May 2021.

Vancouver:

Karmokolias C. Optimal design of the fabrication parameters of integrated circuits. [Internet] [Thesis]. Texas Tech University; 1975. [cited 2021 May 07]. Available from: http://hdl.handle.net/2346/16206.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Karmokolias C. Optimal design of the fabrication parameters of integrated circuits. [Thesis]. Texas Tech University; 1975. Available from: http://hdl.handle.net/2346/16206

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arizona

22. Leone, Ronald Alphonse, 1946-. Investigation of neuristor biasing using pinch resistors .

Degree: 1969, University of Arizona

Subjects/Keywords: Integrated circuits.

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APA (6th Edition):

Leone, Ronald Alphonse, 1. (1969). Investigation of neuristor biasing using pinch resistors . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/318188

Chicago Manual of Style (16th Edition):

Leone, Ronald Alphonse, 1946-. “Investigation of neuristor biasing using pinch resistors .” 1969. Masters Thesis, University of Arizona. Accessed May 07, 2021. http://hdl.handle.net/10150/318188.

MLA Handbook (7th Edition):

Leone, Ronald Alphonse, 1946-. “Investigation of neuristor biasing using pinch resistors .” 1969. Web. 07 May 2021.

Vancouver:

Leone, Ronald Alphonse 1. Investigation of neuristor biasing using pinch resistors . [Internet] [Masters thesis]. University of Arizona; 1969. [cited 2021 May 07]. Available from: http://hdl.handle.net/10150/318188.

Council of Science Editors:

Leone, Ronald Alphonse 1. Investigation of neuristor biasing using pinch resistors . [Masters Thesis]. University of Arizona; 1969. Available from: http://hdl.handle.net/10150/318188


University of Arizona

23. Sonu, Gene Ho, 1948-. Computer aided design of a second-order state variable network .

Degree: 1974, University of Arizona

Subjects/Keywords: Integrated circuits.

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APA (6th Edition):

Sonu, Gene Ho, 1. (1974). Computer aided design of a second-order state variable network . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/554671

Chicago Manual of Style (16th Edition):

Sonu, Gene Ho, 1948-. “Computer aided design of a second-order state variable network .” 1974. Masters Thesis, University of Arizona. Accessed May 07, 2021. http://hdl.handle.net/10150/554671.

MLA Handbook (7th Edition):

Sonu, Gene Ho, 1948-. “Computer aided design of a second-order state variable network .” 1974. Web. 07 May 2021.

Vancouver:

Sonu, Gene Ho 1. Computer aided design of a second-order state variable network . [Internet] [Masters thesis]. University of Arizona; 1974. [cited 2021 May 07]. Available from: http://hdl.handle.net/10150/554671.

Council of Science Editors:

Sonu, Gene Ho 1. Computer aided design of a second-order state variable network . [Masters Thesis]. University of Arizona; 1974. Available from: http://hdl.handle.net/10150/554671


University of Hong Kong

24. 黃冠翔. Electromagnetic compatibility modeling for integrated circuits.

Degree: 2014, University of Hong Kong

 The integrated circuit (IC) packaging electromagnetic compatibility (EMC)/signal integrity (SI)/power integrity (PI) problems have been broadly attested. But IC packaging electromagnetic interference (EMI) was seldom… (more)

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

黃冠翔. (2014). Electromagnetic compatibility modeling for integrated circuits. (Thesis). University of Hong Kong. Retrieved from http://hdl.handle.net/10722/206335

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

黃冠翔. “Electromagnetic compatibility modeling for integrated circuits.” 2014. Thesis, University of Hong Kong. Accessed May 07, 2021. http://hdl.handle.net/10722/206335.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

黃冠翔. “Electromagnetic compatibility modeling for integrated circuits.” 2014. Web. 07 May 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

黃冠翔. Electromagnetic compatibility modeling for integrated circuits. [Internet] [Thesis]. University of Hong Kong; 2014. [cited 2021 May 07]. Available from: http://hdl.handle.net/10722/206335.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

黃冠翔. Electromagnetic compatibility modeling for integrated circuits. [Thesis]. University of Hong Kong; 2014. Available from: http://hdl.handle.net/10722/206335

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation


University of Arizona

25. Wells, Victor Allyn, 1940-. INVESTIGATION OF CHEMICAL VAPOR DEPOSITION PROCESSES FOR INTEGRATED CIRCUIT FABRICATION .

Degree: 1972, University of Arizona

Subjects/Keywords: Integrated circuits.

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APA (6th Edition):

Wells, Victor Allyn, 1. (1972). INVESTIGATION OF CHEMICAL VAPOR DEPOSITION PROCESSES FOR INTEGRATED CIRCUIT FABRICATION . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/287825

Chicago Manual of Style (16th Edition):

Wells, Victor Allyn, 1940-. “INVESTIGATION OF CHEMICAL VAPOR DEPOSITION PROCESSES FOR INTEGRATED CIRCUIT FABRICATION .” 1972. Doctoral Dissertation, University of Arizona. Accessed May 07, 2021. http://hdl.handle.net/10150/287825.

MLA Handbook (7th Edition):

Wells, Victor Allyn, 1940-. “INVESTIGATION OF CHEMICAL VAPOR DEPOSITION PROCESSES FOR INTEGRATED CIRCUIT FABRICATION .” 1972. Web. 07 May 2021.

Vancouver:

Wells, Victor Allyn 1. INVESTIGATION OF CHEMICAL VAPOR DEPOSITION PROCESSES FOR INTEGRATED CIRCUIT FABRICATION . [Internet] [Doctoral dissertation]. University of Arizona; 1972. [cited 2021 May 07]. Available from: http://hdl.handle.net/10150/287825.

Council of Science Editors:

Wells, Victor Allyn 1. INVESTIGATION OF CHEMICAL VAPOR DEPOSITION PROCESSES FOR INTEGRATED CIRCUIT FABRICATION . [Doctoral Dissertation]. University of Arizona; 1972. Available from: http://hdl.handle.net/10150/287825


University of Arizona

26. Ochoa, Agustin, 1949-. COMPOSITE BIPOLAR AND FIELD EFFECT CARRIER DOMAIN DEVICES .

Degree: 1977, University of Arizona

Subjects/Keywords: Integrated circuits.

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APA (6th Edition):

Ochoa, Agustin, 1. (1977). COMPOSITE BIPOLAR AND FIELD EFFECT CARRIER DOMAIN DEVICES . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/289615

Chicago Manual of Style (16th Edition):

Ochoa, Agustin, 1949-. “COMPOSITE BIPOLAR AND FIELD EFFECT CARRIER DOMAIN DEVICES .” 1977. Doctoral Dissertation, University of Arizona. Accessed May 07, 2021. http://hdl.handle.net/10150/289615.

MLA Handbook (7th Edition):

Ochoa, Agustin, 1949-. “COMPOSITE BIPOLAR AND FIELD EFFECT CARRIER DOMAIN DEVICES .” 1977. Web. 07 May 2021.

Vancouver:

Ochoa, Agustin 1. COMPOSITE BIPOLAR AND FIELD EFFECT CARRIER DOMAIN DEVICES . [Internet] [Doctoral dissertation]. University of Arizona; 1977. [cited 2021 May 07]. Available from: http://hdl.handle.net/10150/289615.

Council of Science Editors:

Ochoa, Agustin 1. COMPOSITE BIPOLAR AND FIELD EFFECT CARRIER DOMAIN DEVICES . [Doctoral Dissertation]. University of Arizona; 1977. Available from: http://hdl.handle.net/10150/289615


Georgia Tech

27. Chi, Taiyun. Millimeter-wave and terahertz signal generation and detection in silicon.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 Millimeter-wave (mm-wave) and Terahertz (THz) frequency range is generally defined as frequencies between 30GHz to 3THz. With the recent advancement in mm-wave/THz technologies, it has… (more)

Subjects/Keywords: Millimeter-wave; Terahertz; Integrated circuits

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APA (6th Edition):

Chi, T. (2017). Millimeter-wave and terahertz signal generation and detection in silicon. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/60709

Chicago Manual of Style (16th Edition):

Chi, Taiyun. “Millimeter-wave and terahertz signal generation and detection in silicon.” 2017. Doctoral Dissertation, Georgia Tech. Accessed May 07, 2021. http://hdl.handle.net/1853/60709.

MLA Handbook (7th Edition):

Chi, Taiyun. “Millimeter-wave and terahertz signal generation and detection in silicon.” 2017. Web. 07 May 2021.

Vancouver:

Chi T. Millimeter-wave and terahertz signal generation and detection in silicon. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2021 May 07]. Available from: http://hdl.handle.net/1853/60709.

Council of Science Editors:

Chi T. Millimeter-wave and terahertz signal generation and detection in silicon. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/60709


Rutgers University

28. Zhang, Xiaobing, 1991-. Simulation and optimization of thermo-fluid systems: microchannel cooling and other applications.

Degree: PhD, Mechanical and Aerospace Engineering, 2020, Rutgers University

Microchannel systems for cooling applications such as in thermal management of electronic equipment are investigated and optimized under deterministic and reliability conditions. Numerical simulations are… (more)

Subjects/Keywords: Reliability; Integrated circuits  – Cooling

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APA (6th Edition):

Zhang, Xiaobing, 1. (2020). Simulation and optimization of thermo-fluid systems: microchannel cooling and other applications. (Doctoral Dissertation). Rutgers University. Retrieved from https://rucore.libraries.rutgers.edu/rutgers-lib/62978/

Chicago Manual of Style (16th Edition):

Zhang, Xiaobing, 1991-. “Simulation and optimization of thermo-fluid systems: microchannel cooling and other applications.” 2020. Doctoral Dissertation, Rutgers University. Accessed May 07, 2021. https://rucore.libraries.rutgers.edu/rutgers-lib/62978/.

MLA Handbook (7th Edition):

Zhang, Xiaobing, 1991-. “Simulation and optimization of thermo-fluid systems: microchannel cooling and other applications.” 2020. Web. 07 May 2021.

Vancouver:

Zhang, Xiaobing 1. Simulation and optimization of thermo-fluid systems: microchannel cooling and other applications. [Internet] [Doctoral dissertation]. Rutgers University; 2020. [cited 2021 May 07]. Available from: https://rucore.libraries.rutgers.edu/rutgers-lib/62978/.

Council of Science Editors:

Zhang, Xiaobing 1. Simulation and optimization of thermo-fluid systems: microchannel cooling and other applications. [Doctoral Dissertation]. Rutgers University; 2020. Available from: https://rucore.libraries.rutgers.edu/rutgers-lib/62978/


Rutgers University

29. Venkatanarayanan, Hari Vijay. Jitter reduction circuits to reduce the bit-error rate of high-speed serializer-deserializer (SERDES) circuits.

Degree: PhD, Electrical and Computer Engineering, 2008, Rutgers University

A new jitter reduction technique is proposed for reducing the timing jitter in a serializer-deserializer (SERDES) circuit. The technique involves transmit and receive side jitter… (more)

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

Venkatanarayanan, H. V. (2008). Jitter reduction circuits to reduce the bit-error rate of high-speed serializer-deserializer (SERDES) circuits. (Doctoral Dissertation). Rutgers University. Retrieved from http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17259

Chicago Manual of Style (16th Edition):

Venkatanarayanan, Hari Vijay. “Jitter reduction circuits to reduce the bit-error rate of high-speed serializer-deserializer (SERDES) circuits.” 2008. Doctoral Dissertation, Rutgers University. Accessed May 07, 2021. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17259.

MLA Handbook (7th Edition):

Venkatanarayanan, Hari Vijay. “Jitter reduction circuits to reduce the bit-error rate of high-speed serializer-deserializer (SERDES) circuits.” 2008. Web. 07 May 2021.

Vancouver:

Venkatanarayanan HV. Jitter reduction circuits to reduce the bit-error rate of high-speed serializer-deserializer (SERDES) circuits. [Internet] [Doctoral dissertation]. Rutgers University; 2008. [cited 2021 May 07]. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17259.

Council of Science Editors:

Venkatanarayanan HV. Jitter reduction circuits to reduce the bit-error rate of high-speed serializer-deserializer (SERDES) circuits. [Doctoral Dissertation]. Rutgers University; 2008. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17259


University of Aberdeen

30. Cao, Zhang. The legal issues of interconnection in Chinese telecommunications.

Degree: PhD, 2012, University of Aberdeen

 China does not comply with its WTO obligations except in principle and experiences the problem that the incumbent carrier may use technical and commercial mechanisms… (more)

Subjects/Keywords: 384.0951; Telecommunication; Competition; Integrated circuits

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APA (6th Edition):

Cao, Z. (2012). The legal issues of interconnection in Chinese telecommunications. (Doctoral Dissertation). University of Aberdeen. Retrieved from https://abdn.alma.exlibrisgroup.com/discovery/delivery/44ABE_INST:44ABE_VU1/12153109470005941 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.558610

Chicago Manual of Style (16th Edition):

Cao, Zhang. “The legal issues of interconnection in Chinese telecommunications.” 2012. Doctoral Dissertation, University of Aberdeen. Accessed May 07, 2021. https://abdn.alma.exlibrisgroup.com/discovery/delivery/44ABE_INST:44ABE_VU1/12153109470005941 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.558610.

MLA Handbook (7th Edition):

Cao, Zhang. “The legal issues of interconnection in Chinese telecommunications.” 2012. Web. 07 May 2021.

Vancouver:

Cao Z. The legal issues of interconnection in Chinese telecommunications. [Internet] [Doctoral dissertation]. University of Aberdeen; 2012. [cited 2021 May 07]. Available from: https://abdn.alma.exlibrisgroup.com/discovery/delivery/44ABE_INST:44ABE_VU1/12153109470005941 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.558610.

Council of Science Editors:

Cao Z. The legal issues of interconnection in Chinese telecommunications. [Doctoral Dissertation]. University of Aberdeen; 2012. Available from: https://abdn.alma.exlibrisgroup.com/discovery/delivery/44ABE_INST:44ABE_VU1/12153109470005941 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.558610

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