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You searched for subject:(Integrated circuits Very large scale integration Design AND construction Computer simulation). Showing records 1 – 30 of 4524 total matches.

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Portland State University

1. Park, Hoon. Formal Modeling and Verification of Delay-Insensitive Circuits.

Degree: PhD, Electrical and Computer Engineering, 2015, Portland State University

  Einstein's relativity theory tells us that the notion of simultaneity can only be approximated for events distributed over space. As a result, the use… (more)

Subjects/Keywords: Asynchronous circuits  – Design and construction; Integrated circuits  – Very large scale integration  – Design and construction; Digital Circuits; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, H. (2015). Formal Modeling and Verification of Delay-Insensitive Circuits. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/2639

Chicago Manual of Style (16th Edition):

Park, Hoon. “Formal Modeling and Verification of Delay-Insensitive Circuits.” 2015. Doctoral Dissertation, Portland State University. Accessed December 12, 2019. https://pdxscholar.library.pdx.edu/open_access_etds/2639.

MLA Handbook (7th Edition):

Park, Hoon. “Formal Modeling and Verification of Delay-Insensitive Circuits.” 2015. Web. 12 Dec 2019.

Vancouver:

Park H. Formal Modeling and Verification of Delay-Insensitive Circuits. [Internet] [Doctoral dissertation]. Portland State University; 2015. [cited 2019 Dec 12]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/2639.

Council of Science Editors:

Park H. Formal Modeling and Verification of Delay-Insensitive Circuits. [Doctoral Dissertation]. Portland State University; 2015. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/2639


Massey University

2. Alam, Sadia. Modelling, analysis and design of bioelectronic circuits in VLSI.

Degree: PhD, Electronics and Computer Engineering, 2015, Massey University

 Biological phenomena at the molecular level are being imitated by electronic circuits. The immense effectiveness and versatility of bioelectronic circuits have yielded multiple benefits to… (more)

Subjects/Keywords: Integrated circuits; Very large scale integration; Design and construction; Bioelectronics

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APA (6th Edition):

Alam, S. (2015). Modelling, analysis and design of bioelectronic circuits in VLSI. (Doctoral Dissertation). Massey University. Retrieved from http://hdl.handle.net/10179/7731

Chicago Manual of Style (16th Edition):

Alam, Sadia. “Modelling, analysis and design of bioelectronic circuits in VLSI.” 2015. Doctoral Dissertation, Massey University. Accessed December 12, 2019. http://hdl.handle.net/10179/7731.

MLA Handbook (7th Edition):

Alam, Sadia. “Modelling, analysis and design of bioelectronic circuits in VLSI.” 2015. Web. 12 Dec 2019.

Vancouver:

Alam S. Modelling, analysis and design of bioelectronic circuits in VLSI. [Internet] [Doctoral dissertation]. Massey University; 2015. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/10179/7731.

Council of Science Editors:

Alam S. Modelling, analysis and design of bioelectronic circuits in VLSI. [Doctoral Dissertation]. Massey University; 2015. Available from: http://hdl.handle.net/10179/7731


Portland State University

3. Goshi, Sudheer. Digital Fabric.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2012, Portland State University

  Continuing advances with VLSI have enabled engineers to build high performance computer systems to solve complex problems. The real-world problems and tasks like pattern… (more)

Subjects/Keywords: Neuromorphics; Inter-chip communication; Address event representation; Integrated circuits  – Very large scale integration  – Design and construction; Cognition  – Computer simulation; Neural networks (Computer science)  – Design and construction; Electrical and Computer Engineering

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APA (6th Edition):

Goshi, S. (2012). Digital Fabric. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/115

Chicago Manual of Style (16th Edition):

Goshi, Sudheer. “Digital Fabric.” 2012. Masters Thesis, Portland State University. Accessed December 12, 2019. https://pdxscholar.library.pdx.edu/open_access_etds/115.

MLA Handbook (7th Edition):

Goshi, Sudheer. “Digital Fabric.” 2012. Web. 12 Dec 2019.

Vancouver:

Goshi S. Digital Fabric. [Internet] [Masters thesis]. Portland State University; 2012. [cited 2019 Dec 12]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/115.

Council of Science Editors:

Goshi S. Digital Fabric. [Masters Thesis]. Portland State University; 2012. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/115


Oregon State University

4. Li, Qingwei. Efficient VLSI architectures for MIMO and cryptography systems.

Degree: PhD, Electrical and Computer Engineering, 2008, Oregon State University

 Multiple-input multiple-output (MIMO) communication systems have recently been considered as one of the most significant technology breakthroughs for modern wireless communications, due to the higher… (more)

Subjects/Keywords: VLSI; Integrated circuits  – Very large scale integration  – Design and construction  – Mathematical models

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APA (6th Edition):

Li, Q. (2008). Efficient VLSI architectures for MIMO and cryptography systems. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/7521

Chicago Manual of Style (16th Edition):

Li, Qingwei. “Efficient VLSI architectures for MIMO and cryptography systems.” 2008. Doctoral Dissertation, Oregon State University. Accessed December 12, 2019. http://hdl.handle.net/1957/7521.

MLA Handbook (7th Edition):

Li, Qingwei. “Efficient VLSI architectures for MIMO and cryptography systems.” 2008. Web. 12 Dec 2019.

Vancouver:

Li Q. Efficient VLSI architectures for MIMO and cryptography systems. [Internet] [Doctoral dissertation]. Oregon State University; 2008. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/1957/7521.

Council of Science Editors:

Li Q. Efficient VLSI architectures for MIMO and cryptography systems. [Doctoral Dissertation]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/7521


Portland State University

5. Nain, Rajeev Kumar. Floorplan Design and Yield Enhancement of 3-D Integrated Circuits.

Degree: PhD, Electrical and Computer Engineering, 2011, Portland State University

  We have developed a placement-aware 3-D floorplanning algorithm that enables additional wirelength reduction by planning for 3-D placement of logic gates in selected circuit… (more)

Subjects/Keywords: Three-dimensional integrated circuits  – Design and construction; Integrated circuits  – Very large scale integration  – Computer-aided design; Semiconductor industry  – Technological innovations; Computer Sciences; Electrical and Computer Engineering

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APA (6th Edition):

Nain, R. K. (2011). Floorplan Design and Yield Enhancement of 3-D Integrated Circuits. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/2810

Chicago Manual of Style (16th Edition):

Nain, Rajeev Kumar. “Floorplan Design and Yield Enhancement of 3-D Integrated Circuits.” 2011. Doctoral Dissertation, Portland State University. Accessed December 12, 2019. https://pdxscholar.library.pdx.edu/open_access_etds/2810.

MLA Handbook (7th Edition):

Nain, Rajeev Kumar. “Floorplan Design and Yield Enhancement of 3-D Integrated Circuits.” 2011. Web. 12 Dec 2019.

Vancouver:

Nain RK. Floorplan Design and Yield Enhancement of 3-D Integrated Circuits. [Internet] [Doctoral dissertation]. Portland State University; 2011. [cited 2019 Dec 12]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/2810.

Council of Science Editors:

Nain RK. Floorplan Design and Yield Enhancement of 3-D Integrated Circuits. [Doctoral Dissertation]. Portland State University; 2011. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/2810


Hong Kong University of Science and Technology

6. Liu, Feng. Lifetime maximization through adaptive power allocation in reconfigurable system design for wireless systems.

Degree: 2009, Hong Kong University of Science and Technology

 The recent advances in technologies including wireless communications, VLSI design, and multimedia processing, have offered much stronger processing and communication capabilities to wireless devices and… (more)

Subjects/Keywords: Wireless communication systems  – Design and construction; Wireless communication systems  – Energy conservation; Integrated circuits  – Very large scale integration  – Design and construction

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APA (6th Edition):

Liu, F. (2009). Lifetime maximization through adaptive power allocation in reconfigurable system design for wireless systems. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1070122 ; http://repository.ust.hk/ir/bitstream/1783.1-6354/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Feng. “Lifetime maximization through adaptive power allocation in reconfigurable system design for wireless systems.” 2009. Thesis, Hong Kong University of Science and Technology. Accessed December 12, 2019. https://doi.org/10.14711/thesis-b1070122 ; http://repository.ust.hk/ir/bitstream/1783.1-6354/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Feng. “Lifetime maximization through adaptive power allocation in reconfigurable system design for wireless systems.” 2009. Web. 12 Dec 2019.

Vancouver:

Liu F. Lifetime maximization through adaptive power allocation in reconfigurable system design for wireless systems. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2009. [cited 2019 Dec 12]. Available from: https://doi.org/10.14711/thesis-b1070122 ; http://repository.ust.hk/ir/bitstream/1783.1-6354/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu F. Lifetime maximization through adaptive power allocation in reconfigurable system design for wireless systems. [Thesis]. Hong Kong University of Science and Technology; 2009. Available from: https://doi.org/10.14711/thesis-b1070122 ; http://repository.ust.hk/ir/bitstream/1783.1-6354/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Hong Kong

7. 高雲龍; Ko, Wan-lung. A new optimization model for VLSI placement.

Degree: M. Phil., 1998, University of Hong Kong

published_or_final_version

toc

abstract

Electrical and Electronic Engineering

Master

Master of Philosophy

Subjects/Keywords: Integrated circuits - Very large scale integration - Design and construction.

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APA (6th Edition):

高雲龍; Ko, W. (1998). A new optimization model for VLSI placement. (Masters Thesis). University of Hong Kong. Retrieved from Ko, W. [高雲龍]. (1998). A new optimization model for VLSI placement. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b2981293 ; http://dx.doi.org/10.5353/th_b2981293 ; http://hdl.handle.net/10722/31758

Chicago Manual of Style (16th Edition):

高雲龍; Ko, Wan-lung. “A new optimization model for VLSI placement.” 1998. Masters Thesis, University of Hong Kong. Accessed December 12, 2019. Ko, W. [高雲龍]. (1998). A new optimization model for VLSI placement. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b2981293 ; http://dx.doi.org/10.5353/th_b2981293 ; http://hdl.handle.net/10722/31758.

MLA Handbook (7th Edition):

高雲龍; Ko, Wan-lung. “A new optimization model for VLSI placement.” 1998. Web. 12 Dec 2019.

Vancouver:

高雲龍; Ko W. A new optimization model for VLSI placement. [Internet] [Masters thesis]. University of Hong Kong; 1998. [cited 2019 Dec 12]. Available from: Ko, W. [高雲龍]. (1998). A new optimization model for VLSI placement. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b2981293 ; http://dx.doi.org/10.5353/th_b2981293 ; http://hdl.handle.net/10722/31758.

Council of Science Editors:

高雲龍; Ko W. A new optimization model for VLSI placement. [Masters Thesis]. University of Hong Kong; 1998. Available from: Ko, W. [高雲龍]. (1998). A new optimization model for VLSI placement. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b2981293 ; http://dx.doi.org/10.5353/th_b2981293 ; http://hdl.handle.net/10722/31758


University of Arizona

8. Chen, Ing-yi, 1962-. Efficient reconfiguration by degradation in defect-tolerant VLSI arrays .

Degree: 1989, University of Arizona

 This thesis addresses the problem of constructing a flawless subarray from a defective VLSI/WSI array consists of identical cells such as memory cells or processors.… (more)

Subjects/Keywords: Integrated circuits  – Very large scale integration  – Design and construction.

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APA (6th Edition):

Chen, Ing-yi, 1. (1989). Efficient reconfiguration by degradation in defect-tolerant VLSI arrays . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/277195

Chicago Manual of Style (16th Edition):

Chen, Ing-yi, 1962-. “Efficient reconfiguration by degradation in defect-tolerant VLSI arrays .” 1989. Masters Thesis, University of Arizona. Accessed December 12, 2019. http://hdl.handle.net/10150/277195.

MLA Handbook (7th Edition):

Chen, Ing-yi, 1962-. “Efficient reconfiguration by degradation in defect-tolerant VLSI arrays .” 1989. Web. 12 Dec 2019.

Vancouver:

Chen, Ing-yi 1. Efficient reconfiguration by degradation in defect-tolerant VLSI arrays . [Internet] [Masters thesis]. University of Arizona; 1989. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/10150/277195.

Council of Science Editors:

Chen, Ing-yi 1. Efficient reconfiguration by degradation in defect-tolerant VLSI arrays . [Masters Thesis]. University of Arizona; 1989. Available from: http://hdl.handle.net/10150/277195


Michigan State University

9. Kim, Sangchul. Configuration management and version data modeling in VLSI design environments.

Degree: PhD, Department of Computer Science, 1994, Michigan State University

Subjects/Keywords: Integrated circuits – Very large scale integration – Design and construction

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APA (6th Edition):

Kim, S. (1994). Configuration management and version data modeling in VLSI design environments. (Doctoral Dissertation). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:24288

Chicago Manual of Style (16th Edition):

Kim, Sangchul. “Configuration management and version data modeling in VLSI design environments.” 1994. Doctoral Dissertation, Michigan State University. Accessed December 12, 2019. http://etd.lib.msu.edu/islandora/object/etd:24288.

MLA Handbook (7th Edition):

Kim, Sangchul. “Configuration management and version data modeling in VLSI design environments.” 1994. Web. 12 Dec 2019.

Vancouver:

Kim S. Configuration management and version data modeling in VLSI design environments. [Internet] [Doctoral dissertation]. Michigan State University; 1994. [cited 2019 Dec 12]. Available from: http://etd.lib.msu.edu/islandora/object/etd:24288.

Council of Science Editors:

Kim S. Configuration management and version data modeling in VLSI design environments. [Doctoral Dissertation]. Michigan State University; 1994. Available from: http://etd.lib.msu.edu/islandora/object/etd:24288


University of Arizona

10. Whipple, Thomas Driggs, 1961-. Design and implementation of an integrated VLSI packaging support software environment .

Degree: 1989, University of Arizona

 An interactive software shell has been developed which integrates several packaging simulation tools developed at the University of Arizona which are used to analyze electro-magnetic… (more)

Subjects/Keywords: Integrated circuits  – Simulation methods.; Integrated circuits  – Design and construction.; Integrated circuits  – Very large scale integration.

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APA (6th Edition):

Whipple, Thomas Driggs, 1. (1989). Design and implementation of an integrated VLSI packaging support software environment . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/277105

Chicago Manual of Style (16th Edition):

Whipple, Thomas Driggs, 1961-. “Design and implementation of an integrated VLSI packaging support software environment .” 1989. Masters Thesis, University of Arizona. Accessed December 12, 2019. http://hdl.handle.net/10150/277105.

MLA Handbook (7th Edition):

Whipple, Thomas Driggs, 1961-. “Design and implementation of an integrated VLSI packaging support software environment .” 1989. Web. 12 Dec 2019.

Vancouver:

Whipple, Thomas Driggs 1. Design and implementation of an integrated VLSI packaging support software environment . [Internet] [Masters thesis]. University of Arizona; 1989. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/10150/277105.

Council of Science Editors:

Whipple, Thomas Driggs 1. Design and implementation of an integrated VLSI packaging support software environment . [Masters Thesis]. University of Arizona; 1989. Available from: http://hdl.handle.net/10150/277105


Hong Kong University of Science and Technology

11. Zou, Peiqing. System level power optimization and estimation.

Degree: 2001, Hong Kong University of Science and Technology

 Higher integration density, smaller device geometry, larger chip size, faster clock frequency, and the demand low power consumption have made power related issues increasingly critical… (more)

Subjects/Keywords: Low voltage integrated circuits  – Design and construction; Integrated circuits  – Very large scale integration  – Design and construction; Computer-aided design

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APA (6th Edition):

Zou, P. (2001). System level power optimization and estimation. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b696754 ; http://repository.ust.hk/ir/bitstream/1783.1-4584/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zou, Peiqing. “System level power optimization and estimation.” 2001. Thesis, Hong Kong University of Science and Technology. Accessed December 12, 2019. https://doi.org/10.14711/thesis-b696754 ; http://repository.ust.hk/ir/bitstream/1783.1-4584/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zou, Peiqing. “System level power optimization and estimation.” 2001. Web. 12 Dec 2019.

Vancouver:

Zou P. System level power optimization and estimation. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2001. [cited 2019 Dec 12]. Available from: https://doi.org/10.14711/thesis-b696754 ; http://repository.ust.hk/ir/bitstream/1783.1-4584/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zou P. System level power optimization and estimation. [Thesis]. Hong Kong University of Science and Technology; 2001. Available from: https://doi.org/10.14711/thesis-b696754 ; http://repository.ust.hk/ir/bitstream/1783.1-4584/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of North Texas

12. Ale, Anil Kumar. Comparison and Evaluation of Existing Analog Circuit Simulator using Sigma-Delta Modulator.

Degree: 2006, University of North Texas

 In the world of VLSI (very large scale integration) technology, there are many different types of circuit simulators that are used to design and predict… (more)

Subjects/Keywords: Integrated circuits  – Design and construction.; Integrated circuits  – Very large scale integration.; Simulation methods.; circuit simulation; sigma-delta modulator; nanotechnology

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APA (6th Edition):

Ale, A. K. (2006). Comparison and Evaluation of Existing Analog Circuit Simulator using Sigma-Delta Modulator. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc5422/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ale, Anil Kumar. “Comparison and Evaluation of Existing Analog Circuit Simulator using Sigma-Delta Modulator.” 2006. Thesis, University of North Texas. Accessed December 12, 2019. https://digital.library.unt.edu/ark:/67531/metadc5422/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ale, Anil Kumar. “Comparison and Evaluation of Existing Analog Circuit Simulator using Sigma-Delta Modulator.” 2006. Web. 12 Dec 2019.

Vancouver:

Ale AK. Comparison and Evaluation of Existing Analog Circuit Simulator using Sigma-Delta Modulator. [Internet] [Thesis]. University of North Texas; 2006. [cited 2019 Dec 12]. Available from: https://digital.library.unt.edu/ark:/67531/metadc5422/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ale AK. Comparison and Evaluation of Existing Analog Circuit Simulator using Sigma-Delta Modulator. [Thesis]. University of North Texas; 2006. Available from: https://digital.library.unt.edu/ark:/67531/metadc5422/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Alberta

13. Sahabi, Hossein. Wiring optimization in slicing floorplans.

Degree: MS, Department of Electrical Engineering, 1992, University of Alberta

Subjects/Keywords: Integrated circuits – Very large scale integration.; Integrated circuits – Design and construction.

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APA (6th Edition):

Sahabi, H. (1992). Wiring optimization in slicing floorplans. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/4j03d218k

Chicago Manual of Style (16th Edition):

Sahabi, Hossein. “Wiring optimization in slicing floorplans.” 1992. Masters Thesis, University of Alberta. Accessed December 12, 2019. https://era.library.ualberta.ca/files/4j03d218k.

MLA Handbook (7th Edition):

Sahabi, Hossein. “Wiring optimization in slicing floorplans.” 1992. Web. 12 Dec 2019.

Vancouver:

Sahabi H. Wiring optimization in slicing floorplans. [Internet] [Masters thesis]. University of Alberta; 1992. [cited 2019 Dec 12]. Available from: https://era.library.ualberta.ca/files/4j03d218k.

Council of Science Editors:

Sahabi H. Wiring optimization in slicing floorplans. [Masters Thesis]. University of Alberta; 1992. Available from: https://era.library.ualberta.ca/files/4j03d218k


Hong Kong University of Science and Technology

14. Sun, Yanan. High-performance, low-power, and compact CMOS VLSI circuits with carbon nanotube transistor technology.

Degree: 2014, Hong Kong University of Science and Technology

 Carbon nanotube Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) provides better scalability and performance with suppressed short-channel effects and higher carrier mobility as compared to the conventional silicon… (more)

Subjects/Keywords: Metal oxide semiconductors, Complementary; Design and construction; Integrated circuits; Very large scale integration; Low voltage integrated circuits; Carbon nanotubes; Metal oxide semiconductor field-effect transistors

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APA (6th Edition):

Sun, Y. (2014). High-performance, low-power, and compact CMOS VLSI circuits with carbon nanotube transistor technology. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1432180 ; http://repository.ust.hk/ir/bitstream/1783.1-72512/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sun, Yanan. “High-performance, low-power, and compact CMOS VLSI circuits with carbon nanotube transistor technology.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed December 12, 2019. https://doi.org/10.14711/thesis-b1432180 ; http://repository.ust.hk/ir/bitstream/1783.1-72512/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sun, Yanan. “High-performance, low-power, and compact CMOS VLSI circuits with carbon nanotube transistor technology.” 2014. Web. 12 Dec 2019.

Vancouver:

Sun Y. High-performance, low-power, and compact CMOS VLSI circuits with carbon nanotube transistor technology. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2019 Dec 12]. Available from: https://doi.org/10.14711/thesis-b1432180 ; http://repository.ust.hk/ir/bitstream/1783.1-72512/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sun Y. High-performance, low-power, and compact CMOS VLSI circuits with carbon nanotube transistor technology. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: https://doi.org/10.14711/thesis-b1432180 ; http://repository.ust.hk/ir/bitstream/1783.1-72512/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


McGill University

15. Ivanov, André. Dynamic testibility measures and their use in ATPG.

Degree: M. Eng., Department of Electrical Engineering., 1985, McGill University

Subjects/Keywords: Integrated circuits  – Design and construction  – Data processing.; Integrated circuits  – Testing.; Integrated circuits  – Very large scale integration  – Design and construction.; Integrated circuits  – Very large scale integration  – Testing.

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APA (6th Edition):

Ivanov, A. (1985). Dynamic testibility measures and their use in ATPG. (Masters Thesis). McGill University. Retrieved from http://digitool.library.mcgill.ca/thesisfile63324.pdf

Chicago Manual of Style (16th Edition):

Ivanov, André. “Dynamic testibility measures and their use in ATPG.” 1985. Masters Thesis, McGill University. Accessed December 12, 2019. http://digitool.library.mcgill.ca/thesisfile63324.pdf.

MLA Handbook (7th Edition):

Ivanov, André. “Dynamic testibility measures and their use in ATPG.” 1985. Web. 12 Dec 2019.

Vancouver:

Ivanov A. Dynamic testibility measures and their use in ATPG. [Internet] [Masters thesis]. McGill University; 1985. [cited 2019 Dec 12]. Available from: http://digitool.library.mcgill.ca/thesisfile63324.pdf.

Council of Science Editors:

Ivanov A. Dynamic testibility measures and their use in ATPG. [Masters Thesis]. McGill University; 1985. Available from: http://digitool.library.mcgill.ca/thesisfile63324.pdf


Hong Kong University of Science and Technology

16. Lee, Man. Design, fabrication and characterization of an integrated micro heat pipe system.

Degree: 2002, Hong Kong University of Science and Technology

 The number and density of electronic components in VLSI chips has sharply increased in modem ICs. The heat generated in the chip results in a… (more)

Subjects/Keywords: Integrated circuits  – Very large scale integration  – Heat treatment; Integrated circuits  – Very large scale integration  – Design and construction

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APA (6th Edition):

Lee, M. (2002). Design, fabrication and characterization of an integrated micro heat pipe system. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b770176 ; http://repository.ust.hk/ir/bitstream/1783.1-5236/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Man. “Design, fabrication and characterization of an integrated micro heat pipe system.” 2002. Thesis, Hong Kong University of Science and Technology. Accessed December 12, 2019. https://doi.org/10.14711/thesis-b770176 ; http://repository.ust.hk/ir/bitstream/1783.1-5236/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Man. “Design, fabrication and characterization of an integrated micro heat pipe system.” 2002. Web. 12 Dec 2019.

Vancouver:

Lee M. Design, fabrication and characterization of an integrated micro heat pipe system. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2002. [cited 2019 Dec 12]. Available from: https://doi.org/10.14711/thesis-b770176 ; http://repository.ust.hk/ir/bitstream/1783.1-5236/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee M. Design, fabrication and characterization of an integrated micro heat pipe system. [Thesis]. Hong Kong University of Science and Technology; 2002. Available from: https://doi.org/10.14711/thesis-b770176 ; http://repository.ust.hk/ir/bitstream/1783.1-5236/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Xu Shubing. Hybrid Selective X-masking and X-canceling Multiple Input Signature Register for Test Data Compression Techniques .

Degree: คณะวิศวกรรมศาสตร์ ภาควิชาวิศวกรรมคอมพิวเตอร์, 2011, Prince of Songkla University

Subjects/Keywords: Integrated circuits Very large scale integration Testing; Integrated circuits Very large scale integration Design and construction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shubing, X. (2011). Hybrid Selective X-masking and X-canceling Multiple Input Signature Register for Test Data Compression Techniques . (Thesis). Prince of Songkla University. Retrieved from http://kb.psu.ac.th/psukb/handle/2016/10388

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shubing, Xu. “Hybrid Selective X-masking and X-canceling Multiple Input Signature Register for Test Data Compression Techniques .” 2011. Thesis, Prince of Songkla University. Accessed December 12, 2019. http://kb.psu.ac.th/psukb/handle/2016/10388.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shubing, Xu. “Hybrid Selective X-masking and X-canceling Multiple Input Signature Register for Test Data Compression Techniques .” 2011. Web. 12 Dec 2019.

Vancouver:

Shubing X. Hybrid Selective X-masking and X-canceling Multiple Input Signature Register for Test Data Compression Techniques . [Internet] [Thesis]. Prince of Songkla University; 2011. [cited 2019 Dec 12]. Available from: http://kb.psu.ac.th/psukb/handle/2016/10388.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shubing X. Hybrid Selective X-masking and X-canceling Multiple Input Signature Register for Test Data Compression Techniques . [Thesis]. Prince of Songkla University; 2011. Available from: http://kb.psu.ac.th/psukb/handle/2016/10388

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Simon Fraser University

18. Audet, Yves. A magnetic field sensor array using redundancy schemes for defect avoidance.

Degree: 1997, Simon Fraser University

Subjects/Keywords: Integrated circuits  – Very large scale integration  – Design and construction.; Integrated circuits  – Very large scale integration  – Defects.

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APA (6th Edition):

Audet, Y. (1997). A magnetic field sensor array using redundancy schemes for defect avoidance. (Thesis). Simon Fraser University. Retrieved from http://summit.sfu.ca/item/7497

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Audet, Yves. “A magnetic field sensor array using redundancy schemes for defect avoidance.” 1997. Thesis, Simon Fraser University. Accessed December 12, 2019. http://summit.sfu.ca/item/7497.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Audet, Yves. “A magnetic field sensor array using redundancy schemes for defect avoidance.” 1997. Web. 12 Dec 2019.

Vancouver:

Audet Y. A magnetic field sensor array using redundancy schemes for defect avoidance. [Internet] [Thesis]. Simon Fraser University; 1997. [cited 2019 Dec 12]. Available from: http://summit.sfu.ca/item/7497.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Audet Y. A magnetic field sensor array using redundancy schemes for defect avoidance. [Thesis]. Simon Fraser University; 1997. Available from: http://summit.sfu.ca/item/7497

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

19. Nugent, Steven Paul. A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC).

Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech

 Future opportunities for gigascale integration will be governed by a hierarchy of theoretical and practical limits that can be codified as follows: fundamental, material, device,… (more)

Subjects/Keywords: Chip modeling; Performance modeling; Simulator; Gigascale; Chip modeling; GENESYS; Integrated circuits Very large scale integration Design and construction Computer simulation; System design Computer simulation

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APA (6th Edition):

Nugent, S. P. (2005). A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC). (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6885

Chicago Manual of Style (16th Edition):

Nugent, Steven Paul. “A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC).” 2005. Doctoral Dissertation, Georgia Tech. Accessed December 12, 2019. http://hdl.handle.net/1853/6885.

MLA Handbook (7th Edition):

Nugent, Steven Paul. “A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC).” 2005. Web. 12 Dec 2019.

Vancouver:

Nugent SP. A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC). [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/1853/6885.

Council of Science Editors:

Nugent SP. A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC). [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6885


Massey University

20. Lapshev, Stepan. CMOS VLSI correlator design for radio-astronomical signal processing.

Degree: PhD, Engineering, 2018, Massey University

 Multi-element radio telescopes employ methods of indirect imaging to capture the image of the sky. These methods are in contrast to direct imaging methods whereby… (more)

Subjects/Keywords: Integrated circuits  – Very large scale integration  – Design and construction; Metal oxide semiconductors, Complementary  – Design and construction; Imaging systems in astronomy; Radio astronomy

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APA (6th Edition):

Lapshev, S. (2018). CMOS VLSI correlator design for radio-astronomical signal processing. (Doctoral Dissertation). Massey University. Retrieved from http://hdl.handle.net/10179/14214

Chicago Manual of Style (16th Edition):

Lapshev, Stepan. “CMOS VLSI correlator design for radio-astronomical signal processing.” 2018. Doctoral Dissertation, Massey University. Accessed December 12, 2019. http://hdl.handle.net/10179/14214.

MLA Handbook (7th Edition):

Lapshev, Stepan. “CMOS VLSI correlator design for radio-astronomical signal processing.” 2018. Web. 12 Dec 2019.

Vancouver:

Lapshev S. CMOS VLSI correlator design for radio-astronomical signal processing. [Internet] [Doctoral dissertation]. Massey University; 2018. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/10179/14214.

Council of Science Editors:

Lapshev S. CMOS VLSI correlator design for radio-astronomical signal processing. [Doctoral Dissertation]. Massey University; 2018. Available from: http://hdl.handle.net/10179/14214


Edith Cowan University

21. Tang, Maolin. Intelligent approaches to VLSI routing.

Degree: 2000, Edith Cowan University

Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As… (more)

Subjects/Keywords: Integrated circuits; Very large scale integration; Design and construction; Digital Circuits

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APA (6th Edition):

Tang, M. (2000). Intelligent approaches to VLSI routing. (Thesis). Edith Cowan University. Retrieved from http://ro.ecu.edu.au/theses/1375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tang, Maolin. “Intelligent approaches to VLSI routing.” 2000. Thesis, Edith Cowan University. Accessed December 12, 2019. http://ro.ecu.edu.au/theses/1375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tang, Maolin. “Intelligent approaches to VLSI routing.” 2000. Web. 12 Dec 2019.

Vancouver:

Tang M. Intelligent approaches to VLSI routing. [Internet] [Thesis]. Edith Cowan University; 2000. [cited 2019 Dec 12]. Available from: http://ro.ecu.edu.au/theses/1375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tang M. Intelligent approaches to VLSI routing. [Thesis]. Edith Cowan University; 2000. Available from: http://ro.ecu.edu.au/theses/1375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of North Texas

22. Battina, Brahmasree. An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design.

Degree: 2014, University of North Texas

Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and… (more)

Subjects/Keywords: interactive framework; digital logic design; VLSR Design; integrated circuits; Digital integrated circuits  – Design and construction  – Study and teaching.; Integrated circuits  – Very large scale integration  – Design and construction  – Study and teaching.; Logic design  – Study and teaching.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Battina, B. (2014). An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc799495/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Battina, Brahmasree. “An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design.” 2014. Thesis, University of North Texas. Accessed December 12, 2019. https://digital.library.unt.edu/ark:/67531/metadc799495/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Battina, Brahmasree. “An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design.” 2014. Web. 12 Dec 2019.

Vancouver:

Battina B. An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design. [Internet] [Thesis]. University of North Texas; 2014. [cited 2019 Dec 12]. Available from: https://digital.library.unt.edu/ark:/67531/metadc799495/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Battina B. An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design. [Thesis]. University of North Texas; 2014. Available from: https://digital.library.unt.edu/ark:/67531/metadc799495/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Alberta

23. Savarimuthu, James. Programmable logic array (PLA) folding.

Degree: MS, Department of Electrical Engineering, 1986, University of Alberta

Subjects/Keywords: Algorithms.; Programmable logic devices.; Integrated circuits – Very large scale integration – Design and construction.

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APA (6th Edition):

Savarimuthu, J. (1986). Programmable logic array (PLA) folding. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/q811km63f

Chicago Manual of Style (16th Edition):

Savarimuthu, James. “Programmable logic array (PLA) folding.” 1986. Masters Thesis, University of Alberta. Accessed December 12, 2019. https://era.library.ualberta.ca/files/q811km63f.

MLA Handbook (7th Edition):

Savarimuthu, James. “Programmable logic array (PLA) folding.” 1986. Web. 12 Dec 2019.

Vancouver:

Savarimuthu J. Programmable logic array (PLA) folding. [Internet] [Masters thesis]. University of Alberta; 1986. [cited 2019 Dec 12]. Available from: https://era.library.ualberta.ca/files/q811km63f.

Council of Science Editors:

Savarimuthu J. Programmable logic array (PLA) folding. [Masters Thesis]. University of Alberta; 1986. Available from: https://era.library.ualberta.ca/files/q811km63f

24. Johnson, Timothy E. MOSSTAT An interactive static rule checker for MOS VLSI designs.

Degree: MS, 1986, Oregon Health Sciences University

Subjects/Keywords: Integrated circuits  – Very large scale integration  – Design and construction; Metal oxide semiconductors

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APA (6th Edition):

Johnson, T. E. (1986). MOSSTAT An interactive static rule checker for MOS VLSI designs. (Thesis). Oregon Health Sciences University. Retrieved from doi:10.6083/M4CC0XNQ ; http://digitalcommons.ohsu.edu/etd/206

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Johnson, Timothy E. “MOSSTAT An interactive static rule checker for MOS VLSI designs.” 1986. Thesis, Oregon Health Sciences University. Accessed December 12, 2019. doi:10.6083/M4CC0XNQ ; http://digitalcommons.ohsu.edu/etd/206.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Johnson, Timothy E. “MOSSTAT An interactive static rule checker for MOS VLSI designs.” 1986. Web. 12 Dec 2019.

Vancouver:

Johnson TE. MOSSTAT An interactive static rule checker for MOS VLSI designs. [Internet] [Thesis]. Oregon Health Sciences University; 1986. [cited 2019 Dec 12]. Available from: doi:10.6083/M4CC0XNQ ; http://digitalcommons.ohsu.edu/etd/206.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Johnson TE. MOSSTAT An interactive static rule checker for MOS VLSI designs. [Thesis]. Oregon Health Sciences University; 1986. Available from: doi:10.6083/M4CC0XNQ ; http://digitalcommons.ohsu.edu/etd/206

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Hong Kong

25. Yuen, Chi-kan. A double-track greedy algorithm for VLSI channel routing.

Degree: M. Phil., 1997, University of Hong Kong

published_or_final_version

Electrical and Electronic Engineering

Master

Master of Philosophy

Subjects/Keywords: Integrated circuits - Very large scale integration - Design and construction.; Algorithms.

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APA (6th Edition):

Yuen, C. (1997). A double-track greedy algorithm for VLSI channel routing. (Masters Thesis). University of Hong Kong. Retrieved from Yuen, C. [袁志勤]. (1997). A double-track greedy algorithm for VLSI channel routing. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b3122024 ; http://dx.doi.org/10.5353/th_b3122024 ; http://hdl.handle.net/10722/33399

Chicago Manual of Style (16th Edition):

Yuen, Chi-kan. “A double-track greedy algorithm for VLSI channel routing.” 1997. Masters Thesis, University of Hong Kong. Accessed December 12, 2019. Yuen, C. [袁志勤]. (1997). A double-track greedy algorithm for VLSI channel routing. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b3122024 ; http://dx.doi.org/10.5353/th_b3122024 ; http://hdl.handle.net/10722/33399.

MLA Handbook (7th Edition):

Yuen, Chi-kan. “A double-track greedy algorithm for VLSI channel routing.” 1997. Web. 12 Dec 2019.

Vancouver:

Yuen C. A double-track greedy algorithm for VLSI channel routing. [Internet] [Masters thesis]. University of Hong Kong; 1997. [cited 2019 Dec 12]. Available from: Yuen, C. [袁志勤]. (1997). A double-track greedy algorithm for VLSI channel routing. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b3122024 ; http://dx.doi.org/10.5353/th_b3122024 ; http://hdl.handle.net/10722/33399.

Council of Science Editors:

Yuen C. A double-track greedy algorithm for VLSI channel routing. [Masters Thesis]. University of Hong Kong; 1997. Available from: Yuen, C. [袁志勤]. (1997). A double-track greedy algorithm for VLSI channel routing. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b3122024 ; http://dx.doi.org/10.5353/th_b3122024 ; http://hdl.handle.net/10722/33399


Hong Kong University of Science and Technology

26. Au, Yi-ching. Leakage power modeling and reduction techniques for nanometer scale VLSI circuits.

Degree: 2004, Hong Kong University of Science and Technology

 Minimizing dynamic power consumption in digital circuits was the primary design objective in most of the existing low power design methodology. Voltage reduction was proven… (more)

Subjects/Keywords: Electric leakage  – Prevention; Integrated circuits  – Very large scale integration  – Design and construction

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APA (6th Edition):

Au, Y. (2004). Leakage power modeling and reduction techniques for nanometer scale VLSI circuits. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b842102 ; http://repository.ust.hk/ir/bitstream/1783.1-4712/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Au, Yi-ching. “Leakage power modeling and reduction techniques for nanometer scale VLSI circuits.” 2004. Thesis, Hong Kong University of Science and Technology. Accessed December 12, 2019. https://doi.org/10.14711/thesis-b842102 ; http://repository.ust.hk/ir/bitstream/1783.1-4712/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Au, Yi-ching. “Leakage power modeling and reduction techniques for nanometer scale VLSI circuits.” 2004. Web. 12 Dec 2019.

Vancouver:

Au Y. Leakage power modeling and reduction techniques for nanometer scale VLSI circuits. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2004. [cited 2019 Dec 12]. Available from: https://doi.org/10.14711/thesis-b842102 ; http://repository.ust.hk/ir/bitstream/1783.1-4712/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Au Y. Leakage power modeling and reduction techniques for nanometer scale VLSI circuits. [Thesis]. Hong Kong University of Science and Technology; 2004. Available from: https://doi.org/10.14711/thesis-b842102 ; http://repository.ust.hk/ir/bitstream/1783.1-4712/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


McGill University

27. Draier, Benny. Test vector generation and compaction for easily testable PLAs.

Degree: M. Eng., Department of Electrical Engineering., 1988, McGill University

Subjects/Keywords: Programmable array logic  – Design and construction; Integrated circuits  – Very large scale integration  – Testing

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APA (6th Edition):

Draier, B. (1988). Test vector generation and compaction for easily testable PLAs. (Masters Thesis). McGill University. Retrieved from http://digitool.library.mcgill.ca/thesisfile63970.pdf

Chicago Manual of Style (16th Edition):

Draier, Benny. “Test vector generation and compaction for easily testable PLAs.” 1988. Masters Thesis, McGill University. Accessed December 12, 2019. http://digitool.library.mcgill.ca/thesisfile63970.pdf.

MLA Handbook (7th Edition):

Draier, Benny. “Test vector generation and compaction for easily testable PLAs.” 1988. Web. 12 Dec 2019.

Vancouver:

Draier B. Test vector generation and compaction for easily testable PLAs. [Internet] [Masters thesis]. McGill University; 1988. [cited 2019 Dec 12]. Available from: http://digitool.library.mcgill.ca/thesisfile63970.pdf.

Council of Science Editors:

Draier B. Test vector generation and compaction for easily testable PLAs. [Masters Thesis]. McGill University; 1988. Available from: http://digitool.library.mcgill.ca/thesisfile63970.pdf


University of Adelaide

28. Pope, Michael T. (Michael Travers). VLSI systems simulation / Michael T. Pope.

Degree: 1991, University of Adelaide

Subjects/Keywords: 621.395 20; Integrated circuits Very large scale integration Design and construction Mathematical models.

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APA (6th Edition):

Pope, M. T. (. T. (1991). VLSI systems simulation / Michael T. Pope. (Thesis). University of Adelaide. Retrieved from http://hdl.handle.net/2440/19471

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pope, Michael T (Michael Travers). “VLSI systems simulation / Michael T. Pope.” 1991. Thesis, University of Adelaide. Accessed December 12, 2019. http://hdl.handle.net/2440/19471.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pope, Michael T (Michael Travers). “VLSI systems simulation / Michael T. Pope.” 1991. Web. 12 Dec 2019.

Vancouver:

Pope MT(T. VLSI systems simulation / Michael T. Pope. [Internet] [Thesis]. University of Adelaide; 1991. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2440/19471.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pope MT(T. VLSI systems simulation / Michael T. Pope. [Thesis]. University of Adelaide; 1991. Available from: http://hdl.handle.net/2440/19471

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Adelaide

29. Bishop, Gregory Raymond H. "On stochastic modelling of very large scale integrated circuits : an investigation into the timing behaviour of microelectronic systems".

Degree: 1993, University of Adelaide

Subjects/Keywords: 621.395 20; Integrated circuits Very large scale integration Design and construction Mathematical models.

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APA (6th Edition):

Bishop, G. R. H. (1993). "On stochastic modelling of very large scale integrated circuits : an investigation into the timing behaviour of microelectronic systems". (Thesis). University of Adelaide. Retrieved from http://hdl.handle.net/2440/21376

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bishop, Gregory Raymond H. “"On stochastic modelling of very large scale integrated circuits : an investigation into the timing behaviour of microelectronic systems".” 1993. Thesis, University of Adelaide. Accessed December 12, 2019. http://hdl.handle.net/2440/21376.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bishop, Gregory Raymond H. “"On stochastic modelling of very large scale integrated circuits : an investigation into the timing behaviour of microelectronic systems".” 1993. Web. 12 Dec 2019.

Vancouver:

Bishop GRH. "On stochastic modelling of very large scale integrated circuits : an investigation into the timing behaviour of microelectronic systems". [Internet] [Thesis]. University of Adelaide; 1993. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2440/21376.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bishop GRH. "On stochastic modelling of very large scale integrated circuits : an investigation into the timing behaviour of microelectronic systems". [Thesis]. University of Adelaide; 1993. Available from: http://hdl.handle.net/2440/21376

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New South Wales

30. Tan, Chong Hee. Colossus : a distributed and reconfigurable framework for VLSI design process system synthesis.

Degree: Computer Science & Engineering, 1994, University of New South Wales

Subjects/Keywords: Design and construction; Integrated circuits; Very large scale integration; Thesis Digitisation Program

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tan, C. H. (1994). Colossus : a distributed and reconfigurable framework for VLSI design process system synthesis. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/55630 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:38184/SOURCE01?view=true

Chicago Manual of Style (16th Edition):

Tan, Chong Hee. “Colossus : a distributed and reconfigurable framework for VLSI design process system synthesis.” 1994. Doctoral Dissertation, University of New South Wales. Accessed December 12, 2019. http://handle.unsw.edu.au/1959.4/55630 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:38184/SOURCE01?view=true.

MLA Handbook (7th Edition):

Tan, Chong Hee. “Colossus : a distributed and reconfigurable framework for VLSI design process system synthesis.” 1994. Web. 12 Dec 2019.

Vancouver:

Tan CH. Colossus : a distributed and reconfigurable framework for VLSI design process system synthesis. [Internet] [Doctoral dissertation]. University of New South Wales; 1994. [cited 2019 Dec 12]. Available from: http://handle.unsw.edu.au/1959.4/55630 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:38184/SOURCE01?view=true.

Council of Science Editors:

Tan CH. Colossus : a distributed and reconfigurable framework for VLSI design process system synthesis. [Doctoral Dissertation]. University of New South Wales; 1994. Available from: http://handle.unsw.edu.au/1959.4/55630 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:38184/SOURCE01?view=true

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