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You searched for subject:(Incremental Delta sigma ADC). Showing records 1 – 30 of 4048 total matches.

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1. Bisiaux, Pierre. Etude et conception de CAN haute résolution pour le domaine de l’imagerie : Design of high resolution analog-to-digital converters for CMOS image sensors.

Degree: Docteur es, Electronique et Optoélectronique, Nano- et Microtechnologies, 2018, Université Paris-Saclay (ComUE)

Cette thèse porte sur la conception et la réalisation de convertisseurs analogique/numérique (ADC) haute résolution dans le domaine de l’imagerie spatiale en technologie 0.18 μm.Un… (more)

Subjects/Keywords: Can; Imagerie; Sigma delta incrémental; Inverter-based; ADC; Image sensor; Incremental sigma delta; Inverter-based

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APA (6th Edition):

Bisiaux, P. (2018). Etude et conception de CAN haute résolution pour le domaine de l’imagerie : Design of high resolution analog-to-digital converters for CMOS image sensors. (Doctoral Dissertation). Université Paris-Saclay (ComUE). Retrieved from http://www.theses.fr/2018SACLC030

Chicago Manual of Style (16th Edition):

Bisiaux, Pierre. “Etude et conception de CAN haute résolution pour le domaine de l’imagerie : Design of high resolution analog-to-digital converters for CMOS image sensors.” 2018. Doctoral Dissertation, Université Paris-Saclay (ComUE). Accessed September 19, 2020. http://www.theses.fr/2018SACLC030.

MLA Handbook (7th Edition):

Bisiaux, Pierre. “Etude et conception de CAN haute résolution pour le domaine de l’imagerie : Design of high resolution analog-to-digital converters for CMOS image sensors.” 2018. Web. 19 Sep 2020.

Vancouver:

Bisiaux P. Etude et conception de CAN haute résolution pour le domaine de l’imagerie : Design of high resolution analog-to-digital converters for CMOS image sensors. [Internet] [Doctoral dissertation]. Université Paris-Saclay (ComUE); 2018. [cited 2020 Sep 19]. Available from: http://www.theses.fr/2018SACLC030.

Council of Science Editors:

Bisiaux P. Etude et conception de CAN haute résolution pour le domaine de l’imagerie : Design of high resolution analog-to-digital converters for CMOS image sensors. [Doctoral Dissertation]. Université Paris-Saclay (ComUE); 2018. Available from: http://www.theses.fr/2018SACLC030


Delft University of Technology

2. Chen, C. (author). Energy-Efficient Self-Timed Zero-Crossing-Based Incremental Delta-Sigma ADC.

Degree: 2012, Delft University of Technology

Microelectronics

Microelectronics & Computer Engineering

Electrical Engineering, Mathematics and Computer Science

Advisors/Committee Members: Pertijs, M.A.P. (mentor).

Subjects/Keywords: Incremental Delta-sigma ADC; self-timed; zero-crossing-based circuits; energy-efficient; low-power

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APA (6th Edition):

Chen, C. (. (2012). Energy-Efficient Self-Timed Zero-Crossing-Based Incremental Delta-Sigma ADC. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:077f4577-c9b8-4be7-91a7-49bf751e73ef

Chicago Manual of Style (16th Edition):

Chen, C (author). “Energy-Efficient Self-Timed Zero-Crossing-Based Incremental Delta-Sigma ADC.” 2012. Masters Thesis, Delft University of Technology. Accessed September 19, 2020. http://resolver.tudelft.nl/uuid:077f4577-c9b8-4be7-91a7-49bf751e73ef.

MLA Handbook (7th Edition):

Chen, C (author). “Energy-Efficient Self-Timed Zero-Crossing-Based Incremental Delta-Sigma ADC.” 2012. Web. 19 Sep 2020.

Vancouver:

Chen C(. Energy-Efficient Self-Timed Zero-Crossing-Based Incremental Delta-Sigma ADC. [Internet] [Masters thesis]. Delft University of Technology; 2012. [cited 2020 Sep 19]. Available from: http://resolver.tudelft.nl/uuid:077f4577-c9b8-4be7-91a7-49bf751e73ef.

Council of Science Editors:

Chen C(. Energy-Efficient Self-Timed Zero-Crossing-Based Incremental Delta-Sigma ADC. [Masters Thesis]. Delft University of Technology; 2012. Available from: http://resolver.tudelft.nl/uuid:077f4577-c9b8-4be7-91a7-49bf751e73ef


Delft University of Technology

3. Kamath, U.R. (author). Design of high-resolution photodiode readout circuitry for a bio-implantable continuous glucose sensing chip.

Degree: 2012, Delft University of Technology

Glucose sensors are useful for monitoring and control of blood-sugar concentration for diabetic patients. There are many challenges in their wide-spread use and effectiveness in… (more)

Subjects/Keywords: glucose sensor; incremental Sigma-Delta; current input ADC; dynamic reference; wide-dynamic range; sensor adaptable ADC

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APA (6th Edition):

Kamath, U. R. (. (2012). Design of high-resolution photodiode readout circuitry for a bio-implantable continuous glucose sensing chip. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:ea9d2e1c-5b03-44e9-b916-587fd737313f

Chicago Manual of Style (16th Edition):

Kamath, U R (author). “Design of high-resolution photodiode readout circuitry for a bio-implantable continuous glucose sensing chip.” 2012. Masters Thesis, Delft University of Technology. Accessed September 19, 2020. http://resolver.tudelft.nl/uuid:ea9d2e1c-5b03-44e9-b916-587fd737313f.

MLA Handbook (7th Edition):

Kamath, U R (author). “Design of high-resolution photodiode readout circuitry for a bio-implantable continuous glucose sensing chip.” 2012. Web. 19 Sep 2020.

Vancouver:

Kamath UR(. Design of high-resolution photodiode readout circuitry for a bio-implantable continuous glucose sensing chip. [Internet] [Masters thesis]. Delft University of Technology; 2012. [cited 2020 Sep 19]. Available from: http://resolver.tudelft.nl/uuid:ea9d2e1c-5b03-44e9-b916-587fd737313f.

Council of Science Editors:

Kamath UR(. Design of high-resolution photodiode readout circuitry for a bio-implantable continuous glucose sensing chip. [Masters Thesis]. Delft University of Technology; 2012. Available from: http://resolver.tudelft.nl/uuid:ea9d2e1c-5b03-44e9-b916-587fd737313f


Delft University of Technology

4. Zhan, Xin (author). A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC.

Degree: 2018, Delft University of Technology

 This thesis presents the design and implementation of a low power 3rd-order loop filter and a low power, compact, high-speed inverter-based amplifier designed in 28nm… (more)

Subjects/Keywords: Sigma Delta; ADC; loop filter

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APA (6th Edition):

Zhan, X. (. (2018). A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:40957c09-3edd-474c-b271-f67bda41d652

Chicago Manual of Style (16th Edition):

Zhan, Xin (author). “A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC.” 2018. Masters Thesis, Delft University of Technology. Accessed September 19, 2020. http://resolver.tudelft.nl/uuid:40957c09-3edd-474c-b271-f67bda41d652.

MLA Handbook (7th Edition):

Zhan, Xin (author). “A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC.” 2018. Web. 19 Sep 2020.

Vancouver:

Zhan X(. A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC. [Internet] [Masters thesis]. Delft University of Technology; 2018. [cited 2020 Sep 19]. Available from: http://resolver.tudelft.nl/uuid:40957c09-3edd-474c-b271-f67bda41d652.

Council of Science Editors:

Zhan X(. A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC. [Masters Thesis]. Delft University of Technology; 2018. Available from: http://resolver.tudelft.nl/uuid:40957c09-3edd-474c-b271-f67bda41d652


The Ohio State University

5. Ng, Sheung Yan. A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique.

Degree: PhD, Electrical and Computer Engineering, 2009, The Ohio State University

  This dissertation focuses on the circuit design techniques for an asynchronous sigma delta Analog to Digital Converter (ADC). The key advantage of this ADC(more)

Subjects/Keywords: Electrical Engineering; asynchronous sigma delta ADC; synchronous sigma delta ADC

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APA (6th Edition):

Ng, S. Y. (2009). A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906

Chicago Manual of Style (16th Edition):

Ng, Sheung Yan. “A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique.” 2009. Doctoral Dissertation, The Ohio State University. Accessed September 19, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906.

MLA Handbook (7th Edition):

Ng, Sheung Yan. “A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique.” 2009. Web. 19 Sep 2020.

Vancouver:

Ng SY. A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique. [Internet] [Doctoral dissertation]. The Ohio State University; 2009. [cited 2020 Sep 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906.

Council of Science Editors:

Ng SY. A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique. [Doctoral Dissertation]. The Ohio State University; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906


Delft University of Technology

6. Rout, S. (author). Structured Electronic Design of High-Pass ∆Σ Converters: And their application to cardiac signal acquisition.

Degree: 2016, Delft University of Technology

With the bandwidth of the ECG signal extending from sub-Hz to 200 Hz, a major challenge for an ECG readout system lies in implementing the… (more)

Subjects/Keywords: ECG; State-space forms; High-Pass ∆Σ; orthonormal topology; delta-sigma ADC

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APA (6th Edition):

Rout, S. (. (2016). Structured Electronic Design of High-Pass ∆Σ Converters: And their application to cardiac signal acquisition. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:f6903dcf-87e4-45a1-8a17-60699a478ab0

Chicago Manual of Style (16th Edition):

Rout, S (author). “Structured Electronic Design of High-Pass ∆Σ Converters: And their application to cardiac signal acquisition.” 2016. Masters Thesis, Delft University of Technology. Accessed September 19, 2020. http://resolver.tudelft.nl/uuid:f6903dcf-87e4-45a1-8a17-60699a478ab0.

MLA Handbook (7th Edition):

Rout, S (author). “Structured Electronic Design of High-Pass ∆Σ Converters: And their application to cardiac signal acquisition.” 2016. Web. 19 Sep 2020.

Vancouver:

Rout S(. Structured Electronic Design of High-Pass ∆Σ Converters: And their application to cardiac signal acquisition. [Internet] [Masters thesis]. Delft University of Technology; 2016. [cited 2020 Sep 19]. Available from: http://resolver.tudelft.nl/uuid:f6903dcf-87e4-45a1-8a17-60699a478ab0.

Council of Science Editors:

Rout S(. Structured Electronic Design of High-Pass ∆Σ Converters: And their application to cardiac signal acquisition. [Masters Thesis]. Delft University of Technology; 2016. Available from: http://resolver.tudelft.nl/uuid:f6903dcf-87e4-45a1-8a17-60699a478ab0


University of Toronto

7. Liang, Joshua. A Frequency-scalable 14-bit ADC for Low Power Sensor Applications.

Degree: 2009, University of Toronto

In this thesis, a 14-bit low-power Analog-to-Digital Converter (ADC) is designed for sensor applications. Following on previous work, the ADC is designed to be frequency… (more)

Subjects/Keywords: ADC; scalable; delta-sigma; incremental converter; 0544

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APA (6th Edition):

Liang, J. (2009). A Frequency-scalable 14-bit ADC for Low Power Sensor Applications. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/18802

Chicago Manual of Style (16th Edition):

Liang, Joshua. “A Frequency-scalable 14-bit ADC for Low Power Sensor Applications.” 2009. Masters Thesis, University of Toronto. Accessed September 19, 2020. http://hdl.handle.net/1807/18802.

MLA Handbook (7th Edition):

Liang, Joshua. “A Frequency-scalable 14-bit ADC for Low Power Sensor Applications.” 2009. Web. 19 Sep 2020.

Vancouver:

Liang J. A Frequency-scalable 14-bit ADC for Low Power Sensor Applications. [Internet] [Masters thesis]. University of Toronto; 2009. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1807/18802.

Council of Science Editors:

Liang J. A Frequency-scalable 14-bit ADC for Low Power Sensor Applications. [Masters Thesis]. University of Toronto; 2009. Available from: http://hdl.handle.net/1807/18802


Texas A&M University

8. Rashidi, Negar. Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator.

Degree: PhD, Electrical Engineering, 2016, Texas A&M University

 The demand for higher data rates in receivers with carrier aggregation (CA) such as LTE, increases the efforts to integrate large number of wireless services… (more)

Subjects/Keywords: Sigma Delta Modulator; ADC; Jitter tolerant; calibration

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APA (6th Edition):

Rashidi, N. (2016). Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/161272

Chicago Manual of Style (16th Edition):

Rashidi, Negar. “Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator.” 2016. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/161272.

MLA Handbook (7th Edition):

Rashidi, Negar. “Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator.” 2016. Web. 19 Sep 2020.

Vancouver:

Rashidi N. Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/161272.

Council of Science Editors:

Rashidi N. Low Noise, Jitter Tolerant Continuous-Time Sigma-Delta Modulator. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/161272


University of Akron

9. Karnati, Nikhil Reddy. A Power Efficient Polyphase Sharpened CIC Decimation Filter for Sigma-Delta ADCs.

Degree: MSin Engineering, Electrical Engineering, 2011, University of Akron

 The current thesis presents the design and implementation of a power-efficient poly-phase decimation filter for Sigma-delta ADCs. A cascade of Cascaded-Integrator Comb (CIC) filter and… (more)

Subjects/Keywords: Electrical Engineering; Sigma-delta ADC; decimation filter

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APA (6th Edition):

Karnati, N. R. (2011). A Power Efficient Polyphase Sharpened CIC Decimation Filter for Sigma-Delta ADCs. (Masters Thesis). University of Akron. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=akron1318130811

Chicago Manual of Style (16th Edition):

Karnati, Nikhil Reddy. “A Power Efficient Polyphase Sharpened CIC Decimation Filter for Sigma-Delta ADCs.” 2011. Masters Thesis, University of Akron. Accessed September 19, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=akron1318130811.

MLA Handbook (7th Edition):

Karnati, Nikhil Reddy. “A Power Efficient Polyphase Sharpened CIC Decimation Filter for Sigma-Delta ADCs.” 2011. Web. 19 Sep 2020.

Vancouver:

Karnati NR. A Power Efficient Polyphase Sharpened CIC Decimation Filter for Sigma-Delta ADCs. [Internet] [Masters thesis]. University of Akron; 2011. [cited 2020 Sep 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1318130811.

Council of Science Editors:

Karnati NR. A Power Efficient Polyphase Sharpened CIC Decimation Filter for Sigma-Delta ADCs. [Masters Thesis]. University of Akron; 2011. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1318130811


University of Texas – Austin

10. -1323-3431. System-level design and analysis of an embedded audio signal processing application.

Degree: MSin Engineering, Electrical and Computer engineering, 2016, University of Texas – Austin

 In this report, a design is proposed for an embedded system that implements an audio beamforming application. This design provides the key considerations for both… (more)

Subjects/Keywords: ADC; Delta-sigma; Beamforming; DSP; Matlab

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APA (6th Edition):

-1323-3431. (2016). System-level design and analysis of an embedded audio signal processing application. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/41717

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-1323-3431. “System-level design and analysis of an embedded audio signal processing application.” 2016. Masters Thesis, University of Texas – Austin. Accessed September 19, 2020. http://hdl.handle.net/2152/41717.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-1323-3431. “System-level design and analysis of an embedded audio signal processing application.” 2016. Web. 19 Sep 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-1323-3431. System-level design and analysis of an embedded audio signal processing application. [Internet] [Masters thesis]. University of Texas – Austin; 2016. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/2152/41717.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-1323-3431. System-level design and analysis of an embedded audio signal processing application. [Masters Thesis]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/41717

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

11. Chen, Tsai Yuan. Network Electrophysiology Sensor-On-A- Chip.

Degree: PhD, 2011, Worcester Polytechnic Institute

 " Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) bio-potential signals are commonly recorded in clinical practice. Typically, patients are connected to a bulky and mains-powered… (more)

Subjects/Keywords: EEG; ECG; EMG; Sigma-Delta ADC.

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APA (6th Edition):

Chen, T. Y. (2011). Network Electrophysiology Sensor-On-A- Chip. (Doctoral Dissertation). Worcester Polytechnic Institute. Retrieved from etd-092911-134747 ; https://digitalcommons.wpi.edu/etd-dissertations/389

Chicago Manual of Style (16th Edition):

Chen, Tsai Yuan. “Network Electrophysiology Sensor-On-A- Chip.” 2011. Doctoral Dissertation, Worcester Polytechnic Institute. Accessed September 19, 2020. etd-092911-134747 ; https://digitalcommons.wpi.edu/etd-dissertations/389.

MLA Handbook (7th Edition):

Chen, Tsai Yuan. “Network Electrophysiology Sensor-On-A- Chip.” 2011. Web. 19 Sep 2020.

Vancouver:

Chen TY. Network Electrophysiology Sensor-On-A- Chip. [Internet] [Doctoral dissertation]. Worcester Polytechnic Institute; 2011. [cited 2020 Sep 19]. Available from: etd-092911-134747 ; https://digitalcommons.wpi.edu/etd-dissertations/389.

Council of Science Editors:

Chen TY. Network Electrophysiology Sensor-On-A- Chip. [Doctoral Dissertation]. Worcester Polytechnic Institute; 2011. Available from: etd-092911-134747 ; https://digitalcommons.wpi.edu/etd-dissertations/389


Indian Institute of Science

12. Satyadev, Singh Kamlesh. 0.5V Subthreshold Region Operated Ultra Low Power Passive Sigma Delta ADC in 180 NM CMOS Technology.

Degree: MSc Engg, Engineering, 2019, Indian Institute of Science

 With increasing demand of IoT devices, medical devices, remote sensors; the design of low power analog interface is becoming focus. Generally, for low frequency applications… (more)

Subjects/Keywords: CMOS Technology; Sigma Delta Modulator; Sigma Delta ADC; IoT Devices; SDM ADC; Electrical Communication Engineering

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APA (6th Edition):

Satyadev, S. K. (2019). 0.5V Subthreshold Region Operated Ultra Low Power Passive Sigma Delta ADC in 180 NM CMOS Technology. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/4318

Chicago Manual of Style (16th Edition):

Satyadev, Singh Kamlesh. “0.5V Subthreshold Region Operated Ultra Low Power Passive Sigma Delta ADC in 180 NM CMOS Technology.” 2019. Masters Thesis, Indian Institute of Science. Accessed September 19, 2020. http://etd.iisc.ac.in/handle/2005/4318.

MLA Handbook (7th Edition):

Satyadev, Singh Kamlesh. “0.5V Subthreshold Region Operated Ultra Low Power Passive Sigma Delta ADC in 180 NM CMOS Technology.” 2019. Web. 19 Sep 2020.

Vancouver:

Satyadev SK. 0.5V Subthreshold Region Operated Ultra Low Power Passive Sigma Delta ADC in 180 NM CMOS Technology. [Internet] [Masters thesis]. Indian Institute of Science; 2019. [cited 2020 Sep 19]. Available from: http://etd.iisc.ac.in/handle/2005/4318.

Council of Science Editors:

Satyadev SK. 0.5V Subthreshold Region Operated Ultra Low Power Passive Sigma Delta ADC in 180 NM CMOS Technology. [Masters Thesis]. Indian Institute of Science; 2019. Available from: http://etd.iisc.ac.in/handle/2005/4318


Duke University

13. Aleksanyan, Arnak. Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications .

Degree: 2011, Duke University

  Many medical, environmental, and industrial control applications rely on wide-dynamic-range sensors and A/D converter systems. For most photo-detector-based applications, the input-current is integrated onto… (more)

Subjects/Keywords: Electrical Engineering; delta-sigma adc; low power sensor; programmable adc; rfid

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APA (6th Edition):

Aleksanyan, A. (2011). Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications . (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/3956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Aleksanyan, Arnak. “Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications .” 2011. Thesis, Duke University. Accessed September 19, 2020. http://hdl.handle.net/10161/3956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Aleksanyan, Arnak. “Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications .” 2011. Web. 19 Sep 2020.

Vancouver:

Aleksanyan A. Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications . [Internet] [Thesis]. Duke University; 2011. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/10161/3956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Aleksanyan A. Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications . [Thesis]. Duke University; 2011. Available from: http://hdl.handle.net/10161/3956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

14. Gundala, JayaKrishna. A study on the decimation stage of a Δ-Σ ADC with noise-shaping loop between the stages.

Degree: Electronics System, 2011, Linköping University

  The filter complexity in the multi-stage decimation system of a Δ-Σ ADC increases progressively as one moves to higher stages of decimation due to… (more)

Subjects/Keywords: Oversampling ratio; Noise-shaping; Δ-Σ ADC; Filter Optimization; FIR filter; CIC filter; Decimation; TECHNOLOGY; TEKNIKVETENSKAP

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APA (6th Edition):

Gundala, J. (2011). A study on the decimation stage of a Δ-Σ ADC with noise-shaping loop between the stages. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69319

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gundala, JayaKrishna. “A study on the decimation stage of a Δ-Σ ADC with noise-shaping loop between the stages.” 2011. Thesis, Linköping University. Accessed September 19, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69319.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gundala, JayaKrishna. “A study on the decimation stage of a Δ-Σ ADC with noise-shaping loop between the stages.” 2011. Web. 19 Sep 2020.

Vancouver:

Gundala J. A study on the decimation stage of a Δ-Σ ADC with noise-shaping loop between the stages. [Internet] [Thesis]. Linköping University; 2011. [cited 2020 Sep 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69319.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gundala J. A study on the decimation stage of a Δ-Σ ADC with noise-shaping loop between the stages. [Thesis]. Linköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69319

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

15. Miki, Takashi. An Open-Loop Amplifier Multi-Bit Sigma Delta Modulator.

Degree: MS, Electrical Engineering, 2017, Texas A&M University

 A new multi-bit quantizer for sigma delta modulators is proposed. The multi-bit quantizer has multiple single-bit quantizers, and the output of one of the single-bit… (more)

Subjects/Keywords: adc; multi-bit; quantizer; open-loop; open-loop amplifier; amplifier; sigma delta; delta sigma; sigma; delta; modulator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Miki, T. (2017). An Open-Loop Amplifier Multi-Bit Sigma Delta Modulator. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/169555

Chicago Manual of Style (16th Edition):

Miki, Takashi. “An Open-Loop Amplifier Multi-Bit Sigma Delta Modulator.” 2017. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/169555.

MLA Handbook (7th Edition):

Miki, Takashi. “An Open-Loop Amplifier Multi-Bit Sigma Delta Modulator.” 2017. Web. 19 Sep 2020.

Vancouver:

Miki T. An Open-Loop Amplifier Multi-Bit Sigma Delta Modulator. [Internet] [Masters thesis]. Texas A&M University; 2017. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/169555.

Council of Science Editors:

Miki T. An Open-Loop Amplifier Multi-Bit Sigma Delta Modulator. [Masters Thesis]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/169555


Brno University of Technology

16. Štraus, Pavel. Zvuková karta pro PC s obvodem FPGA: FPGA based sound card for PC.

Degree: 2019, Brno University of Technology

 This project deals with implementation of a first order Sigma–Delta AD converter on the FPGA. This ADC is design for an audio signal processing. ADC(more)

Subjects/Keywords: FPGA; VHDL; ADC; Sigma–Delta převodník; UDP datagram; FPGA; VHDL; ADC; Sigma–Delta converter; UDP datagram

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Štraus, P. (2019). Zvuková karta pro PC s obvodem FPGA: FPGA based sound card for PC. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/7122

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Štraus, Pavel. “Zvuková karta pro PC s obvodem FPGA: FPGA based sound card for PC.” 2019. Thesis, Brno University of Technology. Accessed September 19, 2020. http://hdl.handle.net/11012/7122.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Štraus, Pavel. “Zvuková karta pro PC s obvodem FPGA: FPGA based sound card for PC.” 2019. Web. 19 Sep 2020.

Vancouver:

Štraus P. Zvuková karta pro PC s obvodem FPGA: FPGA based sound card for PC. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/11012/7122.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Štraus P. Zvuková karta pro PC s obvodem FPGA: FPGA based sound card for PC. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/7122

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Berkeley

17. Wu, Chaoying (Charles). Next Generation Wireless Receiver Architecture Design in Deep-Sub-Micron CMOS Technology.

Degree: Electrical Engineering & Computer Sciences, 2014, University of California – Berkeley

 Current advances in wireless receiver technologies are primarily driven by the need for cost reduction through (1) integration of a radio, an ADC and a… (more)

Subjects/Keywords: Electrical engineering; ADC; LTE; Sigma Delta ADC; Software-Defined Radio; Wireless System

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, C. (. (2014). Next Generation Wireless Receiver Architecture Design in Deep-Sub-Micron CMOS Technology. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/34j0x04s

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Chaoying (Charles). “Next Generation Wireless Receiver Architecture Design in Deep-Sub-Micron CMOS Technology.” 2014. Thesis, University of California – Berkeley. Accessed September 19, 2020. http://www.escholarship.org/uc/item/34j0x04s.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Chaoying (Charles). “Next Generation Wireless Receiver Architecture Design in Deep-Sub-Micron CMOS Technology.” 2014. Web. 19 Sep 2020.

Vancouver:

Wu C(. Next Generation Wireless Receiver Architecture Design in Deep-Sub-Micron CMOS Technology. [Internet] [Thesis]. University of California – Berkeley; 2014. [cited 2020 Sep 19]. Available from: http://www.escholarship.org/uc/item/34j0x04s.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C(. Next Generation Wireless Receiver Architecture Design in Deep-Sub-Micron CMOS Technology. [Thesis]. University of California – Berkeley; 2014. Available from: http://www.escholarship.org/uc/item/34j0x04s

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

18. Chen, Hongbo. Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters.

Degree: MS, Electrical Engineering, 2012, Texas A&M University

 Nowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards… (more)

Subjects/Keywords: sigma delta data converter; reconfigurable ADC; quantizer; DAC

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APA (6th Edition):

Chen, H. (2012). Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10522

Chicago Manual of Style (16th Edition):

Chen, Hongbo. “Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters.” 2012. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10522.

MLA Handbook (7th Edition):

Chen, Hongbo. “Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters.” 2012. Web. 19 Sep 2020.

Vancouver:

Chen H. Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10522.

Council of Science Editors:

Chen H. Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10522


NSYSU

19. Luo, Wayne. 2.45 GHz ZigBee Receiver Frontend and Delta-Sigma ADC with Constant-gm Amplifier for Battery Management Systems.

Degree: Master, Electrical Engineering, 2012, NSYSU

 This thesis consists of two topics: A 2.45 GHz ZigBee Receiver Frontend design for home energy-saving systems and a Delta-Sigma ADC with constant-gm amplifier for… (more)

Subjects/Keywords: BMS; ZigBee; receiver; Delta-Sigma ADC; constant-gm amplifier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Luo, W. (2012). 2.45 GHz ZigBee Receiver Frontend and Delta-Sigma ADC with Constant-gm Amplifier for Battery Management Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0707112-015601

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Luo, Wayne. “2.45 GHz ZigBee Receiver Frontend and Delta-Sigma ADC with Constant-gm Amplifier for Battery Management Systems.” 2012. Thesis, NSYSU. Accessed September 19, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0707112-015601.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Luo, Wayne. “2.45 GHz ZigBee Receiver Frontend and Delta-Sigma ADC with Constant-gm Amplifier for Battery Management Systems.” 2012. Web. 19 Sep 2020.

Vancouver:

Luo W. 2.45 GHz ZigBee Receiver Frontend and Delta-Sigma ADC with Constant-gm Amplifier for Battery Management Systems. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Sep 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0707112-015601.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Luo W. 2.45 GHz ZigBee Receiver Frontend and Delta-Sigma ADC with Constant-gm Amplifier for Battery Management Systems. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0707112-015601

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. 西勝, 聡. ベクトルフィルタを用いた並列⊿ΣADCの提案 : Time-interleaved Delta sigma ADC using vector filters.

Degree: 2012, Hosei University / 法政大学

 We propose a method reducing the area of the circuit by using the vector filter for time inter-leaved delta-sigma AD converter (TIΔΣADC). TIΔΣADC can improve… (more)

Subjects/Keywords: Delta-sigma ADC; Time-interleaved; Vector filter; SC-integrator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

西勝, . (2012). ベクトルフィルタを用いた並列⊿ΣADCの提案 : Time-interleaved Delta sigma ADC using vector filters. (Thesis). Hosei University / 法政大学. Retrieved from http://hdl.handle.net/10114/7620

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

西勝, 聡. “ベクトルフィルタを用いた並列⊿ΣADCの提案 : Time-interleaved Delta sigma ADC using vector filters.” 2012. Thesis, Hosei University / 法政大学. Accessed September 19, 2020. http://hdl.handle.net/10114/7620.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

西勝, 聡. “ベクトルフィルタを用いた並列⊿ΣADCの提案 : Time-interleaved Delta sigma ADC using vector filters.” 2012. Web. 19 Sep 2020.

Vancouver:

西勝 . ベクトルフィルタを用いた並列⊿ΣADCの提案 : Time-interleaved Delta sigma ADC using vector filters. [Internet] [Thesis]. Hosei University / 法政大学; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/10114/7620.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

西勝 . ベクトルフィルタを用いた並列⊿ΣADCの提案 : Time-interleaved Delta sigma ADC using vector filters. [Thesis]. Hosei University / 法政大学; 2012. Available from: http://hdl.handle.net/10114/7620

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New South Wales

21. Irfansyah, Astria Nur. Sigma-delta modulation circuits with digital assistance.

Degree: Electrical Engineering & Telecommunications, 2016, University of New South Wales

 CMOS technology scaling has enabled sustained performance improvements of electronic circuits through faster, highly integrated, and more energy efficient digital circuits. In advanced nanometer CMOS… (more)

Subjects/Keywords: Digital-assistance; Sigma-delta; Positive-feedback; DAC; ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Irfansyah, A. N. (2016). Sigma-delta modulation circuits with digital assistance. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/56415 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:40683/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Irfansyah, Astria Nur. “Sigma-delta modulation circuits with digital assistance.” 2016. Doctoral Dissertation, University of New South Wales. Accessed September 19, 2020. http://handle.unsw.edu.au/1959.4/56415 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:40683/SOURCE02?view=true.

MLA Handbook (7th Edition):

Irfansyah, Astria Nur. “Sigma-delta modulation circuits with digital assistance.” 2016. Web. 19 Sep 2020.

Vancouver:

Irfansyah AN. Sigma-delta modulation circuits with digital assistance. [Internet] [Doctoral dissertation]. University of New South Wales; 2016. [cited 2020 Sep 19]. Available from: http://handle.unsw.edu.au/1959.4/56415 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:40683/SOURCE02?view=true.

Council of Science Editors:

Irfansyah AN. Sigma-delta modulation circuits with digital assistance. [Doctoral Dissertation]. University of New South Wales; 2016. Available from: http://handle.unsw.edu.au/1959.4/56415 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:40683/SOURCE02?view=true


University of Texas – Austin

22. Hamilton, Joseph Garrett. VCO-based analog-to-digital conversion.

Degree: PhD, Electrical and Computer Engineering, 2012, University of Texas – Austin

 This dissertation presents a novel [delta sigma] analog-to-digital converter architecture which replaces the operational amplifier-based integrator with a pair of tunable oscillators. A switched-capacitor V-I… (more)

Subjects/Keywords: VCO; Ring oscillator; Delta-sigma; ADC; Time-based

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APA (6th Edition):

Hamilton, J. G. (2012). VCO-based analog-to-digital conversion. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/22041

Chicago Manual of Style (16th Edition):

Hamilton, Joseph Garrett. “VCO-based analog-to-digital conversion.” 2012. Doctoral Dissertation, University of Texas – Austin. Accessed September 19, 2020. http://hdl.handle.net/2152/22041.

MLA Handbook (7th Edition):

Hamilton, Joseph Garrett. “VCO-based analog-to-digital conversion.” 2012. Web. 19 Sep 2020.

Vancouver:

Hamilton JG. VCO-based analog-to-digital conversion. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/2152/22041.

Council of Science Editors:

Hamilton JG. VCO-based analog-to-digital conversion. [Doctoral Dissertation]. University of Texas – Austin; 2012. Available from: http://hdl.handle.net/2152/22041


Arizona State University

23. Schmelter, Brooke. Dual Application ADC using Three Calibration Techniques in 10nm Technology.

Degree: Electrical Engineering, 2017, Arizona State University

 In this work, a 12-bit ADC with three types of calibration is proposed for high speed security applications as well as a precision application. This… (more)

Subjects/Keywords: Electrical engineering; 10nm; ADC; Calibration; Delta-Sigma; Dual Application

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APA (6th Edition):

Schmelter, B. (2017). Dual Application ADC using Three Calibration Techniques in 10nm Technology. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/45946

Chicago Manual of Style (16th Edition):

Schmelter, Brooke. “Dual Application ADC using Three Calibration Techniques in 10nm Technology.” 2017. Masters Thesis, Arizona State University. Accessed September 19, 2020. http://repository.asu.edu/items/45946.

MLA Handbook (7th Edition):

Schmelter, Brooke. “Dual Application ADC using Three Calibration Techniques in 10nm Technology.” 2017. Web. 19 Sep 2020.

Vancouver:

Schmelter B. Dual Application ADC using Three Calibration Techniques in 10nm Technology. [Internet] [Masters thesis]. Arizona State University; 2017. [cited 2020 Sep 19]. Available from: http://repository.asu.edu/items/45946.

Council of Science Editors:

Schmelter B. Dual Application ADC using Three Calibration Techniques in 10nm Technology. [Masters Thesis]. Arizona State University; 2017. Available from: http://repository.asu.edu/items/45946


Louisiana State University

24. Chamakura, Anand K. IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling ADC.

Degree: MS, Electrical and Computer Engineering, 2004, Louisiana State University

 This work presents IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling analog-to-digital converter using a built-in current sensor [BICS]. Gate-drain,… (more)

Subjects/Keywords: iddq; adc; sigma delta modulator

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APA (6th Edition):

Chamakura, A. K. (2004). IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling ADC. (Masters Thesis). Louisiana State University. Retrieved from etd-05272004-162258 ; https://digitalcommons.lsu.edu/gradschool_theses/2428

Chicago Manual of Style (16th Edition):

Chamakura, Anand K. “IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling ADC.” 2004. Masters Thesis, Louisiana State University. Accessed September 19, 2020. etd-05272004-162258 ; https://digitalcommons.lsu.edu/gradschool_theses/2428.

MLA Handbook (7th Edition):

Chamakura, Anand K. “IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling ADC.” 2004. Web. 19 Sep 2020.

Vancouver:

Chamakura AK. IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling ADC. [Internet] [Masters thesis]. Louisiana State University; 2004. [cited 2020 Sep 19]. Available from: etd-05272004-162258 ; https://digitalcommons.lsu.edu/gradschool_theses/2428.

Council of Science Editors:

Chamakura AK. IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling ADC. [Masters Thesis]. Louisiana State University; 2004. Available from: etd-05272004-162258 ; https://digitalcommons.lsu.edu/gradschool_theses/2428


Universidade do Rio Grande do Sul

25. Aguirre, Paulo Cesar Comassetto de. Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD.

Degree: 2014, Universidade do Rio Grande do Sul

Conversores analógico-digitais (ADCs) têm papel fundamental na implementação dos sistemas-em-chip, do inglês System-on-Chip (SoC), atuais. Em razão dos requisitos destes sistemas e dos compromissos entre… (more)

Subjects/Keywords: Sigma-delta modulation; Conversor analogico/digital; Continuous-time sigma-delta modulator; Modulação; Simulação numérica; Analog-to-digital converter (ADC); Behavioral modeling

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APA (6th Edition):

Aguirre, P. C. C. d. (2014). Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/105065

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Aguirre, Paulo Cesar Comassetto de. “Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed September 19, 2020. http://hdl.handle.net/10183/105065.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Aguirre, Paulo Cesar Comassetto de. “Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD.” 2014. Web. 19 Sep 2020.

Vancouver:

Aguirre PCCd. Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/10183/105065.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Aguirre PCCd. Projeto e análise de moduladores sigma-delta em tempo contínuo aplicados à conversão AD. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/105065

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Harikumar, Prakash. A Study on the Design of Reconfigurable ADCs.

Degree: The Institute of Technology, 2011, Linköping UniversityLinköping University

  Analog-to-Digital Converters (ADCs) can be classified into two categories namely Nyquist-rate ADCs and OversampledADCs. Nyquist-rate ADCs can process very high bandwidths while Oversampling ADCs… (more)

Subjects/Keywords: ADC; Sigma-Delta; Delta-Sigma; MASH; Pipelined; Reconfigurable; MDAC; Loop filter; Switched-Capacitor; SNDR; Time-interleaved; Flash; Electrical engineering; Elektroteknik

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APA (6th Edition):

Harikumar, P. (2011). A Study on the Design of Reconfigurable ADCs. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-67867

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harikumar, Prakash. “A Study on the Design of Reconfigurable ADCs.” 2011. Thesis, Linköping UniversityLinköping University. Accessed September 19, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-67867.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harikumar, Prakash. “A Study on the Design of Reconfigurable ADCs.” 2011. Web. 19 Sep 2020.

Vancouver:

Harikumar P. A Study on the Design of Reconfigurable ADCs. [Internet] [Thesis]. Linköping UniversityLinköping University; 2011. [cited 2020 Sep 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-67867.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harikumar P. A Study on the Design of Reconfigurable ADCs. [Thesis]. Linköping UniversityLinköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-67867

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

27. Valehrach, Ondřej. Návrh a realizace Sigma-Delta modulátoru v technice SC: Design of CMOS SC Sigma-Delta Modulator in i3t technology.

Degree: 2019, Brno University of Technology

 Design step for Sigma-Delta ADC is introduced. Suitable solution for performance improvement of the original Sigma-Delta ADC, which meets new requirements on resolution of 16… (more)

Subjects/Keywords: vícebitový Sigma-Delta modulátor; A/D převodník; DWA; DEM; multi-bit Sigma-Delta modulator; ADC; DWA; DEM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Valehrach, O. (2019). Návrh a realizace Sigma-Delta modulátoru v technice SC: Design of CMOS SC Sigma-Delta Modulator in i3t technology. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/9768

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Valehrach, Ondřej. “Návrh a realizace Sigma-Delta modulátoru v technice SC: Design of CMOS SC Sigma-Delta Modulator in i3t technology.” 2019. Thesis, Brno University of Technology. Accessed September 19, 2020. http://hdl.handle.net/11012/9768.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Valehrach, Ondřej. “Návrh a realizace Sigma-Delta modulátoru v technice SC: Design of CMOS SC Sigma-Delta Modulator in i3t technology.” 2019. Web. 19 Sep 2020.

Vancouver:

Valehrach O. Návrh a realizace Sigma-Delta modulátoru v technice SC: Design of CMOS SC Sigma-Delta Modulator in i3t technology. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/11012/9768.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Valehrach O. Návrh a realizace Sigma-Delta modulátoru v technice SC: Design of CMOS SC Sigma-Delta Modulator in i3t technology. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/9768

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

28. Staroň, Martin. Zvukové rozhraní pro průmyslový počítač: Audio Interface for Embedded PC.

Degree: 2019, Brno University of Technology

 The scope of my master thesis is a designing computer sound interface including measurement of audio performance. This work is concerning both design analog front… (more)

Subjects/Keywords: A/D; D/A; převod domén; zvuk; sigma delta; měření; ADC; DAC; domain conversion; audio; sigma-delta; oversampling; measuring

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Staroň, M. (2019). Zvukové rozhraní pro průmyslový počítač: Audio Interface for Embedded PC. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/6115

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Staroň, Martin. “Zvukové rozhraní pro průmyslový počítač: Audio Interface for Embedded PC.” 2019. Thesis, Brno University of Technology. Accessed September 19, 2020. http://hdl.handle.net/11012/6115.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Staroň, Martin. “Zvukové rozhraní pro průmyslový počítač: Audio Interface for Embedded PC.” 2019. Web. 19 Sep 2020.

Vancouver:

Staroň M. Zvukové rozhraní pro průmyslový počítač: Audio Interface for Embedded PC. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/11012/6115.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Staroň M. Zvukové rozhraní pro průmyslový počítač: Audio Interface for Embedded PC. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/6115

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

29. Soares, Antonio Wallace Antunes. Análise e projeto de um Conversor A/D Sigma Delta Incremental Multicanal de 4º Ordem .

Degree: 2018, Universidade do Rio Grande do Norte

 Several applications in the instrumentation field require signal acquisition systems with medium conversion rate and medium to high resolution, among them are the Multielectrode Matrices… (more)

Subjects/Keywords: Conversores analógicos digitais; Sigma delta incremental; Sigma delta; Quarta ordem; Aplicações biomédicas; Matrizes multieletrodos; Modelagem; Capacitores chaveados

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Soares, A. W. A. (2018). Análise e projeto de um Conversor A/D Sigma Delta Incremental Multicanal de 4º Ordem . (Doctoral Dissertation). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/26770

Chicago Manual of Style (16th Edition):

Soares, Antonio Wallace Antunes. “Análise e projeto de um Conversor A/D Sigma Delta Incremental Multicanal de 4º Ordem .” 2018. Doctoral Dissertation, Universidade do Rio Grande do Norte. Accessed September 19, 2020. http://repositorio.ufrn.br/handle/123456789/26770.

MLA Handbook (7th Edition):

Soares, Antonio Wallace Antunes. “Análise e projeto de um Conversor A/D Sigma Delta Incremental Multicanal de 4º Ordem .” 2018. Web. 19 Sep 2020.

Vancouver:

Soares AWA. Análise e projeto de um Conversor A/D Sigma Delta Incremental Multicanal de 4º Ordem . [Internet] [Doctoral dissertation]. Universidade do Rio Grande do Norte; 2018. [cited 2020 Sep 19]. Available from: http://repositorio.ufrn.br/handle/123456789/26770.

Council of Science Editors:

Soares AWA. Análise e projeto de um Conversor A/D Sigma Delta Incremental Multicanal de 4º Ordem . [Doctoral Dissertation]. Universidade do Rio Grande do Norte; 2018. Available from: http://repositorio.ufrn.br/handle/123456789/26770


Université de Bordeaux I

30. Mariano, André Augusto. Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications : Étude d'un émetteur numérique direct RF à base de synthétiseur numérique direct et de verrouillage par injection.

Degree: Docteur es, Electronique, 2008, Université de Bordeaux I

La chaîne de réception des téléphones mobiles de dernière génération utilisent au moins deux étages de transposition en fréquence avant d'effectuer la démodulation en quadrature.… (more)

Subjects/Keywords: Modulateur Sigma-Delta à temps continu; Convertisseur analogique-numérique; Modelisation comportementale; Convertisseur ultra-rapide; CAN Flash CMOS; High-Speed ADC; Continuous-time Delta-Sigma modulator; CMOS Flash ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mariano, A. A. (2008). Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications : Étude d'un émetteur numérique direct RF à base de synthétiseur numérique direct et de verrouillage par injection. (Doctoral Dissertation). Université de Bordeaux I. Retrieved from http://www.theses.fr/2008BOR13644

Chicago Manual of Style (16th Edition):

Mariano, André Augusto. “Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications : Étude d'un émetteur numérique direct RF à base de synthétiseur numérique direct et de verrouillage par injection.” 2008. Doctoral Dissertation, Université de Bordeaux I. Accessed September 19, 2020. http://www.theses.fr/2008BOR13644.

MLA Handbook (7th Edition):

Mariano, André Augusto. “Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications : Étude d'un émetteur numérique direct RF à base de synthétiseur numérique direct et de verrouillage par injection.” 2008. Web. 19 Sep 2020.

Vancouver:

Mariano AA. Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications : Étude d'un émetteur numérique direct RF à base de synthétiseur numérique direct et de verrouillage par injection. [Internet] [Doctoral dissertation]. Université de Bordeaux I; 2008. [cited 2020 Sep 19]. Available from: http://www.theses.fr/2008BOR13644.

Council of Science Editors:

Mariano AA. Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications : Étude d'un émetteur numérique direct RF à base de synthétiseur numérique direct et de verrouillage par injection. [Doctoral Dissertation]. Université de Bordeaux I; 2008. Available from: http://www.theses.fr/2008BOR13644

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