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You searched for subject:(Hyperspace Analog to Language). Showing records 1 – 30 of 69123 total matches.

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University of California – Riverside

1. Kaufman, Allison B. Assessing Animal Vocal Communication Using the Hyperspace Analog to Language (HAL) Model.

Degree: Neuroscience, 2010, University of California – Riverside

 The Hyperspace Analog to Language (HAL) model is used to measure contextual co-occurrence in human language (Lund & Burgess, 1996). In this dissertation, the HAL… (more)

Subjects/Keywords: Psychology, Cognitive; Biology, Zoology; Biology, General; animal cognition; animal communication; animal language; Chomsky; Hyperspace Analog to Language; linguistic modeling

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APA (6th Edition):

Kaufman, A. B. (2010). Assessing Animal Vocal Communication Using the Hyperspace Analog to Language (HAL) Model. (Thesis). University of California – Riverside. Retrieved from http://www.escholarship.org/uc/item/1sm4n21w

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kaufman, Allison B. “Assessing Animal Vocal Communication Using the Hyperspace Analog to Language (HAL) Model.” 2010. Thesis, University of California – Riverside. Accessed October 14, 2019. http://www.escholarship.org/uc/item/1sm4n21w.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kaufman, Allison B. “Assessing Animal Vocal Communication Using the Hyperspace Analog to Language (HAL) Model.” 2010. Web. 14 Oct 2019.

Vancouver:

Kaufman AB. Assessing Animal Vocal Communication Using the Hyperspace Analog to Language (HAL) Model. [Internet] [Thesis]. University of California – Riverside; 2010. [cited 2019 Oct 14]. Available from: http://www.escholarship.org/uc/item/1sm4n21w.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kaufman AB. Assessing Animal Vocal Communication Using the Hyperspace Analog to Language (HAL) Model. [Thesis]. University of California – Riverside; 2010. Available from: http://www.escholarship.org/uc/item/1sm4n21w

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Commonwealth University

2. Finegan, Edward Graham. Intelligent Autonomous Data Categorization.

Degree: MS, Computer Science, 2005, Virginia Commonwealth University

 The goal of this research was to determine if the results of a simple comparison algorithm (SCA) could be improved by adding a hyperspace analogue… (more)

Subjects/Keywords: data organization; internet search; high-dimensional memory model; hyperspace analogue to language; search engine; HAL; Computer Sciences; Physical Sciences and Mathematics

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APA (6th Edition):

Finegan, E. G. (2005). Intelligent Autonomous Data Categorization. (Thesis). Virginia Commonwealth University. Retrieved from https://scholarscompass.vcu.edu/etd/1343

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Finegan, Edward Graham. “Intelligent Autonomous Data Categorization.” 2005. Thesis, Virginia Commonwealth University. Accessed October 14, 2019. https://scholarscompass.vcu.edu/etd/1343.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Finegan, Edward Graham. “Intelligent Autonomous Data Categorization.” 2005. Web. 14 Oct 2019.

Vancouver:

Finegan EG. Intelligent Autonomous Data Categorization. [Internet] [Thesis]. Virginia Commonwealth University; 2005. [cited 2019 Oct 14]. Available from: https://scholarscompass.vcu.edu/etd/1343.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Finegan EG. Intelligent Autonomous Data Categorization. [Thesis]. Virginia Commonwealth University; 2005. Available from: https://scholarscompass.vcu.edu/etd/1343

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

3. Maghari, Nima. Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Delta-sigma analog-to-digital converters (ADCs) are suitable for many applications due to several advantages such as relaxed anti-aliasing filter, high signal-to noise and distortion ratio (SNDR)… (more)

Subjects/Keywords: Analog Ciruits; Analog-to-digital converters

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APA (6th Edition):

Maghari, N. (2010). Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/18851

Chicago Manual of Style (16th Edition):

Maghari, Nima. “Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/18851.

MLA Handbook (7th Edition):

Maghari, Nima. “Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters.” 2010. Web. 14 Oct 2019.

Vancouver:

Maghari N. Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/18851.

Council of Science Editors:

Maghari N. Architectural compensation techniques for analog inaccuracies in ΔΣ analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/18851


Oregon State University

4. Nishida, Yoshio. Improved design techniques for analog and mixed circuits.

Degree: PhD, Electrical and Computer Engineering, 2008, Oregon State University

 Although the digital revolution can realize many of past analog components in the digital forms, our world is surrounded with analog signals such as voice,… (more)

Subjects/Keywords: analog; Analog-to-digital converters  – Design

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APA (6th Edition):

Nishida, Y. (2008). Improved design techniques for analog and mixed circuits. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/7985

Chicago Manual of Style (16th Edition):

Nishida, Yoshio. “Improved design techniques for analog and mixed circuits.” 2008. Doctoral Dissertation, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/7985.

MLA Handbook (7th Edition):

Nishida, Yoshio. “Improved design techniques for analog and mixed circuits.” 2008. Web. 14 Oct 2019.

Vancouver:

Nishida Y. Improved design techniques for analog and mixed circuits. [Internet] [Doctoral dissertation]. Oregon State University; 2008. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/7985.

Council of Science Editors:

Nishida Y. Improved design techniques for analog and mixed circuits. [Doctoral Dissertation]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/7985


Oregon State University

5. Wang, Jingguang. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.

Degree: MS, Electrical and Computer Engineering, 2008, Oregon State University

 Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC… (more)

Subjects/Keywords: ADC; Analog-to-digital converters

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APA (6th Edition):

Wang, J. (2008). Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/10041

Chicago Manual of Style (16th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Masters Thesis, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/10041.

MLA Handbook (7th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Web. 14 Oct 2019.

Vancouver:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Internet] [Masters thesis]. Oregon State University; 2008. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/10041.

Council of Science Editors:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Masters Thesis]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/10041


Oregon State University

6. Hu, Yue. Efficient use of time information in analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University

 Time-domain data conversion has recently drawn increased research attention for its highly digital nature in favor of process technology scaling. Also, as the time information… (more)

Subjects/Keywords: Analog-to-digital converters

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APA (6th Edition):

Hu, Y. (2014). Efficient use of time information in analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/52553

Chicago Manual of Style (16th Edition):

Hu, Yue. “Efficient use of time information in analog-to-digital converters.” 2014. Doctoral Dissertation, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/52553.

MLA Handbook (7th Edition):

Hu, Yue. “Efficient use of time information in analog-to-digital converters.” 2014. Web. 14 Oct 2019.

Vancouver:

Hu Y. Efficient use of time information in analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/52553.

Council of Science Editors:

Hu Y. Efficient use of time information in analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/52553


Oregon State University

7. Tong, Tao. Design techniques for successive approximation register analog-to-digital converters.

Degree: MS, Electrical and Computer Engineering, 2011, Oregon State University

 Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently,… (more)

Subjects/Keywords: analog-to-digital converters

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APA (6th Edition):

Tong, T. (2011). Design techniques for successive approximation register analog-to-digital converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/22662

Chicago Manual of Style (16th Edition):

Tong, Tao. “Design techniques for successive approximation register analog-to-digital converters.” 2011. Masters Thesis, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/22662.

MLA Handbook (7th Edition):

Tong, Tao. “Design techniques for successive approximation register analog-to-digital converters.” 2011. Web. 14 Oct 2019.

Vancouver:

Tong T. Design techniques for successive approximation register analog-to-digital converters. [Internet] [Masters thesis]. Oregon State University; 2011. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/22662.

Council of Science Editors:

Tong T. Design techniques for successive approximation register analog-to-digital converters. [Masters Thesis]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/22662


Ryerson University

8. Park, Young Jun. Time-interleaved pulse-shrinking and all-digital time-to-digital converters.

Degree: 2017, Ryerson University

 This dissertation deals with the design of sub-per-stage delay time-to-digital converters (TDCs). Two classes of TDCs namely pulse-shrinking TDCs and TDCs are investigated. In pulse-shrinking… (more)

Subjects/Keywords: Analog-to-digital converters; Digital-to-analog converters

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APA (6th Edition):

Park, Y. J. (2017). Time-interleaved pulse-shrinking and all-digital time-to-digital converters. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Young Jun. “Time-interleaved pulse-shrinking and all-digital time-to-digital converters.” 2017. Thesis, Ryerson University. Accessed October 14, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A6433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Young Jun. “Time-interleaved pulse-shrinking and all-digital time-to-digital converters.” 2017. Web. 14 Oct 2019.

Vancouver:

Park YJ. Time-interleaved pulse-shrinking and all-digital time-to-digital converters. [Internet] [Thesis]. Ryerson University; 2017. [cited 2019 Oct 14]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park YJ. Time-interleaved pulse-shrinking and all-digital time-to-digital converters. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

9. Larsson, Andreas 1978-. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.

Degree: 2012, Texas A&M University

 The miniaturization and digitization of modern microelectronic systems have made Analog-to-Digital converters (ADC) key building components in many applications. Internet and entertainment technologies demand higher… (more)

Subjects/Keywords: Analog/Mixed Signal Design; Switched-Capacitor; Analog-To-Digital Converter (ADC)

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APA (6th Edition):

Larsson, A. 1. (2012). Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148307

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Larsson, Andreas 1978-. “Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.” 2012. Thesis, Texas A&M University. Accessed October 14, 2019. http://hdl.handle.net/1969.1/148307.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Larsson, Andreas 1978-. “Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters.” 2012. Web. 14 Oct 2019.

Vancouver:

Larsson A1. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1969.1/148307.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Larsson A1. Nyquist-Rate Switched-Capacitor Analog-to-Digital Converters. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/148307

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

10. Shirtliff, Jason Neil. Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters.

Degree: 2010, University of Waterloo

 Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum… (more)

Subjects/Keywords: analog circuit design; timing mismatches; interleaved analog to digital converters; microelectronics

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APA (6th Edition):

Shirtliff, J. N. (2010). Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/5523

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shirtliff, Jason Neil. “Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters.” 2010. Thesis, University of Waterloo. Accessed October 14, 2019. http://hdl.handle.net/10012/5523.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shirtliff, Jason Neil. “Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters.” 2010. Web. 14 Oct 2019.

Vancouver:

Shirtliff JN. Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters. [Internet] [Thesis]. University of Waterloo; 2010. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10012/5523.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shirtliff JN. Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters. [Thesis]. University of Waterloo; 2010. Available from: http://hdl.handle.net/10012/5523

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

11. Yang, Hwai Nien. The parallel axiom in N-dimensional hyperbolic space.

Degree: MS, Mathematics, 1961, Oregon State University

Subjects/Keywords: Hyperspace

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APA (6th Edition):

Yang, H. N. (1961). The parallel axiom in N-dimensional hyperbolic space. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/50511

Chicago Manual of Style (16th Edition):

Yang, Hwai Nien. “The parallel axiom in N-dimensional hyperbolic space.” 1961. Masters Thesis, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/50511.

MLA Handbook (7th Edition):

Yang, Hwai Nien. “The parallel axiom in N-dimensional hyperbolic space.” 1961. Web. 14 Oct 2019.

Vancouver:

Yang HN. The parallel axiom in N-dimensional hyperbolic space. [Internet] [Masters thesis]. Oregon State University; 1961. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/50511.

Council of Science Editors:

Yang HN. The parallel axiom in N-dimensional hyperbolic space. [Masters Thesis]. Oregon State University; 1961. Available from: http://hdl.handle.net/1957/50511


Michigan State University

12. Walcott, Margaret Grace. A study of the correspondence between points of a space of three dimensions and lines of a space of five dimensions.

Degree: MA, 1932, Michigan State University

Subjects/Keywords: Hyperspace

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APA (6th Edition):

Walcott, M. G. (1932). A study of the correspondence between points of a space of three dimensions and lines of a space of five dimensions. (Masters Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:13682

Chicago Manual of Style (16th Edition):

Walcott, Margaret Grace. “A study of the correspondence between points of a space of three dimensions and lines of a space of five dimensions.” 1932. Masters Thesis, Michigan State University. Accessed October 14, 2019. http://etd.lib.msu.edu/islandora/object/etd:13682.

MLA Handbook (7th Edition):

Walcott, Margaret Grace. “A study of the correspondence between points of a space of three dimensions and lines of a space of five dimensions.” 1932. Web. 14 Oct 2019.

Vancouver:

Walcott MG. A study of the correspondence between points of a space of three dimensions and lines of a space of five dimensions. [Internet] [Masters thesis]. Michigan State University; 1932. [cited 2019 Oct 14]. Available from: http://etd.lib.msu.edu/islandora/object/etd:13682.

Council of Science Editors:

Walcott MG. A study of the correspondence between points of a space of three dimensions and lines of a space of five dimensions. [Masters Thesis]. Michigan State University; 1932. Available from: http://etd.lib.msu.edu/islandora/object/etd:13682


Dalhousie University

13. D'souza, Rowena Joan. Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters.

Degree: Master of Applied Science, Department of Electrical & Computer Engineering, 2010, Dalhousie University

 This thesis presents a stable technique for distribution of data in Time Interleaved Digital-to-Analog Converters (TIDAC) that allows usage of the entire Nyquist bandwidth. The… (more)

Subjects/Keywords: Digital-to-analog converters; Time-interleaving

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APA (6th Edition):

D'souza, R. J. (2010). Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters. (Masters Thesis). Dalhousie University. Retrieved from http://hdl.handle.net/10222/12994

Chicago Manual of Style (16th Edition):

D'souza, Rowena Joan. “Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters.” 2010. Masters Thesis, Dalhousie University. Accessed October 14, 2019. http://hdl.handle.net/10222/12994.

MLA Handbook (7th Edition):

D'souza, Rowena Joan. “Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters.” 2010. Web. 14 Oct 2019.

Vancouver:

D'souza RJ. Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters. [Internet] [Masters thesis]. Dalhousie University; 2010. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10222/12994.

Council of Science Editors:

D'souza RJ. Mismatch Calibration of Time-Interleaved Digital-to-Analog Converters. [Masters Thesis]. Dalhousie University; 2010. Available from: http://hdl.handle.net/10222/12994

14. Meganathan D. A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;.

Degree: A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits, 2014, Anna University

High speed and medium resolution Analog to Digital Converters newline ADC are widely used in commercial applications including data newlinecommunication and image signal processing In… (more)

Subjects/Keywords: Analog to Digital Converters; Complementary Metal Oxide

Page 1

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APA (6th Edition):

D, M. (2014). A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/29245

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

D, Meganathan. “A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;.” 2014. Thesis, Anna University. Accessed October 14, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/29245.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

D, Meganathan. “A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;.” 2014. Web. 14 Oct 2019.

Vancouver:

D M. A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;. [Internet] [Thesis]. Anna University; 2014. [cited 2019 Oct 14]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/29245.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

D M. A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/29245

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

15. Rao, Sachin B. Linearizing techniques for voltage controlled oscillator based analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Voltage controlled oscillator (VCO) based ADC is an important class of time-domain ADC that has gained widespread acceptance due to their several desirable properties. VCO-based… (more)

Subjects/Keywords: VCO-based ADC; Analog-to-digital converters

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APA (6th Edition):

Rao, S. B. (2013). Linearizing techniques for voltage controlled oscillator based analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/38709

Chicago Manual of Style (16th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/38709.

MLA Handbook (7th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Web. 14 Oct 2019.

Vancouver:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/38709.

Council of Science Editors:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/38709


Oregon State University

16. Leung, Jerry. Data driven optimization in SAR ADC.

Degree: MS, Electrical and Computer Engineering, 2014, Oregon State University

 Recent publications show that successive approximation register (SAR) analog to digital converters (ADC) are capable of achieving high efficiency over other ADC topologies. Furthermore, techniques… (more)

Subjects/Keywords: SAR; Successive approximation analog-to-digital converters

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APA (6th Edition):

Leung, J. (2014). Data driven optimization in SAR ADC. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/54631

Chicago Manual of Style (16th Edition):

Leung, Jerry. “Data driven optimization in SAR ADC.” 2014. Masters Thesis, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/54631.

MLA Handbook (7th Edition):

Leung, Jerry. “Data driven optimization in SAR ADC.” 2014. Web. 14 Oct 2019.

Vancouver:

Leung J. Data driven optimization in SAR ADC. [Internet] [Masters thesis]. Oregon State University; 2014. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/54631.

Council of Science Editors:

Leung J. Data driven optimization in SAR ADC. [Masters Thesis]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/54631


Oregon State University

17. Waters, Allen. Automated verilog-to-layout synthesis of ADCs using custom analog cells.

Degree: PhD, Electrical and Computer Engineering, 2015, Oregon State University

 A procedure for automating the design and layout of analog-to-digital converters (ADCs) is presented. This procedure makes use of the existing synthesis and place-and-route tools… (more)

Subjects/Keywords: Analog-to-digital converters  – Design and construction

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APA (6th Edition):

Waters, A. (2015). Automated verilog-to-layout synthesis of ADCs using custom analog cells. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/55310

Chicago Manual of Style (16th Edition):

Waters, Allen. “Automated verilog-to-layout synthesis of ADCs using custom analog cells.” 2015. Doctoral Dissertation, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/55310.

MLA Handbook (7th Edition):

Waters, Allen. “Automated verilog-to-layout synthesis of ADCs using custom analog cells.” 2015. Web. 14 Oct 2019.

Vancouver:

Waters A. Automated verilog-to-layout synthesis of ADCs using custom analog cells. [Internet] [Doctoral dissertation]. Oregon State University; 2015. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/55310.

Council of Science Editors:

Waters A. Automated verilog-to-layout synthesis of ADCs using custom analog cells. [Doctoral Dissertation]. Oregon State University; 2015. Available from: http://hdl.handle.net/1957/55310


Hong Kong University of Science and Technology

18. Yang, Shiliang. A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration.

Degree: 2014, Hong Kong University of Science and Technology

 In the deep sub-micron process, the transistor intrinsic gain is low and the supply voltage is low, resulting in the great difficulty in designing a… (more)

Subjects/Keywords: Analog-to-digital converters; Calibration; Operational amplifiers

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APA (6th Edition):

Yang, S. (2014). A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1347291 ; http://repository.ust.hk/ir/bitstream/1783.1-71878/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Shiliang. “A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed October 14, 2019. https://doi.org/10.14711/thesis-b1347291 ; http://repository.ust.hk/ir/bitstream/1783.1-71878/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Shiliang. “A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration.” 2014. Web. 14 Oct 2019.

Vancouver:

Yang S. A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2019 Oct 14]. Available from: https://doi.org/10.14711/thesis-b1347291 ; http://repository.ust.hk/ir/bitstream/1783.1-71878/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang S. A reconfigurable pipelined-ΣΔ ADC with interpolation-based nonlinear calibration. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: https://doi.org/10.14711/thesis-b1347291 ; http://repository.ust.hk/ir/bitstream/1783.1-71878/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

19. Guerber, Jon. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and… (more)

Subjects/Keywords: SAR ADC; Analog-to-digital converters

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APA (6th Edition):

Guerber, J. (2012). Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/36019

Chicago Manual of Style (16th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Doctoral Dissertation, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/36019.

MLA Handbook (7th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Web. 14 Oct 2019.

Vancouver:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/36019.

Council of Science Editors:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/36019


Oregon State University

20. Shen, Weilun. Low-power double-sampled delta-sigma modulator for broadband applications.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on.… (more)

Subjects/Keywords: Analog-to-Digital Converter; Modulators (Electronics)

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APA (6th Edition):

Shen, W. (2010). Low-power double-sampled delta-sigma modulator for broadband applications. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/17568

Chicago Manual of Style (16th Edition):

Shen, Weilun. “Low-power double-sampled delta-sigma modulator for broadband applications.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/17568.

MLA Handbook (7th Edition):

Shen, Weilun. “Low-power double-sampled delta-sigma modulator for broadband applications.” 2010. Web. 14 Oct 2019.

Vancouver:

Shen W. Low-power double-sampled delta-sigma modulator for broadband applications. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/17568.

Council of Science Editors:

Shen W. Low-power double-sampled delta-sigma modulator for broadband applications. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/17568


Oregon State University

21. Musah, Tawfiq. Low power design techniques for analog-to-digital converters in submicron CMOS.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical… (more)

Subjects/Keywords: correlated level shifting; Analog-to-digital converters

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APA (6th Edition):

Musah, T. (2010). Low power design techniques for analog-to-digital converters in submicron CMOS. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/18826

Chicago Manual of Style (16th Edition):

Musah, Tawfiq. “Low power design techniques for analog-to-digital converters in submicron CMOS.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/18826.

MLA Handbook (7th Edition):

Musah, Tawfiq. “Low power design techniques for analog-to-digital converters in submicron CMOS.” 2010. Web. 14 Oct 2019.

Vancouver:

Musah T. Low power design techniques for analog-to-digital converters in submicron CMOS. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/18826.

Council of Science Editors:

Musah T. Low power design techniques for analog-to-digital converters in submicron CMOS. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/18826


Oregon State University

22. Chae, Jeong Seok. Novel structures for high-speed delta-sigma data converters.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 As CMOS processes keep scaling down devices, the maximum operating frequencies of CMOS devices increase, and hence circuits can process very wide band signals. Moreover,… (more)

Subjects/Keywords: Analog-to-digital converter; Modulators (Electronics)

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APA (6th Edition):

Chae, J. S. (2011). Novel structures for high-speed delta-sigma data converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/19813

Chicago Manual of Style (16th Edition):

Chae, Jeong Seok. “Novel structures for high-speed delta-sigma data converters.” 2011. Doctoral Dissertation, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/19813.

MLA Handbook (7th Edition):

Chae, Jeong Seok. “Novel structures for high-speed delta-sigma data converters.” 2011. Web. 14 Oct 2019.

Vancouver:

Chae JS. Novel structures for high-speed delta-sigma data converters. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/19813.

Council of Science Editors:

Chae JS. Novel structures for high-speed delta-sigma data converters. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/19813


Oregon State University

23. Zanbaghi, Ramin. Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high… (more)

Subjects/Keywords: delta-sigma modulator; Analog-to-digital converters

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APA (6th Edition):

Zanbaghi, R. (2011). Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/23456

Chicago Manual of Style (16th Edition):

Zanbaghi, Ramin. “Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters.” 2011. Doctoral Dissertation, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/23456.

MLA Handbook (7th Edition):

Zanbaghi, Ramin. “Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters.” 2011. Web. 14 Oct 2019.

Vancouver:

Zanbaghi R. Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/23456.

Council of Science Editors:

Zanbaghi R. Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/23456


Oregon State University

24. Oh, Taehwan. Power efficient analog-to-digital converters using both voltage and time domain information.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs… (more)

Subjects/Keywords: Delta-sigma; Analog-to-digital converters

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APA (6th Edition):

Oh, T. (2013). Power efficient analog-to-digital converters using both voltage and time domain information. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/39042

Chicago Manual of Style (16th Edition):

Oh, Taehwan. “Power efficient analog-to-digital converters using both voltage and time domain information.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 14, 2019. http://hdl.handle.net/1957/39042.

MLA Handbook (7th Edition):

Oh, Taehwan. “Power efficient analog-to-digital converters using both voltage and time domain information.” 2013. Web. 14 Oct 2019.

Vancouver:

Oh T. Power efficient analog-to-digital converters using both voltage and time domain information. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1957/39042.

Council of Science Editors:

Oh T. Power efficient analog-to-digital converters using both voltage and time domain information. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39042


Cornell University

25. Mukhopadhyay, Ishita. Variation Tolerant Calibration Circuits For High Performance I/O .

Degree: 2015, Cornell University

 Continuous scaling of CMOS processes leads to increasing integration of digital and analog subsystems on one chip. But the impact of process variation on these… (more)

Subjects/Keywords: digital to analog converter; process variation; calibration

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APA (6th Edition):

Mukhopadhyay, I. (2015). Variation Tolerant Calibration Circuits For High Performance I/O . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/39348

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mukhopadhyay, Ishita. “Variation Tolerant Calibration Circuits For High Performance I/O .” 2015. Thesis, Cornell University. Accessed October 14, 2019. http://hdl.handle.net/1813/39348.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mukhopadhyay, Ishita. “Variation Tolerant Calibration Circuits For High Performance I/O .” 2015. Web. 14 Oct 2019.

Vancouver:

Mukhopadhyay I. Variation Tolerant Calibration Circuits For High Performance I/O . [Internet] [Thesis]. Cornell University; 2015. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1813/39348.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mukhopadhyay I. Variation Tolerant Calibration Circuits For High Performance I/O . [Thesis]. Cornell University; 2015. Available from: http://hdl.handle.net/1813/39348

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Nairobi

26. Wafula, Michael J. Design of a PC Data Acquisition System .

Degree: 2014, University of Nairobi

 This report presents the design and implementation of a PC based data acquisition system. The aim of the project is to design a system that… (more)

Subjects/Keywords: Analogue to digital conversion; serial communication; Microcontroller; Sensors.

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APA (6th Edition):

Wafula, M. J. (2014). Design of a PC Data Acquisition System . (Thesis). University of Nairobi. Retrieved from http://hdl.handle.net/11295/71277

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wafula, Michael J. “Design of a PC Data Acquisition System .” 2014. Thesis, University of Nairobi. Accessed October 14, 2019. http://hdl.handle.net/11295/71277.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wafula, Michael J. “Design of a PC Data Acquisition System .” 2014. Web. 14 Oct 2019.

Vancouver:

Wafula MJ. Design of a PC Data Acquisition System . [Internet] [Thesis]. University of Nairobi; 2014. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/11295/71277.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wafula MJ. Design of a PC Data Acquisition System . [Thesis]. University of Nairobi; 2014. Available from: http://hdl.handle.net/11295/71277

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

27. Vasudevamurthy, Rajath. Time-based All-Digital Technique for Analog Built-in Self Test.

Degree: 2013, Indian Institute of Science

 A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis.… (more)

Subjects/Keywords: Electronic Circuits; On-Chip Analog Test Voltages; Electronic Circuit Design; Analog Circuits; Built-in Self Test (BIST); Time-to-Digital Converters; Analog Routing; Analog Built-in Self Test; Time Based Analog-to-Digital Converter; Analog-to-Digital Converters; Integrated Circuit; Analog IP Test; Electronic Engineering

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APA (6th Edition):

Vasudevamurthy, R. (2013). Time-based All-Digital Technique for Analog Built-in Self Test. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2013. Thesis, Indian Institute of Science. Accessed October 14, 2019. http://hdl.handle.net/2005/2841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2013. Web. 14 Oct 2019.

Vancouver:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/2005/2841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Thesis]. Indian Institute of Science; 2013. Available from: http://hdl.handle.net/2005/2841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

28. Mello, Israel Sperotto de. All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage.

Degree: 2015, Universidade do Rio Grande do Sul

 Desde os anos 80 a evolução dos processos de fabricação de circuitos integrados MOS tem buscado a redução da tensão de alimentação, como forma de… (more)

Subjects/Keywords: Microeletrônica; CMOS analog design; Circuitos digitais; Low voltage design; Digital to analog converter; Mismatch

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APA (6th Edition):

Mello, I. S. d. (2015). All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/169086

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mello, Israel Sperotto de. “All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed October 14, 2019. http://hdl.handle.net/10183/169086.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mello, Israel Sperotto de. “All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage.” 2015. Web. 14 Oct 2019.

Vancouver:

Mello ISd. All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10183/169086.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mello ISd. All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/169086

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Younis, Choudhry Jabbar. Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers.

Degree: The Institute of Technology, 2012, Linköping UniversityLinköping University

  Modern communication systems require higher data rates which have increased thedemand for high speed transceivers. For a system to work efficiently, all blocks ofthat… (more)

Subjects/Keywords: Analog front end; data rates; Analog to digital converter; track and hold; bootstrap; averaging; interpolation

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APA (6th Edition):

Younis, C. J. (2012). Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77178

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Younis, Choudhry Jabbar. “Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers.” 2012. Thesis, Linköping UniversityLinköping University. Accessed October 14, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77178.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Younis, Choudhry Jabbar. “Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers.” 2012. Web. 14 Oct 2019.

Vancouver:

Younis CJ. Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers. [Internet] [Thesis]. Linköping UniversityLinköping University; 2012. [cited 2019 Oct 14]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77178.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Younis CJ. Design and Implementation of a high-efficiency low-power analog-to-digital converter for high-speed transceivers. [Thesis]. Linköping UniversityLinköping University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77178

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

30. Bray, Adam. A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters.

Degree: 2013, University of Waterloo

 Time-interleaved analog-to-digital converters are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and… (more)

Subjects/Keywords: ADC; Analog to Digital Converter; Converters; Jitter; Timing Skew; Interleaved; TI-ADC; Time Interleaved; Analog

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APA (6th Edition):

Bray, A. (2013). A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/8053

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bray, Adam. “A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters.” 2013. Thesis, University of Waterloo. Accessed October 14, 2019. http://hdl.handle.net/10012/8053.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bray, Adam. “A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters.” 2013. Web. 14 Oct 2019.

Vancouver:

Bray A. A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters. [Internet] [Thesis]. University of Waterloo; 2013. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10012/8053.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bray A. A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters. [Thesis]. University of Waterloo; 2013. Available from: http://hdl.handle.net/10012/8053

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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