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You searched for subject:(Hybrid co simulation). Showing records 1 – 5 of 5 total matches.

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1. Hegde, Bharatkumar. Look-Ahead Energy Management Strategies for Hybrid Vehicles.

Degree: PhD, Mechanical Engineering, 2018, The Ohio State University

Hybrid electric vehicles are a result of a global push towards cleaner and fuel-efficient vehicles. They use both electrical and traditional fossil-fuel based energy sources,… (more)

Subjects/Keywords: Mechanical Engineering; Transportation; energy management; hybrid vehicle; look ahead control; traffic simulation; velocity prediction; electric vehicle; range extender; series hybrid; co-simulation

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APA (6th Edition):

Hegde, B. (2018). Look-Ahead Energy Management Strategies for Hybrid Vehicles. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu153199304661774

Chicago Manual of Style (16th Edition):

Hegde, Bharatkumar. “Look-Ahead Energy Management Strategies for Hybrid Vehicles.” 2018. Doctoral Dissertation, The Ohio State University. Accessed March 08, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu153199304661774.

MLA Handbook (7th Edition):

Hegde, Bharatkumar. “Look-Ahead Energy Management Strategies for Hybrid Vehicles.” 2018. Web. 08 Mar 2021.

Vancouver:

Hegde B. Look-Ahead Energy Management Strategies for Hybrid Vehicles. [Internet] [Doctoral dissertation]. The Ohio State University; 2018. [cited 2021 Mar 08]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu153199304661774.

Council of Science Editors:

Hegde B. Look-Ahead Energy Management Strategies for Hybrid Vehicles. [Doctoral Dissertation]. The Ohio State University; 2018. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu153199304661774

2. Marc, Nicolas. Méthodologie de dimensionnement d’un véhicule hybride électrique sous contrainte de minimisation des émissions de CO2 : Hybrid electric vehicle sizing methodology under CO2 emissions minimization constraint.

Degree: Docteur es, Energétique, 2013, Université d'Orléans

Ce travail de thèse propose une méthodologie systématique d’évaluation et de comparaison des gains en émissions de CO2 de véhicules hybrides électriques de différentes architectures… (more)

Subjects/Keywords: Véhicule hybride électrique rechargeable; S&S; Architecture hybride parallèle pré-transmission; Dimensionnement; Co-simulation; Gestion optimale de l’énergie; EMS; PMP; HEV; PHEV; S&S; Full hybrid; Sizing; Co-simulation; Parallel hybrid; Optimal energy management; EMS; PMP; 629.229

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APA (6th Edition):

Marc, N. (2013). Méthodologie de dimensionnement d’un véhicule hybride électrique sous contrainte de minimisation des émissions de CO2 : Hybrid electric vehicle sizing methodology under CO2 emissions minimization constraint. (Doctoral Dissertation). Université d'Orléans. Retrieved from http://www.theses.fr/2013ORLE2078

Chicago Manual of Style (16th Edition):

Marc, Nicolas. “Méthodologie de dimensionnement d’un véhicule hybride électrique sous contrainte de minimisation des émissions de CO2 : Hybrid electric vehicle sizing methodology under CO2 emissions minimization constraint.” 2013. Doctoral Dissertation, Université d'Orléans. Accessed March 08, 2021. http://www.theses.fr/2013ORLE2078.

MLA Handbook (7th Edition):

Marc, Nicolas. “Méthodologie de dimensionnement d’un véhicule hybride électrique sous contrainte de minimisation des émissions de CO2 : Hybrid electric vehicle sizing methodology under CO2 emissions minimization constraint.” 2013. Web. 08 Mar 2021.

Vancouver:

Marc N. Méthodologie de dimensionnement d’un véhicule hybride électrique sous contrainte de minimisation des émissions de CO2 : Hybrid electric vehicle sizing methodology under CO2 emissions minimization constraint. [Internet] [Doctoral dissertation]. Université d'Orléans; 2013. [cited 2021 Mar 08]. Available from: http://www.theses.fr/2013ORLE2078.

Council of Science Editors:

Marc N. Méthodologie de dimensionnement d’un véhicule hybride électrique sous contrainte de minimisation des émissions de CO2 : Hybrid electric vehicle sizing methodology under CO2 emissions minimization constraint. [Doctoral Dissertation]. Université d'Orléans; 2013. Available from: http://www.theses.fr/2013ORLE2078

3. Ranaivoniarivo, Manohiaina. Modélisation, caractérisation et analyse de systèmes de PLL intégrés, utilisant une approche globale puce-boîtier-circuit imprimé : Modeling, characterization and analysis of integrated PLL systems using a global chip-package-board approach.

Degree: Docteur es, Electronique, Optronique et Systèmes, 2011, Université Paris-Est

Cette thèse porte sur la caractérisation, la modélisation et l'analyse des phénomènes de «Pulling» et de «Pushing» dans les systèmes de boucles à verrouillage de… (more)

Subjects/Keywords: Pll; Effets de Pulling et de Pushing; Couplages électromagnétique; Co-simulation puce-boîtier-circuit imprimé; Méthodologies hybrides; Modélisation comportementale; Pll; Pulling and Pushing effects; Electromagnetic couplings; Chip-package-board co-simulation; Hybrid methodologies; Behavioral modeling

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APA (6th Edition):

Ranaivoniarivo, M. (2011). Modélisation, caractérisation et analyse de systèmes de PLL intégrés, utilisant une approche globale puce-boîtier-circuit imprimé : Modeling, characterization and analysis of integrated PLL systems using a global chip-package-board approach. (Doctoral Dissertation). Université Paris-Est. Retrieved from http://www.theses.fr/2011PEST1045

Chicago Manual of Style (16th Edition):

Ranaivoniarivo, Manohiaina. “Modélisation, caractérisation et analyse de systèmes de PLL intégrés, utilisant une approche globale puce-boîtier-circuit imprimé : Modeling, characterization and analysis of integrated PLL systems using a global chip-package-board approach.” 2011. Doctoral Dissertation, Université Paris-Est. Accessed March 08, 2021. http://www.theses.fr/2011PEST1045.

MLA Handbook (7th Edition):

Ranaivoniarivo, Manohiaina. “Modélisation, caractérisation et analyse de systèmes de PLL intégrés, utilisant une approche globale puce-boîtier-circuit imprimé : Modeling, characterization and analysis of integrated PLL systems using a global chip-package-board approach.” 2011. Web. 08 Mar 2021.

Vancouver:

Ranaivoniarivo M. Modélisation, caractérisation et analyse de systèmes de PLL intégrés, utilisant une approche globale puce-boîtier-circuit imprimé : Modeling, characterization and analysis of integrated PLL systems using a global chip-package-board approach. [Internet] [Doctoral dissertation]. Université Paris-Est; 2011. [cited 2021 Mar 08]. Available from: http://www.theses.fr/2011PEST1045.

Council of Science Editors:

Ranaivoniarivo M. Modélisation, caractérisation et analyse de systèmes de PLL intégrés, utilisant une approche globale puce-boîtier-circuit imprimé : Modeling, characterization and analysis of integrated PLL systems using a global chip-package-board approach. [Doctoral Dissertation]. Université Paris-Est; 2011. Available from: http://www.theses.fr/2011PEST1045

4. Loghavi, Saeid. Modeling, control analysis, and multi-physics co-simulation supporting high-performance hybrid-electric vehicles.

Degree: MS, Mechanical Engineering, 2017, Georgia Tech

 This thesis presents a series of model-based studies and associated considerations supporting the development of a high-performance HEV. Due to increasingly strict governmental regulations and… (more)

Subjects/Keywords: Hybrid-electric vehicle; Multi-physics co-simulation; Electro-thermal model

…properties of the coolant 58 Table 4.6: Definition of Connectors in co-simulation configuration… …58 Figure 4.14: Fluid domain interactions 58 Figure 4.15: Co-simulation process 60… …Figure 4.16: Definition of co-simulation parameters (Abaqus Standard model) 61… …Figure 4.17: Definition of co-simulation parameters (Abaqus Fluid model). 62 Figure… …4.18: Co-simulation configuration file document header 64 Figure 4.19: Configuration file… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Loghavi, S. (2017). Modeling, control analysis, and multi-physics co-simulation supporting high-performance hybrid-electric vehicles. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58751

Chicago Manual of Style (16th Edition):

Loghavi, Saeid. “Modeling, control analysis, and multi-physics co-simulation supporting high-performance hybrid-electric vehicles.” 2017. Masters Thesis, Georgia Tech. Accessed March 08, 2021. http://hdl.handle.net/1853/58751.

MLA Handbook (7th Edition):

Loghavi, Saeid. “Modeling, control analysis, and multi-physics co-simulation supporting high-performance hybrid-electric vehicles.” 2017. Web. 08 Mar 2021.

Vancouver:

Loghavi S. Modeling, control analysis, and multi-physics co-simulation supporting high-performance hybrid-electric vehicles. [Internet] [Masters thesis]. Georgia Tech; 2017. [cited 2021 Mar 08]. Available from: http://hdl.handle.net/1853/58751.

Council of Science Editors:

Loghavi S. Modeling, control analysis, and multi-physics co-simulation supporting high-performance hybrid-electric vehicles. [Masters Thesis]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58751

5. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…Hardware-Software Co-Simulation” [3]. Chapter 9 is based on a publication to appear in… …x28;e.g., RTL) simulation. 3. Hybrid hashing does not require designer-crafted… …12 12 14 17 CHAPTER 3 RELATED WORK . . 3.1 Hybrid Quick Error Detection 3.2 Modulo Shadow… …19 19 21 23 CHAPTER 4 HYBRID QUICK ERROR DETECTION 4.1 Basic Principles… …4.2 Hybrid Tracing vs. Hybrid Hashing . . . . . . . 4.3 Effectiveness and Practicality… 

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APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 08, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 08 Mar 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 08]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

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