Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

You searched for subject:(Hybrid Memory Models). One record found.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters

1. Kumar, Pankaj. Analysis of memory architecture of parallel processing computer.

Degree: Computer Science, 2010, Integral University

In modern time the focus of parallel computer development is being shifted from the processor perspective to the memory system perspective. If we will go to the Moore’s law, we will find the reason, which says that the performance of processor generally doubled in every year, whereas in recent year the performance of memory is increasing minutely, which causes an increasing discrepancy between processor & memory. So it becomes necessary to design a principle for memory architecture of parallel computer. Lots of memory architecture for parallel computer are designed so for. The research gives an extensive view of different memory architecture used in parallel computer; mainly it covers shared memory. After analyzing different memory architecture for shared memory abstraction, we choose Distributed Shared Memory (DSM) architecture for our research work. The performance and the programmability of the DSM system depend upon the Memory Consistency Model and Memory Coherency. The memory consistency model of a DSM system specifies the ordering constraints on concurrent memory accesses by multiple processors. Lots of Consistency Model are defined by a wide variety of source including architecture system, application programmer etc.

Conclusion p. 196-201, Appendix p. 202-209, Bibliography p. 210-218

Advisors/Committee Members: Bal, Gopal, Beg, Rizwan.

Subjects/Keywords: Parallel Processing System; Computer applications; DSM System; DSM Architecture; Uniform Memory Model; Hybrid Memory Models

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kumar, P. (2010). Analysis of memory architecture of parallel processing computer. (Thesis). Integral University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/3398

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kumar, Pankaj. “Analysis of memory architecture of parallel processing computer.” 2010. Thesis, Integral University. Accessed July 15, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/3398.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kumar, Pankaj. “Analysis of memory architecture of parallel processing computer.” 2010. Web. 15 Jul 2020.

Vancouver:

Kumar P. Analysis of memory architecture of parallel processing computer. [Internet] [Thesis]. Integral University; 2010. [cited 2020 Jul 15]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/3398.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kumar P. Analysis of memory architecture of parallel processing computer. [Thesis]. Integral University; 2010. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/3398

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.