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You searched for subject:(High performance processors). Showing records 1 – 30 of 31 total matches.

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Ryerson University

1. Khogali, Rashid. Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors.

Degree: 2013, Ryerson University

 We synthesize online scheduling algorithms to optimally assign a set of arriving heterogeneous tasks to heterogeneous speed-scalable processors under the single threaded computing architecture. By… (more)

Subjects/Keywords: High performance processors

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APA (6th Edition):

Khogali, R. (2013). Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A2919

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Khogali, Rashid. “Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors.” 2013. Thesis, Ryerson University. Accessed April 23, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A2919.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Khogali, Rashid. “Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors.” 2013. Web. 23 Apr 2019.

Vancouver:

Khogali R. Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors. [Internet] [Thesis]. Ryerson University; 2013. [cited 2019 Apr 23]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A2919.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Khogali R. Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors. [Thesis]. Ryerson University; 2013. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A2919

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

2. Sathe, Nikhil. Thermal modeling of many-core processors.

Degree: MS, Electrical and Computer Engineering, 2010, Georgia Tech

 Sustaining high performance demand has led to the development of manycore processors. These manycore processors have thermal properties which are different from conventional processors. In… (more)

Subjects/Keywords: Weight based thermal management; Manycore processors; Thermal management; High performance processors; Heat Transmission; Waste heat

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APA (6th Edition):

Sathe, N. (2010). Thermal modeling of many-core processors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/34834

Chicago Manual of Style (16th Edition):

Sathe, Nikhil. “Thermal modeling of many-core processors.” 2010. Masters Thesis, Georgia Tech. Accessed April 23, 2019. http://hdl.handle.net/1853/34834.

MLA Handbook (7th Edition):

Sathe, Nikhil. “Thermal modeling of many-core processors.” 2010. Web. 23 Apr 2019.

Vancouver:

Sathe N. Thermal modeling of many-core processors. [Internet] [Masters thesis]. Georgia Tech; 2010. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/1853/34834.

Council of Science Editors:

Sathe N. Thermal modeling of many-core processors. [Masters Thesis]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/34834


University of New Mexico

3. Laros, James Howard, III. Measuring and tuning energy efficiency on large scale high performance computing platforms.

Degree: Electrical and Computer Engineering, 2012, University of New Mexico

 Recognition of the importance of power in the field of High Performance Computing, whether it be as an obstacle, expense or design consideration, has never… (more)

Subjects/Keywords: Computer platforms – Energy consumption – Measurement; High performance processors – Energy consumption – Measurement; High performance computing.

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APA (6th Edition):

Laros, James Howard, I. (2012). Measuring and tuning energy efficiency on large scale high performance computing platforms. (Masters Thesis). University of New Mexico. Retrieved from http://hdl.handle.net/1928/20773

Chicago Manual of Style (16th Edition):

Laros, James Howard, III. “Measuring and tuning energy efficiency on large scale high performance computing platforms.” 2012. Masters Thesis, University of New Mexico. Accessed April 23, 2019. http://hdl.handle.net/1928/20773.

MLA Handbook (7th Edition):

Laros, James Howard, III. “Measuring and tuning energy efficiency on large scale high performance computing platforms.” 2012. Web. 23 Apr 2019.

Vancouver:

Laros, James Howard I. Measuring and tuning energy efficiency on large scale high performance computing platforms. [Internet] [Masters thesis]. University of New Mexico; 2012. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/1928/20773.

Council of Science Editors:

Laros, James Howard I. Measuring and tuning energy efficiency on large scale high performance computing platforms. [Masters Thesis]. University of New Mexico; 2012. Available from: http://hdl.handle.net/1928/20773


Georgia Tech

4. VanDerheyden, Andrew Louis. Characterization of thermal coupling in chip multiprocessors.

Degree: MS, Electrical and Computer Engineering, 2014, Georgia Tech

 For semiconductor processors temperature increases leakage current, which in turn in- creases the temperature of the processor. This increase in heat is seen by other… (more)

Subjects/Keywords: Thermal management; Thermal characterization; Thermal coupling; High performance processors; Thermal analysis

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APA (6th Edition):

VanDerheyden, A. L. (2014). Characterization of thermal coupling in chip multiprocessors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51892

Chicago Manual of Style (16th Edition):

VanDerheyden, Andrew Louis. “Characterization of thermal coupling in chip multiprocessors.” 2014. Masters Thesis, Georgia Tech. Accessed April 23, 2019. http://hdl.handle.net/1853/51892.

MLA Handbook (7th Edition):

VanDerheyden, Andrew Louis. “Characterization of thermal coupling in chip multiprocessors.” 2014. Web. 23 Apr 2019.

Vancouver:

VanDerheyden AL. Characterization of thermal coupling in chip multiprocessors. [Internet] [Masters thesis]. Georgia Tech; 2014. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/1853/51892.

Council of Science Editors:

VanDerheyden AL. Characterization of thermal coupling in chip multiprocessors. [Masters Thesis]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51892


Virginia Tech

5. Li, Dong. Scalable and Energy Efficient Execution Methods for Multicore Systems.

Degree: PhD, Computer Science, 2011, Virginia Tech

 Multicore architectures impose great pressure on resource management. The exploration spaces available for resource management increase explosively, especially for large-scale high end computing systems. The… (more)

Subjects/Keywords: Performance Modeling and Analysis; Multicore Processors; Power-Aware Computing; Concurrency Throttling; High-Performance Computing

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APA (6th Edition):

Li, D. (2011). Scalable and Energy Efficient Execution Methods for Multicore Systems. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/26098

Chicago Manual of Style (16th Edition):

Li, Dong. “Scalable and Energy Efficient Execution Methods for Multicore Systems.” 2011. Doctoral Dissertation, Virginia Tech. Accessed April 23, 2019. http://hdl.handle.net/10919/26098.

MLA Handbook (7th Edition):

Li, Dong. “Scalable and Energy Efficient Execution Methods for Multicore Systems.” 2011. Web. 23 Apr 2019.

Vancouver:

Li D. Scalable and Energy Efficient Execution Methods for Multicore Systems. [Internet] [Doctoral dissertation]. Virginia Tech; 2011. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/10919/26098.

Council of Science Editors:

Li D. Scalable and Energy Efficient Execution Methods for Multicore Systems. [Doctoral Dissertation]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/26098


Georgia Tech

6. Woo, Dong Hyuk. Designing heterogeneous many-core processors to provide high performance under limited chip power budget.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 This thesis describes the efficient design of a future many-core processor that can provide higher performance under the limited chip power budget. To achieve such… (more)

Subjects/Keywords: Heterogeneous many-core architecture; Heterogeneous computing; Parallel processing (Electronic computers); Multiprocessors; Microprocessors; High performance processors

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APA (6th Edition):

Woo, D. H. (2010). Designing heterogeneous many-core processors to provide high performance under limited chip power budget. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/37294

Chicago Manual of Style (16th Edition):

Woo, Dong Hyuk. “Designing heterogeneous many-core processors to provide high performance under limited chip power budget.” 2010. Doctoral Dissertation, Georgia Tech. Accessed April 23, 2019. http://hdl.handle.net/1853/37294.

MLA Handbook (7th Edition):

Woo, Dong Hyuk. “Designing heterogeneous many-core processors to provide high performance under limited chip power budget.” 2010. Web. 23 Apr 2019.

Vancouver:

Woo DH. Designing heterogeneous many-core processors to provide high performance under limited chip power budget. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/1853/37294.

Council of Science Editors:

Woo DH. Designing heterogeneous many-core processors to provide high performance under limited chip power budget. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/37294


University of Victoria

7. Atoofian, Ehsan. Energy and performance improvement relying on trivial instructions and speculative snooping in high-performance processors.

Degree: Dept. of Electrical and Computer Engineering, 2010, University of Victoria

 This thesis introduces energy and performance optimization techniques for high-performance processors. Our optimization techniques target both single processors and chip multiprocessors (CMPs). In single processors,… (more)

Subjects/Keywords: High-performance processors; Multiprocessors; UVic Subject Index::Sciences and Engineering::Applied Sciences::Computer science

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APA (6th Edition):

Atoofian, E. (2010). Energy and performance improvement relying on trivial instructions and speculative snooping in high-performance processors. (Thesis). University of Victoria. Retrieved from http://hdl.handle.net/1828/2568

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Atoofian, Ehsan. “Energy and performance improvement relying on trivial instructions and speculative snooping in high-performance processors.” 2010. Thesis, University of Victoria. Accessed April 23, 2019. http://hdl.handle.net/1828/2568.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Atoofian, Ehsan. “Energy and performance improvement relying on trivial instructions and speculative snooping in high-performance processors.” 2010. Web. 23 Apr 2019.

Vancouver:

Atoofian E. Energy and performance improvement relying on trivial instructions and speculative snooping in high-performance processors. [Internet] [Thesis]. University of Victoria; 2010. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/1828/2568.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Atoofian E. Energy and performance improvement relying on trivial instructions and speculative snooping in high-performance processors. [Thesis]. University of Victoria; 2010. Available from: http://hdl.handle.net/1828/2568

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New Mexico

8. Dosanjh, Matthew G. F. Improving HPC Communication Library Performance on Modern Architectures.

Degree: Department of Computer Science, 2017, University of New Mexico

  As high-performance computing (HPC) systems advance towards exascale (1018 operations per second), they must leverage increasing levels of parallelism to achieve their performance goals.… (more)

Subjects/Keywords: High Performance Computing; MPI; Many Core Processors; Networking; Digital Communications and Networking; OS and Networks

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APA (6th Edition):

Dosanjh, M. G. F. (2017). Improving HPC Communication Library Performance on Modern Architectures. (Doctoral Dissertation). University of New Mexico. Retrieved from https://digitalrepository.unm.edu/cs_etds/88

Chicago Manual of Style (16th Edition):

Dosanjh, Matthew G F. “Improving HPC Communication Library Performance on Modern Architectures.” 2017. Doctoral Dissertation, University of New Mexico. Accessed April 23, 2019. https://digitalrepository.unm.edu/cs_etds/88.

MLA Handbook (7th Edition):

Dosanjh, Matthew G F. “Improving HPC Communication Library Performance on Modern Architectures.” 2017. Web. 23 Apr 2019.

Vancouver:

Dosanjh MGF. Improving HPC Communication Library Performance on Modern Architectures. [Internet] [Doctoral dissertation]. University of New Mexico; 2017. [cited 2019 Apr 23]. Available from: https://digitalrepository.unm.edu/cs_etds/88.

Council of Science Editors:

Dosanjh MGF. Improving HPC Communication Library Performance on Modern Architectures. [Doctoral Dissertation]. University of New Mexico; 2017. Available from: https://digitalrepository.unm.edu/cs_etds/88


University of Rochester

9. Balasubramonian, Rajeev. Dynamic Management of Microarchitecture Resources in Future Microprocessors.

Degree: PhD, 2009, University of Rochester

 Improvements in technology have resulted in steadily improving microprocessor performance. However, the shrinking of process technologies and increasing clock speeds introduce new bottlenecks to performance,… (more)

Subjects/Keywords: low-power microarchitectures; data caches; register files; clustered processors; high-performance microprocessors; memory hierarchy bottlenecks

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APA (6th Edition):

Balasubramonian, R. (2009). Dynamic Management of Microarchitecture Resources in Future Microprocessors. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/821

Chicago Manual of Style (16th Edition):

Balasubramonian, Rajeev. “Dynamic Management of Microarchitecture Resources in Future Microprocessors.” 2009. Doctoral Dissertation, University of Rochester. Accessed April 23, 2019. http://hdl.handle.net/1802/821.

MLA Handbook (7th Edition):

Balasubramonian, Rajeev. “Dynamic Management of Microarchitecture Resources in Future Microprocessors.” 2009. Web. 23 Apr 2019.

Vancouver:

Balasubramonian R. Dynamic Management of Microarchitecture Resources in Future Microprocessors. [Internet] [Doctoral dissertation]. University of Rochester; 2009. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/1802/821.

Council of Science Editors:

Balasubramonian R. Dynamic Management of Microarchitecture Resources in Future Microprocessors. [Doctoral Dissertation]. University of Rochester; 2009. Available from: http://hdl.handle.net/1802/821


Penn State University

10. Jadidi, Amin. ARCHITECTURAL TECHNIQUES TO ENABLE RELIABLE AND HIGH PERFORMANCE MEMORY HIERARCHY IN CHIP MULTI-PROCESSORS.

Degree: 2018, Penn State University

 Constant technology scaling has enabled modern computing systems to achieve high degrees of thread-level parallelism, making the design of a highly scalable and dense memory… (more)

Subjects/Keywords: Memory Hierarchy; Non-volatile Memory Technologies; Hybrid Memory Hierarchy; Reliability; High Performance; Chip Multi-Processors

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APA (6th Edition):

Jadidi, A. (2018). ARCHITECTURAL TECHNIQUES TO ENABLE RELIABLE AND HIGH PERFORMANCE MEMORY HIERARCHY IN CHIP MULTI-PROCESSORS. (Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/15383axj945

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jadidi, Amin. “ARCHITECTURAL TECHNIQUES TO ENABLE RELIABLE AND HIGH PERFORMANCE MEMORY HIERARCHY IN CHIP MULTI-PROCESSORS.” 2018. Thesis, Penn State University. Accessed April 23, 2019. https://etda.libraries.psu.edu/catalog/15383axj945.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jadidi, Amin. “ARCHITECTURAL TECHNIQUES TO ENABLE RELIABLE AND HIGH PERFORMANCE MEMORY HIERARCHY IN CHIP MULTI-PROCESSORS.” 2018. Web. 23 Apr 2019.

Vancouver:

Jadidi A. ARCHITECTURAL TECHNIQUES TO ENABLE RELIABLE AND HIGH PERFORMANCE MEMORY HIERARCHY IN CHIP MULTI-PROCESSORS. [Internet] [Thesis]. Penn State University; 2018. [cited 2019 Apr 23]. Available from: https://etda.libraries.psu.edu/catalog/15383axj945.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jadidi A. ARCHITECTURAL TECHNIQUES TO ENABLE RELIABLE AND HIGH PERFORMANCE MEMORY HIERARCHY IN CHIP MULTI-PROCESSORS. [Thesis]. Penn State University; 2018. Available from: https://etda.libraries.psu.edu/catalog/15383axj945

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

11. Johnson, Daniel. Multithreaded architectures for manycore throughput processors.

Degree: PhD, 1200, 2013, University of Illinois – Urbana-Champaign

 This dissertation describes work on the architecture of throughput-oriented accelerator processors. First, we examine the limitations of current accelerator processors and identify an opportunity to… (more)

Subjects/Keywords: Processors; Multiprocessors; Computer Architecture; Parallel processing; Multithreading; High Performance Computing (HPC); visual computing; Accelerator processor; coprocessor; cache coherence; parallel computing; computer systems; graphics processors

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APA (6th Edition):

Johnson, D. (2013). Multithreaded architectures for manycore throughput processors. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44751

Chicago Manual of Style (16th Edition):

Johnson, Daniel. “Multithreaded architectures for manycore throughput processors.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 23, 2019. http://hdl.handle.net/2142/44751.

MLA Handbook (7th Edition):

Johnson, Daniel. “Multithreaded architectures for manycore throughput processors.” 2013. Web. 23 Apr 2019.

Vancouver:

Johnson D. Multithreaded architectures for manycore throughput processors. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/2142/44751.

Council of Science Editors:

Johnson D. Multithreaded architectures for manycore throughput processors. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44751


University of Edinburgh

12. Franke, Bjorn. Compilation techniques for high-performance embedded systems with multiple processors.

Degree: PhD, 2004, University of Edinburgh

 Despite the progress made in developing more advanced compilers for embedded systems, programming of embedded high-performance computing systems based on Digital Signal Processors (DSPs) is… (more)

Subjects/Keywords: 004; Multiple Processors; Compilation Techniques; High-Performance Embedded Systems

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APA (6th Edition):

Franke, B. (2004). Compilation techniques for high-performance embedded systems with multiple processors. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/568

Chicago Manual of Style (16th Edition):

Franke, Bjorn. “Compilation techniques for high-performance embedded systems with multiple processors.” 2004. Doctoral Dissertation, University of Edinburgh. Accessed April 23, 2019. http://hdl.handle.net/1842/568.

MLA Handbook (7th Edition):

Franke, Bjorn. “Compilation techniques for high-performance embedded systems with multiple processors.” 2004. Web. 23 Apr 2019.

Vancouver:

Franke B. Compilation techniques for high-performance embedded systems with multiple processors. [Internet] [Doctoral dissertation]. University of Edinburgh; 2004. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/1842/568.

Council of Science Editors:

Franke B. Compilation techniques for high-performance embedded systems with multiple processors. [Doctoral Dissertation]. University of Edinburgh; 2004. Available from: http://hdl.handle.net/1842/568


University of California – Irvine

13. YANTIR, Hasan Erdem. Efficient Acceleration of Computation Using Associative In-memory Processing.

Degree: Electrical and Computer Engineering, 2018, University of California – Irvine

 The complexity of the computational problems is rising faster than the computational platforms' capabilities. This forces researchers to find alternative paradigms and methods for efficient… (more)

Subjects/Keywords: Computer engineering; Computer science; Electrical engineering; Associative Processors; Computer Architecture; Content Addressable Memories; High-performance Computing; In-memory Computation; Parallel Processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

YANTIR, H. E. (2018). Efficient Acceleration of Computation Using Associative In-memory Processing. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/3939f48b

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

YANTIR, Hasan Erdem. “Efficient Acceleration of Computation Using Associative In-memory Processing.” 2018. Thesis, University of California – Irvine. Accessed April 23, 2019. http://www.escholarship.org/uc/item/3939f48b.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

YANTIR, Hasan Erdem. “Efficient Acceleration of Computation Using Associative In-memory Processing.” 2018. Web. 23 Apr 2019.

Vancouver:

YANTIR HE. Efficient Acceleration of Computation Using Associative In-memory Processing. [Internet] [Thesis]. University of California – Irvine; 2018. [cited 2019 Apr 23]. Available from: http://www.escholarship.org/uc/item/3939f48b.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

YANTIR HE. Efficient Acceleration of Computation Using Associative In-memory Processing. [Thesis]. University of California – Irvine; 2018. Available from: http://www.escholarship.org/uc/item/3939f48b

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


KTH

14. Netzer, Gilbert. Efficient LU Factorization for Texas Instruments Keystone Architecture Digital Signal Processors.

Degree: Computer Science and Communication (CSC), 2015, KTH

The energy consumption of large-scale high-performance computer (HPC) systems has become one of the foremost concerns of both data-center operators and computer manufacturers. This… (more)

Subjects/Keywords: LU factorization; digital signal processors; Texas Instruments; Keystone architecture; high-performance LINPACK; benchmark; performance; energy efficiency; software-pipelined loops; direct memory access; optimization; Computer Sciences; Datavetenskap (datalogi)

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APA (6th Edition):

Netzer, G. (2015). Efficient LU Factorization for Texas Instruments Keystone Architecture Digital Signal Processors. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-170445

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Netzer, Gilbert. “Efficient LU Factorization for Texas Instruments Keystone Architecture Digital Signal Processors.” 2015. Thesis, KTH. Accessed April 23, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-170445.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Netzer, Gilbert. “Efficient LU Factorization for Texas Instruments Keystone Architecture Digital Signal Processors.” 2015. Web. 23 Apr 2019.

Vancouver:

Netzer G. Efficient LU Factorization for Texas Instruments Keystone Architecture Digital Signal Processors. [Internet] [Thesis]. KTH; 2015. [cited 2019 Apr 23]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-170445.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Netzer G. Efficient LU Factorization for Texas Instruments Keystone Architecture Digital Signal Processors. [Thesis]. KTH; 2015. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-170445

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Autònoma de Barcelona

15. Allande Álvarez, César. Modeling performance degradation in OpenMP memory bound applications on multicore multisocket systems.

Degree: Departament d'Arquitectura de Computadors i Sistemes Operatius, 2015, Universitat Autònoma de Barcelona

 The evolution of multicore processors has completely changed the evolution of current HPC systems. The multicore architectures were mainly designed to avoid three design walls,… (more)

Subjects/Keywords: Computació d'altes prestacions; Computación de alto rendimiento; High performance computing; Model de rendiment; Modelo de rendimiento; Performance model; Processadors multicore; Procesadores multicore; Multicore processors; Tecnologies; 004

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APA (6th Edition):

Allande Álvarez, C. (2015). Modeling performance degradation in OpenMP memory bound applications on multicore multisocket systems. (Thesis). Universitat Autònoma de Barcelona. Retrieved from http://hdl.handle.net/10803/371463

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Allande Álvarez, César. “Modeling performance degradation in OpenMP memory bound applications on multicore multisocket systems.” 2015. Thesis, Universitat Autònoma de Barcelona. Accessed April 23, 2019. http://hdl.handle.net/10803/371463.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Allande Álvarez, César. “Modeling performance degradation in OpenMP memory bound applications on multicore multisocket systems.” 2015. Web. 23 Apr 2019.

Vancouver:

Allande Álvarez C. Modeling performance degradation in OpenMP memory bound applications on multicore multisocket systems. [Internet] [Thesis]. Universitat Autònoma de Barcelona; 2015. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/10803/371463.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Allande Álvarez C. Modeling performance degradation in OpenMP memory bound applications on multicore multisocket systems. [Thesis]. Universitat Autònoma de Barcelona; 2015. Available from: http://hdl.handle.net/10803/371463

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

16. Blagojevic, Filip. Scheduling on Asymmetric Architectures.

Degree: PhD, Computer Science, 2008, Virginia Tech

 We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate conventional cores that run legacy codes… (more)

Subjects/Keywords: process scheduling; performance prediction; high-performance computing; runtime adaptation; Multicore processors; Cell BE

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APA (6th Edition):

Blagojevic, F. (2008). Scheduling on Asymmetric Architectures. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/27952

Chicago Manual of Style (16th Edition):

Blagojevic, Filip. “Scheduling on Asymmetric Architectures.” 2008. Doctoral Dissertation, Virginia Tech. Accessed April 23, 2019. http://hdl.handle.net/10919/27952.

MLA Handbook (7th Edition):

Blagojevic, Filip. “Scheduling on Asymmetric Architectures.” 2008. Web. 23 Apr 2019.

Vancouver:

Blagojevic F. Scheduling on Asymmetric Architectures. [Internet] [Doctoral dissertation]. Virginia Tech; 2008. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/10919/27952.

Council of Science Editors:

Blagojevic F. Scheduling on Asymmetric Architectures. [Doctoral Dissertation]. Virginia Tech; 2008. Available from: http://hdl.handle.net/10919/27952


Universidade do Rio Grande do Sul

17. Binotto, Alécio Pedro Delazari. A dynamic scheduling runtime and tuning system for heterogeneous multi and many-core desktop platforms.

Degree: 2011, Universidade do Rio Grande do Sul

Atualmente, o computador pessoal (PC) moderno poder ser considerado como um cluster heterogênedo de um nodo, o qual processa simultâneamente inúmeras tarefas provenientes das aplicações.… (more)

Subjects/Keywords: High-performance computing; Processamento paralelo; Scheduling; Microeletrônica; Dynamic load-balancing; Processamento : Imagem; Heterogenous systems; Processamento : Alto desempenho; Graphics processors; Solvers for systems of linear equations

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APA (6th Edition):

Binotto, A. P. D. (2011). A dynamic scheduling runtime and tuning system for heterogeneous multi and many-core desktop platforms. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/34768

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Binotto, Alécio Pedro Delazari. “A dynamic scheduling runtime and tuning system for heterogeneous multi and many-core desktop platforms.” 2011. Thesis, Universidade do Rio Grande do Sul. Accessed April 23, 2019. http://hdl.handle.net/10183/34768.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Binotto, Alécio Pedro Delazari. “A dynamic scheduling runtime and tuning system for heterogeneous multi and many-core desktop platforms.” 2011. Web. 23 Apr 2019.

Vancouver:

Binotto APD. A dynamic scheduling runtime and tuning system for heterogeneous multi and many-core desktop platforms. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2011. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/10183/34768.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Binotto APD. A dynamic scheduling runtime and tuning system for heterogeneous multi and many-core desktop platforms. [Thesis]. Universidade do Rio Grande do Sul; 2011. Available from: http://hdl.handle.net/10183/34768

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université Paris-Sud – Paris XI

18. Saidani, Tarik. Optimisation multi-niveau d’une application de traitement d’images sur machines parallèles : Multi-level optimisation of an image processing application on parallel machines.

Degree: Docteur es, Physique, 2012, Université Paris-Sud – Paris XI

Cette thèse vise à définir une méthodologie de mise en œuvre d’applications performantes sur les processeurs embarqués du futur. Ces architectures nécessitent notamment d’exploiter au… (more)

Subjects/Keywords: Programmation parallèle; Processeur CELL; Traitement d’images; Squelettes algorithmiques; Calcul hautes performances; Méta-programmation; Processeur embarqué; Parallel programming; CELL processor; Image processing; Algorithmic skeletons; High performance computing; Meta-programming; Embedded processors

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APA (6th Edition):

Saidani, T. (2012). Optimisation multi-niveau d’une application de traitement d’images sur machines parallèles : Multi-level optimisation of an image processing application on parallel machines. (Doctoral Dissertation). Université Paris-Sud – Paris XI. Retrieved from http://www.theses.fr/2012PA112268

Chicago Manual of Style (16th Edition):

Saidani, Tarik. “Optimisation multi-niveau d’une application de traitement d’images sur machines parallèles : Multi-level optimisation of an image processing application on parallel machines.” 2012. Doctoral Dissertation, Université Paris-Sud – Paris XI. Accessed April 23, 2019. http://www.theses.fr/2012PA112268.

MLA Handbook (7th Edition):

Saidani, Tarik. “Optimisation multi-niveau d’une application de traitement d’images sur machines parallèles : Multi-level optimisation of an image processing application on parallel machines.” 2012. Web. 23 Apr 2019.

Vancouver:

Saidani T. Optimisation multi-niveau d’une application de traitement d’images sur machines parallèles : Multi-level optimisation of an image processing application on parallel machines. [Internet] [Doctoral dissertation]. Université Paris-Sud – Paris XI; 2012. [cited 2019 Apr 23]. Available from: http://www.theses.fr/2012PA112268.

Council of Science Editors:

Saidani T. Optimisation multi-niveau d’une application de traitement d’images sur machines parallèles : Multi-level optimisation of an image processing application on parallel machines. [Doctoral Dissertation]. Université Paris-Sud – Paris XI; 2012. Available from: http://www.theses.fr/2012PA112268


McGill University

19. Al Assaad, Sevin, 1984-. Biochemical system simulation on a heterogeneous multicore processor.

Degree: M. Eng., Department of Electrical and Computer Engineering., 2009, McGill University

 Biological system simulation is an increasingly popular field of study that provides biologists with the tools necessary to simulate biochemical systems in order to obtain… (more)

Subjects/Keywords: High performance processors.; Parallel processing (Electronic computers); Systems biology.; Bioinformatics.

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APA (6th Edition):

Al Assaad, Sevin, 1. (2009). Biochemical system simulation on a heterogeneous multicore processor. (Masters Thesis). McGill University. Retrieved from http://digitool.library.mcgill.ca/thesisfile115988.pdf

Chicago Manual of Style (16th Edition):

Al Assaad, Sevin, 1984-. “Biochemical system simulation on a heterogeneous multicore processor.” 2009. Masters Thesis, McGill University. Accessed April 23, 2019. http://digitool.library.mcgill.ca/thesisfile115988.pdf.

MLA Handbook (7th Edition):

Al Assaad, Sevin, 1984-. “Biochemical system simulation on a heterogeneous multicore processor.” 2009. Web. 23 Apr 2019.

Vancouver:

Al Assaad, Sevin 1. Biochemical system simulation on a heterogeneous multicore processor. [Internet] [Masters thesis]. McGill University; 2009. [cited 2019 Apr 23]. Available from: http://digitool.library.mcgill.ca/thesisfile115988.pdf.

Council of Science Editors:

Al Assaad, Sevin 1. Biochemical system simulation on a heterogeneous multicore processor. [Masters Thesis]. McGill University; 2009. Available from: http://digitool.library.mcgill.ca/thesisfile115988.pdf

20. Davis, Spring. Chitin Microparticles (CMPs) Induce M1 Macrophage Activation via Intracellular TLR2 Signaling Mechanism.

Degree: MS, 2016, Florida Atlantic University

Summary: Chitin Microparticles (CMPs, 1-10um), a special form of the ubiquitous and nontoxic polysaccharide Chitin (GlcNAc), is capable of inducing a switch in macrophages from… (more)

Subjects/Keywords: Biopharmaceutics.; Macrophages.; Cell receptors.; Ligands (Biochemistry); High performance processors.

…2006). All the members of the TLR2 subfamily have high amino acid sequence homology… 

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APA (6th Edition):

Davis, S. (2016). Chitin Microparticles (CMPs) Induce M1 Macrophage Activation via Intracellular TLR2 Signaling Mechanism. (Masters Thesis). Florida Atlantic University. Retrieved from http://purl.flvc.org/fau/fd/FA00004762 ; (URL) http://purl.flvc.org/fau/fd/FA00004762

Chicago Manual of Style (16th Edition):

Davis, Spring. “Chitin Microparticles (CMPs) Induce M1 Macrophage Activation via Intracellular TLR2 Signaling Mechanism.” 2016. Masters Thesis, Florida Atlantic University. Accessed April 23, 2019. http://purl.flvc.org/fau/fd/FA00004762 ; (URL) http://purl.flvc.org/fau/fd/FA00004762.

MLA Handbook (7th Edition):

Davis, Spring. “Chitin Microparticles (CMPs) Induce M1 Macrophage Activation via Intracellular TLR2 Signaling Mechanism.” 2016. Web. 23 Apr 2019.

Vancouver:

Davis S. Chitin Microparticles (CMPs) Induce M1 Macrophage Activation via Intracellular TLR2 Signaling Mechanism. [Internet] [Masters thesis]. Florida Atlantic University; 2016. [cited 2019 Apr 23]. Available from: http://purl.flvc.org/fau/fd/FA00004762 ; (URL) http://purl.flvc.org/fau/fd/FA00004762.

Council of Science Editors:

Davis S. Chitin Microparticles (CMPs) Induce M1 Macrophage Activation via Intracellular TLR2 Signaling Mechanism. [Masters Thesis]. Florida Atlantic University; 2016. Available from: http://purl.flvc.org/fau/fd/FA00004762 ; (URL) http://purl.flvc.org/fau/fd/FA00004762

21. Perais, Arthur. Increasing the performance of superscalar processors through value prediction : La prédiction de valeurs comme moyen d'augmenter la performance des processeurs superscalaires.

Degree: Docteur es, Informatique, 2015, Rennes 1

Bien que les processeurs actuels possèdent plus de 10 cœurs, de nombreux programmes restent purement séquentiels. Cela peut être dû à l'algorithme que le programme… (more)

Subjects/Keywords: Architecture des processeurs; Processeurs à hautes performances; Exécution spéculative; Prédiction de valeurs; Processeurs superscalaires; Exécution dans le désordre; Processor architecture; High performance processors; Speculative execution; Value prediction; Superscalar processors; Out-Of-Order execution

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APA (6th Edition):

Perais, A. (2015). Increasing the performance of superscalar processors through value prediction : La prédiction de valeurs comme moyen d'augmenter la performance des processeurs superscalaires. (Doctoral Dissertation). Rennes 1. Retrieved from http://www.theses.fr/2015REN1S070

Chicago Manual of Style (16th Edition):

Perais, Arthur. “Increasing the performance of superscalar processors through value prediction : La prédiction de valeurs comme moyen d'augmenter la performance des processeurs superscalaires.” 2015. Doctoral Dissertation, Rennes 1. Accessed April 23, 2019. http://www.theses.fr/2015REN1S070.

MLA Handbook (7th Edition):

Perais, Arthur. “Increasing the performance of superscalar processors through value prediction : La prédiction de valeurs comme moyen d'augmenter la performance des processeurs superscalaires.” 2015. Web. 23 Apr 2019.

Vancouver:

Perais A. Increasing the performance of superscalar processors through value prediction : La prédiction de valeurs comme moyen d'augmenter la performance des processeurs superscalaires. [Internet] [Doctoral dissertation]. Rennes 1; 2015. [cited 2019 Apr 23]. Available from: http://www.theses.fr/2015REN1S070.

Council of Science Editors:

Perais A. Increasing the performance of superscalar processors through value prediction : La prédiction de valeurs comme moyen d'augmenter la performance des processeurs superscalaires. [Doctoral Dissertation]. Rennes 1; 2015. Available from: http://www.theses.fr/2015REN1S070


Georgia Tech

22. Puttaswamy, Kiran. Designing High-Performance Microprocessors in 3-Dimensional Integration Technology.

Degree: PhD, Electrical and Computer Engineering, 2007, Georgia Tech

 The main contribution of this dissertation is the demonstration of the impact of a new emerging technology called 3D-integration technology on conventional high-performance microprocessors. 3D-integration… (more)

Subjects/Keywords: High-performance microprocessors; 3D integration technology; Integrated circuits Large scale integration; Temperature control; High performance processors

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APA (6th Edition):

Puttaswamy, K. (2007). Designing High-Performance Microprocessors in 3-Dimensional Integration Technology. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/19759

Chicago Manual of Style (16th Edition):

Puttaswamy, Kiran. “Designing High-Performance Microprocessors in 3-Dimensional Integration Technology.” 2007. Doctoral Dissertation, Georgia Tech. Accessed April 23, 2019. http://hdl.handle.net/1853/19759.

MLA Handbook (7th Edition):

Puttaswamy, Kiran. “Designing High-Performance Microprocessors in 3-Dimensional Integration Technology.” 2007. Web. 23 Apr 2019.

Vancouver:

Puttaswamy K. Designing High-Performance Microprocessors in 3-Dimensional Integration Technology. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/1853/19759.

Council of Science Editors:

Puttaswamy K. Designing High-Performance Microprocessors in 3-Dimensional Integration Technology. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/19759


Northeastern University

23. Moazzemi, Kasra. Calibrative source-level multi-target performance estimation.

Degree: MS, College of Engineering. Department of Electrical and Computer Engineering, 2015, Northeastern University

 The growing system complexity and decrease in time-to-market make designing a sys- tem more and more challenging. In order to solve these challenges, trends are… (more)

Subjects/Keywords: Calibrative approach; design space exploration; high level estimation; Performance estimation; system level design; Computer Engineering; Electrical and Computer Engineering; Engineering; System design; Estimates; Cost effectiveness; Database design; Estimates; Cost effectiveness; Configuration management; Estimates; High performance processors; Computer input-output equipment; Linear programming; Mathematical models

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APA (6th Edition):

Moazzemi, K. (2015). Calibrative source-level multi-target performance estimation. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20009301

Chicago Manual of Style (16th Edition):

Moazzemi, Kasra. “Calibrative source-level multi-target performance estimation.” 2015. Masters Thesis, Northeastern University. Accessed April 23, 2019. http://hdl.handle.net/2047/d20009301.

MLA Handbook (7th Edition):

Moazzemi, Kasra. “Calibrative source-level multi-target performance estimation.” 2015. Web. 23 Apr 2019.

Vancouver:

Moazzemi K. Calibrative source-level multi-target performance estimation. [Internet] [Masters thesis]. Northeastern University; 2015. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/2047/d20009301.

Council of Science Editors:

Moazzemi K. Calibrative source-level multi-target performance estimation. [Masters Thesis]. Northeastern University; 2015. Available from: http://hdl.handle.net/2047/d20009301


Georgia Tech

24. Zhuang, Xiaotong. Compiler Optimizations for Multithreaded Multicore Network Processors.

Degree: PhD, Computing, 2006, Georgia Tech

 Network processors are new types of multithreaded multicore processors geared towards achieving both fast processing speed and flexibility of programming. The architecture of network processors(more)

Subjects/Keywords: Runtime constraints; Register allocation; Compiler optimization; Multitheading; Multicore; Network processors; Registers (Computers); Packet switching (Data transmission); High performance processors; Compilers (Computer programs)

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APA (6th Edition):

Zhuang, X. (2006). Compiler Optimizations for Multithreaded Multicore Network Processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/11566

Chicago Manual of Style (16th Edition):

Zhuang, Xiaotong. “Compiler Optimizations for Multithreaded Multicore Network Processors.” 2006. Doctoral Dissertation, Georgia Tech. Accessed April 23, 2019. http://hdl.handle.net/1853/11566.

MLA Handbook (7th Edition):

Zhuang, Xiaotong. “Compiler Optimizations for Multithreaded Multicore Network Processors.” 2006. Web. 23 Apr 2019.

Vancouver:

Zhuang X. Compiler Optimizations for Multithreaded Multicore Network Processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/1853/11566.

Council of Science Editors:

Zhuang X. Compiler Optimizations for Multithreaded Multicore Network Processors. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/11566


Virginia Tech

25. Curtis-Maury, Matthew. Improving the Efficiency of Parallel Applications on Multithreaded and Multicore Systems.

Degree: PhD, Computer Science, 2008, Virginia Tech

 The scalability of parallel applications executing on multithreaded and multicore multiprocessors is often quite limited due to large degrees of contention over shared resources on… (more)

Subjects/Keywords: power-aware computing; high-performance computing; performance prediction; multicore processors; runtime adaptation; concurrency throttling

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APA (6th Edition):

Curtis-Maury, M. (2008). Improving the Efficiency of Parallel Applications on Multithreaded and Multicore Systems. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/26697

Chicago Manual of Style (16th Edition):

Curtis-Maury, Matthew. “Improving the Efficiency of Parallel Applications on Multithreaded and Multicore Systems.” 2008. Doctoral Dissertation, Virginia Tech. Accessed April 23, 2019. http://hdl.handle.net/10919/26697.

MLA Handbook (7th Edition):

Curtis-Maury, Matthew. “Improving the Efficiency of Parallel Applications on Multithreaded and Multicore Systems.” 2008. Web. 23 Apr 2019.

Vancouver:

Curtis-Maury M. Improving the Efficiency of Parallel Applications on Multithreaded and Multicore Systems. [Internet] [Doctoral dissertation]. Virginia Tech; 2008. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/10919/26697.

Council of Science Editors:

Curtis-Maury M. Improving the Efficiency of Parallel Applications on Multithreaded and Multicore Systems. [Doctoral Dissertation]. Virginia Tech; 2008. Available from: http://hdl.handle.net/10919/26697


Virginia Tech

26. Shah, Ankur Savailal. Prediction Models for Multi-dimensional Power-Performance Optimization on Many Cores.

Degree: MS, Computer Science, 2008, Virginia Tech

 Power has become a primary concern for HPC systems. Dynamic voltage and frequency scaling (DVFS) and dynamic concurrency throttling (DCT) are two software tools (or… (more)

Subjects/Keywords: concurrency throttling; power-aware computing; runtime adaptation; performance prediction; high-performance computing; Multicore processors

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APA (6th Edition):

Shah, A. S. (2008). Prediction Models for Multi-dimensional Power-Performance Optimization on Many Cores. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31826

Chicago Manual of Style (16th Edition):

Shah, Ankur Savailal. “Prediction Models for Multi-dimensional Power-Performance Optimization on Many Cores.” 2008. Masters Thesis, Virginia Tech. Accessed April 23, 2019. http://hdl.handle.net/10919/31826.

MLA Handbook (7th Edition):

Shah, Ankur Savailal. “Prediction Models for Multi-dimensional Power-Performance Optimization on Many Cores.” 2008. Web. 23 Apr 2019.

Vancouver:

Shah AS. Prediction Models for Multi-dimensional Power-Performance Optimization on Many Cores. [Internet] [Masters thesis]. Virginia Tech; 2008. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/10919/31826.

Council of Science Editors:

Shah AS. Prediction Models for Multi-dimensional Power-Performance Optimization on Many Cores. [Masters Thesis]. Virginia Tech; 2008. Available from: http://hdl.handle.net/10919/31826

27. Nagarajan, Ramadass, 1977-. Design and evaluation of a technology-scalable architecture for instruction-level parallelism.

Degree: Computer Sciences, 2007, University of Texas – Austin

 Future performance improvements must come from the exploitation of concurrency at all levels. Recent approaches that focus on thread-level and data-level concurrency are a natural… (more)

Subjects/Keywords: Computer architecture – Design; Computer architecture – Evaluation; High performance processors – Design and construction; High performance processors – Evaluation; Parallel processing (Electronic computers); Threads (Computer programs)

…are yet to reap the benefits of the high-ILP TRIPS core, but exceed the performance of the… …operating systems, process rich streaming media, and even execute high-performance applications… …deep pipelines [74] have ended the reign of clock rates in high performance… …designer productivity, and increasing performance for a given power budget. These processors… …the raw performance results measured on the hardware. It reports the potential for high… 

Page 1 Page 2 Page 3 Page 4 Page 5 Sample image Sample image Sample image

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APA (6th Edition):

Nagarajan, Ramadass, 1. (2007). Design and evaluation of a technology-scalable architecture for instruction-level parallelism. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/3534

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nagarajan, Ramadass, 1977-. “Design and evaluation of a technology-scalable architecture for instruction-level parallelism.” 2007. Thesis, University of Texas – Austin. Accessed April 23, 2019. http://hdl.handle.net/2152/3534.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nagarajan, Ramadass, 1977-. “Design and evaluation of a technology-scalable architecture for instruction-level parallelism.” 2007. Web. 23 Apr 2019.

Vancouver:

Nagarajan, Ramadass 1. Design and evaluation of a technology-scalable architecture for instruction-level parallelism. [Internet] [Thesis]. University of Texas – Austin; 2007. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/2152/3534.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nagarajan, Ramadass 1. Design and evaluation of a technology-scalable architecture for instruction-level parallelism. [Thesis]. University of Texas – Austin; 2007. Available from: http://hdl.handle.net/2152/3534

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. Kultursay, Emre. Compiler-based Memory Optimizations for High Performance Computing Systems.

Degree: PhD, Computer Science and Engineering, 2013, Penn State University

 Parallelism has always been the primary method to achieve higher performance. To advance the computational capabilities of state-of-the-art high performance computing systems, we continue to… (more)

Subjects/Keywords: Compilers; memory optimizations; high performance computing; application-specific hardware accelerators; many-core processors

processors. A successful latency-hiding mechanism is required to sustain high performance. Such… …ul... xiv Chapter 1 Introduction High performance computing, or supercomputing is a… …form of computing that uses the cutting edge of technology. High performance computing… …memory problems identified above for the two types of high performance computing systems… …computing, high performance computing systems will exhibit an unprecedented degree of parallelism… 

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APA (6th Edition):

Kultursay, E. (2013). Compiler-based Memory Optimizations for High Performance Computing Systems. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/18832

Chicago Manual of Style (16th Edition):

Kultursay, Emre. “Compiler-based Memory Optimizations for High Performance Computing Systems.” 2013. Doctoral Dissertation, Penn State University. Accessed April 23, 2019. https://etda.libraries.psu.edu/catalog/18832.

MLA Handbook (7th Edition):

Kultursay, Emre. “Compiler-based Memory Optimizations for High Performance Computing Systems.” 2013. Web. 23 Apr 2019.

Vancouver:

Kultursay E. Compiler-based Memory Optimizations for High Performance Computing Systems. [Internet] [Doctoral dissertation]. Penn State University; 2013. [cited 2019 Apr 23]. Available from: https://etda.libraries.psu.edu/catalog/18832.

Council of Science Editors:

Kultursay E. Compiler-based Memory Optimizations for High Performance Computing Systems. [Doctoral Dissertation]. Penn State University; 2013. Available from: https://etda.libraries.psu.edu/catalog/18832


Universitat Politècnica de Catalunya

29. García Almiñana, Jordi. Automatic data distribution for massively parallel processors.

Degree: Departament d'Arquitectura de Computadors, 1997, Universitat Politècnica de Catalunya

 Massively Parallel Processor systems provide the required computational power to solve most large scale High Performance Computing applications. Machines with physically distributed memory allow a… (more)

Subjects/Keywords: massively parallel processors; high performance fortran; automatic data recomposition; multicomputers; automatic data distribution; automatic data happing; 3304. Tecnologia dels ordinadors; 004; 62

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APA (6th Edition):

García Almiñana, J. (1997). Automatic data distribution for massively parallel processors. (Thesis). Universitat Politècnica de Catalunya. Retrieved from http://hdl.handle.net/10803/5981

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

García Almiñana, Jordi. “Automatic data distribution for massively parallel processors.” 1997. Thesis, Universitat Politècnica de Catalunya. Accessed April 23, 2019. http://hdl.handle.net/10803/5981.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

García Almiñana, Jordi. “Automatic data distribution for massively parallel processors.” 1997. Web. 23 Apr 2019.

Vancouver:

García Almiñana J. Automatic data distribution for massively parallel processors. [Internet] [Thesis]. Universitat Politècnica de Catalunya; 1997. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/10803/5981.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

García Almiñana J. Automatic data distribution for massively parallel processors. [Thesis]. Universitat Politècnica de Catalunya; 1997. Available from: http://hdl.handle.net/10803/5981

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Dasika, Ganesh Suryanarayan. Power-Efficient Accelerators for High-Performance Applications.

Degree: PhD, Computer Science & Engineering, 2011, University of Michigan

 Computers, regardless of their function, are always better if they can operate more quickly. The addition of computation resources allows for improved response times, greater… (more)

Subjects/Keywords: High-performance Computing; Low-power Computing; Power-efficient Computing; SIMD Architectures; Streaming Architectures; Application-specific Processors; Computer Science; Electrical Engineering; Engineering

high-performance commercial processors and GPUs are provided: ARM Cortex-A8, Intel Pentium M… …comparison, the peak performance and power of several commercial processors and GPGPUs are provided… …High-Performance Applications by Ganesh Suryanarayan Dasika Chair: Scott Mahlke Computers… …processors, particularly those used to execute applications that have stringent performance… …These GPGPUs are quickly becoming the platform of choice for many high-performance, highly… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dasika, G. S. (2011). Power-Efficient Accelerators for High-Performance Applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86478

Chicago Manual of Style (16th Edition):

Dasika, Ganesh Suryanarayan. “Power-Efficient Accelerators for High-Performance Applications.” 2011. Doctoral Dissertation, University of Michigan. Accessed April 23, 2019. http://hdl.handle.net/2027.42/86478.

MLA Handbook (7th Edition):

Dasika, Ganesh Suryanarayan. “Power-Efficient Accelerators for High-Performance Applications.” 2011. Web. 23 Apr 2019.

Vancouver:

Dasika GS. Power-Efficient Accelerators for High-Performance Applications. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2019 Apr 23]. Available from: http://hdl.handle.net/2027.42/86478.

Council of Science Editors:

Dasika GS. Power-Efficient Accelerators for High-Performance Applications. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86478

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