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You searched for subject:(High level synthesis). Showing records 1 – 30 of 165 total matches.

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University of Illinois – Urbana-Champaign

1. Sun, Zelei. VAST-LP: clock gating in high-level synthesis.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

High-level synthesis (HLS) promises high-quality hardware with minimal develop- ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST and propose… (more)

Subjects/Keywords: low power; high level synthesis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sun, Z. (2016). VAST-LP: clock gating in high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sun, Zelei. “VAST-LP: clock gating in high-level synthesis.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed April 18, 2021. http://hdl.handle.net/2142/90970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sun, Zelei. “VAST-LP: clock gating in high-level synthesis.” 2016. Web. 18 Apr 2021.

Vancouver:

Sun Z. VAST-LP: clock gating in high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2142/90970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sun Z. VAST-LP: clock gating in high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. -7307-3794. Approximate high-level synthesis of quality and energy optimized hardware processors.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 Approximate computing is a technique that exploits trade-offs between energy/performance and quality of computed results. Such techniques have been explored at various design levels for… (more)

Subjects/Keywords: Approximate computing; High-level synthesis

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APA (6th Edition):

-7307-3794. (2018). Approximate high-level synthesis of quality and energy optimized hardware processors. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63811

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-7307-3794. “Approximate high-level synthesis of quality and energy optimized hardware processors.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed April 18, 2021. http://hdl.handle.net/2152/63811.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-7307-3794. “Approximate high-level synthesis of quality and energy optimized hardware processors.” 2018. Web. 18 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-7307-3794. Approximate high-level synthesis of quality and energy optimized hardware processors. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2152/63811.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-7307-3794. Approximate high-level synthesis of quality and energy optimized hardware processors. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/63811

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Texas – Austin

3. Lee, Dongwook. Learning-based system-level power modeling of hardware IPs.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin

 Accurate power models for hardware components at high levels of abstraction are a critical component to enable system-level power analysis and optimization. Virtual platform prototypes… (more)

Subjects/Keywords: Power estimation; High-level synthesis

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APA (6th Edition):

Lee, D. (2017). Learning-based system-level power modeling of hardware IPs. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63013

Chicago Manual of Style (16th Edition):

Lee, Dongwook. “Learning-based system-level power modeling of hardware IPs.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed April 18, 2021. http://hdl.handle.net/2152/63013.

MLA Handbook (7th Edition):

Lee, Dongwook. “Learning-based system-level power modeling of hardware IPs.” 2017. Web. 18 Apr 2021.

Vancouver:

Lee D. Learning-based system-level power modeling of hardware IPs. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2152/63013.

Council of Science Editors:

Lee D. Learning-based system-level power modeling of hardware IPs. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/63013


Penn State University

4. Chen, Yibo. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS .

Degree: 2011, Penn State University

 Variability in circuit delay and power dissipation is one of the most critical challenges in nanometer VLSI era. Traditionally, performance/power variations are handled by a… (more)

Subjects/Keywords: High-Level Synthesis; Behavioral Synthesis; ESL

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APA (6th Edition):

Chen, Y. (2011). VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12416

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Yibo. “VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS .” 2011. Thesis, Penn State University. Accessed April 18, 2021. https://submit-etda.libraries.psu.edu/catalog/12416.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Yibo. “VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS .” 2011. Web. 18 Apr 2021.

Vancouver:

Chen Y. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS . [Internet] [Thesis]. Penn State University; 2011. [cited 2021 Apr 18]. Available from: https://submit-etda.libraries.psu.edu/catalog/12416.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12416

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

5. Li, Chaofan. Synthesis Techniques for Power-Efficient Integrated Circuits.

Degree: PhD, Computer Engineering, 2018, Texas A&M University

 In the past few years, power efficiency has been increasingly important for integrated circuits. As the Moore’s law effects slows down, the improvement of power… (more)

Subjects/Keywords: High-Level Synthesis; Adaptive Supply Voltage

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APA (6th Edition):

Li, C. (2018). Synthesis Techniques for Power-Efficient Integrated Circuits. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173652

Chicago Manual of Style (16th Edition):

Li, Chaofan. “Synthesis Techniques for Power-Efficient Integrated Circuits.” 2018. Doctoral Dissertation, Texas A&M University. Accessed April 18, 2021. http://hdl.handle.net/1969.1/173652.

MLA Handbook (7th Edition):

Li, Chaofan. “Synthesis Techniques for Power-Efficient Integrated Circuits.” 2018. Web. 18 Apr 2021.

Vancouver:

Li C. Synthesis Techniques for Power-Efficient Integrated Circuits. [Internet] [Doctoral dissertation]. Texas A&M University; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1969.1/173652.

Council of Science Editors:

Li C. Synthesis Techniques for Power-Efficient Integrated Circuits. [Doctoral Dissertation]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173652


University of Waterloo

6. Morcos, Benjamin. NengoFPGA: an FPGA Backend for the Nengo Neural Simulator.

Degree: 2019, University of Waterloo

 Low-power, high-speed neural networks are critical for providing deployable embedded AI applications at the edge. We describe a Xilinx FPGA implementation of Neural Engineering Framework… (more)

Subjects/Keywords: neural networks; FPGA; nengo; high-level synthesis

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APA (6th Edition):

Morcos, B. (2019). NengoFPGA: an FPGA Backend for the Nengo Neural Simulator. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/14923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Morcos, Benjamin. “NengoFPGA: an FPGA Backend for the Nengo Neural Simulator.” 2019. Thesis, University of Waterloo. Accessed April 18, 2021. http://hdl.handle.net/10012/14923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Morcos, Benjamin. “NengoFPGA: an FPGA Backend for the Nengo Neural Simulator.” 2019. Web. 18 Apr 2021.

Vancouver:

Morcos B. NengoFPGA: an FPGA Backend for the Nengo Neural Simulator. [Internet] [Thesis]. University of Waterloo; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10012/14923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Morcos B. NengoFPGA: an FPGA Backend for the Nengo Neural Simulator. [Thesis]. University of Waterloo; 2019. Available from: http://hdl.handle.net/10012/14923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

7. Darounkola, Nazanin Calagar. Source-level Debugging Framework Design for FPGA High-level Synthesis.

Degree: 2014, University of Toronto

HighLevel Synthesis tools have become more attractive in recent years. However, in order to be fully utilized for largescale applications, HLS tools need to address… (more)

Subjects/Keywords: Debugging; FPGA; High-level synthesis; 0464

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APA (6th Edition):

Darounkola, N. C. (2014). Source-level Debugging Framework Design for FPGA High-level Synthesis. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/68069

Chicago Manual of Style (16th Edition):

Darounkola, Nazanin Calagar. “Source-level Debugging Framework Design for FPGA High-level Synthesis.” 2014. Masters Thesis, University of Toronto. Accessed April 18, 2021. http://hdl.handle.net/1807/68069.

MLA Handbook (7th Edition):

Darounkola, Nazanin Calagar. “Source-level Debugging Framework Design for FPGA High-level Synthesis.” 2014. Web. 18 Apr 2021.

Vancouver:

Darounkola NC. Source-level Debugging Framework Design for FPGA High-level Synthesis. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1807/68069.

Council of Science Editors:

Darounkola NC. Source-level Debugging Framework Design for FPGA High-level Synthesis. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/68069


University of Toronto

8. Liu, Li. Automated Debugging Framework for High-level Synthesis.

Degree: 2013, University of Toronto

This thesis proposes a automated test case generation technique for the aim of verifying/debugging High-level synthesis (HLS) tools. The work in this thesis builds a… (more)

Subjects/Keywords: Debug; High-level Synthesis; 0544; 0984

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APA (6th Edition):

Liu, L. (2013). Automated Debugging Framework for High-level Synthesis. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/35123

Chicago Manual of Style (16th Edition):

Liu, Li. “Automated Debugging Framework for High-level Synthesis.” 2013. Masters Thesis, University of Toronto. Accessed April 18, 2021. http://hdl.handle.net/1807/35123.

MLA Handbook (7th Edition):

Liu, Li. “Automated Debugging Framework for High-level Synthesis.” 2013. Web. 18 Apr 2021.

Vancouver:

Liu L. Automated Debugging Framework for High-level Synthesis. [Internet] [Masters thesis]. University of Toronto; 2013. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1807/35123.

Council of Science Editors:

Liu L. Automated Debugging Framework for High-level Synthesis. [Masters Thesis]. University of Toronto; 2013. Available from: http://hdl.handle.net/1807/35123


Princeton University

9. Liu, Feng. Static and Dynamic Instruction Mappingfor Spatial Architectures .

Degree: PhD, 2018, Princeton University

 In response to the technology scaling trends, spatial architectures have emerged as a new style of processors for executing programs more efficiently. Unlike traditional Out-of-Order… (more)

Subjects/Keywords: compiling; computer architecture; high level synthesis; reconfigurable

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APA (6th Edition):

Liu, F. (2018). Static and Dynamic Instruction Mappingfor Spatial Architectures . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01kk91fp258

Chicago Manual of Style (16th Edition):

Liu, Feng. “Static and Dynamic Instruction Mappingfor Spatial Architectures .” 2018. Doctoral Dissertation, Princeton University. Accessed April 18, 2021. http://arks.princeton.edu/ark:/88435/dsp01kk91fp258.

MLA Handbook (7th Edition):

Liu, Feng. “Static and Dynamic Instruction Mappingfor Spatial Architectures .” 2018. Web. 18 Apr 2021.

Vancouver:

Liu F. Static and Dynamic Instruction Mappingfor Spatial Architectures . [Internet] [Doctoral dissertation]. Princeton University; 2018. [cited 2021 Apr 18]. Available from: http://arks.princeton.edu/ark:/88435/dsp01kk91fp258.

Council of Science Editors:

Liu F. Static and Dynamic Instruction Mappingfor Spatial Architectures . [Doctoral Dissertation]. Princeton University; 2018. Available from: http://arks.princeton.edu/ark:/88435/dsp01kk91fp258


University of Windsor

10. Tang, Qing Yun. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.

Degree: MA, Electrical and Computer Engineering, 2016, University of Windsor

 FPGAs have shown great promise for accelerating computationally intensive algorithms. However, FPGA-based accelerator design is tedious and time consuming if we rely on traditional HDL… (more)

Subjects/Keywords: FPGA; Hardware Acceleration; High Level Synthesis; OpenCL

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APA (6th Edition):

Tang, Q. Y. (2016). FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5669

Chicago Manual of Style (16th Edition):

Tang, Qing Yun. “FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.” 2016. Masters Thesis, University of Windsor. Accessed April 18, 2021. https://scholar.uwindsor.ca/etd/5669.

MLA Handbook (7th Edition):

Tang, Qing Yun. “FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.” 2016. Web. 18 Apr 2021.

Vancouver:

Tang QY. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. [Internet] [Masters thesis]. University of Windsor; 2016. [cited 2021 Apr 18]. Available from: https://scholar.uwindsor.ca/etd/5669.

Council of Science Editors:

Tang QY. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. [Masters Thesis]. University of Windsor; 2016. Available from: https://scholar.uwindsor.ca/etd/5669

11. Sundari, B. Bala Tripura. Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -.

Degree: Engineering, 2004, Amrita Vishwa Vidyapeetham (University)

The high integration density of very large scale integrated (VLSI) circuits has made system on chip design (SoC) become a reality. With increasing complexity of… (more)

Subjects/Keywords: Multi-level nested loop algorithms;

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APA (6th Edition):

Sundari, B. B. T. (2004). Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -. (Thesis). Amrita Vishwa Vidyapeetham (University). Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/13051

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sundari, B Bala Tripura. “Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -.” 2004. Thesis, Amrita Vishwa Vidyapeetham (University). Accessed April 18, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/13051.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sundari, B Bala Tripura. “Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -.” 2004. Web. 18 Apr 2021.

Vancouver:

Sundari BBT. Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -. [Internet] [Thesis]. Amrita Vishwa Vidyapeetham (University); 2004. [cited 2021 Apr 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13051.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sundari BBT. Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -. [Thesis]. Amrita Vishwa Vidyapeetham (University); 2004. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13051

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

12. Kupka, David. Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy: Mapping of Algorithms to FPGA Using High-Level Synthesis Tools.

Degree: 2019, Brno University of Technology

 This thesis deals with ways to describe hardware. It presents the methods used in the synthesis of the description and then it compares on a… (more)

Subjects/Keywords: Vyskoúrovňová syntéza; VHDL; syntéza; popis hardware; srovnání; High-Level Synthesis; VHDL; synthesis; hardware description; comparsion

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kupka, D. (2019). Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy: Mapping of Algorithms to FPGA Using High-Level Synthesis Tools. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/55739

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kupka, David. “Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy: Mapping of Algorithms to FPGA Using High-Level Synthesis Tools.” 2019. Thesis, Brno University of Technology. Accessed April 18, 2021. http://hdl.handle.net/11012/55739.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kupka, David. “Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy: Mapping of Algorithms to FPGA Using High-Level Synthesis Tools.” 2019. Web. 18 Apr 2021.

Vancouver:

Kupka D. Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy: Mapping of Algorithms to FPGA Using High-Level Synthesis Tools. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/11012/55739.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kupka D. Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy: Mapping of Algorithms to FPGA Using High-Level Synthesis Tools. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/55739

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

13. Soldavini, Stephanie. Using Reduced Graphs for Efficient HLS Scheduling.

Degree: MS, Computer Engineering, 2019, Rochester Institute of Technology

High-Level Synthesis (HLS) is the process of inferring a digital circuit from a high-level algorithmic description provided as a software implementation, usually in C/C++.… (more)

Subjects/Keywords: High-level synthesis; HLS; Reduced data flow graph; Resource efficient; Scheduling

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APA (6th Edition):

Soldavini, S. (2019). Using Reduced Graphs for Efficient HLS Scheduling. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10311

Chicago Manual of Style (16th Edition):

Soldavini, Stephanie. “Using Reduced Graphs for Efficient HLS Scheduling.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed April 18, 2021. https://scholarworks.rit.edu/theses/10311.

MLA Handbook (7th Edition):

Soldavini, Stephanie. “Using Reduced Graphs for Efficient HLS Scheduling.” 2019. Web. 18 Apr 2021.

Vancouver:

Soldavini S. Using Reduced Graphs for Efficient HLS Scheduling. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2021 Apr 18]. Available from: https://scholarworks.rit.edu/theses/10311.

Council of Science Editors:

Soldavini S. Using Reduced Graphs for Efficient HLS Scheduling. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10311


Rochester Institute of Technology

14. Conn, Bradley E. Exploring High Level Synthesis to Improve the Design of Turbo Code Error Correction in a Software Defined Radio Context.

Degree: MS, Computer Engineering, 2018, Rochester Institute of Technology

  With the ever improving progress of technology, Software Defined Radio (SDR) has become a more widely available technique for implementing radio communication. SDRs are… (more)

Subjects/Keywords: High level synthesis; Software defined radio; Turbo code error correction

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APA (6th Edition):

Conn, B. E. (2018). Exploring High Level Synthesis to Improve the Design of Turbo Code Error Correction in a Software Defined Radio Context. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9839

Chicago Manual of Style (16th Edition):

Conn, Bradley E. “Exploring High Level Synthesis to Improve the Design of Turbo Code Error Correction in a Software Defined Radio Context.” 2018. Masters Thesis, Rochester Institute of Technology. Accessed April 18, 2021. https://scholarworks.rit.edu/theses/9839.

MLA Handbook (7th Edition):

Conn, Bradley E. “Exploring High Level Synthesis to Improve the Design of Turbo Code Error Correction in a Software Defined Radio Context.” 2018. Web. 18 Apr 2021.

Vancouver:

Conn BE. Exploring High Level Synthesis to Improve the Design of Turbo Code Error Correction in a Software Defined Radio Context. [Internet] [Masters thesis]. Rochester Institute of Technology; 2018. [cited 2021 Apr 18]. Available from: https://scholarworks.rit.edu/theses/9839.

Council of Science Editors:

Conn BE. Exploring High Level Synthesis to Improve the Design of Turbo Code Error Correction in a Software Defined Radio Context. [Masters Thesis]. Rochester Institute of Technology; 2018. Available from: https://scholarworks.rit.edu/theses/9839


University of Alberta

15. Hashemi, Seyyed Ali. Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization.

Degree: MS, Department of Electrical and Computer Engineering, 2011, University of Alberta

 This thesis is concerned with the development of a novel discrete particle swarm optimization (PSO) technique and its application to the discrete optimization of digital… (more)

Subjects/Keywords: Particle swarm optimization; Digital filters; High-level synthesis

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APA (6th Edition):

Hashemi, S. A. (2011). Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/gt54kn61s

Chicago Manual of Style (16th Edition):

Hashemi, Seyyed Ali. “Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization.” 2011. Masters Thesis, University of Alberta. Accessed April 18, 2021. https://era.library.ualberta.ca/files/gt54kn61s.

MLA Handbook (7th Edition):

Hashemi, Seyyed Ali. “Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization.” 2011. Web. 18 Apr 2021.

Vancouver:

Hashemi SA. Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization. [Internet] [Masters thesis]. University of Alberta; 2011. [cited 2021 Apr 18]. Available from: https://era.library.ualberta.ca/files/gt54kn61s.

Council of Science Editors:

Hashemi SA. Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization. [Masters Thesis]. University of Alberta; 2011. Available from: https://era.library.ualberta.ca/files/gt54kn61s


University of Illinois – Urbana-Champaign

16. Liu, Xinheng. Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.

Degree: MS, Electrical & Computer Engr, 2018, University of Illinois – Urbana-Champaign

 Targeting convolutional neural networks (CNNs), we adopt the high level synthesis (HLS) design methodology and explore various optimization and synthesis techniques to optimize design on… (more)

Subjects/Keywords: FPGA; Convolutional Neural Network; Optimization; Acceleration; High-Level Synthesis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, X. (2018). Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/101228

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Xinheng. “Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.” 2018. Thesis, University of Illinois – Urbana-Champaign. Accessed April 18, 2021. http://hdl.handle.net/2142/101228.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Xinheng. “Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.” 2018. Web. 18 Apr 2021.

Vancouver:

Liu X. Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2142/101228.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu X. Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices. [Thesis]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/101228

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

17. Kim, Taemin. Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs.

Degree: PhD, Computer Engineering, 2009, North Carolina State University

 Optimization techniques during high level synthesis procedure are often preferred since design decisions at early stages of a design flow are believed to have a… (more)

Subjects/Keywords: High Level Synthesis; Global Interconnect; VLSI CAD; Optimization; Algorithm

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APA (6th Edition):

Kim, T. (2009). Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/4109

Chicago Manual of Style (16th Edition):

Kim, Taemin. “Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs.” 2009. Doctoral Dissertation, North Carolina State University. Accessed April 18, 2021. http://www.lib.ncsu.edu/resolver/1840.16/4109.

MLA Handbook (7th Edition):

Kim, Taemin. “Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs.” 2009. Web. 18 Apr 2021.

Vancouver:

Kim T. Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs. [Internet] [Doctoral dissertation]. North Carolina State University; 2009. [cited 2021 Apr 18]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4109.

Council of Science Editors:

Kim T. Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs. [Doctoral Dissertation]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4109


University of Toronto

18. Tai, Justin Isaiah. High-level Synthesis of Datacenter Services.

Degree: 2017, University of Toronto

Field programmable gate arrays have become of great interest for implementing datacenter applications due to high performance gains over traditional compute hardware at a fraction… (more)

Subjects/Keywords: Datacenter; Field Programmable Gate Array; High-Level Synthesis; 0464

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APA (6th Edition):

Tai, J. I. (2017). High-level Synthesis of Datacenter Services. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/76671

Chicago Manual of Style (16th Edition):

Tai, Justin Isaiah. “High-level Synthesis of Datacenter Services.” 2017. Masters Thesis, University of Toronto. Accessed April 18, 2021. http://hdl.handle.net/1807/76671.

MLA Handbook (7th Edition):

Tai, Justin Isaiah. “High-level Synthesis of Datacenter Services.” 2017. Web. 18 Apr 2021.

Vancouver:

Tai JI. High-level Synthesis of Datacenter Services. [Internet] [Masters thesis]. University of Toronto; 2017. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1807/76671.

Council of Science Editors:

Tai JI. High-level Synthesis of Datacenter Services. [Masters Thesis]. University of Toronto; 2017. Available from: http://hdl.handle.net/1807/76671


University of Toronto

19. Choi, Jongsok. Enabling Hardware/Software Co-design in High-level Synthesis.

Degree: 2012, University of Toronto

A hardware implementation can bring orders of magnitude improvements in performance and energy consumption over a software implementation. Hardware design, however, can be extremely difficult.… (more)

Subjects/Keywords: FPGA; high-level synthesis; hardware/software co-design; LegUp; 0544; 0984

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Choi, J. (2012). Enabling Hardware/Software Co-design in High-level Synthesis. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/33380

Chicago Manual of Style (16th Edition):

Choi, Jongsok. “Enabling Hardware/Software Co-design in High-level Synthesis.” 2012. Masters Thesis, University of Toronto. Accessed April 18, 2021. http://hdl.handle.net/1807/33380.

MLA Handbook (7th Edition):

Choi, Jongsok. “Enabling Hardware/Software Co-design in High-level Synthesis.” 2012. Web. 18 Apr 2021.

Vancouver:

Choi J. Enabling Hardware/Software Co-design in High-level Synthesis. [Internet] [Masters thesis]. University of Toronto; 2012. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1807/33380.

Council of Science Editors:

Choi J. Enabling Hardware/Software Co-design in High-level Synthesis. [Masters Thesis]. University of Toronto; 2012. Available from: http://hdl.handle.net/1807/33380


Brigham Young University

20. Ashcraft, Matthew B. Compiler-Based Tools to Aid in Data Transfer Optimization and On-Chip Debug of Heterogeneous Compute Systems.

Degree: PhD, 2020, Brigham Young University

 First, we present techniques to efficiently schedule data transfers through compiler analyses. Compared to transferring data immediately before and after the kernel executes, our scheduling… (more)

Subjects/Keywords: compilers; accelerators; GPGPU; data transfers; HLS; high-level Synthesis; FPGA; Engineering

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APA (6th Edition):

Ashcraft, M. B. (2020). Compiler-Based Tools to Aid in Data Transfer Optimization and On-Chip Debug of Heterogeneous Compute Systems. (Doctoral Dissertation). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9613&context=etd

Chicago Manual of Style (16th Edition):

Ashcraft, Matthew B. “Compiler-Based Tools to Aid in Data Transfer Optimization and On-Chip Debug of Heterogeneous Compute Systems.” 2020. Doctoral Dissertation, Brigham Young University. Accessed April 18, 2021. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9613&context=etd.

MLA Handbook (7th Edition):

Ashcraft, Matthew B. “Compiler-Based Tools to Aid in Data Transfer Optimization and On-Chip Debug of Heterogeneous Compute Systems.” 2020. Web. 18 Apr 2021.

Vancouver:

Ashcraft MB. Compiler-Based Tools to Aid in Data Transfer Optimization and On-Chip Debug of Heterogeneous Compute Systems. [Internet] [Doctoral dissertation]. Brigham Young University; 2020. [cited 2021 Apr 18]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9613&context=etd.

Council of Science Editors:

Ashcraft MB. Compiler-Based Tools to Aid in Data Transfer Optimization and On-Chip Debug of Heterogeneous Compute Systems. [Doctoral Dissertation]. Brigham Young University; 2020. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9613&context=etd


University of Illinois – Chicago

21. Liu, Yu. Power and Energy Efficient Error Detection Techniques.

Degree: 2013, University of Illinois – Chicago

 Over the past decades significant technological progress has been made in Very Deep Sub-Micron and nanometer technology domains. However, the performance improvement due to shrinking… (more)

Subjects/Keywords: high level synthesis; faulty security; power efficiency; integer linear programing

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APA (6th Edition):

Liu, Y. (2013). Power and Energy Efficient Error Detection Techniques. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/10015

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Yu. “Power and Energy Efficient Error Detection Techniques.” 2013. Thesis, University of Illinois – Chicago. Accessed April 18, 2021. http://hdl.handle.net/10027/10015.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Yu. “Power and Energy Efficient Error Detection Techniques.” 2013. Web. 18 Apr 2021.

Vancouver:

Liu Y. Power and Energy Efficient Error Detection Techniques. [Internet] [Thesis]. University of Illinois – Chicago; 2013. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10027/10015.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Power and Energy Efficient Error Detection Techniques. [Thesis]. University of Illinois – Chicago; 2013. Available from: http://hdl.handle.net/10027/10015

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

22. Ren, X. (author). RTL Implementation of an Optical Flow Algorithm (Lucas) Using the Catapult C High-Level Synthesis tool.

Degree: 2011, Delft University of Technology

With the development of the technology, today's digital systems' growing design complexity has outpaced the traditional RTL design flow. The manual steps of micro-architecture definition,… (more)

Subjects/Keywords: optical flow algorithm; high-level synthesis; catapult C

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APA (6th Edition):

Ren, X. (. (2011). RTL Implementation of an Optical Flow Algorithm (Lucas) Using the Catapult C High-Level Synthesis tool. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:a5fd26f9-f5de-4d8c-9043-92a92f83dd6c

Chicago Manual of Style (16th Edition):

Ren, X (author). “RTL Implementation of an Optical Flow Algorithm (Lucas) Using the Catapult C High-Level Synthesis tool.” 2011. Masters Thesis, Delft University of Technology. Accessed April 18, 2021. http://resolver.tudelft.nl/uuid:a5fd26f9-f5de-4d8c-9043-92a92f83dd6c.

MLA Handbook (7th Edition):

Ren, X (author). “RTL Implementation of an Optical Flow Algorithm (Lucas) Using the Catapult C High-Level Synthesis tool.” 2011. Web. 18 Apr 2021.

Vancouver:

Ren X(. RTL Implementation of an Optical Flow Algorithm (Lucas) Using the Catapult C High-Level Synthesis tool. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2021 Apr 18]. Available from: http://resolver.tudelft.nl/uuid:a5fd26f9-f5de-4d8c-9043-92a92f83dd6c.

Council of Science Editors:

Ren X(. RTL Implementation of an Optical Flow Algorithm (Lucas) Using the Catapult C High-Level Synthesis tool. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:a5fd26f9-f5de-4d8c-9043-92a92f83dd6c


University of Windsor

23. Janik, Ian Spencer. High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs.

Degree: MA, Electrical and Computer Engineering, 2015, University of Windsor

  Secure hash algorithms (SHAs) are important components of cryptographic applications. SHA performance on central processing units (CPUs) is slow, therefore, acceleration must be done… (more)

Subjects/Keywords: FPGAs; Hardware Acceleration; High Level Synthesis; SHA1; SHA2; SHA3

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APA (6th Edition):

Janik, I. S. (2015). High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5470

Chicago Manual of Style (16th Edition):

Janik, Ian Spencer. “High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs.” 2015. Masters Thesis, University of Windsor. Accessed April 18, 2021. https://scholar.uwindsor.ca/etd/5470.

MLA Handbook (7th Edition):

Janik, Ian Spencer. “High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs.” 2015. Web. 18 Apr 2021.

Vancouver:

Janik IS. High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs. [Internet] [Masters thesis]. University of Windsor; 2015. [cited 2021 Apr 18]. Available from: https://scholar.uwindsor.ca/etd/5470.

Council of Science Editors:

Janik IS. High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs. [Masters Thesis]. University of Windsor; 2015. Available from: https://scholar.uwindsor.ca/etd/5470


Georgia Tech

24. Kersey, Chad Daniel. A multi-paradigm C++-based hardware description language.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 A generative hardware description library for C++, the CHDL Hardware Design Library or CHDL, along with a body of supporting libraries and a description of… (more)

Subjects/Keywords: Hardware description language; HDL; Domain-specific language; High-level synthesis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kersey, C. D. (2019). A multi-paradigm C++-based hardware description language. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62342

Chicago Manual of Style (16th Edition):

Kersey, Chad Daniel. “A multi-paradigm C++-based hardware description language.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/62342.

MLA Handbook (7th Edition):

Kersey, Chad Daniel. “A multi-paradigm C++-based hardware description language.” 2019. Web. 18 Apr 2021.

Vancouver:

Kersey CD. A multi-paradigm C++-based hardware description language. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/62342.

Council of Science Editors:

Kersey CD. A multi-paradigm C++-based hardware description language. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62342


Virginia Tech

25. Shi, Zhun. Rapid Prototyping of an FPGA-Based Video Processing System.

Degree: MS, Computer Engineering, 2016, Virginia Tech

 Computer vision technology can be seen in a variety of applications ranging from mobile phones to autonomous vehicles. Many computer vision applications such as drones… (more)

Subjects/Keywords: FPGA; Computer Vision; Video Processing; Rapid Prototyping; High-Level Synthesis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shi, Z. (2016). Rapid Prototyping of an FPGA-Based Video Processing System. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/71389

Chicago Manual of Style (16th Edition):

Shi, Zhun. “Rapid Prototyping of an FPGA-Based Video Processing System.” 2016. Masters Thesis, Virginia Tech. Accessed April 18, 2021. http://hdl.handle.net/10919/71389.

MLA Handbook (7th Edition):

Shi, Zhun. “Rapid Prototyping of an FPGA-Based Video Processing System.” 2016. Web. 18 Apr 2021.

Vancouver:

Shi Z. Rapid Prototyping of an FPGA-Based Video Processing System. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10919/71389.

Council of Science Editors:

Shi Z. Rapid Prototyping of an FPGA-Based Video Processing System. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/71389


University of Texas – Austin

26. Lavasani, Maysam. Generating irregular data-stream accelerators : methodology and applications.

Degree: PhD, Electrical and Computer Engineering, 2015, University of Texas – Austin

 This thesis presents Gorilla++, a language and a compiler for generating customized hardware accelerators that process input streams of data. Gorilla++ uses a hierarchical programming… (more)

Subjects/Keywords: Hardware accelerators; High-level synthesis; Auto-refinement; Big-data

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APA (6th Edition):

Lavasani, M. (2015). Generating irregular data-stream accelerators : methodology and applications. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/31409

Chicago Manual of Style (16th Edition):

Lavasani, Maysam. “Generating irregular data-stream accelerators : methodology and applications.” 2015. Doctoral Dissertation, University of Texas – Austin. Accessed April 18, 2021. http://hdl.handle.net/2152/31409.

MLA Handbook (7th Edition):

Lavasani, Maysam. “Generating irregular data-stream accelerators : methodology and applications.” 2015. Web. 18 Apr 2021.

Vancouver:

Lavasani M. Generating irregular data-stream accelerators : methodology and applications. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2015. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2152/31409.

Council of Science Editors:

Lavasani M. Generating irregular data-stream accelerators : methodology and applications. [Doctoral Dissertation]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/31409


Rochester Institute of Technology

27. Morrison, Braeden. Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms.

Degree: MS, Computer Engineering, 2020, Rochester Institute of Technology

  It is well-known that custom hardware accelerators implemented as application-specific integrated circuits (ASICs) or on field-programmable gate arrays (FPGAs) can solve many problems much… (more)

Subjects/Keywords: Field-programmable gate array; High-level synthesis; Recursion

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APA (6th Edition):

Morrison, B. (2020). Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10617

Chicago Manual of Style (16th Edition):

Morrison, Braeden. “Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms.” 2020. Masters Thesis, Rochester Institute of Technology. Accessed April 18, 2021. https://scholarworks.rit.edu/theses/10617.

MLA Handbook (7th Edition):

Morrison, Braeden. “Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms.” 2020. Web. 18 Apr 2021.

Vancouver:

Morrison B. Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms. [Internet] [Masters thesis]. Rochester Institute of Technology; 2020. [cited 2021 Apr 18]. Available from: https://scholarworks.rit.edu/theses/10617.

Council of Science Editors:

Morrison B. Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms. [Masters Thesis]. Rochester Institute of Technology; 2020. Available from: https://scholarworks.rit.edu/theses/10617


University of Illinois – Urbana-Champaign

28. Papakonstantinou, Alexandros. High-level automation of custom hardware design for high-performance computing.

Degree: PhD, 1200, 2013, University of Illinois – Urbana-Champaign

 This dissertation focuses on efficient generation of custom processors from high-level language descriptions. Our work exploits compiler-based optimizations and transformations in tandem with high-level synthesis(more)

Subjects/Keywords: High-level synthesis; Field-Programmable Gate Array (FPGA); CUDA; parallel programming; High Performance Computing (HPC)

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APA (6th Edition):

Papakonstantinou, A. (2013). High-level automation of custom hardware design for high-performance computing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/42137

Chicago Manual of Style (16th Edition):

Papakonstantinou, Alexandros. “High-level automation of custom hardware design for high-performance computing.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 18, 2021. http://hdl.handle.net/2142/42137.

MLA Handbook (7th Edition):

Papakonstantinou, Alexandros. “High-level automation of custom hardware design for high-performance computing.” 2013. Web. 18 Apr 2021.

Vancouver:

Papakonstantinou A. High-level automation of custom hardware design for high-performance computing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2142/42137.

Council of Science Editors:

Papakonstantinou A. High-level automation of custom hardware design for high-performance computing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/42137


Brno University of Technology

29. Nosko, Svetozár. Akcelerace HDR tone-mappingu na platformě Xilinx Zynq: HDR Tone-Mapping Acceleration on Xilinx Zynq Platform.

Degree: 2018, Brno University of Technology

 This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This… (more)

Subjects/Keywords: Xilinx Zynq; SoC; HLS; High Level Synthesis; Vivado; Vivado HLS; HDR; mapovanie tónov; Xilinx Zynq; SoC; HLS; High Level Synthesis; Vivado; Vivado HLS; HDR; tone mapping

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APA (6th Edition):

Nosko, S. (2018). Akcelerace HDR tone-mappingu na platformě Xilinx Zynq: HDR Tone-Mapping Acceleration on Xilinx Zynq Platform. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/61821

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nosko, Svetozár. “Akcelerace HDR tone-mappingu na platformě Xilinx Zynq: HDR Tone-Mapping Acceleration on Xilinx Zynq Platform.” 2018. Thesis, Brno University of Technology. Accessed April 18, 2021. http://hdl.handle.net/11012/61821.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nosko, Svetozár. “Akcelerace HDR tone-mappingu na platformě Xilinx Zynq: HDR Tone-Mapping Acceleration on Xilinx Zynq Platform.” 2018. Web. 18 Apr 2021.

Vancouver:

Nosko S. Akcelerace HDR tone-mappingu na platformě Xilinx Zynq: HDR Tone-Mapping Acceleration on Xilinx Zynq Platform. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/11012/61821.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nosko S. Akcelerace HDR tone-mappingu na platformě Xilinx Zynq: HDR Tone-Mapping Acceleration on Xilinx Zynq Platform. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/61821

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

30. Choi, Jongsok. From Software Threads to Parallel Hardware with LegUp High-level Synthesis.

Degree: PhD, 2016, University of Toronto

High-level synthesis (HLS) can automatically synthesize software to hardware. With the design specification in software, HLS can reduce the lengthy design cycles of hardware, and… (more)

Subjects/Keywords: Field-programmable gate array; Hardware/Software co-design; High-level synthesis; LegUp High-Level Synthesis Framework; Parallel hardware; System-on-Chip; 0464

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Choi, J. (2016). From Software Threads to Parallel Hardware with LegUp High-level Synthesis. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/76380

Chicago Manual of Style (16th Edition):

Choi, Jongsok. “From Software Threads to Parallel Hardware with LegUp High-level Synthesis.” 2016. Doctoral Dissertation, University of Toronto. Accessed April 18, 2021. http://hdl.handle.net/1807/76380.

MLA Handbook (7th Edition):

Choi, Jongsok. “From Software Threads to Parallel Hardware with LegUp High-level Synthesis.” 2016. Web. 18 Apr 2021.

Vancouver:

Choi J. From Software Threads to Parallel Hardware with LegUp High-level Synthesis. [Internet] [Doctoral dissertation]. University of Toronto; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1807/76380.

Council of Science Editors:

Choi J. From Software Threads to Parallel Hardware with LegUp High-level Synthesis. [Doctoral Dissertation]. University of Toronto; 2016. Available from: http://hdl.handle.net/1807/76380

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