subject:(High level synthesis)

University of Illinois – Urbana-Champaign

1. Sun, Zelei. VAST-LP: clock gating in high-level synthesis.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

► High-level synthesis (HLS) promises high-quality hardware with minimal develop- ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST and propose… (more)

Subjects/Keywords: low power; high level synthesis

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Sun, Z. (2016). VAST-LP: clock gating in high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Sun, Zelei. “VAST-LP: clock gating in high-level synthesis.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed April 18, 2021. http://hdl.handle.net/2142/90970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Sun, Zelei. “VAST-LP: clock gating in high-level synthesis.” 2016. Web. 18 Apr 2021.

Vancouver:

Sun Z. VAST-LP: clock gating in high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2142/90970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sun Z. VAST-LP: clock gating in high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. -7307-3794. Approximate high-level synthesis of quality and energy optimized hardware processors.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

URL: http://hdl.handle.net/2152/63811

► Approximate computing is a technique that exploits trade-offs between energy/performance and quality of computed results. Such techniques have been explored at various design levels for… (more)

▼ Approximate computing is a technique that exploits trade-offs between energy/performance and quality of computed results. Such techniques have been explored at various design levels for inherently error-tolerant applications, such as image/video processing and machine learning. At the hardware level, various components, such as arithmetic and logic units (ALUs) or memories have been proposed to build general processor or custom hardware designs. Existing work on designing custom approximate hardware processors has been mostly ad-hoc or using expensive iterative simulation and re-synthesis for design space exploration. In this dissertation, the focus is on a novel approximate high-level synthesis (AHLS) approach that utilizes approximate operators in synthesizing an energy-optimal register-transfer level (RTL) design from its high-level C description under overall quality constraints at the design's outputs. In effective AHLS, fast and accurate quality and energy models are required together with an optimization technique to efficiently find an optimal design. Quality effects of hardware approximations strongly depend on input data. Existing work either uses over-simplified models or relies on time-consuming simulations. By contrast, in this work, a statistical formulation is employed to capture input dependency and analytically estimate quality using one-time profiling only. Such a quality analysis is first presented for fine-grain bit length optimization of individual operations in a given design. The analysis approach is then further extended to support general hardware approximations using arbitrary adder and multiplier designs proposed in literature. Energy savings due to approximations stem from reductions in both switching activity and delay. The latter can be exploited for voltage scaling, but existing approaches do not fully exploit such opportunities. To include voltage scaling in energy savings, a novel approach is presented that estimates the performance impact of approximations while taking into account the tight interactions with existing scheduling and binding tasks in an overall high-level synthesis framework. Quality, performance, and energy estimation methods presented in this dissertation are further combined with a novel AHLS-specific optimization technique and heuristic solver that finds a near-optimal solutions efficiently in a breadth-first manner. Results show that quality estimation is 28 times faster than simulation-based approaches, and up to 24.5 % higher energy savings is achieved comparing to approaches that only consider switching activity. The heuristic solver is able to find Pareto-optimal solutions within 0.1 % compared to an exhaustive search, all while being up to 168 times faster. The models and AHLS flow are further extended to incorporate a novel loop approximation technique, which mainly targets performance improvements. Loops are often the most performance-critical application code structures, and in a loop, different iterations can have different impact on output quality… Advisors/Committee Members: Gerstlauer, Andreas, 1970- (advisor), Swartzlander, Earl (committee member), John, Lizy K (committee member), Orshansky, Michael (committee member), Han, Kyungtae (committee member).

Subjects/Keywords: Approximate computing; High-level synthesis

8 more images…

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

-7307-3794. (2018). Approximate high-level synthesis of quality and energy optimized hardware processors. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63811

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16^th Edition):

-7307-3794. “Approximate high-level synthesis of quality and energy optimized hardware processors.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed April 18, 2021. http://hdl.handle.net/2152/63811.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7^th Edition):

-7307-3794. “Approximate high-level synthesis of quality and energy optimized hardware processors.” 2018. Web. 18 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-7307-3794. Approximate high-level synthesis of quality and energy optimized hardware processors. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2152/63811.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-7307-3794. Approximate high-level synthesis of quality and energy optimized hardware processors. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/63811

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

University of Texas – Austin

3. Lee, Dongwook. Learning-based system-level power modeling of hardware IPs.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin

URL: http://hdl.handle.net/2152/63013

► Accurate power models for hardware components at high levels of abstraction are a critical component to enable system-level power analysis and optimization. Virtual platform prototypes… (more)

▼ Accurate power models for hardware components at high levels of abstraction are a critical component to enable system-level power analysis and optimization. Virtual platform prototypes are widely utilized to support early system-level design space exploration. There is, however, a lack of accurate and fast power models of hardware components at such high-levels of abstraction. In this dissertation, we present novel learning‑based approaches for extending fast functional simulation models of white-, gray-, and black-box custom hardware intellectual property components (IPs) with accurate power estimates. Depending on the observability, we extend high-level functional models with the capability to capture data-dependent resource, block, or I/O activity without a significant loss in simulation speed. We further leverage state-of-the-art machine learning techniques to synthesize abstract power models that can predict cycle-, block-, and invocation-level power from low-level hardware implementations, where we introduce novel structural decomposition techniques to reduce model complexities and increase estimation accuracy. Our white-box approach integrates with existing high-level synthesis (HLS) tools to automatically extract resource mapping information, which is used to trace data-dependent resource-level activity and drive a cycle-accurate online power-performance model during functional simulation. Our gray-box approach supports power estimation at coarser basic block granularity. It uses only limited information about block inputs and outputs to extract light-weight block-level activity from a functional simulation and drive a basic block-level power model that utilizes a control flow decomposition to improve accuracy and speed. It is faster than cycle-level models, while providing a finer granularity than invocation-level models, which allows to further navigate accuracy and speed trade-offs. We finally propose a novel approach for extending behavioral models of black-box hardware IPs with an invocation-level power estimate. Our black-box model only uses input and output history to track data-dependent pipeline behavior, where we introduce a specialized ensemble learning that is composed out of individually selected cycle-by-cycle models with reduced complexity and increased accuracy. The proposed approaches are fully automated by integrating with existing, commercial HLS tools for custom hardware synthesized by HLS. Results of applying our approaches to various industrial‑strength design examples show that our power models can predict cycle‑, basic block-, and invocation-level power consumption to within 10%, 9%, and 3% of a commercial gate-level power estimation tool, respectively, all while running at several order of magnitude faster speeds of 1-10Mcycles/sec. Advisors/Committee Members: Gerstlauer, Andreas, 1970- (advisor), Abraham, Jacob (committee member), John, Lizy K. (committee member), Pingali, Keshav (committee member), Kim, Taemin (committee member).

Subjects/Keywords: Power estimation; High-level synthesis

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lee, D. (2017). Learning-based system-level power modeling of hardware IPs. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63013

Chicago Manual of Style (16^th Edition):

Lee, Dongwook. “Learning-based system-level power modeling of hardware IPs.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed April 18, 2021. http://hdl.handle.net/2152/63013.

MLA Handbook (7^th Edition):

Lee, Dongwook. “Learning-based system-level power modeling of hardware IPs.” 2017. Web. 18 Apr 2021.

Vancouver:

Lee D. Learning-based system-level power modeling of hardware IPs. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2152/63013.

Council of Science Editors:

Lee D. Learning-based system-level power modeling of hardware IPs. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/63013

Penn State University

4. Chen, Yibo. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS .

Degree: 2011, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/12416

► Variability in circuit delay and power dissipation is one of the most critical challenges in nanometer VLSI era. Traditionally, performance/power variations are handled by a… (more)

Subjects/Keywords: High-Level Synthesis; Behavioral Synthesis; ESL

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chen, Y. (2011). VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12416

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Yibo. “VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS .” 2011. Thesis, Penn State University. Accessed April 18, 2021. https://submit-etda.libraries.psu.edu/catalog/12416.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Yibo. “VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS .” 2011. Web. 18 Apr 2021.

Vancouver:

Chen Y. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS . [Internet] [Thesis]. Penn State University; 2011. [cited 2021 Apr 18]. Available from: https://submit-etda.libraries.psu.edu/catalog/12416.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12416

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Texas A&M University

5. Li, Chaofan. Synthesis Techniques for Power-Efficient Integrated Circuits.

Degree: PhD, Computer Engineering, 2018, Texas A&M University

URL: http://hdl.handle.net/1969.1/173652

► In the past few years, power efficiency has been increasingly important for integrated circuits. As the Moore’s law effects slows down, the improvement of power… (more)

▼ In the past few years, power efficiency has been increasingly important for integrated circuits. As the Moore’s law effects slows down, the improvement of power consumption through scaling of silicon process technology is hitting the limits. At the same time, IC chips are more often embedded into mobile devices, which usually have no outer continuous power supply. The power efficiency is even more critical due to the limited electricity stored in batteries of these mobile devices. Besides, the high-performance ICs used in server farms or data centers also require improved power efficiency to alleviate the heat dissipation of the chips, which causes additional cost to lower the temperature of the facilities. The profit of crypto-currency mining is even directly affected by the electrical energy consumption of the mining hardware including ASICs, GPUs and FPGAs, which accounts for the largest part of the cost. Thus, more techniques for power efficiency were exploited in recent years to achieve further power reduction in addition to that achieved by silicon process advancements. Among the techniques for improving power efficiency, approximate computing has been recognized as an effective low power technique for applications with intrinsic error tolerance, such as image processing and machine learning. Existing efforts on this are mostly focused on approximate circuit design, approximate logic synthesis or processor architecture approximation techniques. Chapter 2 of this research aims to make good use of approximate circuits at system and block levels. In particular, approximation aware scheduling, functional unit allocation and binding algorithms are developed for data intensive applications. Simple yet credible error models, essential for precision control in the optimizations, are investigated. The algorithms are further extended to include bitwidth optimization in fixed point computations. Experimental results, including those from Verilog simulations, indicate that the proposed techniques facilitate desired energy savings under latency and accuracy constraints. With their flexibility in allowing reconfiguration for different applications, hardware such as FPGAs have become increasingly preferred over ASICs as a platform for high-performance comii puting like accelerators. However, this advantage is partially defeated by the time-intensive highlevel synthesis (HLS) process and the poor controllability for the synthesized architecture. We propose a fast mapping-based high level synthesis technique friendly to local incremental change. It exploits the SSA (Static Single Assignment) form with array SSA extension and ϕ-function based flow control. It first maps the SSA form based IR to a fully pipelined circuit, then alters the circuit to a partially pipelined or nonpipelined circuit by resource sharing in an optional phase of resource optimization. Pipeline interlocking to address the pipeline hazards is also provided, which has better power-efficiency. Adaptive Supply Voltage (ASV) is another power-efficient approach… Advisors/Committee Members: Hu, Jiang (advisor), Choi, Gwan S (committee member), Walker, Duncan M (committee member), Liu, Tie (committee member).

Subjects/Keywords: High-Level Synthesis; Adaptive Supply Voltage

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Li, C. (2018). Synthesis Techniques for Power-Efficient Integrated Circuits. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173652

Chicago Manual of Style (16^th Edition):

Li, Chaofan. “Synthesis Techniques for Power-Efficient Integrated Circuits.” 2018. Doctoral Dissertation, Texas A&M University. Accessed April 18, 2021. http://hdl.handle.net/1969.1/173652.

MLA Handbook (7^th Edition):

Li, Chaofan. “Synthesis Techniques for Power-Efficient Integrated Circuits.” 2018. Web. 18 Apr 2021.

Vancouver:

Li C. Synthesis Techniques for Power-Efficient Integrated Circuits. [Internet] [Doctoral dissertation]. Texas A&M University; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1969.1/173652.

Council of Science Editors:

Li C. Synthesis Techniques for Power-Efficient Integrated Circuits. [Doctoral Dissertation]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173652

University of Waterloo

6. Morcos, Benjamin. NengoFPGA: an FPGA Backend for the Nengo Neural Simulator.

Degree: 2019, University of Waterloo

URL: http://hdl.handle.net/10012/14923

► Low-power, high-speed neural networks are critical for providing deployable embedded AI applications at the edge. We describe a Xilinx FPGA implementation of Neural Engineering Framework… (more)

▼ Low-power, high-speed neural networks are critical for providing deployable embedded AI applications at the edge. We describe a Xilinx FPGA implementation of Neural Engineering Framework (NEF) networks with online learning that outperforms mobile Nvidia GPU implementations by an order of magnitude or more. Specifically, we provide an embedded Python-capable PYNQ FPGA implementation supported with a Xilinx Vivado High-Level Synthesis (HLS) workflow that allows sub-millisecond implementation of adaptive neural networks with low-latency, direct I/O access to the physical world. The outcome of this work is NengoFPGA, a seamless and user-friendly extension to the neural compiler Python package Nengo. To reduce memory requirements and improve performance we tune the precision of the different intermediate variables in the code to achieve competitive absolute accuracy against slower and larger floating-point reference designs. The online learning component of the neural network exploits immediate feedback to adjust the network weights to best support a given arithmetic precision. As the space of possible design configurations of such quantized networks is vast and is subject to a target accuracy constraint, we use the Hyperopt hyper-parameter tuning tool instead of manual search to find Pareto optimal designs. Specifically, we are able to generate the optimized designs in under 500 short iterations of Vivado HLS C synthesis before running the complete Vivado place-and-route phase on that subset, a much longer process not conducive to rapid exploration. For neural network populations of 64–4096 neurons and 1–8 representational dimensions our optimized FPGA implementation generated by Hyperopt has a speedup of 10–484× over a competing cuBLAS implementation on the Jetson TX1 GPU while using 2.4–9.5× less power. Our speedups are a result of HLS-specific reformulation (15× improvement), precision adaptation (3× improvement), and low-latency direct I/O access (1000× improvement).

Subjects/Keywords: neural networks; FPGA; nengo; high-level synthesis

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Morcos, B. (2019). NengoFPGA: an FPGA Backend for the Nengo Neural Simulator. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/14923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Morcos, Benjamin. “NengoFPGA: an FPGA Backend for the Nengo Neural Simulator.” 2019. Thesis, University of Waterloo. Accessed April 18, 2021. http://hdl.handle.net/10012/14923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Morcos, Benjamin. “NengoFPGA: an FPGA Backend for the Nengo Neural Simulator.” 2019. Web. 18 Apr 2021.

Vancouver:

Morcos B. NengoFPGA: an FPGA Backend for the Nengo Neural Simulator. [Internet] [Thesis]. University of Waterloo; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10012/14923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Morcos B. NengoFPGA: an FPGA Backend for the Nengo Neural Simulator. [Thesis]. University of Waterloo; 2019. Available from: http://hdl.handle.net/10012/14923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Toronto

7. Darounkola, Nazanin Calagar. Source-level Debugging Framework Design for FPGA High-level Synthesis.

Degree: 2014, University of Toronto

URL: http://hdl.handle.net/1807/68069

►

HighLevel Synthesis tools have become more attractive in recent years. However, in order to be fully utilized for largescale applications, HLS tools need to address… (more)

Subjects/Keywords: Debugging; FPGA; High-level synthesis; 0464

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Darounkola, N. C. (2014). Source-level Debugging Framework Design for FPGA High-level Synthesis. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/68069

Chicago Manual of Style (16^th Edition):

Darounkola, Nazanin Calagar. “Source-level Debugging Framework Design for FPGA High-level Synthesis.” 2014. Masters Thesis, University of Toronto. Accessed April 18, 2021. http://hdl.handle.net/1807/68069.

MLA Handbook (7^th Edition):

Darounkola, Nazanin Calagar. “Source-level Debugging Framework Design for FPGA High-level Synthesis.” 2014. Web. 18 Apr 2021.

Vancouver:

Darounkola NC. Source-level Debugging Framework Design for FPGA High-level Synthesis. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1807/68069.

Council of Science Editors:

Darounkola NC. Source-level Debugging Framework Design for FPGA High-level Synthesis. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/68069

University of Toronto

8. Liu, Li. Automated Debugging Framework for High-level Synthesis.

Degree: 2013, University of Toronto

URL: http://hdl.handle.net/1807/35123

►

This thesis proposes a automated test case generation technique for the aim of verifying/debugging High-level synthesis (HLS) tools. The work in this thesis builds a… (more)

Subjects/Keywords: Debug; High-level Synthesis; 0544; 0984

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liu, L. (2013). Automated Debugging Framework for High-level Synthesis. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/35123

Chicago Manual of Style (16^th Edition):

Liu, Li. “Automated Debugging Framework for High-level Synthesis.” 2013. Masters Thesis, University of Toronto. Accessed April 18, 2021. http://hdl.handle.net/1807/35123.

MLA Handbook (7^th Edition):

Liu, Li. “Automated Debugging Framework for High-level Synthesis.” 2013. Web. 18 Apr 2021.

Vancouver:

Liu L. Automated Debugging Framework for High-level Synthesis. [Internet] [Masters thesis]. University of Toronto; 2013. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1807/35123.

Council of Science Editors:

Liu L. Automated Debugging Framework for High-level Synthesis. [Masters Thesis]. University of Toronto; 2013. Available from: http://hdl.handle.net/1807/35123

Princeton University

9. Liu, Feng. Static and Dynamic Instruction Mappingfor Spatial Architectures .

Degree: PhD, 2018, Princeton University

URL: http://arks.princeton.edu/ark:/88435/dsp01kk91fp258

► In response to the technology scaling trends, spatial architectures have emerged as a new style of processors for executing programs more efficiently. Unlike traditional Out-of-Order… (more)

▼ In response to the technology scaling trends, spatial architectures have emerged as a new style of processors for executing programs more efficiently. Unlike traditional Out-of-Order (OoO) processors, which time-share a small set of functional units, a spatial computer is composed of hundreds or even thousands of simple and replicated functional units. Spatial architectures avoid the overheads of time-sharing and of generating schedules repeatedly, by mapping instruction sequences onto the functional units explicitly and reusing the schedules across multiple invocations. Currently, spatial architectures mainly use static methods to map instructions onto the arrays of functional units. The existing methods have several limitations: First, for programs with irregular memory accesses and control flows, they yield poor performance because the functional units need to be invoked sequentially to respect data and control dependences. Second, static methods cannot fully exploit speculation techniques, which are the dominant performance sources in OoO processors. Finally, static methods cannot adapt to changing workloads and are not compatible across hardware generations. To address these issues and improve the applicability of spatial architectures, this dissertation proposes two techniques. The first, Coarse-Grained Pipelined Accelerators (CGPA), is a static compiling framework that exploits the hidden parallelism within irregular C/C++ loops and translates them into spatial hardware modules. The proposed technique has been implemented as a compiler pass and the experiment shows 3.3x speedup over the performance achieved by an open-source tool baseline. The second technique, Dynamic Spatial Architecture Mapping (DYNASPAM), reuses the speculation system in the OoO processors to dynamically produce high-performance scheduling and execution on a dedicated spatial fabric. The proposed technique is modeled by a cycle accurate simulator and the experiment shows the new technique can achieve 1.4x geomean performance improvement and 23.9% energy consumption reduction, compared to an OoO processor baseline. Advisors/Committee Members: August, David (advisor).

Subjects/Keywords: compiling; computer architecture; high level synthesis; reconfigurable

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liu, F. (2018). Static and Dynamic Instruction Mappingfor Spatial Architectures . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01kk91fp258

Chicago Manual of Style (16^th Edition):

Liu, Feng. “Static and Dynamic Instruction Mappingfor Spatial Architectures .” 2018. Doctoral Dissertation, Princeton University. Accessed April 18, 2021. http://arks.princeton.edu/ark:/88435/dsp01kk91fp258.

MLA Handbook (7^th Edition):

Liu, Feng. “Static and Dynamic Instruction Mappingfor Spatial Architectures .” 2018. Web. 18 Apr 2021.

Vancouver:

Liu F. Static and Dynamic Instruction Mappingfor Spatial Architectures . [Internet] [Doctoral dissertation]. Princeton University; 2018. [cited 2021 Apr 18]. Available from: http://arks.princeton.edu/ark:/88435/dsp01kk91fp258.

Council of Science Editors:

Liu F. Static and Dynamic Instruction Mappingfor Spatial Architectures . [Doctoral Dissertation]. Princeton University; 2018. Available from: http://arks.princeton.edu/ark:/88435/dsp01kk91fp258

University of Windsor

10. Tang, Qing Yun. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.

Degree: MA, Electrical and Computer Engineering, 2016, University of Windsor

URL: https://scholar.uwindsor.ca/etd/5669

► FPGAs have shown great promise for accelerating computationally intensive algorithms. However, FPGA-based accelerator design is tedious and time consuming if we rely on traditional HDL… (more)

Subjects/Keywords: FPGA; Hardware Acceleration; High Level Synthesis; OpenCL

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tang, Q. Y. (2016). FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5669

Chicago Manual of Style (16^th Edition):

Tang, Qing Yun. “FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.” 2016. Masters Thesis, University of Windsor. Accessed April 18, 2021. https://scholar.uwindsor.ca/etd/5669.

MLA Handbook (7^th Edition):

Tang, Qing Yun. “FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.” 2016. Web. 18 Apr 2021.

Vancouver:

Tang QY. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. [Internet] [Masters thesis]. University of Windsor; 2016. [cited 2021 Apr 18]. Available from: https://scholar.uwindsor.ca/etd/5669.

Council of Science Editors:

Tang QY. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. [Masters Thesis]. University of Windsor; 2016. Available from: https://scholar.uwindsor.ca/etd/5669

11. Sundari, B. Bala Tripura. Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -.

Degree: Engineering, 2004, Amrita Vishwa Vidyapeetham (University)

URL: http://shodhganga.inflibnet.ac.in/handle/10603/13051

►

The high integration density of very large scale integrated (VLSI) circuits has made system on chip design (SoC) become a reality. With increasing complexity of… (more)

Subjects/Keywords: Multi-level nested loop algorithms;

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Sundari, B. B. T. (2004). Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -. (Thesis). Amrita Vishwa Vidyapeetham (University). Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/13051

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Sundari, B Bala Tripura. “Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -.” 2004. Thesis, Amrita Vishwa Vidyapeetham (University). Accessed April 18, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/13051.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Sundari, B Bala Tripura. “Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -.” 2004. Web. 18 Apr 2021.

Vancouver:

Sundari BBT. Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -. [Internet] [Thesis]. Amrita Vishwa Vidyapeetham (University); 2004. [cited 2021 Apr 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13051.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sundari BBT. Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -. [Thesis]. Amrita Vishwa Vidyapeetham (University); 2004. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13051

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

12. Kupka, David. Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy: Mapping of Algorithms to FPGA Using High-Level Synthesis Tools.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/55739

► This thesis deals with ways to describe hardware. It presents the methods used in the synthesis of the description and then it compares on a… (more)

Subjects/Keywords: Vyskoúrovňová syntéza; VHDL; syntéza; popis hardware; srovnání; High-Level Synthesis; VHDL; synthesis; hardware description; comparsion

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kupka, D. (2019). Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy: Mapping of Algorithms to FPGA Using High-Level Synthesis Tools. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/55739

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Kupka, David. “Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy: Mapping of Algorithms to FPGA Using High-Level Synthesis Tools.” 2019. Thesis, Brno University of Technology. Accessed April 18, 2021. http://hdl.handle.net/11012/55739.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Kupka, David. “Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy: Mapping of Algorithms to FPGA Using High-Level Synthesis Tools.” 2019. Web. 18 Apr 2021.

Vancouver:

Kupka D. Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy: Mapping of Algorithms to FPGA Using High-Level Synthesis Tools. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/11012/55739.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kupka D. Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy: Mapping of Algorithms to FPGA Using High-Level Synthesis Tools. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/55739

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Rochester Institute of Technology

13. Soldavini, Stephanie. Using Reduced Graphs for Efficient HLS Scheduling.

Degree: MS, Computer Engineering, 2019, Rochester Institute of Technology

URL: https://scholarworks.rit.edu/theses/10311

► High-Level Synthesis (HLS) is the process of inferring a digital circuit from a high-level algorithmic description provided as a software implementation, usually in C/C++.… (more)

Subjects/Keywords: High-level synthesis; HLS; Reduced data flow graph; Resource efficient; Scheduling

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Soldavini, S. (2019). Using Reduced Graphs for Efficient HLS Scheduling. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10311

Chicago Manual of Style (16^th Edition):

Soldavini, Stephanie. “Using Reduced Graphs for Efficient HLS Scheduling.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed April 18, 2021. https://scholarworks.rit.edu/theses/10311.

MLA Handbook (7^th Edition):

Soldavini, Stephanie. “Using Reduced Graphs for Efficient HLS Scheduling.” 2019. Web. 18 Apr 2021.

Vancouver:

Soldavini S. Using Reduced Graphs for Efficient HLS Scheduling. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2021 Apr 18]. Available from: https://scholarworks.rit.edu/theses/10311.

Council of Science Editors:

Soldavini S. Using Reduced Graphs for Efficient HLS Scheduling. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10311

Rochester Institute of Technology

14. Conn, Bradley E. Exploring High Level Synthesis to Improve the Design of Turbo Code Error Correction in a Software Defined Radio Context.

Degree: MS, Computer Engineering, 2018, Rochester Institute of Technology

URL: https://scholarworks.rit.edu/theses/9839

► With the ever improving progress of technology, Software Defined Radio (SDR) has become a more widely available technique for implementing radio communication. SDRs are… (more)

▼ With the ever improving progress of technology, Software Defined Radio (SDR) has become a more widely available technique for implementing radio communication. SDRs are sought after for their advantages over traditional radio communication mostly in flexibility, and hardware simplification. The greatest challenges SDRs face are often with their real time performance requirements. Forward error correction is an example of an SDR block that can exemplify these challenges as the error correction can be very computationally intensive. Due to these constraints, SDR implementations are commonly found in or alongside Field Programmable Gate Arrays (FPGAs) to enable performance that general purpose processors alone cannot achieve. The main challenge with FPGAs however, is in Register Transfer Level (RTL) development. High Level Synthesis (HLS) tools are a method of creating hardware descriptions from high level code, in an effort to ease this development process. In this work a turbo code decoder, a form of computationally intensive error correction codes, was accelerated with the help of FPGAs, using HLS tools. This accelerator was implemented on a Xilinx Zynq platform, which integrates a hard core ARM processor alongside programmable logic on a single chip. Important aspects of the design process using HLS were identified and explained. The design process emphasizes the idea that for the best results the high level code should be created with a hardware mindset, and written in an attempt to describe a hardware design. The power of the HLS tools was demonstrated in its flexibility by providing a method of tailoring the hardware parameters through simply changing values in a macro file, and by exploration the design space through different data types and three different designs, each one improving from what was learned in the previous implementation. Ultimately, the best hardware implementation was over 56 times faster than the optimized software implementation. Comparing the HLS to a manually optimized design shows that the HLS implementation was able to achieve over a 19% throughput, with many areas for further improvement identified, demonstrating the competitiveness of the HLS tools. Advisors/Committee Members: Sonia Lopez Alarcon.

Subjects/Keywords: High level synthesis; Software defined radio; Turbo code error correction

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Conn, B. E. (2018). Exploring High Level Synthesis to Improve the Design of Turbo Code Error Correction in a Software Defined Radio Context. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9839

Chicago Manual of Style (16^th Edition):

Conn, Bradley E. “Exploring High Level Synthesis to Improve the Design of Turbo Code Error Correction in a Software Defined Radio Context.” 2018. Masters Thesis, Rochester Institute of Technology. Accessed April 18, 2021. https://scholarworks.rit.edu/theses/9839.

MLA Handbook (7^th Edition):

Conn, Bradley E. “Exploring High Level Synthesis to Improve the Design of Turbo Code Error Correction in a Software Defined Radio Context.” 2018. Web. 18 Apr 2021.

Vancouver:

Conn BE. Exploring High Level Synthesis to Improve the Design of Turbo Code Error Correction in a Software Defined Radio Context. [Internet] [Masters thesis]. Rochester Institute of Technology; 2018. [cited 2021 Apr 18]. Available from: https://scholarworks.rit.edu/theses/9839.

Council of Science Editors:

Conn BE. Exploring High Level Synthesis to Improve the Design of Turbo Code Error Correction in a Software Defined Radio Context. [Masters Thesis]. Rochester Institute of Technology; 2018. Available from: https://scholarworks.rit.edu/theses/9839

University of Alberta

15. Hashemi, Seyyed Ali. Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization.

Degree: MS, Department of Electrical and Computer Engineering, 2011, University of Alberta

URL: https://era.library.ualberta.ca/files/gt54kn61s

► This thesis is concerned with the development of a novel discrete particle swarm optimization (PSO) technique and its application to the discrete optimization of digital… (more)

Subjects/Keywords: Particle swarm optimization; Digital filters; High-level synthesis

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hashemi, S. A. (2011). Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/gt54kn61s

Chicago Manual of Style (16^th Edition):

Hashemi, Seyyed Ali. “Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization.” 2011. Masters Thesis, University of Alberta. Accessed April 18, 2021. https://era.library.ualberta.ca/files/gt54kn61s.

MLA Handbook (7^th Edition):

Hashemi, Seyyed Ali. “Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization.” 2011. Web. 18 Apr 2021.

Vancouver:

Hashemi SA. Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization. [Internet] [Masters thesis]. University of Alberta; 2011. [cited 2021 Apr 18]. Available from: https://era.library.ualberta.ca/files/gt54kn61s.

Council of Science Editors:

Hashemi SA. Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization. [Masters Thesis]. University of Alberta; 2011. Available from: https://era.library.ualberta.ca/files/gt54kn61s

University of Illinois – Urbana-Champaign

16. Liu, Xinheng. Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.

Degree: MS, Electrical & Computer Engr, 2018, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/101228

► Targeting convolutional neural networks (CNNs), we adopt the high level synthesis (HLS) design methodology and explore various optimization and synthesis techniques to optimize design on… (more)

Subjects/Keywords: FPGA; Convolutional Neural Network; Optimization; Acceleration; High-Level Synthesis

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liu, X. (2018). Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/101228

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liu, Xinheng. “Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.” 2018. Thesis, University of Illinois – Urbana-Champaign. Accessed April 18, 2021. http://hdl.handle.net/2142/101228.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liu, Xinheng. “Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.” 2018. Web. 18 Apr 2021.

Vancouver:

Liu X. Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2142/101228.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu X. Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices. [Thesis]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/101228

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

North Carolina State University

17. Kim, Taemin. Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs.

Degree: PhD, Computer Engineering, 2009, North Carolina State University

URL: http://www.lib.ncsu.edu/resolver/1840.16/4109

► Optimization techniques during high level synthesis procedure are often preferred since design decisions at early stages of a design Ã¯Â¬â€šow are believed to have a… (more)

Subjects/Keywords: High Level Synthesis; Global Interconnect; VLSI CAD; Optimization; Algorithm

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kim, T. (2009). Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/4109

Chicago Manual of Style (16^th Edition):

Kim, Taemin. “Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs.” 2009. Doctoral Dissertation, North Carolina State University. Accessed April 18, 2021. http://www.lib.ncsu.edu/resolver/1840.16/4109.

MLA Handbook (7^th Edition):

Kim, Taemin. “Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs.” 2009. Web. 18 Apr 2021.

Vancouver:

Kim T. Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs. [Internet] [Doctoral dissertation]. North Carolina State University; 2009. [cited 2021 Apr 18]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4109.

Council of Science Editors:

Kim T. Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs. [Doctoral Dissertation]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4109

University of Toronto

18. Tai, Justin Isaiah. High-level Synthesis of Datacenter Services.

Degree: 2017, University of Toronto

URL: http://hdl.handle.net/1807/76671

►

Field programmable gate arrays have become of great interest for implementing datacenter applications due to high performance gains over traditional compute hardware at a fraction… (more)

Subjects/Keywords: Datacenter; Field Programmable Gate Array; High-Level Synthesis; 0464

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tai, J. I. (2017). High-level Synthesis of Datacenter Services. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/76671

Chicago Manual of Style (16^th Edition):

Tai, Justin Isaiah. “High-level Synthesis of Datacenter Services.” 2017. Masters Thesis, University of Toronto. Accessed April 18, 2021. http://hdl.handle.net/1807/76671.

MLA Handbook (7^th Edition):

Tai, Justin Isaiah. “High-level Synthesis of Datacenter Services.” 2017. Web. 18 Apr 2021.

Vancouver:

Tai JI. High-level Synthesis of Datacenter Services. [Internet] [Masters thesis]. University of Toronto; 2017. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1807/76671.

Council of Science Editors:

Tai JI. High-level Synthesis of Datacenter Services. [Masters Thesis]. University of Toronto; 2017. Available from: http://hdl.handle.net/1807/76671

University of Toronto

19. Choi, Jongsok. Enabling Hardware/Software Co-design in High-level Synthesis.

Degree: 2012, University of Toronto

URL: http://hdl.handle.net/1807/33380

►

A hardware implementation can bring orders of magnitude improvements in performance and energy consumption over a software implementation. Hardware design, however, can be extremely difficult.… (more)

Subjects/Keywords: FPGA; high-level synthesis; hardware/software co-design; LegUp; 0544; 0984

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Choi, J. (2012). Enabling Hardware/Software Co-design in High-level Synthesis. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/33380

Chicago Manual of Style (16^th Edition):

Choi, Jongsok. “Enabling Hardware/Software Co-design in High-level Synthesis.” 2012. Masters Thesis, University of Toronto. Accessed April 18, 2021. http://hdl.handle.net/1807/33380.

MLA Handbook (7^th Edition):

Choi, Jongsok. “Enabling Hardware/Software Co-design in High-level Synthesis.” 2012. Web. 18 Apr 2021.

Vancouver:

Choi J. Enabling Hardware/Software Co-design in High-level Synthesis. [Internet] [Masters thesis]. University of Toronto; 2012. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1807/33380.

Council of Science Editors:

Choi J. Enabling Hardware/Software Co-design in High-level Synthesis. [Masters Thesis]. University of Toronto; 2012. Available from: http://hdl.handle.net/1807/33380

Brigham Young University

20. Ashcraft, Matthew B. Compiler-Based Tools to Aid in Data Transfer Optimization and On-Chip Debug of Heterogeneous Compute Systems.

Degree: PhD, 2020, Brigham Young University

URL: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9613&context=etd

► First, we present techniques to efficiently schedule data transfers through compiler analyses. Compared to transferring data immediately before and after the kernel executes, our scheduling… (more)

Subjects/Keywords: compilers; accelerators; GPGPU; data transfers; HLS; high-level Synthesis; FPGA; Engineering

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ashcraft, M. B. (2020). Compiler-Based Tools to Aid in Data Transfer Optimization and On-Chip Debug of Heterogeneous Compute Systems. (Doctoral Dissertation). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9613&context=etd

Chicago Manual of Style (16^th Edition):

Ashcraft, Matthew B. “Compiler-Based Tools to Aid in Data Transfer Optimization and On-Chip Debug of Heterogeneous Compute Systems.” 2020. Doctoral Dissertation, Brigham Young University. Accessed April 18, 2021. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9613&context=etd.

MLA Handbook (7^th Edition):

Ashcraft, Matthew B. “Compiler-Based Tools to Aid in Data Transfer Optimization and On-Chip Debug of Heterogeneous Compute Systems.” 2020. Web. 18 Apr 2021.

Vancouver:

Ashcraft MB. Compiler-Based Tools to Aid in Data Transfer Optimization and On-Chip Debug of Heterogeneous Compute Systems. [Internet] [Doctoral dissertation]. Brigham Young University; 2020. [cited 2021 Apr 18]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9613&context=etd.

Council of Science Editors:

Ashcraft MB. Compiler-Based Tools to Aid in Data Transfer Optimization and On-Chip Debug of Heterogeneous Compute Systems. [Doctoral Dissertation]. Brigham Young University; 2020. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9613&context=etd

University of Illinois – Chicago

21. Liu, Yu. Power and Energy Efficient Error Detection Techniques.

Degree: 2013, University of Illinois – Chicago

URL: http://hdl.handle.net/10027/10015

► Over the past decades significant technological progress has been made in Very Deep Sub-Micron and nanometer technology domains. However, the performance improvement due to shrinking… (more)

Subjects/Keywords: high level synthesis; faulty security; power efficiency; integer linear programing

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liu, Y. (2013). Power and Energy Efficient Error Detection Techniques. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/10015

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liu, Yu. “Power and Energy Efficient Error Detection Techniques.” 2013. Thesis, University of Illinois – Chicago. Accessed April 18, 2021. http://hdl.handle.net/10027/10015.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liu, Yu. “Power and Energy Efficient Error Detection Techniques.” 2013. Web. 18 Apr 2021.

Vancouver:

Liu Y. Power and Energy Efficient Error Detection Techniques. [Internet] [Thesis]. University of Illinois – Chicago; 2013. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10027/10015.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Power and Energy Efficient Error Detection Techniques. [Thesis]. University of Illinois – Chicago; 2013. Available from: http://hdl.handle.net/10027/10015

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Delft University of Technology

22. Ren, X. (author). RTL Implementation of an Optical Flow Algorithm (Lucas) Using the Catapult C High-Level Synthesis tool.

Degree: 2011, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:a5fd26f9-f5de-4d8c-9043-92a92f83dd6c

►

With the development of the technology, today's digital systems' growing design complexity has outpaced the traditional RTL design flow. The manual steps of micro-architecture definition,… (more)

Subjects/Keywords: optical flow algorithm; high-level synthesis; catapult C

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ren, X. (. (2011). RTL Implementation of an Optical Flow Algorithm (Lucas) Using the Catapult C High-Level Synthesis tool. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:a5fd26f9-f5de-4d8c-9043-92a92f83dd6c

Chicago Manual of Style (16^th Edition):

Ren, X (author). “RTL Implementation of an Optical Flow Algorithm (Lucas) Using the Catapult C High-Level Synthesis tool.” 2011. Masters Thesis, Delft University of Technology. Accessed April 18, 2021. http://resolver.tudelft.nl/uuid:a5fd26f9-f5de-4d8c-9043-92a92f83dd6c.

MLA Handbook (7^th Edition):

Ren, X (author). “RTL Implementation of an Optical Flow Algorithm (Lucas) Using the Catapult C High-Level Synthesis tool.” 2011. Web. 18 Apr 2021.

Vancouver:

Ren X(. RTL Implementation of an Optical Flow Algorithm (Lucas) Using the Catapult C High-Level Synthesis tool. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2021 Apr 18]. Available from: http://resolver.tudelft.nl/uuid:a5fd26f9-f5de-4d8c-9043-92a92f83dd6c.

Council of Science Editors:

Ren X(. RTL Implementation of an Optical Flow Algorithm (Lucas) Using the Catapult C High-Level Synthesis tool. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:a5fd26f9-f5de-4d8c-9043-92a92f83dd6c

University of Windsor

23. Janik, Ian Spencer. High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs.

Degree: MA, Electrical and Computer Engineering, 2015, University of Windsor

URL: https://scholar.uwindsor.ca/etd/5470

► Secure hash algorithms (SHAs) are important components of cryptographic applications. SHA performance on central processing units (CPUs) is slow, therefore, acceleration must be done… (more)

Subjects/Keywords: FPGAs; Hardware Acceleration; High Level Synthesis; SHA1; SHA2; SHA3

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Janik, I. S. (2015). High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5470

Chicago Manual of Style (16^th Edition):

Janik, Ian Spencer. “High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs.” 2015. Masters Thesis, University of Windsor. Accessed April 18, 2021. https://scholar.uwindsor.ca/etd/5470.

MLA Handbook (7^th Edition):

Janik, Ian Spencer. “High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs.” 2015. Web. 18 Apr 2021.

Vancouver:

Janik IS. High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs. [Internet] [Masters thesis]. University of Windsor; 2015. [cited 2021 Apr 18]. Available from: https://scholar.uwindsor.ca/etd/5470.

Council of Science Editors:

Janik IS. High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs. [Masters Thesis]. University of Windsor; 2015. Available from: https://scholar.uwindsor.ca/etd/5470

Georgia Tech

24. Kersey, Chad Daniel. A multi-paradigm C++-based hardware description language.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

URL: http://hdl.handle.net/1853/62342

► A generative hardware description library for C++, the CHDL Hardware Design Library or CHDL, along with a body of supporting libraries and a description of… (more)

Subjects/Keywords: Hardware description language; HDL; Domain-specific language; High-level synthesis

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kersey, C. D. (2019). A multi-paradigm C++-based hardware description language. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/62342

Chicago Manual of Style (16^th Edition):

Kersey, Chad Daniel. “A multi-paradigm C++-based hardware description language.” 2019. Doctoral Dissertation, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/62342.

MLA Handbook (7^th Edition):

Kersey, Chad Daniel. “A multi-paradigm C++-based hardware description language.” 2019. Web. 18 Apr 2021.

Vancouver:

Kersey CD. A multi-paradigm C++-based hardware description language. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/62342.

Council of Science Editors:

Kersey CD. A multi-paradigm C++-based hardware description language. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/62342

Virginia Tech

25. Shi, Zhun. Rapid Prototyping of an FPGA-Based Video Processing System.

Degree: MS, Computer Engineering, 2016, Virginia Tech

URL: http://hdl.handle.net/10919/71389

► Computer vision technology can be seen in a variety of applications ranging from mobile phones to autonomous vehicles. Many computer vision applications such as drones… (more)

▼ Computer vision technology can be seen in a variety of applications ranging from mobile phones to autonomous vehicles. Many computer vision applications such as drones and autonomous vehicles requires real-time processing capability in order to communicate with the control unit for sending commands in real time. Besides real-time processing capability, it is crucial to keep the power consumption low in order to extend the battery life of not only mobile devices, but also drones and autonomous vehicles. FPGAs are desired platforms that can provide high-performance and low-power solutions for real-time video processing. As hardware designs typically are more time consuming than equivalent software designs, this thesis proposes a rapid prototyping flow for FPGA-based video processing system design by taking advantage of the use of high performance AXI interface and a high level synthesis tool, Vivado HLS. Vivado HLS provides the convenience of automatically synthesizing a software implementation to hardware implementation. But the tool is far from being perfect, and users still need embedded hardware knowledge and experience in order to accomplish a successful design. In order to effectively create a stream type video processing system as well as to utilize the fastest memory on an FPGA, a sliding window memory architecture is proposed. This memory architecture can be applied to a series of video processing algorithms while the latency between an input pixel and an output pixel is minimized. By comparing my approach with other works, this optimized memory architecture proves to offer better performance and lower resource usage over what other works could offer. Its reconfigurability also provides better adaptability of other algorithms. In addition, this work includes performance and power analysis among an Intel CPU based design, an ARM based design, and an FPGA-based embedded design. Advisors/Committee Members: Athanas, Peter M. (committeechair), Zeng, Haibo (committee member), Martin, Thomas L. (committee member).

Subjects/Keywords: FPGA; Computer Vision; Video Processing; Rapid Prototyping; High-Level Synthesis

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Shi, Z. (2016). Rapid Prototyping of an FPGA-Based Video Processing System. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/71389

Chicago Manual of Style (16^th Edition):

Shi, Zhun. “Rapid Prototyping of an FPGA-Based Video Processing System.” 2016. Masters Thesis, Virginia Tech. Accessed April 18, 2021. http://hdl.handle.net/10919/71389.

MLA Handbook (7^th Edition):

Shi, Zhun. “Rapid Prototyping of an FPGA-Based Video Processing System.” 2016. Web. 18 Apr 2021.

Vancouver:

Shi Z. Rapid Prototyping of an FPGA-Based Video Processing System. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10919/71389.

Council of Science Editors:

Shi Z. Rapid Prototyping of an FPGA-Based Video Processing System. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/71389

University of Texas – Austin

26. Lavasani, Maysam. Generating irregular data-stream accelerators : methodology and applications.

Degree: PhD, Electrical and Computer Engineering, 2015, University of Texas – Austin

URL: http://hdl.handle.net/2152/31409

► This thesis presents Gorilla++, a language and a compiler for generating customized hardware accelerators that process input streams of data. Gorilla++ uses a hierarchical programming… (more)

Subjects/Keywords: Hardware accelerators; High-level synthesis; Auto-refinement; Big-data

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lavasani, M. (2015). Generating irregular data-stream accelerators : methodology and applications. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/31409

Chicago Manual of Style (16^th Edition):

Lavasani, Maysam. “Generating irregular data-stream accelerators : methodology and applications.” 2015. Doctoral Dissertation, University of Texas – Austin. Accessed April 18, 2021. http://hdl.handle.net/2152/31409.

MLA Handbook (7^th Edition):

Lavasani, Maysam. “Generating irregular data-stream accelerators : methodology and applications.” 2015. Web. 18 Apr 2021.

Vancouver:

Lavasani M. Generating irregular data-stream accelerators : methodology and applications. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2015. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2152/31409.

Council of Science Editors:

Lavasani M. Generating irregular data-stream accelerators : methodology and applications. [Doctoral Dissertation]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/31409

Rochester Institute of Technology

27. Morrison, Braeden. Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms.

Degree: MS, Computer Engineering, 2020, Rochester Institute of Technology

URL: https://scholarworks.rit.edu/theses/10617

► It is well-known that custom hardware accelerators implemented as application-specific integrated circuits (ASICs) or on field-programmable gate arrays (FPGAs) can solve many problems much… (more)

▼ It is well-known that custom hardware accelerators implemented as application-specific integrated circuits (ASICs) or on field-programmable gate arrays (FPGAs) can solve many problems much faster than software running on a central processing unit (CPU). This is because FPGAs and ASICs can have handcrafted data and control paths which exploit parallelism in ways that CPUs cannot. However, designing custom hardware is complicated and implementing algorithms in a way that takes advantage of the desired parallelism can be difficult. One class of algorithms that exemplifies this is divide-and-conquer algorithms. A divide-and-conquer algorithm is a type of recursive algorithm that solves a problem by repeatedly dividing it into smaller sub-problems. These algorithms have a lot of parallelism because they generate a large number of sub-problems that can be computed independently of each other. Unfortunately, traditional stack-based approaches to handling recursion in hardware make exploiting this parallelism difficult. This work proposes a new general-purpose approach to implementing recursive functions in hardware, which we call TreeRecur. TreeRecur uses trees to represent the branching recursive function calls of divide-and-conquer algorithms, which makes it possible to take advantage of their procedure-level parallelism. To allow for design flexibility, TreeRecur executes algorithms using a configurable number of independent function processors. These processors are generated using high-level synthesis, making it easy to implement a variety of different algorithms. Our solution was tested on three different algorithms and compared against software implementations of the same algorithms. Performance results were collected in terms of execution speed and energy consumption. TreeRecur was found to have execution speeds comparable to software when differences in clock speed were accounted for and was found to consume up to 11.2 times less energy. Advisors/Committee Members: Marcin Lukowiak.

Subjects/Keywords: Field-programmable gate array; High-level synthesis; Recursion

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Morrison, B. (2020). Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10617

Chicago Manual of Style (16^th Edition):

Morrison, Braeden. “Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms.” 2020. Masters Thesis, Rochester Institute of Technology. Accessed April 18, 2021. https://scholarworks.rit.edu/theses/10617.

MLA Handbook (7^th Edition):

Morrison, Braeden. “Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms.” 2020. Web. 18 Apr 2021.

Vancouver:

Morrison B. Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms. [Internet] [Masters thesis]. Rochester Institute of Technology; 2020. [cited 2021 Apr 18]. Available from: https://scholarworks.rit.edu/theses/10617.

Council of Science Editors:

Morrison B. Tree-Based Hardware Recursion for Divide-and-Conquer Algorithms. [Masters Thesis]. Rochester Institute of Technology; 2020. Available from: https://scholarworks.rit.edu/theses/10617

University of Illinois – Urbana-Champaign

28. Papakonstantinou, Alexandros. High-level automation of custom hardware design for high-performance computing.

Degree: PhD, 1200, 2013, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/42137

► This dissertation focuses on efficient generation of custom processors from high-level language descriptions. Our work exploits compiler-based optimizations and transformations in tandem with high-level synthesis… (more)

▼ This dissertation focuses on efficient generation of custom processors from high-level language descriptions. Our work exploits compiler-based optimizations and transformations in tandem with high-level synthesis (HLS) to build high-performance custom processors. The goal is to offer a common multiplatform high-abstraction programming interface for heterogeneous compute systems where the benefits of custom reconfigurable (or fixed) processors can be exploited by the application developers. The research presented in this dissertation supports the following thesis: In an increasingly heterogeneous compute environment it is important to leverage the compute capabilities of each heterogeneous processor efficiently. In the case of FPGA and ASIC accelerators this can be achieved through HLS-based flows that (i) extract parallelism at coarser than basic block granularities, (ii) leverage common high-level parallel programming languages, and (iii) employ high-level source-to-source transformations to generate high-throughput custom processors. First, we propose a novel HLS flow that extracts instruction level parallelism beyond the boundary of basic blocks from C code. Subsequently, we describe FCUDA, an HLS-based framework for mapping fine-grained and coarse-grained parallelism from parallel CUDA kernels onto spatial parallelism. FCUDA provides a common programming model for acceleration on heterogeneous devices (i.e. GPUs and FPGAs). Moreover, the FCUDA framework balances multilevel granularity parallelism synthesis using efficient techniques that leverage fast and accurate estimation models (i.e. do not rely on lengthy physical implementation tools). Finally, we describe an advanced source-to-source transformation framework for throughput-driven parallelism synthesis (TDPS), which appropriately restructures CUDA kernel code to maximize throughput on FPGA devices. We have integrated the TDPS framework into the FCUDA flow to enable automatic performance porting of CUDA kernels designed for the GPU architecture onto the FPGA architecture. Advisors/Committee Members: Chen, Deming (advisor), Chen, Deming (Committee Chair), Cong, Jason (committee member), Hwu, Wen-Mei W. (committee member), Wong, Martin D.F. (committee member).

Subjects/Keywords: High-level synthesis; Field-Programmable Gate Array (FPGA); CUDA; parallel programming; High Performance Computing (HPC)

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Papakonstantinou, A. (2013). High-level automation of custom hardware design for high-performance computing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/42137

Chicago Manual of Style (16^th Edition):

Papakonstantinou, Alexandros. “High-level automation of custom hardware design for high-performance computing.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 18, 2021. http://hdl.handle.net/2142/42137.

MLA Handbook (7^th Edition):

Papakonstantinou, Alexandros. “High-level automation of custom hardware design for high-performance computing.” 2013. Web. 18 Apr 2021.

Vancouver:

Papakonstantinou A. High-level automation of custom hardware design for high-performance computing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2142/42137.

Council of Science Editors:

Papakonstantinou A. High-level automation of custom hardware design for high-performance computing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/42137

Brno University of Technology

29. Nosko, Svetozár. Akcelerace HDR tone-mappingu na platformě Xilinx Zynq: HDR Tone-Mapping Acceleration on Xilinx Zynq Platform.

Degree: 2018, Brno University of Technology

URL: http://hdl.handle.net/11012/61821

► This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This… (more)

Subjects/Keywords: Xilinx Zynq; SoC; HLS; High Level Synthesis; Vivado; Vivado HLS; HDR; mapovanie tónov; Xilinx Zynq; SoC; HLS; High Level Synthesis; Vivado; Vivado HLS; HDR; tone mapping

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Nosko, S. (2018). Akcelerace HDR tone-mappingu na platformě Xilinx Zynq: HDR Tone-Mapping Acceleration on Xilinx Zynq Platform. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/61821

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Nosko, Svetozár. “Akcelerace HDR tone-mappingu na platformě Xilinx Zynq: HDR Tone-Mapping Acceleration on Xilinx Zynq Platform.” 2018. Thesis, Brno University of Technology. Accessed April 18, 2021. http://hdl.handle.net/11012/61821.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Nosko, Svetozár. “Akcelerace HDR tone-mappingu na platformě Xilinx Zynq: HDR Tone-Mapping Acceleration on Xilinx Zynq Platform.” 2018. Web. 18 Apr 2021.

Vancouver:

Nosko S. Akcelerace HDR tone-mappingu na platformě Xilinx Zynq: HDR Tone-Mapping Acceleration on Xilinx Zynq Platform. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/11012/61821.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nosko S. Akcelerace HDR tone-mappingu na platformě Xilinx Zynq: HDR Tone-Mapping Acceleration on Xilinx Zynq Platform. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/61821

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Toronto

30. Choi, Jongsok. From Software Threads to Parallel Hardware with LegUp High-level Synthesis.

Degree: PhD, 2016, University of Toronto

URL: http://hdl.handle.net/1807/76380

► High-level synthesis (HLS) can automatically synthesize software to hardware. With the design specification in software, HLS can reduce the lengthy design cycles of hardware, and… (more)

▼ High-level synthesis (HLS) can automatically synthesize software to hardware. With the design specification in software, HLS can reduce the lengthy design cycles of hardware, and make the performance and energy-efficiency benefits of hardware accessible to those without hardware skills. Since the introduction of the first C-based HLS tools more than a decade ago, however, the adaption of the technology has been slow by both software and hardware engineers. We attribute this to two key factors: 1) For hardware engineers, there is still a gap between HLS-generated hardware and human-designed hardware, partly due to the inability of HLS tools to fully exploit hardware parallelism, and 2) for software engineers, HLS remains to be a difficult endeavour, as many parts of the design, such as system integration, largely remain a manual process. This dissertation provides an HLS framework, LegUp, which seeks to address both issues. LegUp can compile an entire software program to hardware to produce a hardware-only system, or it can also automatically partition the program to generate a processor-accelerator hybrid system, wherein the compute-intensive program segments are accelerated by hardware, with the remaining segments executed in software on a processor. In both cases, a complete system is generated, including necessary memories and interconnect. To allow one to easily exploit hardware parallelism, we provide HLS support for synthesizing parallel software to parallel hardware. In particular, we support automatically compiling a multi-threaded program with Pthreads and OpenMP to parallel hardware accelerators that operate concurrently within a hardware-only or a processor-accelerator hybrid system. In the context of parallel hardware, we investigate architectural and memory optimizations that help to improve circuit performance and area, and discuss a method of using the producer-consumer pattern in software to infer a streaming circuit in hardware. With these techniques, we show that LegUp can produce high-performance hardware that can be competitive to circuits that are generated by commercial HLS tools, and demonstrate that LegUp-generated circuits can also outperform software executing on x86 processors. Advisors/Committee Members: Anderson, Jason H, Brown, Stephen D, Electrical and Computer Engineering.

Subjects/Keywords: Field-programmable gate array; Hardware/Software co-design; High-level synthesis; LegUp High-Level Synthesis Framework; Parallel hardware; System-on-Chip; 0464

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Choi, J. (2016). From Software Threads to Parallel Hardware with LegUp High-level Synthesis. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/76380

Chicago Manual of Style (16^th Edition):

Choi, Jongsok. “From Software Threads to Parallel Hardware with LegUp High-level Synthesis.” 2016. Doctoral Dissertation, University of Toronto. Accessed April 18, 2021. http://hdl.handle.net/1807/76380.

MLA Handbook (7^th Edition):

Choi, Jongsok. “From Software Threads to Parallel Hardware with LegUp High-level Synthesis.” 2016. Web. 18 Apr 2021.

Vancouver:

Choi J. From Software Threads to Parallel Hardware with LegUp High-level Synthesis. [Internet] [Doctoral dissertation]. University of Toronto; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1807/76380.

Council of Science Editors:

Choi J. From Software Threads to Parallel Hardware with LegUp High-level Synthesis. [Doctoral Dissertation]. University of Toronto; 2016. Available from: http://hdl.handle.net/1807/76380

		in
And / Or
		in
And / Or
		in
And / Or
		in

Open Access Theses and Dissertations