Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(High Level Synthesis HLS ). Showing records 1 – 30 of 46326 total matches.

[1] [2] [3] [4] [5] … [1545]

Search Limiters

Last 2 Years | English Only

Degrees

Languages

Country

▼ Search Limiters


Brno University of Technology

1. Nosko, Svetozár. Akcelerace HDR tone-mappingu na platformě Xilinx Zynq .

Degree: 2016, Brno University of Technology

 Tato diplomová práca je zameraná predovšetkým na syntézu na systémovej úrovni (HLS). Prvá časť obsahuje teoretické detaily a postupy, ktoré sa využívajú v HLS nástrojoch.… (more)

Subjects/Keywords: Xilinx Zynq; SoC; HLS; High Level Synthesis; Vivado; Vivado HLS; HDR; mapovanie tónov; Xilinx Zynq; SoC; HLS; High Level Synthesis; Vivado; Vivado HLS; HDR; tone mapping

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nosko, S. (2016). Akcelerace HDR tone-mappingu na platformě Xilinx Zynq . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/61821

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nosko, Svetozár. “Akcelerace HDR tone-mappingu na platformě Xilinx Zynq .” 2016. Thesis, Brno University of Technology. Accessed December 15, 2019. http://hdl.handle.net/11012/61821.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nosko, Svetozár. “Akcelerace HDR tone-mappingu na platformě Xilinx Zynq .” 2016. Web. 15 Dec 2019.

Vancouver:

Nosko S. Akcelerace HDR tone-mappingu na platformě Xilinx Zynq . [Internet] [Thesis]. Brno University of Technology; 2016. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/11012/61821.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nosko S. Akcelerace HDR tone-mappingu na platformě Xilinx Zynq . [Thesis]. Brno University of Technology; 2016. Available from: http://hdl.handle.net/11012/61821

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

2. Sikora, Martin. Vliv jazyků vysoké úrovně na výsledný fyzický návrh číslicových obvodů do FPGA .

Degree: 2018, Brno University of Technology

 Popularita vysokoúrovňové syntézy (HLS) se postupně zvyšuje a nástrojů pro ni stále přibývá. Otázkou je, jaký dopad mají tyto nástroje na konečný návrh číslicového obvodu… (more)

Subjects/Keywords: HLS; RTL; FPGA; VHDL; vysokoúrovňová syntéza; MachSuite; HLS; RTL; FPGA; VHDL; High-level synthesis; MachSuite

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sikora, M. (2018). Vliv jazyků vysoké úrovně na výsledný fyzický návrh číslicových obvodů do FPGA . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/82010

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sikora, Martin. “Vliv jazyků vysoké úrovně na výsledný fyzický návrh číslicových obvodů do FPGA .” 2018. Thesis, Brno University of Technology. Accessed December 15, 2019. http://hdl.handle.net/11012/82010.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sikora, Martin. “Vliv jazyků vysoké úrovně na výsledný fyzický návrh číslicových obvodů do FPGA .” 2018. Web. 15 Dec 2019.

Vancouver:

Sikora M. Vliv jazyků vysoké úrovně na výsledný fyzický návrh číslicových obvodů do FPGA . [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/11012/82010.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sikora M. Vliv jazyků vysoké úrovně na výsledný fyzický návrh číslicových obvodů do FPGA . [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/82010

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Windsor

3. Luthra, Siddhant. High Level Synthesis and Evaluation of an Automotive RADAR Signal Processing algorithm for FPGAs.

Degree: MA, Electrical and Computer Engineering, 2017, University of Windsor

High Level Synthesis (HLS) is a technology used to design and develop hardware (HW) using high-level languages such as C/C++. An HLS model of an… (more)

Subjects/Keywords: automotive; FPGA; High Level Synthesis; RADAR; Vivado HLS; Xilinx

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Luthra, S. (2017). High Level Synthesis and Evaluation of an Automotive RADAR Signal Processing algorithm for FPGAs. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/7274

Chicago Manual of Style (16th Edition):

Luthra, Siddhant. “High Level Synthesis and Evaluation of an Automotive RADAR Signal Processing algorithm for FPGAs.” 2017. Masters Thesis, University of Windsor. Accessed December 15, 2019. https://scholar.uwindsor.ca/etd/7274.

MLA Handbook (7th Edition):

Luthra, Siddhant. “High Level Synthesis and Evaluation of an Automotive RADAR Signal Processing algorithm for FPGAs.” 2017. Web. 15 Dec 2019.

Vancouver:

Luthra S. High Level Synthesis and Evaluation of an Automotive RADAR Signal Processing algorithm for FPGAs. [Internet] [Masters thesis]. University of Windsor; 2017. [cited 2019 Dec 15]. Available from: https://scholar.uwindsor.ca/etd/7274.

Council of Science Editors:

Luthra S. High Level Synthesis and Evaluation of an Automotive RADAR Signal Processing algorithm for FPGAs. [Masters Thesis]. University of Windsor; 2017. Available from: https://scholar.uwindsor.ca/etd/7274


University of Oulu

4. Hänninen, T. (Tuomo). Detection algorithms and FPGA implementations for SC-FDMA uplink receivers.

Degree: 2018, University of Oulu

Abstract The demand in mobile broadband communications is increasing dramatically. It is expected that 1000 times more mobile-network capacity will be needed within 10 years.… (more)

Subjects/Keywords: detection; high-level synthesis; receiver; uplink; HLS; ilmaisin; vastaanotin; FPGA; LTE; MIMO; SC-FDMA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hänninen, T. (. (2018). Detection algorithms and FPGA implementations for SC-FDMA uplink receivers. (Doctoral Dissertation). University of Oulu. Retrieved from http://urn.fi/urn:isbn:9789526219691

Chicago Manual of Style (16th Edition):

Hänninen, T (Tuomo). “Detection algorithms and FPGA implementations for SC-FDMA uplink receivers.” 2018. Doctoral Dissertation, University of Oulu. Accessed December 15, 2019. http://urn.fi/urn:isbn:9789526219691.

MLA Handbook (7th Edition):

Hänninen, T (Tuomo). “Detection algorithms and FPGA implementations for SC-FDMA uplink receivers.” 2018. Web. 15 Dec 2019.

Vancouver:

Hänninen T(. Detection algorithms and FPGA implementations for SC-FDMA uplink receivers. [Internet] [Doctoral dissertation]. University of Oulu; 2018. [cited 2019 Dec 15]. Available from: http://urn.fi/urn:isbn:9789526219691.

Council of Science Editors:

Hänninen T(. Detection algorithms and FPGA implementations for SC-FDMA uplink receivers. [Doctoral Dissertation]. University of Oulu; 2018. Available from: http://urn.fi/urn:isbn:9789526219691


Brno University of Technology

5. Jendrušák, Ján. Behaviorální syntéza digitálních obvodů .

Degree: 2017, Brno University of Technology

 Táto práca sa zaoberá praktickým otestovaním behaviorálnej syntézy ako spôsobu návrhu digitálnych obvodov a jej momentálnym progresom pri tvorbe RTL popisov. V úvode práce sú… (more)

Subjects/Keywords: ASIC; behaviorálna syntéza; diskrétna Fourierova transformácia; FPGA; HLS; RTL; rýchla Fourierova transformácia; Stratus High-Level Synthesis; SystemC; ASIC; discrete Fourier transform; fast Fourier transform; FPGA; high-level synthesis; HLS; RTL; Stratus High-Level Synthesis; SystemC

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jendrušák, J. (2017). Behaviorální syntéza digitálních obvodů . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/68202

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jendrušák, Ján. “Behaviorální syntéza digitálních obvodů .” 2017. Thesis, Brno University of Technology. Accessed December 15, 2019. http://hdl.handle.net/11012/68202.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jendrušák, Ján. “Behaviorální syntéza digitálních obvodů .” 2017. Web. 15 Dec 2019.

Vancouver:

Jendrušák J. Behaviorální syntéza digitálních obvodů . [Internet] [Thesis]. Brno University of Technology; 2017. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/11012/68202.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jendrušák J. Behaviorální syntéza digitálních obvodů . [Thesis]. Brno University of Technology; 2017. Available from: http://hdl.handle.net/11012/68202

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

6. Nilsson, Petter. Built-in self-test of analog-to-digital converters in FPGAs.

Degree: Electronics System, 2014, Linköping University

  When designing an ADC it is desirable to test its performance at two different points in the development process. The first is characterization and… (more)

Subjects/Keywords: FPGA; BIST; ADC; dynamic test; static test; linearity; DNL; INL; offset; gain error; FFT; SNR; THD; delta-sigma; sigma-delta; DAC; high-level synthesis; HLS; IEEE Standard 1241

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nilsson, P. (2014). Built-in self-test of analog-to-digital converters in FPGAs. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106602

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nilsson, Petter. “Built-in self-test of analog-to-digital converters in FPGAs.” 2014. Thesis, Linköping University. Accessed December 15, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106602.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nilsson, Petter. “Built-in self-test of analog-to-digital converters in FPGAs.” 2014. Web. 15 Dec 2019.

Vancouver:

Nilsson P. Built-in self-test of analog-to-digital converters in FPGAs. [Internet] [Thesis]. Linköping University; 2014. [cited 2019 Dec 15]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106602.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nilsson P. Built-in self-test of analog-to-digital converters in FPGAs. [Thesis]. Linköping University; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106602

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Nane, R. Automatic Hardware Generation for Reconfigurable Architectures.

Degree: 2014, CPI Koninklijke Wohrmann

 Reconfigurable Architectures (RA) have been gaining popularity rapidly in the last decade for two reasons. First, processor clock frequencies reached threshold values past which power… (more)

Subjects/Keywords: high-level synthesis; hardware; reconfigurable; architecture; compiler; survey; dwarv; HLS; optimization

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nane, R. (2014). Automatic Hardware Generation for Reconfigurable Architectures. (Doctoral Dissertation). CPI Koninklijke Wohrmann. Retrieved from http://resolver.tudelft.nl/uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60 ; urn:NBN:nl:ui:24-uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60 ; urn:NBN:nl:ui:24-uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60 ; http://resolver.tudelft.nl/uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60

Chicago Manual of Style (16th Edition):

Nane, R. “Automatic Hardware Generation for Reconfigurable Architectures.” 2014. Doctoral Dissertation, CPI Koninklijke Wohrmann. Accessed December 15, 2019. http://resolver.tudelft.nl/uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60 ; urn:NBN:nl:ui:24-uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60 ; urn:NBN:nl:ui:24-uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60 ; http://resolver.tudelft.nl/uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60.

MLA Handbook (7th Edition):

Nane, R. “Automatic Hardware Generation for Reconfigurable Architectures.” 2014. Web. 15 Dec 2019.

Vancouver:

Nane R. Automatic Hardware Generation for Reconfigurable Architectures. [Internet] [Doctoral dissertation]. CPI Koninklijke Wohrmann; 2014. [cited 2019 Dec 15]. Available from: http://resolver.tudelft.nl/uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60 ; urn:NBN:nl:ui:24-uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60 ; urn:NBN:nl:ui:24-uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60 ; http://resolver.tudelft.nl/uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60.

Council of Science Editors:

Nane R. Automatic Hardware Generation for Reconfigurable Architectures. [Doctoral Dissertation]. CPI Koninklijke Wohrmann; 2014. Available from: http://resolver.tudelft.nl/uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60 ; urn:NBN:nl:ui:24-uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60 ; urn:NBN:nl:ui:24-uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60 ; http://resolver.tudelft.nl/uuid:650ec0d0-4613-4dae-96b1-1f685dff0e60

8. Ben Hammouda, Mohamed. A design flow to automatically Generate on chip monitors during high-level synthesis of Hardware accelarators : Un flot de conception pour générer automatiquement des moniteurs sur puce pendant la synthèse de haut niveau d'accélérateurs matériels.

Degree: Docteur es, Stic, 2014, Brest

 Les systèmes embarqués sont de plus en plus utilisés dans des domaines divers tels que le transport, l’automatisation industrielle, les télécommunications ou la santé pour… (more)

Subjects/Keywords: Synthèse de haut niveau (HLS); Accélérateur matériel (HWAcc); Moniteur sur puce (OCM); Propriétés; Flot de contrôle; Erreurs; High-Level Synthesis (HLS); Hardware Accelerator (HWacc); On-Chip Monitor (OCM); Assertions; Control Flow; Errors

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ben Hammouda, M. (2014). A design flow to automatically Generate on chip monitors during high-level synthesis of Hardware accelarators : Un flot de conception pour générer automatiquement des moniteurs sur puce pendant la synthèse de haut niveau d'accélérateurs matériels. (Doctoral Dissertation). Brest. Retrieved from http://www.theses.fr/2014BRES0115

Chicago Manual of Style (16th Edition):

Ben Hammouda, Mohamed. “A design flow to automatically Generate on chip monitors during high-level synthesis of Hardware accelarators : Un flot de conception pour générer automatiquement des moniteurs sur puce pendant la synthèse de haut niveau d'accélérateurs matériels.” 2014. Doctoral Dissertation, Brest. Accessed December 15, 2019. http://www.theses.fr/2014BRES0115.

MLA Handbook (7th Edition):

Ben Hammouda, Mohamed. “A design flow to automatically Generate on chip monitors during high-level synthesis of Hardware accelarators : Un flot de conception pour générer automatiquement des moniteurs sur puce pendant la synthèse de haut niveau d'accélérateurs matériels.” 2014. Web. 15 Dec 2019.

Vancouver:

Ben Hammouda M. A design flow to automatically Generate on chip monitors during high-level synthesis of Hardware accelarators : Un flot de conception pour générer automatiquement des moniteurs sur puce pendant la synthèse de haut niveau d'accélérateurs matériels. [Internet] [Doctoral dissertation]. Brest; 2014. [cited 2019 Dec 15]. Available from: http://www.theses.fr/2014BRES0115.

Council of Science Editors:

Ben Hammouda M. A design flow to automatically Generate on chip monitors during high-level synthesis of Hardware accelarators : Un flot de conception pour générer automatiquement des moniteurs sur puce pendant la synthèse de haut niveau d'accélérateurs matériels. [Doctoral Dissertation]. Brest; 2014. Available from: http://www.theses.fr/2014BRES0115


University of Illinois – Urbana-Champaign

9. Sun, Zelei. VAST-LP: clock gating in high-level synthesis.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

High-level synthesis (HLS) promises high-quality hardware with minimal develop- ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST and propose… (more)

Subjects/Keywords: low power; high level synthesis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sun, Z. (2016). VAST-LP: clock gating in high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sun, Zelei. “VAST-LP: clock gating in high-level synthesis.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed December 15, 2019. http://hdl.handle.net/2142/90970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sun, Zelei. “VAST-LP: clock gating in high-level synthesis.” 2016. Web. 15 Dec 2019.

Vancouver:

Sun Z. VAST-LP: clock gating in high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/2142/90970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sun Z. VAST-LP: clock gating in high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

10. Lee, Dongwook. Learning-based system-level power modeling of hardware IPs.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin

 Accurate power models for hardware components at high levels of abstraction are a critical component to enable system-level power analysis and optimization. Virtual platform prototypes… (more)

Subjects/Keywords: Power estimation; High-level synthesis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, D. (2017). Learning-based system-level power modeling of hardware IPs. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63013

Chicago Manual of Style (16th Edition):

Lee, Dongwook. “Learning-based system-level power modeling of hardware IPs.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed December 15, 2019. http://hdl.handle.net/2152/63013.

MLA Handbook (7th Edition):

Lee, Dongwook. “Learning-based system-level power modeling of hardware IPs.” 2017. Web. 15 Dec 2019.

Vancouver:

Lee D. Learning-based system-level power modeling of hardware IPs. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/2152/63013.

Council of Science Editors:

Lee D. Learning-based system-level power modeling of hardware IPs. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/63013

11. -7307-3794. Approximate high-level synthesis of quality and energy optimized hardware processors.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 Approximate computing is a technique that exploits trade-offs between energy/performance and quality of computed results. Such techniques have been explored at various design levels for… (more)

Subjects/Keywords: Approximate computing; High-level synthesis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

-7307-3794. (2018). Approximate high-level synthesis of quality and energy optimized hardware processors. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63811

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-7307-3794. “Approximate high-level synthesis of quality and energy optimized hardware processors.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed December 15, 2019. http://hdl.handle.net/2152/63811.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-7307-3794. “Approximate high-level synthesis of quality and energy optimized hardware processors.” 2018. Web. 15 Dec 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-7307-3794. Approximate high-level synthesis of quality and energy optimized hardware processors. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/2152/63811.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-7307-3794. Approximate high-level synthesis of quality and energy optimized hardware processors. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/63811

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Penn State University

12. Chen, Yibo. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS.

Degree: PhD, Computer Science and Engineering, 2011, Penn State University

 Variability in circuit delay and power dissipation is one of the most critical challenges in nanometer VLSI era. Traditionally, performance/power variations are handled by a… (more)

Subjects/Keywords: High-Level Synthesis; Behavioral Synthesis; ESL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2011). VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/12416

Chicago Manual of Style (16th Edition):

Chen, Yibo. “VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS.” 2011. Doctoral Dissertation, Penn State University. Accessed December 15, 2019. https://etda.libraries.psu.edu/catalog/12416.

MLA Handbook (7th Edition):

Chen, Yibo. “VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS.” 2011. Web. 15 Dec 2019.

Vancouver:

Chen Y. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS. [Internet] [Doctoral dissertation]. Penn State University; 2011. [cited 2019 Dec 15]. Available from: https://etda.libraries.psu.edu/catalog/12416.

Council of Science Editors:

Chen Y. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS. [Doctoral Dissertation]. Penn State University; 2011. Available from: https://etda.libraries.psu.edu/catalog/12416

13. Feenstra, C. A Memory Access and Operator Usage Profiler Framework for HLS Optimization: Using the Lucas Optical Flow Algorithm as Case Study:.

Degree: 2011, Delft University of Technology

 As reconfigurable hardware such as FPGA’s become bigger and bigger, large and complex systems can be implemented in such devices. It becomes a challenge for… (more)

Subjects/Keywords: framework; gcc; plugin; parser; analyze; high level synthesis; HLS; memory access; operator usage

…experiments with High Level Synthesis (HLS) are published. The main goal is to be able to… …Contents Abstract v Acknowledgments vii 1 Introduction 1 1.1 High Level Synthesis… …to be implemented in hardware using High Level Synthesis. In the first part of this chapter… …a short introduction to High Level Synthesis as well as the common challenges a designer… …faces when implementing an algorithm with High Level Synthesis are given. The need for… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Feenstra, C. (2011). A Memory Access and Operator Usage Profiler Framework for HLS Optimization: Using the Lucas Optical Flow Algorithm as Case Study:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:b4aef4d6-61b1-4dda-9fb3-638e2ec10eb0

Chicago Manual of Style (16th Edition):

Feenstra, C. “A Memory Access and Operator Usage Profiler Framework for HLS Optimization: Using the Lucas Optical Flow Algorithm as Case Study:.” 2011. Masters Thesis, Delft University of Technology. Accessed December 15, 2019. http://resolver.tudelft.nl/uuid:b4aef4d6-61b1-4dda-9fb3-638e2ec10eb0.

MLA Handbook (7th Edition):

Feenstra, C. “A Memory Access and Operator Usage Profiler Framework for HLS Optimization: Using the Lucas Optical Flow Algorithm as Case Study:.” 2011. Web. 15 Dec 2019.

Vancouver:

Feenstra C. A Memory Access and Operator Usage Profiler Framework for HLS Optimization: Using the Lucas Optical Flow Algorithm as Case Study:. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2019 Dec 15]. Available from: http://resolver.tudelft.nl/uuid:b4aef4d6-61b1-4dda-9fb3-638e2ec10eb0.

Council of Science Editors:

Feenstra C. A Memory Access and Operator Usage Profiler Framework for HLS Optimization: Using the Lucas Optical Flow Algorithm as Case Study:. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:b4aef4d6-61b1-4dda-9fb3-638e2ec10eb0


Virginia Tech

14. Stamenkovich, Joseph Allan. Enhancing Trust in Autonomous Systems without Verifying Software.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 Autonomous systems are surprisingly vulnerable, not just from malicious hackers, but from design errors and oversights. The lines of code required can quickly climb into… (more)

Subjects/Keywords: Autonomy; Runtime Verification; FPGA; Field Programmable Gate Array; Monitor; Formal Methods; UAS; UAV; Security; Linear Temporal Logic; LTL; High-Level Synthesis; HLS; monitor; model; checking; drone; malware; assurance; robotics; firmware; hardware

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Stamenkovich, J. A. (2019). Enhancing Trust in Autonomous Systems without Verifying Software. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/89950

Chicago Manual of Style (16th Edition):

Stamenkovich, Joseph Allan. “Enhancing Trust in Autonomous Systems without Verifying Software.” 2019. Masters Thesis, Virginia Tech. Accessed December 15, 2019. http://hdl.handle.net/10919/89950.

MLA Handbook (7th Edition):

Stamenkovich, Joseph Allan. “Enhancing Trust in Autonomous Systems without Verifying Software.” 2019. Web. 15 Dec 2019.

Vancouver:

Stamenkovich JA. Enhancing Trust in Autonomous Systems without Verifying Software. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/10919/89950.

Council of Science Editors:

Stamenkovich JA. Enhancing Trust in Autonomous Systems without Verifying Software. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/89950


Université Paris-Sud – Paris XI

15. Ye, Haixiong. Impact des transformations algorithmiques sur la synthèse de haut niveau : application au traitement du signal et des images : Impact of algorithmic transforms for High Level Synthesis (HLS) : application to signal and image processing.

Degree: Docteur es, Physique, 2014, Université Paris-Sud – Paris XI

La thèse porte sur l'impact d'optimisations algorithmiques pour la synthèse automatique HLS pour ASIC. Ces optimisations algorithmiques sont des transformations de haut niveau, qui de… (more)

Subjects/Keywords: Synthèse de haut niveau; Transformation de haut niveau; Filtre FIR; Filtre IIR; Sigma Delta; Filtre morphologique; Catapult-C; Métaprogrammation; Traitement du signal; Traitement des images; High Level Synthesis (HLS); High Level Transform (HLT); FIR filter; IIR filter; Sigma Delta; Morphological filter; Catapult-C; Metaprogrammation; Signal processing; Image processing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ye, H. (2014). Impact des transformations algorithmiques sur la synthèse de haut niveau : application au traitement du signal et des images : Impact of algorithmic transforms for High Level Synthesis (HLS) : application to signal and image processing. (Doctoral Dissertation). Université Paris-Sud – Paris XI. Retrieved from http://www.theses.fr/2014PA112092

Chicago Manual of Style (16th Edition):

Ye, Haixiong. “Impact des transformations algorithmiques sur la synthèse de haut niveau : application au traitement du signal et des images : Impact of algorithmic transforms for High Level Synthesis (HLS) : application to signal and image processing.” 2014. Doctoral Dissertation, Université Paris-Sud – Paris XI. Accessed December 15, 2019. http://www.theses.fr/2014PA112092.

MLA Handbook (7th Edition):

Ye, Haixiong. “Impact des transformations algorithmiques sur la synthèse de haut niveau : application au traitement du signal et des images : Impact of algorithmic transforms for High Level Synthesis (HLS) : application to signal and image processing.” 2014. Web. 15 Dec 2019.

Vancouver:

Ye H. Impact des transformations algorithmiques sur la synthèse de haut niveau : application au traitement du signal et des images : Impact of algorithmic transforms for High Level Synthesis (HLS) : application to signal and image processing. [Internet] [Doctoral dissertation]. Université Paris-Sud – Paris XI; 2014. [cited 2019 Dec 15]. Available from: http://www.theses.fr/2014PA112092.

Council of Science Editors:

Ye H. Impact des transformations algorithmiques sur la synthèse de haut niveau : application au traitement du signal et des images : Impact of algorithmic transforms for High Level Synthesis (HLS) : application to signal and image processing. [Doctoral Dissertation]. Université Paris-Sud – Paris XI; 2014. Available from: http://www.theses.fr/2014PA112092

16. Abid, Mariem. System-Level Hardwa Synthesis of Dataflow Programs with HEVC as Study Use Case : Synthèse matérielle au niveau système des programmes flots-de-données : étude de cas du décodeur HEVC.

Degree: Docteur es, Traitement du Signal et de l'Image, 2016, Rennes, INSA; École nationale d'Ingénieurs de Sfax (Tunisie)

Les applications de traitement d'image et vidéo sont caractérisées par le traitement d'une grande quantité de données. La conception de ces applications complexes avec des… (more)

Subjects/Keywords: Traitement d'image; Traitement de vidéo; Modélisation; HEVC; FPGA; System-level; Hardware-Synthesis; Video decoder; HLS; SoC; ESL; 621.382

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Abid, M. (2016). System-Level Hardwa Synthesis of Dataflow Programs with HEVC as Study Use Case : Synthèse matérielle au niveau système des programmes flots-de-données : étude de cas du décodeur HEVC. (Doctoral Dissertation). Rennes, INSA; École nationale d'Ingénieurs de Sfax (Tunisie). Retrieved from http://www.theses.fr/2016ISAR0002

Chicago Manual of Style (16th Edition):

Abid, Mariem. “System-Level Hardwa Synthesis of Dataflow Programs with HEVC as Study Use Case : Synthèse matérielle au niveau système des programmes flots-de-données : étude de cas du décodeur HEVC.” 2016. Doctoral Dissertation, Rennes, INSA; École nationale d'Ingénieurs de Sfax (Tunisie). Accessed December 15, 2019. http://www.theses.fr/2016ISAR0002.

MLA Handbook (7th Edition):

Abid, Mariem. “System-Level Hardwa Synthesis of Dataflow Programs with HEVC as Study Use Case : Synthèse matérielle au niveau système des programmes flots-de-données : étude de cas du décodeur HEVC.” 2016. Web. 15 Dec 2019.

Vancouver:

Abid M. System-Level Hardwa Synthesis of Dataflow Programs with HEVC as Study Use Case : Synthèse matérielle au niveau système des programmes flots-de-données : étude de cas du décodeur HEVC. [Internet] [Doctoral dissertation]. Rennes, INSA; École nationale d'Ingénieurs de Sfax (Tunisie); 2016. [cited 2019 Dec 15]. Available from: http://www.theses.fr/2016ISAR0002.

Council of Science Editors:

Abid M. System-Level Hardwa Synthesis of Dataflow Programs with HEVC as Study Use Case : Synthèse matérielle au niveau système des programmes flots-de-données : étude de cas du décodeur HEVC. [Doctoral Dissertation]. Rennes, INSA; École nationale d'Ingénieurs de Sfax (Tunisie); 2016. Available from: http://www.theses.fr/2016ISAR0002

17. Mena morales, Valentin. Approche de conception haut-niveau pour l'accélération matérielle de calcul haute performance en finance : High-level approach for hardware acceleration of high-performance computing in finance.

Degree: Docteur es, Sciences et Technologies de l'Information et de la Communication, 2017, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire

Les applications de calcul haute-performance (HPC) nécessitent des capacités de calcul conséquentes, qui sont généralement atteintes à l'aide de fermes de serveurs au détriment de… (more)

Subjects/Keywords: Conception haut-Niveau; OpenCL; Fpga; Gpu; Finance; Accélération matérielle; Hpc; Hls; Prototypage; High-Level design; OpenCL; Fpga; Gpu; Quantitative finance; Hardware acceleration; Hpc; Hls; Prototyping; 004

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mena morales, V. (2017). Approche de conception haut-niveau pour l'accélération matérielle de calcul haute performance en finance : High-level approach for hardware acceleration of high-performance computing in finance. (Doctoral Dissertation). Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire. Retrieved from http://www.theses.fr/2017IMTA0018

Chicago Manual of Style (16th Edition):

Mena morales, Valentin. “Approche de conception haut-niveau pour l'accélération matérielle de calcul haute performance en finance : High-level approach for hardware acceleration of high-performance computing in finance.” 2017. Doctoral Dissertation, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire. Accessed December 15, 2019. http://www.theses.fr/2017IMTA0018.

MLA Handbook (7th Edition):

Mena morales, Valentin. “Approche de conception haut-niveau pour l'accélération matérielle de calcul haute performance en finance : High-level approach for hardware acceleration of high-performance computing in finance.” 2017. Web. 15 Dec 2019.

Vancouver:

Mena morales V. Approche de conception haut-niveau pour l'accélération matérielle de calcul haute performance en finance : High-level approach for hardware acceleration of high-performance computing in finance. [Internet] [Doctoral dissertation]. Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire; 2017. [cited 2019 Dec 15]. Available from: http://www.theses.fr/2017IMTA0018.

Council of Science Editors:

Mena morales V. Approche de conception haut-niveau pour l'accélération matérielle de calcul haute performance en finance : High-level approach for hardware acceleration of high-performance computing in finance. [Doctoral Dissertation]. Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire; 2017. Available from: http://www.theses.fr/2017IMTA0018


Penn State University

18. Wang, Feng. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS.

Degree: PhD, Computer Science and Engineering, 2008, Penn State University

 Technology scaling provides an integration capacity of billions of transistors and continuously enhances system performance. However, fabricating transistors at feature sizes in the deep sub-micron… (more)

Subjects/Keywords: high level synthesis; design automation; process variations

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, F. (2008). DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/8173

Chicago Manual of Style (16th Edition):

Wang, Feng. “DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS.” 2008. Doctoral Dissertation, Penn State University. Accessed December 15, 2019. https://etda.libraries.psu.edu/catalog/8173.

MLA Handbook (7th Edition):

Wang, Feng. “DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS.” 2008. Web. 15 Dec 2019.

Vancouver:

Wang F. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS. [Internet] [Doctoral dissertation]. Penn State University; 2008. [cited 2019 Dec 15]. Available from: https://etda.libraries.psu.edu/catalog/8173.

Council of Science Editors:

Wang F. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS. [Doctoral Dissertation]. Penn State University; 2008. Available from: https://etda.libraries.psu.edu/catalog/8173


University of Toronto

19. Darounkola, Nazanin Calagar. Source-level Debugging Framework Design for FPGA High-level Synthesis.

Degree: 2014, University of Toronto

HighLevel Synthesis tools have become more attractive in recent years. However, in order to be fully utilized for largescale applications, HLS tools need to address… (more)

Subjects/Keywords: Debugging; FPGA; High-level synthesis; 0464

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Darounkola, N. C. (2014). Source-level Debugging Framework Design for FPGA High-level Synthesis. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/68069

Chicago Manual of Style (16th Edition):

Darounkola, Nazanin Calagar. “Source-level Debugging Framework Design for FPGA High-level Synthesis.” 2014. Masters Thesis, University of Toronto. Accessed December 15, 2019. http://hdl.handle.net/1807/68069.

MLA Handbook (7th Edition):

Darounkola, Nazanin Calagar. “Source-level Debugging Framework Design for FPGA High-level Synthesis.” 2014. Web. 15 Dec 2019.

Vancouver:

Darounkola NC. Source-level Debugging Framework Design for FPGA High-level Synthesis. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/1807/68069.

Council of Science Editors:

Darounkola NC. Source-level Debugging Framework Design for FPGA High-level Synthesis. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/68069


University of Windsor

20. Tang, Qing Yun. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.

Degree: MA, Electrical and Computer Engineering, 2016, University of Windsor

 FPGAs have shown great promise for accelerating computationally intensive algorithms. However, FPGA-based accelerator design is tedious and time consuming if we rely on traditional HDL… (more)

Subjects/Keywords: FPGA; Hardware Acceleration; High Level Synthesis; OpenCL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tang, Q. Y. (2016). FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5669

Chicago Manual of Style (16th Edition):

Tang, Qing Yun. “FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.” 2016. Masters Thesis, University of Windsor. Accessed December 15, 2019. https://scholar.uwindsor.ca/etd/5669.

MLA Handbook (7th Edition):

Tang, Qing Yun. “FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.” 2016. Web. 15 Dec 2019.

Vancouver:

Tang QY. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. [Internet] [Masters thesis]. University of Windsor; 2016. [cited 2019 Dec 15]. Available from: https://scholar.uwindsor.ca/etd/5669.

Council of Science Editors:

Tang QY. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. [Masters Thesis]. University of Windsor; 2016. Available from: https://scholar.uwindsor.ca/etd/5669


University of Toronto

21. Liu, Li. Automated Debugging Framework for High-level Synthesis.

Degree: 2013, University of Toronto

This thesis proposes a automated test case generation technique for the aim of verifying/debugging High-level synthesis (HLS) tools. The work in this thesis builds a… (more)

Subjects/Keywords: Debug; High-level Synthesis; 0544; 0984

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, L. (2013). Automated Debugging Framework for High-level Synthesis. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/35123

Chicago Manual of Style (16th Edition):

Liu, Li. “Automated Debugging Framework for High-level Synthesis.” 2013. Masters Thesis, University of Toronto. Accessed December 15, 2019. http://hdl.handle.net/1807/35123.

MLA Handbook (7th Edition):

Liu, Li. “Automated Debugging Framework for High-level Synthesis.” 2013. Web. 15 Dec 2019.

Vancouver:

Liu L. Automated Debugging Framework for High-level Synthesis. [Internet] [Masters thesis]. University of Toronto; 2013. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/1807/35123.

Council of Science Editors:

Liu L. Automated Debugging Framework for High-level Synthesis. [Masters Thesis]. University of Toronto; 2013. Available from: http://hdl.handle.net/1807/35123


University of Illinois – Urbana-Champaign

22. Umenthum, Kenneth Richard. Open-source high-level synthesis of tensorflow dataflow graphs using LegUp.

Degree: MS, Electrical & Computer Engr, 2019, University of Illinois – Urbana-Champaign

 A flow is presented for synthesizing Tensorflow computation graphs into FPGA accelerators using the open-source high-level synthesis (HLS) tool LegUp. The Tensorflow computation graph is… (more)

Subjects/Keywords: high level synthesis; machine learning; tensorflow; legup

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Umenthum, K. R. (2019). Open-source high-level synthesis of tensorflow dataflow graphs using LegUp. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/104949

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Umenthum, Kenneth Richard. “Open-source high-level synthesis of tensorflow dataflow graphs using LegUp.” 2019. Thesis, University of Illinois – Urbana-Champaign. Accessed December 15, 2019. http://hdl.handle.net/2142/104949.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Umenthum, Kenneth Richard. “Open-source high-level synthesis of tensorflow dataflow graphs using LegUp.” 2019. Web. 15 Dec 2019.

Vancouver:

Umenthum KR. Open-source high-level synthesis of tensorflow dataflow graphs using LegUp. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2019. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/2142/104949.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Umenthum KR. Open-source high-level synthesis of tensorflow dataflow graphs using LegUp. [Thesis]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/104949

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

23. Morcos, Benjamin. NengoFPGA: an FPGA Backend for the Nengo Neural Simulator.

Degree: 2019, University of Waterloo

 Low-power, high-speed neural networks are critical for providing deployable embedded AI applications at the edge. We describe a Xilinx FPGA implementation of Neural Engineering Framework… (more)

Subjects/Keywords: neural networks; FPGA; nengo; high-level synthesis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Morcos, B. (2019). NengoFPGA: an FPGA Backend for the Nengo Neural Simulator. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/14923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Morcos, Benjamin. “NengoFPGA: an FPGA Backend for the Nengo Neural Simulator.” 2019. Thesis, University of Waterloo. Accessed December 15, 2019. http://hdl.handle.net/10012/14923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Morcos, Benjamin. “NengoFPGA: an FPGA Backend for the Nengo Neural Simulator.” 2019. Web. 15 Dec 2019.

Vancouver:

Morcos B. NengoFPGA: an FPGA Backend for the Nengo Neural Simulator. [Internet] [Thesis]. University of Waterloo; 2019. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/10012/14923.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Morcos B. NengoFPGA: an FPGA Backend for the Nengo Neural Simulator. [Thesis]. University of Waterloo; 2019. Available from: http://hdl.handle.net/10012/14923

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Princeton University

24. Liu, Feng. Static and Dynamic Instruction Mappingfor Spatial Architectures .

Degree: PhD, 2018, Princeton University

 In response to the technology scaling trends, spatial architectures have emerged as a new style of processors for executing programs more efficiently. Unlike traditional Out-of-Order… (more)

Subjects/Keywords: compiling; computer architecture; high level synthesis; reconfigurable

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, F. (2018). Static and Dynamic Instruction Mappingfor Spatial Architectures . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01kk91fp258

Chicago Manual of Style (16th Edition):

Liu, Feng. “Static and Dynamic Instruction Mappingfor Spatial Architectures .” 2018. Doctoral Dissertation, Princeton University. Accessed December 15, 2019. http://arks.princeton.edu/ark:/88435/dsp01kk91fp258.

MLA Handbook (7th Edition):

Liu, Feng. “Static and Dynamic Instruction Mappingfor Spatial Architectures .” 2018. Web. 15 Dec 2019.

Vancouver:

Liu F. Static and Dynamic Instruction Mappingfor Spatial Architectures . [Internet] [Doctoral dissertation]. Princeton University; 2018. [cited 2019 Dec 15]. Available from: http://arks.princeton.edu/ark:/88435/dsp01kk91fp258.

Council of Science Editors:

Liu F. Static and Dynamic Instruction Mappingfor Spatial Architectures . [Doctoral Dissertation]. Princeton University; 2018. Available from: http://arks.princeton.edu/ark:/88435/dsp01kk91fp258


University of Cincinnati

25. Joshi, Manasi. On Reverse Engineering of Encrypted High Level Synthesis Designs.

Degree: MS, Engineering and Applied Science: Electrical Engineering, 2018, University of Cincinnati

 Various technical and business challenges make it difficult for every IC company to own and maintain its own foundry. This makes the role of third… (more)

Subjects/Keywords: Electrical Engineering; Hardware Security; High level synthesis; SAT; Recover flow graph; encrypted high level synthesis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Joshi, M. (2018). On Reverse Engineering of Encrypted High Level Synthesis Designs. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535466997060049

Chicago Manual of Style (16th Edition):

Joshi, Manasi. “On Reverse Engineering of Encrypted High Level Synthesis Designs.” 2018. Masters Thesis, University of Cincinnati. Accessed December 15, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535466997060049.

MLA Handbook (7th Edition):

Joshi, Manasi. “On Reverse Engineering of Encrypted High Level Synthesis Designs.” 2018. Web. 15 Dec 2019.

Vancouver:

Joshi M. On Reverse Engineering of Encrypted High Level Synthesis Designs. [Internet] [Masters thesis]. University of Cincinnati; 2018. [cited 2019 Dec 15]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535466997060049.

Council of Science Editors:

Joshi M. On Reverse Engineering of Encrypted High Level Synthesis Designs. [Masters Thesis]. University of Cincinnati; 2018. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535466997060049


Kaunas University of Technology

26. Chaladauskas, Mindaugas. GSM LPC komponento realizavimas ir tyrimas.

Degree: Master, Informatics, 2010, Kaunas University of Technology

Kiekvienas, kuris kuria aparatūrinę įrangą, nori, tai atlikti kiek įmanoma greičiau ir už kuo mažesnius kaštus. Gaminys turi greitai patekti į rinką, nes egzistuojanti konkurencija… (more)

Subjects/Keywords: LPC; HLS; Sintezė; VHDL; LPC; HLS; Synthesis; VHDL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chaladauskas, Mindaugas. (2010). GSM LPC komponento realizavimas ir tyrimas. (Masters Thesis). Kaunas University of Technology. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100813_113026-64398 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

Chaladauskas, Mindaugas. “GSM LPC komponento realizavimas ir tyrimas.” 2010. Masters Thesis, Kaunas University of Technology. Accessed December 15, 2019. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100813_113026-64398 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

Chaladauskas, Mindaugas. “GSM LPC komponento realizavimas ir tyrimas.” 2010. Web. 15 Dec 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Chaladauskas, Mindaugas. GSM LPC komponento realizavimas ir tyrimas. [Internet] [Masters thesis]. Kaunas University of Technology; 2010. [cited 2019 Dec 15]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100813_113026-64398 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

Chaladauskas, Mindaugas. GSM LPC komponento realizavimas ir tyrimas. [Masters Thesis]. Kaunas University of Technology; 2010. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100813_113026-64398 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

27. Sundari, B. Bala Tripura. Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -.

Degree: Engineering, 2004, Amrita Vishwa Vidyapeetham (University)

The high integration density of very large scale integrated (VLSI) circuits has made system on chip design (SoC) become a reality. With increasing complexity of… (more)

Subjects/Keywords: Multi-level nested loop algorithms;

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sundari, B. B. T. (2004). Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -. (Thesis). Amrita Vishwa Vidyapeetham (University). Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/13051

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sundari, B Bala Tripura. “Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -.” 2004. Thesis, Amrita Vishwa Vidyapeetham (University). Accessed December 15, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/13051.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sundari, B Bala Tripura. “Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -.” 2004. Web. 15 Dec 2019.

Vancouver:

Sundari BBT. Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -. [Internet] [Thesis]. Amrita Vishwa Vidyapeetham (University); 2004. [cited 2019 Dec 15]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13051.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sundari BBT. Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design; -. [Thesis]. Amrita Vishwa Vidyapeetham (University); 2004. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13051

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

28. Kupka, David. Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy .

Degree: 2011, Brno University of Technology

 Tato práce se zabývá způsoby popisu hardware. Představuje metody používané při syntéze popisu a následně na sadě algoritmů porovnává dnes běžný nízkoúrovňový popis v jazyce… (more)

Subjects/Keywords: Vyskoúrovňová syntéza; VHDL; syntéza; popis hardware; srovnání; High-Level Synthesis; VHDL; synthesis; hardware description; comparsion

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kupka, D. (2011). Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/55739

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kupka, David. “Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy .” 2011. Thesis, Brno University of Technology. Accessed December 15, 2019. http://hdl.handle.net/11012/55739.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kupka, David. “Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy .” 2011. Web. 15 Dec 2019.

Vancouver:

Kupka D. Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy . [Internet] [Thesis]. Brno University of Technology; 2011. [cited 2019 Dec 15]. Available from: http://hdl.handle.net/11012/55739.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kupka D. Mapování algoritmů do technologie FPGA s využitím nástrojů vysokoúrovňové syntézy . [Thesis]. Brno University of Technology; 2011. Available from: http://hdl.handle.net/11012/55739

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Alberta

29. Hashemi, Seyyed Ali. Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization.

Degree: MS, Department of Electrical and Computer Engineering, 2011, University of Alberta

 This thesis is concerned with the development of a novel discrete particle swarm optimization (PSO) technique and its application to the discrete optimization of digital… (more)

Subjects/Keywords: Particle swarm optimization; Digital filters; High-level synthesis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hashemi, S. A. (2011). Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/gt54kn61s

Chicago Manual of Style (16th Edition):

Hashemi, Seyyed Ali. “Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization.” 2011. Masters Thesis, University of Alberta. Accessed December 15, 2019. https://era.library.ualberta.ca/files/gt54kn61s.

MLA Handbook (7th Edition):

Hashemi, Seyyed Ali. “Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization.” 2011. Web. 15 Dec 2019.

Vancouver:

Hashemi SA. Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization. [Internet] [Masters thesis]. University of Alberta; 2011. [cited 2019 Dec 15]. Available from: https://era.library.ualberta.ca/files/gt54kn61s.

Council of Science Editors:

Hashemi SA. Design, high-level synthesis, and discrete optimization of digital filters based on particle swarm optimization. [Masters Thesis]. University of Alberta; 2011. Available from: https://era.library.ualberta.ca/files/gt54kn61s


EPFL

30. George, Nithin. FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages.

Degree: 2016, EPFL

 Field Programmable Gate Arrays (FPGAs) have the unique ability to be configured into application-specific architectures that are well suited to specific computing problems. This enables… (more)

Subjects/Keywords: High-level synthesis; domain-specific languages; computational patterns; FPGA; reconfigurable computing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

George, N. (2016). FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages. (Thesis). EPFL. Retrieved from http://infoscience.epfl.ch/record/218533

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

George, Nithin. “FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages.” 2016. Thesis, EPFL. Accessed December 15, 2019. http://infoscience.epfl.ch/record/218533.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

George, Nithin. “FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages.” 2016. Web. 15 Dec 2019.

Vancouver:

George N. FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages. [Internet] [Thesis]. EPFL; 2016. [cited 2019 Dec 15]. Available from: http://infoscience.epfl.ch/record/218533.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

George N. FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages. [Thesis]. EPFL; 2016. Available from: http://infoscience.epfl.ch/record/218533

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] … [1545]

.