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You searched for subject:(Heterogeneous cores). Showing records 1 – 5 of 5 total matches.

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Arizona State University

1. Jain, Sankalp. Energy-efficient Scheduling for Heterogeneous Servers in the Dark Silicon Era.

Degree: Electrical Engineering, 2015, Arizona State University

 Driven by stringent power and thermal constraints, heterogeneous multi-core processors, such as the ARM big-LITTLE architecture, are becoming increasingly popular. In this thesis, the use… (more)

Subjects/Keywords: Electrical engineering; Heterogeneous Servers; Multi-cores; Scheduling Algorithms; Threshold based algorithms

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APA (6th Edition):

Jain, S. (2015). Energy-efficient Scheduling for Heterogeneous Servers in the Dark Silicon Era. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/29678

Chicago Manual of Style (16th Edition):

Jain, Sankalp. “Energy-efficient Scheduling for Heterogeneous Servers in the Dark Silicon Era.” 2015. Masters Thesis, Arizona State University. Accessed July 19, 2019. http://repository.asu.edu/items/29678.

MLA Handbook (7th Edition):

Jain, Sankalp. “Energy-efficient Scheduling for Heterogeneous Servers in the Dark Silicon Era.” 2015. Web. 19 Jul 2019.

Vancouver:

Jain S. Energy-efficient Scheduling for Heterogeneous Servers in the Dark Silicon Era. [Internet] [Masters thesis]. Arizona State University; 2015. [cited 2019 Jul 19]. Available from: http://repository.asu.edu/items/29678.

Council of Science Editors:

Jain S. Energy-efficient Scheduling for Heterogeneous Servers in the Dark Silicon Era. [Masters Thesis]. Arizona State University; 2015. Available from: http://repository.asu.edu/items/29678

2. Suleman, Muhammad Aater. An asymmetric multi-core architecture for efficiently accelerating critical paths in multithreaded programs.

Degree: Electrical and Computer Engineering, 2010, University of Texas – Austin

 Extracting high-performance from Chip Multiprocessors (CMPs) requires that the application be parallelized i.e., divided into threads which execute concurrently on multiple cores. To save programmer… (more)

Subjects/Keywords: Multi-core; Multithreading; CMPs; ACMP; Heterogeneous cores

…i.e., divided into threads which execute concurrently on multiple cores. To save programmer… …pipeline, become the critical path of the program when the number of cores increases, thereby… …execution of the serial portions and multiple slow, small cores for high throughput on the… …large, high-performance core and many small, power-efficient cores. We develop hardware… …5.1.3.1 Modifications to the small cores . . . . . . . . . . . 5.1.3.2 Critical Section Request… 

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APA (6th Edition):

Suleman, M. A. (2010). An asymmetric multi-core architecture for efficiently accelerating critical paths in multithreaded programs. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2010-05-1407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Suleman, Muhammad Aater. “An asymmetric multi-core architecture for efficiently accelerating critical paths in multithreaded programs.” 2010. Thesis, University of Texas – Austin. Accessed July 19, 2019. http://hdl.handle.net/2152/ETD-UT-2010-05-1407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Suleman, Muhammad Aater. “An asymmetric multi-core architecture for efficiently accelerating critical paths in multithreaded programs.” 2010. Web. 19 Jul 2019.

Vancouver:

Suleman MA. An asymmetric multi-core architecture for efficiently accelerating critical paths in multithreaded programs. [Internet] [Thesis]. University of Texas – Austin; 2010. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/2152/ETD-UT-2010-05-1407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Suleman MA. An asymmetric multi-core architecture for efficiently accelerating critical paths in multithreaded programs. [Thesis]. University of Texas – Austin; 2010. Available from: http://hdl.handle.net/2152/ETD-UT-2010-05-1407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

3. Garg, Ankita. Characterization of voltage noise in big, small and single-ISA heterogeneous systems.

Degree: Computer Sciences, 2013, University of Texas – Austin

 Sensitivity of the microprocessor to voltage fluctuations is becoming a major concern with growing emphasis on designing power-efficient microprocessors. Voltage fluctuations that exceed a certain… (more)

Subjects/Keywords: Voltage noise; Multi-cores; Single-ISA heterogeneous; Power modeling; Voltage modeling; Reliability

…performance processors has led to another class of multi-cores, called heterogeneous multi-cores… …Heterogeneous systems may consist of different-ISA cores, like CPU and GPU, e.g, Intel’s Sandy Bridge… …that such heterogeneous multi-cores can provide energy efficiency when workloads are… …appropriately scheduled on the most suitable cores. Thus, heterogeneous system architec2 ture is a… …Noise in Out-of-Order Cores 5.2.1 Correlation with Current Variations . . . . . . . . 5.2.2… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Garg, A. (2013). Characterization of voltage noise in big, small and single-ISA heterogeneous systems. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/40992

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Garg, Ankita. “Characterization of voltage noise in big, small and single-ISA heterogeneous systems.” 2013. Thesis, University of Texas – Austin. Accessed July 19, 2019. http://hdl.handle.net/2152/40992.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Garg, Ankita. “Characterization of voltage noise in big, small and single-ISA heterogeneous systems.” 2013. Web. 19 Jul 2019.

Vancouver:

Garg A. Characterization of voltage noise in big, small and single-ISA heterogeneous systems. [Internet] [Thesis]. University of Texas – Austin; 2013. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/2152/40992.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Garg A. Characterization of voltage noise in big, small and single-ISA heterogeneous systems. [Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/40992

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Gupta, Vishakha. Coordinated system level resource management for heterogeneous many-core platforms.

Degree: PhD, Computing, 2011, Georgia Tech

 A challenge posed by future computer architectures is the efficient exploitation of their many and sometimes heterogeneous computational cores. This challenge is exacerbated by the… (more)

Subjects/Keywords: Coordinated scheduling; Heterogeneous many-core systems; Asymmetric multi-cores; Virtualization; Kinship model; Performance points; Virtual computer systems; Computing platforms; Computer architecture; Heterogeneous computing; High performance computing

…SUMMARY Heterogeneous multi-cores—platforms comprised of both general purpose and accelerator… …heterogeneous hardware like CUDA-based codes that can run on x86 cores as well as NVIDIA GPUs… …cryptographic tasks leading to an integration of heterogeneous cores like network and graphics on chip… …heterogeneous cores, whether on-chip or off-chip (connected via high speed interconnects)… …x29;, where differences in the execution of a VM across heterogeneous cores are captured by… 

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APA (6th Edition):

Gupta, V. (2011). Coordinated system level resource management for heterogeneous many-core platforms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42750

Chicago Manual of Style (16th Edition):

Gupta, Vishakha. “Coordinated system level resource management for heterogeneous many-core platforms.” 2011. Doctoral Dissertation, Georgia Tech. Accessed July 19, 2019. http://hdl.handle.net/1853/42750.

MLA Handbook (7th Edition):

Gupta, Vishakha. “Coordinated system level resource management for heterogeneous many-core platforms.” 2011. Web. 19 Jul 2019.

Vancouver:

Gupta V. Coordinated system level resource management for heterogeneous many-core platforms. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Jul 19]. Available from: http://hdl.handle.net/1853/42750.

Council of Science Editors:

Gupta V. Coordinated system level resource management for heterogeneous many-core platforms. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42750

5. Endo, Fernando Akira. Génération dynamique de code pour l'optimisation énergétique : Online Auto-Tuning for Performance and Energy through Micro-Architecture Dependent Code Generation.

Degree: Docteur es, Informatique, 2015, Grenoble Alpes

 Dans les systèmes informatiques, la consommation énergétique est devenue le facteur le plus limitant de la croissance de performance observée pendant les décennies précédentes. Conséquemment,… (more)

Subjects/Keywords: Micro-architecture; Simulation; Gem5; McPAT; Exécution dans l’ordre; Exécution dans le désordre; Coeurs hétérogènes; Pipeline; Génération dynamique de code; DeGoal; Spécialisation de donnée; Spécialisation de programme; Auto-tuning à la volée; Systèmes embarqués; Micro-architecture; Simulation; Gem5; McPAT; In-order; Out-of-order; Heterogeneous cores; Pipeline; Dynamic code generation; DeGoal; Data specialization; Program specialization; Online auto-tuning; Embedded systems; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Endo, F. A. (2015). Génération dynamique de code pour l'optimisation énergétique : Online Auto-Tuning for Performance and Energy through Micro-Architecture Dependent Code Generation. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2015GREAM044

Chicago Manual of Style (16th Edition):

Endo, Fernando Akira. “Génération dynamique de code pour l'optimisation énergétique : Online Auto-Tuning for Performance and Energy through Micro-Architecture Dependent Code Generation.” 2015. Doctoral Dissertation, Grenoble Alpes. Accessed July 19, 2019. http://www.theses.fr/2015GREAM044.

MLA Handbook (7th Edition):

Endo, Fernando Akira. “Génération dynamique de code pour l'optimisation énergétique : Online Auto-Tuning for Performance and Energy through Micro-Architecture Dependent Code Generation.” 2015. Web. 19 Jul 2019.

Vancouver:

Endo FA. Génération dynamique de code pour l'optimisation énergétique : Online Auto-Tuning for Performance and Energy through Micro-Architecture Dependent Code Generation. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2015. [cited 2019 Jul 19]. Available from: http://www.theses.fr/2015GREAM044.

Council of Science Editors:

Endo FA. Génération dynamique de code pour l'optimisation énergétique : Online Auto-Tuning for Performance and Energy through Micro-Architecture Dependent Code Generation. [Doctoral Dissertation]. Grenoble Alpes; 2015. Available from: http://www.theses.fr/2015GREAM044

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