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You searched for subject:(Hardware). Showing records 1 – 30 of 2278 total matches.

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University of Arkansas

1. Ding, Hongyuan. Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking.

Degree: PhD, 2017, University of Arkansas

  With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance… (more)

Subjects/Keywords: FPGA; Hardware Abstraction; Hardware Acceleration; Hardware Multitasking; MPSoC; OpenCL; Hardware Systems

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APA (6th Edition):

Ding, H. (2017). Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1985

Chicago Manual of Style (16th Edition):

Ding, Hongyuan. “Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking.” 2017. Doctoral Dissertation, University of Arkansas. Accessed February 22, 2020. https://scholarworks.uark.edu/etd/1985.

MLA Handbook (7th Edition):

Ding, Hongyuan. “Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking.” 2017. Web. 22 Feb 2020.

Vancouver:

Ding H. Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking. [Internet] [Doctoral dissertation]. University of Arkansas; 2017. [cited 2020 Feb 22]. Available from: https://scholarworks.uark.edu/etd/1985.

Council of Science Editors:

Ding H. Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking. [Doctoral Dissertation]. University of Arkansas; 2017. Available from: https://scholarworks.uark.edu/etd/1985


University of Waterloo

2. Imeson, Frank. An Attack and a Defence in the Context of Hardware Security.

Degree: 2013, University of Waterloo

 The security of digital Integrated Circuits (ICs) is essential to the security of a computer system that comprises them. We present an improved attack on… (more)

Subjects/Keywords: Security; Hardware

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APA (6th Edition):

Imeson, F. (2013). An Attack and a Defence in the Context of Hardware Security. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/7596

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Imeson, Frank. “An Attack and a Defence in the Context of Hardware Security.” 2013. Thesis, University of Waterloo. Accessed February 22, 2020. http://hdl.handle.net/10012/7596.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Imeson, Frank. “An Attack and a Defence in the Context of Hardware Security.” 2013. Web. 22 Feb 2020.

Vancouver:

Imeson F. An Attack and a Defence in the Context of Hardware Security. [Internet] [Thesis]. University of Waterloo; 2013. [cited 2020 Feb 22]. Available from: http://hdl.handle.net/10012/7596.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Imeson F. An Attack and a Defence in the Context of Hardware Security. [Thesis]. University of Waterloo; 2013. Available from: http://hdl.handle.net/10012/7596

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Victoria

3. Moein, Samer. Systematic Analysis and Methodologies for Hardware Security.

Degree: Department of Electrical and Computer Engineering, 2015, University of Victoria

 With the increase in globalization of Integrated Circuit (IC) design and production, hardware trojans have become a serious threat to manufacturers as well as consumers.… (more)

Subjects/Keywords: Hardware Attack Mitigation; Hardware Attacks; Hardware Security; Hardware Trojan Detection; Hardware Trojans; 3D-ART Schema

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APA (6th Edition):

Moein, S. (2015). Systematic Analysis and Methodologies for Hardware Security. (Thesis). University of Victoria. Retrieved from http://hdl.handle.net/1828/6954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Moein, Samer. “Systematic Analysis and Methodologies for Hardware Security.” 2015. Thesis, University of Victoria. Accessed February 22, 2020. http://hdl.handle.net/1828/6954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Moein, Samer. “Systematic Analysis and Methodologies for Hardware Security.” 2015. Web. 22 Feb 2020.

Vancouver:

Moein S. Systematic Analysis and Methodologies for Hardware Security. [Internet] [Thesis]. University of Victoria; 2015. [cited 2020 Feb 22]. Available from: http://hdl.handle.net/1828/6954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Moein S. Systematic Analysis and Methodologies for Hardware Security. [Thesis]. University of Victoria; 2015. Available from: http://hdl.handle.net/1828/6954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

4. CULLEY, ROBERT J. FDTD METHODS USING PARALLEL COMPUTATIONS AND HARDWARE OPTIMIZATION.

Degree: MS, Engineering : Computer Engineering, 2007, University of Cincinnati

 To achieve faster computation rates using cluster computers, reconfigurable resources are beginning to be utilized in computations. The Finite-Difference Time-Domain (FDTD) is a powerful method… (more)

Subjects/Keywords: FDTD; Reconfigurable Hardware

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APA (6th Edition):

CULLEY, R. J. (2007). FDTD METHODS USING PARALLEL COMPUTATIONS AND HARDWARE OPTIMIZATION. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1182524209

Chicago Manual of Style (16th Edition):

CULLEY, ROBERT J. “FDTD METHODS USING PARALLEL COMPUTATIONS AND HARDWARE OPTIMIZATION.” 2007. Masters Thesis, University of Cincinnati. Accessed February 22, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1182524209.

MLA Handbook (7th Edition):

CULLEY, ROBERT J. “FDTD METHODS USING PARALLEL COMPUTATIONS AND HARDWARE OPTIMIZATION.” 2007. Web. 22 Feb 2020.

Vancouver:

CULLEY RJ. FDTD METHODS USING PARALLEL COMPUTATIONS AND HARDWARE OPTIMIZATION. [Internet] [Masters thesis]. University of Cincinnati; 2007. [cited 2020 Feb 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1182524209.

Council of Science Editors:

CULLEY RJ. FDTD METHODS USING PARALLEL COMPUTATIONS AND HARDWARE OPTIMIZATION. [Masters Thesis]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1182524209

5. Jaurapoma Hilario, Grimson Brandi. Propuesta de virtualización de escritorios en instituciones educativas.

Degree: 2015, National University of San Marcos

 El presente trabajo de investigación tiene por objetivo analizar las diferentes soluciones de virtualización del mercado informático y a partir de ello lanzar una propuesta… (more)

Subjects/Keywords: Virtualización; Software; Hardware

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APA (6th Edition):

Jaurapoma Hilario, G. B. (2015). Propuesta de virtualización de escritorios en instituciones educativas. (Thesis). National University of San Marcos. Retrieved from http://cybertesis.unmsm.edu.pe/handle/cybertesis/4612 ; http://cybertesis.unmsm.edu.pe/bitstream/cybertesis%2F4612/2/bitstream ; http://cybertesis.unmsm.edu.pe/bitstream/cybertesis%2F4612/1/bitstream

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jaurapoma Hilario, Grimson Brandi. “Propuesta de virtualización de escritorios en instituciones educativas.” 2015. Thesis, National University of San Marcos. Accessed February 22, 2020. http://cybertesis.unmsm.edu.pe/handle/cybertesis/4612 ; http://cybertesis.unmsm.edu.pe/bitstream/cybertesis%2F4612/2/bitstream ; http://cybertesis.unmsm.edu.pe/bitstream/cybertesis%2F4612/1/bitstream.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jaurapoma Hilario, Grimson Brandi. “Propuesta de virtualización de escritorios en instituciones educativas.” 2015. Web. 22 Feb 2020.

Vancouver:

Jaurapoma Hilario GB. Propuesta de virtualización de escritorios en instituciones educativas. [Internet] [Thesis]. National University of San Marcos; 2015. [cited 2020 Feb 22]. Available from: http://cybertesis.unmsm.edu.pe/handle/cybertesis/4612 ; http://cybertesis.unmsm.edu.pe/bitstream/cybertesis%2F4612/2/bitstream ; http://cybertesis.unmsm.edu.pe/bitstream/cybertesis%2F4612/1/bitstream.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jaurapoma Hilario GB. Propuesta de virtualización de escritorios en instituciones educativas. [Thesis]. National University of San Marcos; 2015. Available from: http://cybertesis.unmsm.edu.pe/handle/cybertesis/4612 ; http://cybertesis.unmsm.edu.pe/bitstream/cybertesis%2F4612/2/bitstream ; http://cybertesis.unmsm.edu.pe/bitstream/cybertesis%2F4612/1/bitstream

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rice University

6. Rostami, Masoud. Indelible Physical Randomness for Security: Silicon, Bisignals, Biometrics.

Degree: PhD, Engineering, 2014, Rice University

 In this thesis, I investigate the nature and properties of several indelible physical randomness phenomena. I leverage these indelible statistical properties to design robust and… (more)

Subjects/Keywords: IMDs; Hardware Security

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APA (6th Edition):

Rostami, M. (2014). Indelible Physical Randomness for Security: Silicon, Bisignals, Biometrics. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/88120

Chicago Manual of Style (16th Edition):

Rostami, Masoud. “Indelible Physical Randomness for Security: Silicon, Bisignals, Biometrics.” 2014. Doctoral Dissertation, Rice University. Accessed February 22, 2020. http://hdl.handle.net/1911/88120.

MLA Handbook (7th Edition):

Rostami, Masoud. “Indelible Physical Randomness for Security: Silicon, Bisignals, Biometrics.” 2014. Web. 22 Feb 2020.

Vancouver:

Rostami M. Indelible Physical Randomness for Security: Silicon, Bisignals, Biometrics. [Internet] [Doctoral dissertation]. Rice University; 2014. [cited 2020 Feb 22]. Available from: http://hdl.handle.net/1911/88120.

Council of Science Editors:

Rostami M. Indelible Physical Randomness for Security: Silicon, Bisignals, Biometrics. [Doctoral Dissertation]. Rice University; 2014. Available from: http://hdl.handle.net/1911/88120

7. Correia, Vasco Martins. ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável - operadores e grafos a fluxo de dados.

Degree: Mestrado, Ciências de Computação e Matemática Computacional, 2009, University of São Paulo

ChipCflow é o projeto de uma ferramenta para execução de algoritmos escritos em linguagem C utilizando o modelo a fluxo de dados dinâmico em hardware(more)

Subjects/Keywords: Dataflow; Dataflow; FPGA; FPGA; Hardware reconfigurable; Hardware reconfigurável; Hardware reconfigurável FPGA Dataflow

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APA (6th Edition):

Correia, V. M. (2009). ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável - operadores e grafos a fluxo de dados. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/55/55134/tde-06052009-203745/ ;

Chicago Manual of Style (16th Edition):

Correia, Vasco Martins. “ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável - operadores e grafos a fluxo de dados.” 2009. Masters Thesis, University of São Paulo. Accessed February 22, 2020. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-06052009-203745/ ;.

MLA Handbook (7th Edition):

Correia, Vasco Martins. “ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável - operadores e grafos a fluxo de dados.” 2009. Web. 22 Feb 2020.

Vancouver:

Correia VM. ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável - operadores e grafos a fluxo de dados. [Internet] [Masters thesis]. University of São Paulo; 2009. [cited 2020 Feb 22]. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-06052009-203745/ ;.

Council of Science Editors:

Correia VM. ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável - operadores e grafos a fluxo de dados. [Masters Thesis]. University of São Paulo; 2009. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-06052009-203745/ ;


University of Arkansas

8. Weaver, Lucas. Hardware Trojan Detection via Golden Reference Library Matching.

Degree: MSCmpE, 2016, University of Arkansas

  Due to the proliferation of hardware Trojans in third party Intellectual Property (IP) designs, the issue of hardware security has risen to the forefront… (more)

Subjects/Keywords: Applied sciences; Golden reference library; Hardware security; Hardware trojan; Hardware Systems; Information Security

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APA (6th Edition):

Weaver, L. (2016). Hardware Trojan Detection via Golden Reference Library Matching. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1460

Chicago Manual of Style (16th Edition):

Weaver, Lucas. “Hardware Trojan Detection via Golden Reference Library Matching.” 2016. Masters Thesis, University of Arkansas. Accessed February 22, 2020. https://scholarworks.uark.edu/etd/1460.

MLA Handbook (7th Edition):

Weaver, Lucas. “Hardware Trojan Detection via Golden Reference Library Matching.” 2016. Web. 22 Feb 2020.

Vancouver:

Weaver L. Hardware Trojan Detection via Golden Reference Library Matching. [Internet] [Masters thesis]. University of Arkansas; 2016. [cited 2020 Feb 22]. Available from: https://scholarworks.uark.edu/etd/1460.

Council of Science Editors:

Weaver L. Hardware Trojan Detection via Golden Reference Library Matching. [Masters Thesis]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/1460


Cornell University

9. Ilbeyi, Berkin. Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation .

Degree: 2019, Cornell University

 Performance of computers has enjoyed consistent gains due to the availability of faster and cheaper transistors, more complex hardware designs, and better hardware design tools.… (more)

Subjects/Keywords: Computer engineering; Computer science; compiler; Hardware; Hardware Acceleration; Hardware Design; JIT; Meta-Tracing

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APA (6th Edition):

Ilbeyi, B. (2019). Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/67316

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ilbeyi, Berkin. “Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation .” 2019. Thesis, Cornell University. Accessed February 22, 2020. http://hdl.handle.net/1813/67316.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ilbeyi, Berkin. “Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation .” 2019. Web. 22 Feb 2020.

Vancouver:

Ilbeyi B. Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation . [Internet] [Thesis]. Cornell University; 2019. [cited 2020 Feb 22]. Available from: http://hdl.handle.net/1813/67316.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ilbeyi B. Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation . [Thesis]. Cornell University; 2019. Available from: http://hdl.handle.net/1813/67316

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. Dofe, Jaya. HARDWARE ATTACK DETECTION AND PREVENTION FOR CHIP SECURITY.

Degree: MS, 2015, University of New Hampshire

Hardware security is a serious emerging concern in chip designs and applications. Due to the globalization of the semiconductor design and fabrication process, integrated circuits… (more)

Subjects/Keywords: Fault Attack; Hardware Attacks; Hardware Security; Hardware Trojan; Memristor; Electrical engineering; Engineering

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APA (6th Edition):

Dofe, J. (2015). HARDWARE ATTACK DETECTION AND PREVENTION FOR CHIP SECURITY. (Thesis). University of New Hampshire. Retrieved from https://scholars.unh.edu/thesis/1028

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dofe, Jaya. “HARDWARE ATTACK DETECTION AND PREVENTION FOR CHIP SECURITY.” 2015. Thesis, University of New Hampshire. Accessed February 22, 2020. https://scholars.unh.edu/thesis/1028.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dofe, Jaya. “HARDWARE ATTACK DETECTION AND PREVENTION FOR CHIP SECURITY.” 2015. Web. 22 Feb 2020.

Vancouver:

Dofe J. HARDWARE ATTACK DETECTION AND PREVENTION FOR CHIP SECURITY. [Internet] [Thesis]. University of New Hampshire; 2015. [cited 2020 Feb 22]. Available from: https://scholars.unh.edu/thesis/1028.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dofe J. HARDWARE ATTACK DETECTION AND PREVENTION FOR CHIP SECURITY. [Thesis]. University of New Hampshire; 2015. Available from: https://scholars.unh.edu/thesis/1028

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

11. McGeehan, Brendan. Hardware IP Classification through Weighted Characteristics.

Degree: MSCmpE, 2019, University of Arkansas

  Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) due to the many benefits it can bring to a company. For… (more)

Subjects/Keywords: Classifcation; Hardware; Trojans; Hardware Systems; Information Security; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

McGeehan, B. (2019). Hardware IP Classification through Weighted Characteristics. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3166

Chicago Manual of Style (16th Edition):

McGeehan, Brendan. “Hardware IP Classification through Weighted Characteristics.” 2019. Masters Thesis, University of Arkansas. Accessed February 22, 2020. https://scholarworks.uark.edu/etd/3166.

MLA Handbook (7th Edition):

McGeehan, Brendan. “Hardware IP Classification through Weighted Characteristics.” 2019. Web. 22 Feb 2020.

Vancouver:

McGeehan B. Hardware IP Classification through Weighted Characteristics. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2020 Feb 22]. Available from: https://scholarworks.uark.edu/etd/3166.

Council of Science Editors:

McGeehan B. Hardware IP Classification through Weighted Characteristics. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3166


Harvard University

12. Reagen, Brandon. On the Design and Optimization of Specialized Hardware With Applications in Deep Learning.

Degree: PhD, 2018, Harvard University

Traditional computer architecture no longer offers sufficient performance scaling. As power now bounds the capabilities of integrated circuits, new architectures and mechanisms are needed to… (more)

Subjects/Keywords: Computer Architecture; Deep Learning; Hardware Accelerators; Hardware for Deep Learning; Low-Power Hardware

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APA (6th Edition):

Reagen, B. (2018). On the Design and Optimization of Specialized Hardware With Applications in Deep Learning. (Doctoral Dissertation). Harvard University. Retrieved from http://nrs.harvard.edu/urn-3:HUL.InstRepos:41129181

Chicago Manual of Style (16th Edition):

Reagen, Brandon. “On the Design and Optimization of Specialized Hardware With Applications in Deep Learning.” 2018. Doctoral Dissertation, Harvard University. Accessed February 22, 2020. http://nrs.harvard.edu/urn-3:HUL.InstRepos:41129181.

MLA Handbook (7th Edition):

Reagen, Brandon. “On the Design and Optimization of Specialized Hardware With Applications in Deep Learning.” 2018. Web. 22 Feb 2020.

Vancouver:

Reagen B. On the Design and Optimization of Specialized Hardware With Applications in Deep Learning. [Internet] [Doctoral dissertation]. Harvard University; 2018. [cited 2020 Feb 22]. Available from: http://nrs.harvard.edu/urn-3:HUL.InstRepos:41129181.

Council of Science Editors:

Reagen B. On the Design and Optimization of Specialized Hardware With Applications in Deep Learning. [Doctoral Dissertation]. Harvard University; 2018. Available from: http://nrs.harvard.edu/urn-3:HUL.InstRepos:41129181

13. Lopes, Joelmir José. Estudos e avaliações de compiladores para arquiteturas reconfiguráveis.

Degree: Mestrado, Ciências de Computação e Matemática Computacional, 2007, University of São Paulo

Com o aumento crescente das capacidades dos circuitos integrado e conseqüente complexidade das aplicações, em especial as embarcadas, um requisito tem se tornado fundamental no… (more)

Subjects/Keywords: Benchmark; Benchmarks; C language; Hardware design languages; Hardware reconfigurável; Linguagem C; Linguagens de descrição de hardware; Reconfigurable hardware

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APA (6th Edition):

Lopes, J. J. (2007). Estudos e avaliações de compiladores para arquiteturas reconfiguráveis. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/55/55134/tde-13092007-102252/ ;

Chicago Manual of Style (16th Edition):

Lopes, Joelmir José. “Estudos e avaliações de compiladores para arquiteturas reconfiguráveis.” 2007. Masters Thesis, University of São Paulo. Accessed February 22, 2020. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-13092007-102252/ ;.

MLA Handbook (7th Edition):

Lopes, Joelmir José. “Estudos e avaliações de compiladores para arquiteturas reconfiguráveis.” 2007. Web. 22 Feb 2020.

Vancouver:

Lopes JJ. Estudos e avaliações de compiladores para arquiteturas reconfiguráveis. [Internet] [Masters thesis]. University of São Paulo; 2007. [cited 2020 Feb 22]. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-13092007-102252/ ;.

Council of Science Editors:

Lopes JJ. Estudos e avaliações de compiladores para arquiteturas reconfiguráveis. [Masters Thesis]. University of São Paulo; 2007. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-13092007-102252/ ;


University of Alberta

14. Fouladi Fard, Saeed. Compact and accurate hardware simulation of wireless channels for single and multiple antenna systems.

Degree: PhD, Department of Electrical and Computer Engineering, 2009, University of Alberta

 The accurate simulation of wireless channels is important since it permits the realistic and repeatable performance measurement of wireless systems. While software simulation is a… (more)

Subjects/Keywords: Simulation; FPGA; MIMO; Hardware; Fading

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APA (6th Edition):

Fouladi Fard, S. (2009). Compact and accurate hardware simulation of wireless channels for single and multiple antenna systems. (Doctoral Dissertation). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/jh343s826

Chicago Manual of Style (16th Edition):

Fouladi Fard, Saeed. “Compact and accurate hardware simulation of wireless channels for single and multiple antenna systems.” 2009. Doctoral Dissertation, University of Alberta. Accessed February 22, 2020. https://era.library.ualberta.ca/files/jh343s826.

MLA Handbook (7th Edition):

Fouladi Fard, Saeed. “Compact and accurate hardware simulation of wireless channels for single and multiple antenna systems.” 2009. Web. 22 Feb 2020.

Vancouver:

Fouladi Fard S. Compact and accurate hardware simulation of wireless channels for single and multiple antenna systems. [Internet] [Doctoral dissertation]. University of Alberta; 2009. [cited 2020 Feb 22]. Available from: https://era.library.ualberta.ca/files/jh343s826.

Council of Science Editors:

Fouladi Fard S. Compact and accurate hardware simulation of wireless channels for single and multiple antenna systems. [Doctoral Dissertation]. University of Alberta; 2009. Available from: https://era.library.ualberta.ca/files/jh343s826

15. Kesavan, G. Hardware Implementation of Video Watermarking Algorithms; -.

Degree: Electronics and Communication Engineering, 2013, Jawaharlal Nehru Technological University, Hyderabad

DEMs have become an essential input products for orthorectification in operational data processing chain, and also found to be very useful data source in recent… (more)

Subjects/Keywords: Algorithms; Graphical; Hardware; Video; Watermarking

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kesavan, G. (2013). Hardware Implementation of Video Watermarking Algorithms; -. (Thesis). Jawaharlal Nehru Technological University, Hyderabad. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/18843

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kesavan, G. “Hardware Implementation of Video Watermarking Algorithms; -.” 2013. Thesis, Jawaharlal Nehru Technological University, Hyderabad. Accessed February 22, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/18843.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kesavan, G. “Hardware Implementation of Video Watermarking Algorithms; -.” 2013. Web. 22 Feb 2020.

Vancouver:

Kesavan G. Hardware Implementation of Video Watermarking Algorithms; -. [Internet] [Thesis]. Jawaharlal Nehru Technological University, Hyderabad; 2013. [cited 2020 Feb 22]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/18843.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kesavan G. Hardware Implementation of Video Watermarking Algorithms; -. [Thesis]. Jawaharlal Nehru Technological University, Hyderabad; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/18843

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

16. Uma Rajaram. Design of fir filter for adaptive noise cancellation using context switching reconfigurable EHW architecture; -.

Degree: Information and Communication Engineering, 2014, Anna University

newlineConventional non adaptive filters perform well as long as the input newlinesignal is varying uniformly with noise Reconfigurable computing has been newlineproposed for signal processing… (more)

Subjects/Keywords: Adaptive filters; Hardware logic circuits

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APA (6th Edition):

Rajaram, U. (2014). Design of fir filter for adaptive noise cancellation using context switching reconfigurable EHW architecture; -. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/27245

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rajaram, Uma. “Design of fir filter for adaptive noise cancellation using context switching reconfigurable EHW architecture; -.” 2014. Thesis, Anna University. Accessed February 22, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/27245.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rajaram, Uma. “Design of fir filter for adaptive noise cancellation using context switching reconfigurable EHW architecture; -.” 2014. Web. 22 Feb 2020.

Vancouver:

Rajaram U. Design of fir filter for adaptive noise cancellation using context switching reconfigurable EHW architecture; -. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Feb 22]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/27245.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rajaram U. Design of fir filter for adaptive noise cancellation using context switching reconfigurable EHW architecture; -. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/27245

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

17. Thiago Massariolli Sigrist. Restructuring of ArchC for integration to TLM-based project.

Degree: Instituto de Computação, 2007, Universidade Estadual de Campinas

The advent of SoCs (Systems-on-Chip) lead to the development of project methodologies based on TLM (Transaction-Level Modelling), which consist of several modelling layers between pure… (more)

Subjects/Keywords: Simulação (Computadores digitais) - Metodos de simulação; Digital computer simulation; Hardware - Linguagens descritivas; Hardware - Arquitetura; Computer hardware description languages; Hardware

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APA (6th Edition):

Sigrist, T. M. (2007). Restructuring of ArchC for integration to TLM-based project. (Thesis). Universidade Estadual de Campinas. Retrieved from http://libdigi.unicamp.br/document/?code=vtls000417851

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sigrist, Thiago Massariolli. “Restructuring of ArchC for integration to TLM-based project.” 2007. Thesis, Universidade Estadual de Campinas. Accessed February 22, 2020. http://libdigi.unicamp.br/document/?code=vtls000417851.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sigrist, Thiago Massariolli. “Restructuring of ArchC for integration to TLM-based project.” 2007. Web. 22 Feb 2020.

Vancouver:

Sigrist TM. Restructuring of ArchC for integration to TLM-based project. [Internet] [Thesis]. Universidade Estadual de Campinas; 2007. [cited 2020 Feb 22]. Available from: http://libdigi.unicamp.br/document/?code=vtls000417851.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sigrist TM. Restructuring of ArchC for integration to TLM-based project. [Thesis]. Universidade Estadual de Campinas; 2007. Available from: http://libdigi.unicamp.br/document/?code=vtls000417851

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

18. Maldikar, Pranita. Adaptive cache prefetching using machine learning and monitoring hardware performance counters.

Degree: MS, Electrical Engineering, 2014, University of Minnesota

 Many improvements have been made in developing better prefetchers. Improvements in prefetching usually starts by coming up with a new heuristic. The static threshold values… (more)

Subjects/Keywords: Hardware prefetching; Machine learning; Prefetching

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Maldikar, P. (2014). Adaptive cache prefetching using machine learning and monitoring hardware performance counters. (Masters Thesis). University of Minnesota. Retrieved from http://hdl.handle.net/11299/165565

Chicago Manual of Style (16th Edition):

Maldikar, Pranita. “Adaptive cache prefetching using machine learning and monitoring hardware performance counters.” 2014. Masters Thesis, University of Minnesota. Accessed February 22, 2020. http://hdl.handle.net/11299/165565.

MLA Handbook (7th Edition):

Maldikar, Pranita. “Adaptive cache prefetching using machine learning and monitoring hardware performance counters.” 2014. Web. 22 Feb 2020.

Vancouver:

Maldikar P. Adaptive cache prefetching using machine learning and monitoring hardware performance counters. [Internet] [Masters thesis]. University of Minnesota; 2014. [cited 2020 Feb 22]. Available from: http://hdl.handle.net/11299/165565.

Council of Science Editors:

Maldikar P. Adaptive cache prefetching using machine learning and monitoring hardware performance counters. [Masters Thesis]. University of Minnesota; 2014. Available from: http://hdl.handle.net/11299/165565


University of Illinois – Urbana-Champaign

19. Konigsmark, Sven Tenzing Choden. A system for multi-level authentication with physically unclonable functions.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 We analyze deficiencies in existing Physically Unclonable Function (PUF) systems and protocols, and propose a new system of PUFs (SoP) that is numerically secure under… (more)

Subjects/Keywords: Physically Unclonable Functions; Hardware Security

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Konigsmark, S. T. C. (2014). A system for multi-level authentication with physically unclonable functions. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/46931

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Konigsmark, Sven Tenzing Choden. “A system for multi-level authentication with physically unclonable functions.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed February 22, 2020. http://hdl.handle.net/2142/46931.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Konigsmark, Sven Tenzing Choden. “A system for multi-level authentication with physically unclonable functions.” 2014. Web. 22 Feb 2020.

Vancouver:

Konigsmark STC. A system for multi-level authentication with physically unclonable functions. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2020 Feb 22]. Available from: http://hdl.handle.net/2142/46931.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Konigsmark STC. A system for multi-level authentication with physically unclonable functions. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/46931

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Addis Ababa University

20. Daniel, Dilbie Tessema. Leakage Aware Hardware Architecture and Dynamic Power Scheduling for Mobile Devices .

Degree: 2012, Addis Ababa University

 In the last couple of decades, battery powered mobile devices such as smart phones have become one of the most prolific electronic devices in history.… (more)

Subjects/Keywords: Hardware Architecture; Power Scheduling; Dynamic

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APA (6th Edition):

Daniel, D. T. (2012). Leakage Aware Hardware Architecture and Dynamic Power Scheduling for Mobile Devices . (Thesis). Addis Ababa University. Retrieved from http://etd.aau.edu.et/dspace/handle/123456789/4459

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Daniel, Dilbie Tessema. “Leakage Aware Hardware Architecture and Dynamic Power Scheduling for Mobile Devices .” 2012. Thesis, Addis Ababa University. Accessed February 22, 2020. http://etd.aau.edu.et/dspace/handle/123456789/4459.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Daniel, Dilbie Tessema. “Leakage Aware Hardware Architecture and Dynamic Power Scheduling for Mobile Devices .” 2012. Web. 22 Feb 2020.

Vancouver:

Daniel DT. Leakage Aware Hardware Architecture and Dynamic Power Scheduling for Mobile Devices . [Internet] [Thesis]. Addis Ababa University; 2012. [cited 2020 Feb 22]. Available from: http://etd.aau.edu.et/dspace/handle/123456789/4459.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Daniel DT. Leakage Aware Hardware Architecture and Dynamic Power Scheduling for Mobile Devices . [Thesis]. Addis Ababa University; 2012. Available from: http://etd.aau.edu.et/dspace/handle/123456789/4459

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

21. Lin, Chin-li. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Although the rendering speed of modern GPUs is dramatically improved, it is still not fast enough for some applications such as real time rendering and… (more)

Subjects/Keywords: GPU; hardware; billboard; impostor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, C. (2014). A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Chin-li. “A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.” 2014. Thesis, NSYSU. Accessed February 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Chin-li. “A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.” 2014. Web. 22 Feb 2020.

Vancouver:

Lin C. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

22. Linford, John Christian. Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies.

Degree: PhD, Computer Science, 2010, Virginia Tech

 The new generations of multi-core chipset architectures achieve unprecedented levels of computational power while respecting physical and economical constraints. The cost of this power is… (more)

Subjects/Keywords: hardware; high performance computing; software

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APA (6th Edition):

Linford, J. C. (2010). Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/27599

Chicago Manual of Style (16th Edition):

Linford, John Christian. “Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies.” 2010. Doctoral Dissertation, Virginia Tech. Accessed February 22, 2020. http://hdl.handle.net/10919/27599.

MLA Handbook (7th Edition):

Linford, John Christian. “Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies.” 2010. Web. 22 Feb 2020.

Vancouver:

Linford JC. Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies. [Internet] [Doctoral dissertation]. Virginia Tech; 2010. [cited 2020 Feb 22]. Available from: http://hdl.handle.net/10919/27599.

Council of Science Editors:

Linford JC. Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies. [Doctoral Dissertation]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/27599


Cal Poly

23. Day, Steven M. A Graphical Approach to Testing Real-Time Embedded Devices.

Degree: MS, Computer Science, 2009, Cal Poly

 Software Testing is both a vital and expensive part of the software development lifecycle. Improving the testing process has the potential for large returns. Current… (more)

Subjects/Keywords: Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Day, S. M. (2009). A Graphical Approach to Testing Real-Time Embedded Devices. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/114 ; 10.15368/theses.2009.70

Chicago Manual of Style (16th Edition):

Day, Steven M. “A Graphical Approach to Testing Real-Time Embedded Devices.” 2009. Masters Thesis, Cal Poly. Accessed February 22, 2020. https://digitalcommons.calpoly.edu/theses/114 ; 10.15368/theses.2009.70.

MLA Handbook (7th Edition):

Day, Steven M. “A Graphical Approach to Testing Real-Time Embedded Devices.” 2009. Web. 22 Feb 2020.

Vancouver:

Day SM. A Graphical Approach to Testing Real-Time Embedded Devices. [Internet] [Masters thesis]. Cal Poly; 2009. [cited 2020 Feb 22]. Available from: https://digitalcommons.calpoly.edu/theses/114 ; 10.15368/theses.2009.70.

Council of Science Editors:

Day SM. A Graphical Approach to Testing Real-Time Embedded Devices. [Masters Thesis]. Cal Poly; 2009. Available from: https://digitalcommons.calpoly.edu/theses/114 ; 10.15368/theses.2009.70


Brunel University

24. Sazali, Mohd. Approximated transform and quantisation for complexity-reduced high efficiency video coding.

Degree: PhD, 2017, Brunel University

 The transform-quantisation stage is one of the most complex operations in the state-of-the-art High Efficiency Video Coding (HEVC) standard, accounting for 11–41% share of the… (more)

Subjects/Keywords: 621.39; Hardware complexity; Quantisation; Transform

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APA (6th Edition):

Sazali, M. (2017). Approximated transform and quantisation for complexity-reduced high efficiency video coding. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/14724 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.715913

Chicago Manual of Style (16th Edition):

Sazali, Mohd. “Approximated transform and quantisation for complexity-reduced high efficiency video coding.” 2017. Doctoral Dissertation, Brunel University. Accessed February 22, 2020. http://bura.brunel.ac.uk/handle/2438/14724 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.715913.

MLA Handbook (7th Edition):

Sazali, Mohd. “Approximated transform and quantisation for complexity-reduced high efficiency video coding.” 2017. Web. 22 Feb 2020.

Vancouver:

Sazali M. Approximated transform and quantisation for complexity-reduced high efficiency video coding. [Internet] [Doctoral dissertation]. Brunel University; 2017. [cited 2020 Feb 22]. Available from: http://bura.brunel.ac.uk/handle/2438/14724 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.715913.

Council of Science Editors:

Sazali M. Approximated transform and quantisation for complexity-reduced high efficiency video coding. [Doctoral Dissertation]. Brunel University; 2017. Available from: http://bura.brunel.ac.uk/handle/2438/14724 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.715913


Virginia Tech

25. Farhady Ghalaty, Nahid. Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics.

Degree: PhD, Electrical and Computer Engineering, 2016, Virginia Tech

 Recent research has demonstrated that there is no sharp distinction between passive attacks based on side-channel leakage and active attacks based on fault injection. Fault… (more)

Subjects/Keywords: Hardware Security; Physical Attacks; Cryptography

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Farhady Ghalaty, N. (2016). Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/72280

Chicago Manual of Style (16th Edition):

Farhady Ghalaty, Nahid. “Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics.” 2016. Doctoral Dissertation, Virginia Tech. Accessed February 22, 2020. http://hdl.handle.net/10919/72280.

MLA Handbook (7th Edition):

Farhady Ghalaty, Nahid. “Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics.” 2016. Web. 22 Feb 2020.

Vancouver:

Farhady Ghalaty N. Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics. [Internet] [Doctoral dissertation]. Virginia Tech; 2016. [cited 2020 Feb 22]. Available from: http://hdl.handle.net/10919/72280.

Council of Science Editors:

Farhady Ghalaty N. Fault Attacks on Cryptosystems: Novel Threat Models, Countermeasures and Evaluation Metrics. [Doctoral Dissertation]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/72280


Virginia Tech

26. Shrestha, Gyanendra. Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Globalization of semiconductor design and manufacturing has led to a concern of trust in the final product. The components may now be designed and manufactured… (more)

Subjects/Keywords: BMC; Miter; RTL; Hardware Trojan

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shrestha, G. (2012). Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/44889

Chicago Manual of Style (16th Edition):

Shrestha, Gyanendra. “Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking.” 2012. Masters Thesis, Virginia Tech. Accessed February 22, 2020. http://hdl.handle.net/10919/44889.

MLA Handbook (7th Edition):

Shrestha, Gyanendra. “Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking.” 2012. Web. 22 Feb 2020.

Vancouver:

Shrestha G. Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Feb 22]. Available from: http://hdl.handle.net/10919/44889.

Council of Science Editors:

Shrestha G. Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/44889

27. Fakir Sharif Hossain. Variation-Aware Hardware Trojan Detection through Power Side-channel Analysis : パワーサイドチャネル解析によるプロセスばらつきを考慮したハードウェアトロイ回路検出手法; パワー サイド チャネル カイセキ ニ ヨル プロセス バラツキ オ コウリョ シタ ハードウェア トロイ カイロ ケンシュツ シュホウ.

Degree: 博士(工学), 2018, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: Hardware Trojan

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APA (6th Edition):

Hossain, F. S. (2018). Variation-Aware Hardware Trojan Detection through Power Side-channel Analysis : パワーサイドチャネル解析によるプロセスばらつきを考慮したハードウェアトロイ回路検出手法; パワー サイド チャネル カイセキ ニ ヨル プロセス バラツキ オ コウリョ シタ ハードウェア トロイ カイロ ケンシュツ シュホウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/12513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hossain, Fakir Sharif. “Variation-Aware Hardware Trojan Detection through Power Side-channel Analysis : パワーサイドチャネル解析によるプロセスばらつきを考慮したハードウェアトロイ回路検出手法; パワー サイド チャネル カイセキ ニ ヨル プロセス バラツキ オ コウリョ シタ ハードウェア トロイ カイロ ケンシュツ シュホウ.” 2018. Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed February 22, 2020. http://hdl.handle.net/10061/12513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hossain, Fakir Sharif. “Variation-Aware Hardware Trojan Detection through Power Side-channel Analysis : パワーサイドチャネル解析によるプロセスばらつきを考慮したハードウェアトロイ回路検出手法; パワー サイド チャネル カイセキ ニ ヨル プロセス バラツキ オ コウリョ シタ ハードウェア トロイ カイロ ケンシュツ シュホウ.” 2018. Web. 22 Feb 2020.

Vancouver:

Hossain FS. Variation-Aware Hardware Trojan Detection through Power Side-channel Analysis : パワーサイドチャネル解析によるプロセスばらつきを考慮したハードウェアトロイ回路検出手法; パワー サイド チャネル カイセキ ニ ヨル プロセス バラツキ オ コウリョ シタ ハードウェア トロイ カイロ ケンシュツ シュホウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; 2018. [cited 2020 Feb 22]. Available from: http://hdl.handle.net/10061/12513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hossain FS. Variation-Aware Hardware Trojan Detection through Power Side-channel Analysis : パワーサイドチャネル解析によるプロセスばらつきを考慮したハードウェアトロイ回路検出手法; パワー サイド チャネル カイセキ ニ ヨル プロセス バラツキ オ コウリョ シタ ハードウェア トロイ カイロ ケンシュツ シュホウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; 2018. Available from: http://hdl.handle.net/10061/12513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Debrecen

28. Uzonyi, Anett. Die Entwicklung der Hardware .

Degree: DE – Bölcsészettudományi Kar, 2014, University of Debrecen

 In der Diplomarbeit wurde die Entwicklung der Datenträger erläutert. Innerhalb der Entwicklung wurde die Arbeitsweise der unterschiedlichen Datenträger, also von Floppy bis zur SSD ausführlich… (more)

Subjects/Keywords: Hardware; Datenträger; Festplatten; Datenspeicherung

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Uzonyi, A. (2014). Die Entwicklung der Hardware . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/193209

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Uzonyi, Anett. “Die Entwicklung der Hardware .” 2014. Thesis, University of Debrecen. Accessed February 22, 2020. http://hdl.handle.net/2437/193209.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Uzonyi, Anett. “Die Entwicklung der Hardware .” 2014. Web. 22 Feb 2020.

Vancouver:

Uzonyi A. Die Entwicklung der Hardware . [Internet] [Thesis]. University of Debrecen; 2014. [cited 2020 Feb 22]. Available from: http://hdl.handle.net/2437/193209.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Uzonyi A. Die Entwicklung der Hardware . [Thesis]. University of Debrecen; 2014. Available from: http://hdl.handle.net/2437/193209

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Univerzitet u Beogradu

29. Rajović, Vladimir, 1976-. Hardverska realizacija jednoprolaznog brzog kodeka sa visokim stepenom kompresije i minimalnim zahtevanim resursima.

Degree: Elektrotehnički fakultet, 2016, Univerzitet u Beogradu

Tehničke nauke, Elektrotehnika - elektronika / technical sciences, electrical engineering - Technical sciences, Electrical engineering

Kompresija i kodovanje digitalne slike bave se minimizacijom memorijskih resursa… (more)

Subjects/Keywords: image compression; hardware realization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rajović, Vladimir, 1. (2016). Hardverska realizacija jednoprolaznog brzog kodeka sa visokim stepenom kompresije i minimalnim zahtevanim resursima. (Thesis). Univerzitet u Beogradu. Retrieved from https://fedorabg.bg.ac.rs/fedora/get/o:11735/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rajović, Vladimir, 1976-. “Hardverska realizacija jednoprolaznog brzog kodeka sa visokim stepenom kompresije i minimalnim zahtevanim resursima.” 2016. Thesis, Univerzitet u Beogradu. Accessed February 22, 2020. https://fedorabg.bg.ac.rs/fedora/get/o:11735/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rajović, Vladimir, 1976-. “Hardverska realizacija jednoprolaznog brzog kodeka sa visokim stepenom kompresije i minimalnim zahtevanim resursima.” 2016. Web. 22 Feb 2020.

Vancouver:

Rajović, Vladimir 1. Hardverska realizacija jednoprolaznog brzog kodeka sa visokim stepenom kompresije i minimalnim zahtevanim resursima. [Internet] [Thesis]. Univerzitet u Beogradu; 2016. [cited 2020 Feb 22]. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:11735/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rajović, Vladimir 1. Hardverska realizacija jednoprolaznog brzog kodeka sa visokim stepenom kompresije i minimalnim zahtevanim resursima. [Thesis]. Univerzitet u Beogradu; 2016. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:11735/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

30. Kobayashi, K. A power-aware fault-tolerant hardware system for a custom reconfigurable platform:.

Degree: 2010, Delft University of Technology

 Electronics systems in deep-submicron era face many new challenges. Increased intricacy of the manufacturing process will likely to increase the manufacturing defect while testing of… (more)

Subjects/Keywords: bio-inspired; reconfigurable hardware

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kobayashi, K. (2010). A power-aware fault-tolerant hardware system for a custom reconfigurable platform:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:9beb172a-6e38-43ee-8d08-9180411e26f9

Chicago Manual of Style (16th Edition):

Kobayashi, K. “A power-aware fault-tolerant hardware system for a custom reconfigurable platform:.” 2010. Masters Thesis, Delft University of Technology. Accessed February 22, 2020. http://resolver.tudelft.nl/uuid:9beb172a-6e38-43ee-8d08-9180411e26f9.

MLA Handbook (7th Edition):

Kobayashi, K. “A power-aware fault-tolerant hardware system for a custom reconfigurable platform:.” 2010. Web. 22 Feb 2020.

Vancouver:

Kobayashi K. A power-aware fault-tolerant hardware system for a custom reconfigurable platform:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2020 Feb 22]. Available from: http://resolver.tudelft.nl/uuid:9beb172a-6e38-43ee-8d08-9180411e26f9.

Council of Science Editors:

Kobayashi K. A power-aware fault-tolerant hardware system for a custom reconfigurable platform:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:9beb172a-6e38-43ee-8d08-9180411e26f9

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