subject:(Hardware oriented)

Penn State University

1. Gomatam, Priyanka. Object Recognition Using Structured Feature Extraction With A Reconfigurable, Neurosynaptic Processor.

Degree: 2017, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/13945pkg5076

► Neuromorphic hardware has culminated increased interest, with a focus on designing efficient platforms that can support neural network tasks. Many algorithms used in applications today… (more)

Subjects/Keywords: Truenorth; neuromorphic hardware; object detection; histogram of oriented gradients; neural network hardware

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APA (6^th Edition):

Gomatam, P. (2017). Object Recognition Using Structured Feature Extraction With A Reconfigurable, Neurosynaptic Processor. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/13945pkg5076

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Gomatam, Priyanka. “Object Recognition Using Structured Feature Extraction With A Reconfigurable, Neurosynaptic Processor.” 2017. Thesis, Penn State University. Accessed April 13, 2021. https://submit-etda.libraries.psu.edu/catalog/13945pkg5076.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Gomatam, Priyanka. “Object Recognition Using Structured Feature Extraction With A Reconfigurable, Neurosynaptic Processor.” 2017. Web. 13 Apr 2021.

Vancouver:

Gomatam P. Object Recognition Using Structured Feature Extraction With A Reconfigurable, Neurosynaptic Processor. [Internet] [Thesis]. Penn State University; 2017. [cited 2021 Apr 13]. Available from: https://submit-etda.libraries.psu.edu/catalog/13945pkg5076.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gomatam P. Object Recognition Using Structured Feature Extraction With A Reconfigurable, Neurosynaptic Processor. [Thesis]. Penn State University; 2017. Available from: https://submit-etda.libraries.psu.edu/catalog/13945pkg5076

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Weidler, Nathanael R. Built-In Return-Oriented Programs in Embedded Systems and Deep Learning for Hardware Trojan Detection.

Degree: PhD, Electrical and Computer Engineering, 2019, Utah State University

URL: https://digitalcommons.usu.edu/etd/7620

► Microcontrollers and integrated circuits in general have become ubiquitous in the world today. All aspects of our lives depend on them from driving to… (more)

Subjects/Keywords: Return-oriented programming; hardware trojans; hardware security; integrated circuit; Electrical and Computer Engineering

10 more images…

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APA (6^th Edition):

Weidler, N. R. (2019). Built-In Return-Oriented Programs in Embedded Systems and Deep Learning for Hardware Trojan Detection. (Doctoral Dissertation). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/7620

Chicago Manual of Style (16^th Edition):

Weidler, Nathanael R. “Built-In Return-Oriented Programs in Embedded Systems and Deep Learning for Hardware Trojan Detection.” 2019. Doctoral Dissertation, Utah State University. Accessed April 13, 2021. https://digitalcommons.usu.edu/etd/7620.

MLA Handbook (7^th Edition):

Weidler, Nathanael R. “Built-In Return-Oriented Programs in Embedded Systems and Deep Learning for Hardware Trojan Detection.” 2019. Web. 13 Apr 2021.

Vancouver:

Weidler NR. Built-In Return-Oriented Programs in Embedded Systems and Deep Learning for Hardware Trojan Detection. [Internet] [Doctoral dissertation]. Utah State University; 2019. [cited 2021 Apr 13]. Available from: https://digitalcommons.usu.edu/etd/7620.

Council of Science Editors:

Weidler NR. Built-In Return-Oriented Programs in Embedded Systems and Deep Learning for Hardware Trojan Detection. [Doctoral Dissertation]. Utah State University; 2019. Available from: https://digitalcommons.usu.edu/etd/7620

University of New South Wales

3. Ge, Qian. Principled Elimination of Microarchitectural Timing Channels through Operating-System Enforced Time Protection.

Degree: Computer Science & Engineering, 2019, University of New South Wales

URL: http://handle.unsw.edu.au/1959.4/64228 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:61710/SOURCE02?view=true

► Microarchitectural timing channels exploit resource contentions on a shared hardware platform to cause information leakage through timing variance. These channels threaten system security by providing… (more)

▼ Microarchitectural timing channels exploit resource contentions on a shared hardware platform to cause information leakage through timing variance. These channels threaten system security by providing unauthorised information flow in violation of the system’s security policy. Present operating systems lack the means for systematic prevention of such channels. To address this problem, we propose time protection as an operating system (OS) abstraction, which provides mandatory temporal isolation analogous to the spatial isolation provided by the established memory protection abstraction.In order to fully understand microarchitectural timing channels, we first study all published microarchitectural timing attacks, their countermeasures and analyse the underlying causes. Then we define two application scenarios, a confinement scenario and a cloud scenario, which between them represent a large class of security-critical use cases, and aim to develop a solution that supports both.Our study identifies competition for limited hardware resources as the underlying cause for microarchitectural timing channels. From this we derive the requirement that proper isolation requires that all shared resources must be partitioned, either spatially or temporally (time-shared). We then analyse a number of recent processors across two instruction-set architectures (ISAs), x86 and Arm, for their support for such partitioning. We discover that all examined processors exhibit hardware state that cannot be partitioned by architected means, meaning that they all have uncloseable channels.We define the requirements hardware must satisfy for timing-channel prevention, and propose an augmented ISA as a new, security-oriented hardware-software contract.Assuming conforming hardware, we then define the requirements that OS-provided time protection must satisfy. We propose a concrete design of time protection, consisting of a set of policy-free mechanisms, and present an implementation in the seL4 microkernel. We evaluate the efficacy and efficiency of the implementation, and show that it is highly effective at closing timing channels, to the degree supported by the underlying hardware. We also find that the performance overheads are small to negligible. We can conclude that principled prevention of timing channels is possible though mandatory, black-box enforcement by the OS, subject to hardware manufacturers providing mechanisms for scrubbing all shared microarchitectural state. Advisors/Committee Members: Heiser, Gernot, Computer Science & Engineering, Faculty of Engineering, UNSW, Elphinstone, Kevin, Computer Science & Engineering, Faculty of Engineering, UNSW.

Subjects/Keywords: Microarchitectural timing channels; Security-oriented hardware-software contract

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APA (6^th Edition):

Ge, Q. (2019). Principled Elimination of Microarchitectural Timing Channels through Operating-System Enforced Time Protection. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/64228 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:61710/SOURCE02?view=true

Chicago Manual of Style (16^th Edition):

Ge, Qian. “Principled Elimination of Microarchitectural Timing Channels through Operating-System Enforced Time Protection.” 2019. Doctoral Dissertation, University of New South Wales. Accessed April 13, 2021. http://handle.unsw.edu.au/1959.4/64228 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:61710/SOURCE02?view=true.

MLA Handbook (7^th Edition):

Ge, Qian. “Principled Elimination of Microarchitectural Timing Channels through Operating-System Enforced Time Protection.” 2019. Web. 13 Apr 2021.

Vancouver:

Ge Q. Principled Elimination of Microarchitectural Timing Channels through Operating-System Enforced Time Protection. [Internet] [Doctoral dissertation]. University of New South Wales; 2019. [cited 2021 Apr 13]. Available from: http://handle.unsw.edu.au/1959.4/64228 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:61710/SOURCE02?view=true.

Council of Science Editors:

Ge Q. Principled Elimination of Microarchitectural Timing Channels through Operating-System Enforced Time Protection. [Doctoral Dissertation]. University of New South Wales; 2019. Available from: http://handle.unsw.edu.au/1959.4/64228 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:61710/SOURCE02?view=true

4. Sergio Queiroz de Medeiros. Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC.

Degree: 2006, Universidade Federal do Rio Grande do Norte

URL: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=701

►

Novos paradigmas de linguagens de programação vêem sendo comumente testados e geralmente são incorporados depois por linguagens de descrição de hardware. Recentemente, a programação orientada… (more)

Subjects/Keywords: Linguagem de programação; Programação orientada a aspectos (POA); Java; Sistema hardware; SystemC; SISTEMAS DE COMPUTACAO; Programming language; Aspect-oriented programming (AOP); Java; Hardware system; SystemC

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APA (6^th Edition):

Medeiros, S. Q. d. (2006). Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC. (Thesis). Universidade Federal do Rio Grande do Norte. Retrieved from http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=701

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Medeiros, Sergio Queiroz de. “Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC.” 2006. Thesis, Universidade Federal do Rio Grande do Norte. Accessed April 13, 2021. http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=701.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Medeiros, Sergio Queiroz de. “Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC.” 2006. Web. 13 Apr 2021.

Vancouver:

Medeiros SQd. Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC. [Internet] [Thesis]. Universidade Federal do Rio Grande do Norte; 2006. [cited 2021 Apr 13]. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=701.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Medeiros SQd. Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC. [Thesis]. Universidade Federal do Rio Grande do Norte; 2006. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=701

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Toledo

5. Gujja, Swetha. Temperature Variation Effects on Asynchronous PUF Design using FPGAs.

Degree: MS, Electrical Engineering, 2014, University of Toledo

URL: http://rave.ohiolink.edu/etdc/view?acc_num=toledo1417716527

► A variety of logic circuits can be implemented on configurable platforms like Field Programmable Gate Arrays (FPGAs). FPGAs have attracted attention because of their usability… (more)

▼ A variety of logic circuits can be implemented on configurable platforms like Field Programmable Gate Arrays (FPGAs). FPGAs have attracted attention because of their usability over the last decade owing to their greater flexibility compared to full-Custom ICs and ASICs. With their growing popularity, FPGAs have become an attractive target for piracy and therefore, there is a need to develop techniques for their security. Integrated circuits are facing security issues like cloning, reverse engineering, overbuilding, and physical tampering. In order to overcome this challenge, the idea of Physical Unclonable Functions (PUFs) came into existence. PUFs are special challenge-response entities, embedded in a physical device and are used as hardware primitives in the field of hardware oriented security. PUFs extract secret keys from the unique physical characteristics of the chips, i.e., the manufacturing process variations in the chips, in order to authenticate an FPGA. In this thesis, a Self-Timed Ring Oscillator (STRO) based Asynchronous Physical Unclonable Function is implemented on an FPGA. Unlike synchronous ring oscillators, STROs use an asynchronous logic that eliminates the need for a global or centralized clock in its architecture. Synchronous circuits face challenges such as time closure effects, increasing clock rates, clock skews, and performance overhead, etc. The asynchronous logic employed in STROs overcomes these challenges. STROs act as building blocks for our proposed Asynchronous PUF design. In this design, the identically placed self-timed ring oscillators utilize the manufacturing process variations to obtain varying frequencies from the PUF. The output frequencies from STROs help in generating the response bits, which act as unique signatures to serve FPGA authentication, cryptographic key generation, and random number generation. The delay variation of interconnects and transistors on a chip is dependent on the junction temperatures, which could affect the response bits when there is a significant change in environmental temperatures. To determine the robustness, the proposed Asynchronous PUF design is validated by testing at 4 different locations on 13 FPGAs at different temperatures: room temperature, 0o C, 20o C, 45o C, and 70o C. At these temperatures, the frequencies are recorded and compared in order to generate the response bits. The uniqueness and reliability of the obtained responses are observed to be 48.04% (near to the desired 50%) and 97.66%, respectively. It is found that the reliability of the asynchronous design increases with increase in temperature. Advisors/Committee Members: Niamat, Mohammed (Committee Chair).

Subjects/Keywords: Electrical Engineering; PUFs, Hardware oriented security, Asynchronous Physical Unclonable Functions, uniqueness and reliability of PUFs, Temperature variation

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APA (6^th Edition):

Gujja, S. (2014). Temperature Variation Effects on Asynchronous PUF Design using FPGAs. (Masters Thesis). University of Toledo. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=toledo1417716527

Chicago Manual of Style (16^th Edition):

Gujja, Swetha. “Temperature Variation Effects on Asynchronous PUF Design using FPGAs.” 2014. Masters Thesis, University of Toledo. Accessed April 13, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1417716527.

MLA Handbook (7^th Edition):

Gujja, Swetha. “Temperature Variation Effects on Asynchronous PUF Design using FPGAs.” 2014. Web. 13 Apr 2021.

Vancouver:

Gujja S. Temperature Variation Effects on Asynchronous PUF Design using FPGAs. [Internet] [Masters thesis]. University of Toledo; 2014. [cited 2021 Apr 13]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=toledo1417716527.

Council of Science Editors:

Gujja S. Temperature Variation Effects on Asynchronous PUF Design using FPGAs. [Masters Thesis]. University of Toledo; 2014. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=toledo1417716527

ETH Zürich

6. Emmenegger, Markus. An object-oriented design for efficient microsystem simulation.

Degree: 1999, ETH Zürich

URL: http://hdl.handle.net/20.500.11850/144402

Subjects/Keywords: SIMULATION (HARDWARE); OBJEKTORIENTIERTE PROGRAMMIERUNG (PROGRAMMIERMETHODEN); TRANSIENTENANALYSE (ELEKTROTECHNIK); MIKROPROZESSOREN + MIKROCOMPUTER (HARDWARE); SIMULATION (HARDWARE); OBJECT-ORIENTED PROGRAMMING (PROGRAMMING METHODS); TRANSIENT ANALYSIS (ELECTRICAL ENGINEERING); MICROPROCESSORS + MICROCOMPUTERS (HARDWARE); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Emmenegger, M. (1999). An object-oriented design for efficient microsystem simulation. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/144402

Chicago Manual of Style (16^th Edition):

Emmenegger, Markus. “An object-oriented design for efficient microsystem simulation.” 1999. Doctoral Dissertation, ETH Zürich. Accessed April 13, 2021. http://hdl.handle.net/20.500.11850/144402.

MLA Handbook (7^th Edition):

Emmenegger, Markus. “An object-oriented design for efficient microsystem simulation.” 1999. Web. 13 Apr 2021.

Vancouver:

Emmenegger M. An object-oriented design for efficient microsystem simulation. [Internet] [Doctoral dissertation]. ETH Zürich; 1999. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/20.500.11850/144402.

Council of Science Editors:

Emmenegger M. An object-oriented design for efficient microsystem simulation. [Doctoral Dissertation]. ETH Zürich; 1999. Available from: http://hdl.handle.net/20.500.11850/144402

Universidade do Rio Grande do Norte

7. Medeiros, Sergio Queiroz de. Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC .

Degree: 2006, Universidade do Rio Grande do Norte

URL: http://repositorio.ufrn.br/handle/123456789/18072

► New programming language paradigms have commonly been tested and eventually incorporated into hardware description languages. Recently, aspect-oriented programming (AOP) has shown successful in improving the… (more)

Subjects/Keywords: Linguagem de programação; Programação orientada a aspectos (POA); Java; Sistema hardware; SystemC; Programming language; Aspect-oriented programming (AOP); Java; Hardware system; SystemC

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APA (6^th Edition):

Medeiros, S. Q. d. (2006). Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/18072

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Medeiros, Sergio Queiroz de. “Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC .” 2006. Thesis, Universidade do Rio Grande do Norte. Accessed April 13, 2021. http://repositorio.ufrn.br/handle/123456789/18072.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Medeiros, Sergio Queiroz de. “Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC .” 2006. Web. 13 Apr 2021.

Vancouver:

Medeiros SQd. Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2006. [cited 2021 Apr 13]. Available from: http://repositorio.ufrn.br/handle/123456789/18072.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Medeiros SQd. Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC . [Thesis]. Universidade do Rio Grande do Norte; 2006. Available from: http://repositorio.ufrn.br/handle/123456789/18072

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

8. Chan, Jun-Mao. Hardware Acceleration of Feature Extraction Algorithms.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809115-033644

► The description of local features of images has been successfully applied to many areas, including object recognition, texture recognition, image retrieval, robot localization, video data… (more)

Subjects/Keywords: image feature extraction; pedestrian detection; SIFT (Scale-Invariant Feature Transform); SURF (Speeded-Up Robust Feature); hardware acceleration; computer vision; LBP (Local Binary Pattern); HOG (Histograms of Oriented Gradients); FAST (Feature from Accelerated Segment Test)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chan, J. (2015). Hardware Acceleration of Feature Extraction Algorithms. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809115-033644

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chan, Jun-Mao. “Hardware Acceleration of Feature Extraction Algorithms.” 2015. Thesis, NSYSU. Accessed April 13, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809115-033644.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chan, Jun-Mao. “Hardware Acceleration of Feature Extraction Algorithms.” 2015. Web. 13 Apr 2021.

Vancouver:

Chan J. Hardware Acceleration of Feature Extraction Algorithms. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Apr 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809115-033644.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chan J. Hardware Acceleration of Feature Extraction Algorithms. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809115-033644

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Saskatchewan

9. Atta-Konadu, Rodney Kwaku Chapman. Design and implementation of a modular controller for robotic machines.

Degree: 2006, University of Saskatchewan

URL: http://hdl.handle.net/10388/etd-09222006-151842

► This research focused on the design and implementation of an Intelligent Modular Controller (IMC) architecture designed to be reconfigurable over a robust network. The design… (more)

▼ This research focused on the design and implementation of an Intelligent Modular Controller (IMC) architecture designed to be reconfigurable over a robust network. The design incorporates novel communication, hardware, and software architectures. This was motivated by current industrial needs for distributed control systems due to growing demand for less complexity, more processing power, flexibility, and greater fault tolerance. To this end, three main contributions were made. Most distributed control architectures depend on multi-tier heterogeneous communication networks requiring linking devices and/or complex middleware. In this study, first, a communication architecture was proposed and implemented with a homogenous network employing the ubiquitous Ethernet for both real-time and non real-time communication. This was achieved by a producer-consumer coordination model for real-time data communication over a segmented network, and a client-server model for point-to-point transactions. The protocols deployed use a Time-Triggered (TT) approach to schedule real-time tasks on the network. Unlike other TT approaches, the scheduling mechanism does not need to be configured explicitly when controller nodes are added or removed. An implicit clock synchronization technique was also developed to complement the architecture. Second, a reconfigurable mechanism based on an auto-configuration protocol was developed. Modules on the network use this protocol to automatically detect themselves, establish communication, and negotiate for a desired configuration. Third, the research demonstrated hardware/software co-design as a contribution to the growing discipline of mechatronics. The IMC consists of a motion controller board designed and prototyped in-house, and a Java microcontroller. An IMC is mapped to each machine/robot axis, and an additional IMC can be configured to serve as a real-time coordinator. The entire architecture was implemented in Java, thus reinforcing uniformity, simplicity, modularity, and openness. Evaluation results showed the potential of the flexible controller to meet medium to high performance machining requirements. Advisors/Committee Members: Zhang, W. J. (Chris), Lang, Sherman, Schoenau, Greg J., Pufahl, Dennis E., Orban, Peter, Hertz, P. Barry, Gander, Robert, Dolovich, Allan T..

Subjects/Keywords: software architecture; hardware architecture; communication architecture; distributed control; embedded systems; real-time network; robots; Ethernet; Zeroconf; reconfigurable; object-oriented; Java; modular

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APA (6^th Edition):

Atta-Konadu, R. K. C. (2006). Design and implementation of a modular controller for robotic machines. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/etd-09222006-151842

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Atta-Konadu, Rodney Kwaku Chapman. “Design and implementation of a modular controller for robotic machines.” 2006. Thesis, University of Saskatchewan. Accessed April 13, 2021. http://hdl.handle.net/10388/etd-09222006-151842.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Atta-Konadu, Rodney Kwaku Chapman. “Design and implementation of a modular controller for robotic machines.” 2006. Web. 13 Apr 2021.

Vancouver:

Atta-Konadu RKC. Design and implementation of a modular controller for robotic machines. [Internet] [Thesis]. University of Saskatchewan; 2006. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/10388/etd-09222006-151842.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Atta-Konadu RKC. Design and implementation of a modular controller for robotic machines. [Thesis]. University of Saskatchewan; 2006. Available from: http://hdl.handle.net/10388/etd-09222006-151842

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Michigan State University

10. Coombs, Gretel Van Lente. Object-oriented design of embedded systems with translation to VHDL.

Degree: MS, Department of Computer Science, 1998, Michigan State University

URL: http://etd.lib.msu.edu/islandora/object/etd:26945

Subjects/Keywords: VHDL (Computer hardware description language); Embedded computer systems; Software engineering; Object-oriented methods (Computer science)

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APA (6^th Edition):

Coombs, G. V. L. (1998). Object-oriented design of embedded systems with translation to VHDL. (Masters Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:26945

Chicago Manual of Style (16^th Edition):

Coombs, Gretel Van Lente. “Object-oriented design of embedded systems with translation to VHDL.” 1998. Masters Thesis, Michigan State University. Accessed April 13, 2021. http://etd.lib.msu.edu/islandora/object/etd:26945.

MLA Handbook (7^th Edition):

Coombs, Gretel Van Lente. “Object-oriented design of embedded systems with translation to VHDL.” 1998. Web. 13 Apr 2021.

Vancouver:

Coombs GVL. Object-oriented design of embedded systems with translation to VHDL. [Internet] [Masters thesis]. Michigan State University; 1998. [cited 2021 Apr 13]. Available from: http://etd.lib.msu.edu/islandora/object/etd:26945.

Council of Science Editors:

Coombs GVL. Object-oriented design of embedded systems with translation to VHDL. [Masters Thesis]. Michigan State University; 1998. Available from: http://etd.lib.msu.edu/islandora/object/etd:26945

11. Μαριάτος, Ευαγγελινός. ΣΥΣΧΕΔΙΑΣΗ ΣΥΣΤΗΜΑΤΩΝ ΥΛΙΚΟΥ-ΛΟΓΙΣΜΙΚΟΥ ΒΑΣΙΣΜΕΝΗ ΣΕ ΑΝΤΙΚΕΙΜΕΝΟΣΤΡΕ- ΦΕΙΣ ΜΕΘΟΔΟΥΣ.

Degree: 1998, Πανεπιστήμιο Πατρών; University of Patras

URL: http://hdl.handle.net/10442/hedi/11016

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H ΔΙΑΤΡΙΒΗ ΠΑΡΟΥΣΙΑΖΕΙ ΜΙΑ ΝΕΑ ΜΕΘΟΔΟ ΣΧΕΔΙΑΣΗΣ ΗΛΕΚΤΡΟΝΙΚΩΝ ΣΥΣΤΗΜΑΤΩΝ.ΜΕ ΤΗΝΠΡΟΤΕΙΝΟΜΕΝΗ ΜΕΘΟΔΟ ΤΟ ΣΥΣΤΗΜΑ ΑΝΤΙΜΕΤΩΠΙΖΕΤΑΙ ΩΣ ΕΝΑ ΜΟΝΤΕΛΟ ΠΡΟΒΛΗΜΑΤΟΣ ΚΑΙ ΑΠΕΙΚΟΝΙΖΕΤΑΙ ΑΥΤΟΜΑΤΑ ΣΕ ΕΝΑ ΣΥΝΟΛΟ ΑΠΟ… (more)

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H ΔΙΑΤΡΙΒΗ ΠΑΡΟΥΣΙΑΖΕΙ ΜΙΑ ΝΕΑ ΜΕΘΟΔΟ ΣΧΕΔΙΑΣΗΣ ΗΛΕΚΤΡΟΝΙΚΩΝ ΣΥΣΤΗΜΑΤΩΝ.ΜΕ ΤΗΝΠΡΟΤΕΙΝΟΜΕΝΗ ΜΕΘΟΔΟ ΤΟ ΣΥΣΤΗΜΑ ΑΝΤΙΜΕΤΩΠΙΖΕΤΑΙ ΩΣ ΕΝΑ ΜΟΝΤΕΛΟ ΠΡΟΒΛΗΜΑΤΟΣ ΚΑΙ ΑΠΕΙΚΟΝΙΖΕΤΑΙ ΑΥΤΟΜΑΤΑ ΣΕ ΕΝΑ ΣΥΝΟΛΟ ΑΠΟ ΕΝΑΛΛΑΚΤΙΚΕΣ ΑΡΧΙΤΕΚΤΟΝΙΚΕΣ-ΣΤΟΧΟΥΣ. ΤΟ ΑΠΟΤΕΛΕΣΜΑ ΕΙΝΑΙ ΜΙΑ ΒΕΛΤΙΣΤΗ ΑΠΕΙΚΟΝΗΣΗ,ΠΟΥ ΜΑΣ ΕΠΙΤΡΕΠΕΙ ΝΑ ΠΑΡΑΓΟΥΜΕ ΜΕ ΑΥΤΟΜΑΤΑ ΕΡΓΑΛΕΙΑ ΤΟ ΤΕΛΙΚΟ ΜΟΝΤΕΛΟ ΥΛΟΠΟΙΗΣΗΣ.ΓΙΑ ΝΑ ΕΠΙΤΕΥΧΘΕΙ Ο ΑΥΤΟΜΑΤΙΣΜΟΣ ΒΑΣΙΖΟΜΑΣΤΕ ΣΕ ΕΝΑ ΜΑΘΗΜΑΤΙΚΟ ΦΟΡΜΑΛΙΣΜΟ ΠΟΥ ΠΗΓΑΖΕΙ ΑΠΟ ΤΗΝ ΘΕΩΡΙΑΚΑΤΗΓΟΡΙΩΝ. ΣΕ ΜΙΑ ΕΙΔΙΚΗ ΚΑΤΗΓΟΡΙΑ ΜΟΝΤΕΛΩΝ ΠΟΥ ΟΡΙΖΕΤΑΙ ΠΕΡΙΓΡΑΦΟΥΜΕ ΤΙΣ ΠΡΑΞΕΙΣ ΤΗΣ ΑΝΑΠΤΥΞΗΣ ΩΣ ΔΙΑΓΡΑΜΜΑΤΑ.ΕΤΣΙ ΒΡΙΣΚΟΝΤΑΙ ΟΙ ΒΑΣΙΚΕΣ ΠΡΟΔΙΑΓΡΑΦΕΣ ΜΙΑΣ ΓΛΩΣΣΑΣ ΠΕΡΙΓΡΑΦΗΣ ΜΟΝΤΕΛΩΝ ΠΟΥ ΘΑ ΜΑΣ ΕΠΙΤΡΕΨΕΙ ΝΑ ΧΕΙΡΙΣΤΟΥΜΕ ΤΟ ΠΡΟΒΛΗΜΑ ΤΗΣ ΑΠΕΙΚΟΝΗΣΗΣ ΩΣ ΠΡΟΒΛΗΜΑ ΑΝΑΘΕΣΗΣ (ΚΑΙ ΣΥΝΕΠΩΣ ΝΑ ΤΟ ΛΥΣΟΥΜΕ ΜΕ ΑΥΤΟΜΑΤΑ ΕΡΓΑΛΕΙΑ). ΜΙΑ ΤΕΤΟΙΑ ΓΛΩΣΣΑ ΕΙΝΑΙ ΚΑΙ Η ΑΝΤΙΚΕΙΜΕΝΟΣΤΡΕΦΗΣ ΣΗΜΕΙΟΛΟΓΙΑ ΠΟΥ ΧΡΗΣΙΜΟΠΟΙΕΙΤΑΙ ΣΤΗΝ ΔΙΑΤΡΙΒΗ.ΤΟ ΑΠΟΤΕΛΕΣΜΑ ΤΗΣ ΕΡΓΑΣΙΑΣ ΑΠΟΔΕΙΚΝΥΕΙ ΠΩΣ ΑΝ ΕΦΑΡΜΟΣΤΟΥΝ ΜΑΘΗΜΑΤΙΚΑ-ΟΡΘΟΙ ΜΕΤΑΣΧΗΜΑΤΙΣΜΟΙ ΚΑΙ ΣΥΣΧΕΤΙΣΕΙΣ ΑΝΑΜΕΣΑ ΣΕΜΟΝΤΕΛΑ,ΕΙΝΑΙ ΕΦΙΚΤΗ Η ΑΥΤΟΜΑΤΟΠΟΙΗΣΗ ΤΗΣ ΔΙΑΔΙΚΑΣΙΑΣ ΣΧΕΔΙΑΣΗΣ ΓΙΑ ΠΟΛΥΠΛΟΚΑ ΣΥΣΤΗΜΑΤΑ. ΑΥΤΟ ΘΑ ΕΠΙΤΡΕΨΕΙ ΣΕ ΕΝΑΝ ΣΧΕΔΙΑΣΤΗ ΝΑ ΔΙΕΡΕΥΝΑ ΠΟΛΥ ΜΕΓΑΛΥΤΕΡΟ ΕΥΡΟΣ ΑΠΟ ΤΟΝ ΧΩΡΟ ΤΩΝ ΛΥΣΕΩΝ,ΕΠΙΤΥΓΧΑΝΟΝΤΑΣ ΚΑΛΥΤΕΡΟ ΤΕΛΙΚΟ ΣΥΣΤΗΜΑ ΣΕ ΣΥΝΤΟΜΟΤΕΡΟ ΧΡΟΝΟ. (ΤΕΛΟΣ ΠΕΡΙΛΗΨΗΣ).

THIS PHD IS IN THE DOMAIN OF HARDWARE-SOFTWARE CODESIGN.IN THE CONTEXT OF OURREASEARCH WE FOCUSED ON TWO POINTS: ON THE INTRODUCTION OF A NEW DEVELOPMENT- CYCLE MODEL FOR EMBEDDED SYSTEM BUILDING WHICH EMPFASIZED THE ARCHITECTURALEXPLORATION PHASE,AND ON ITS SUPPORT WITH NEW AUTOMATIC ALGORITHMS AND AN OBJECT ORIENTED LANGUAGE. WE APPLIED A FORMALISM BASED ON CATEGORY THEORY.WE HAVE DEFINED AN OMT-BASED NOTATION THAT ALLOWS SPECIFICATION AND DESING OF SYSTEMS THAT ARE TERGETED TO HARDWARE OR SOFTWARE.A SIMPLER CORE LANGUAGE HASALSO BEEN DEFINED AS A BASIS FOR CONSTRUCTING AND RUNNING THE ALGORITHMS WHICH IMPLEMENT OPERATIONS IN THE PROPOSED DCM.THE CENTRAL OPERATION IN THE DCM IS MAPPING FROM MODEL OF SPECIFICATIONS TO MODELS OF ARCHITECTURES, WHICH LEADS TO AN IMPLEMENTATION PROPOSAL.(ABSTR. TRUNC.)

Subjects/Keywords: Category theory; EMBEDDED SYSTEM; Hardware; Object - oriented design; Software; System design; Αντικειμενοστραφής; ΕΝΣΩΜΑΤΩΜΕΝΟ ΣΥΣΤΗΜΑ; Θεωρία κατηγοριών; Λογισμικό; Σχεδίαση συστημάτων; Υλικό

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Μαριάτος, �. (1998). ΣΥΣΧΕΔΙΑΣΗ ΣΥΣΤΗΜΑΤΩΝ ΥΛΙΚΟΥ-ΛΟΓΙΣΜΙΚΟΥ ΒΑΣΙΣΜΕΝΗ ΣΕ ΑΝΤΙΚΕΙΜΕΝΟΣΤΡΕ- ΦΕΙΣ ΜΕΘΟΔΟΥΣ. (Thesis). Πανεπιστήμιο Πατρών; University of Patras. Retrieved from http://hdl.handle.net/10442/hedi/11016

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Μαριάτος, Ευαγγελινός. “ΣΥΣΧΕΔΙΑΣΗ ΣΥΣΤΗΜΑΤΩΝ ΥΛΙΚΟΥ-ΛΟΓΙΣΜΙΚΟΥ ΒΑΣΙΣΜΕΝΗ ΣΕ ΑΝΤΙΚΕΙΜΕΝΟΣΤΡΕ- ΦΕΙΣ ΜΕΘΟΔΟΥΣ.” 1998. Thesis, Πανεπιστήμιο Πατρών; University of Patras. Accessed April 13, 2021. http://hdl.handle.net/10442/hedi/11016.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Μαριάτος, Ευαγγελινός. “ΣΥΣΧΕΔΙΑΣΗ ΣΥΣΤΗΜΑΤΩΝ ΥΛΙΚΟΥ-ΛΟΓΙΣΜΙΚΟΥ ΒΑΣΙΣΜΕΝΗ ΣΕ ΑΝΤΙΚΕΙΜΕΝΟΣΤΡΕ- ΦΕΙΣ ΜΕΘΟΔΟΥΣ.” 1998. Web. 13 Apr 2021.

Vancouver:

Μαριάτος �. ΣΥΣΧΕΔΙΑΣΗ ΣΥΣΤΗΜΑΤΩΝ ΥΛΙΚΟΥ-ΛΟΓΙΣΜΙΚΟΥ ΒΑΣΙΣΜΕΝΗ ΣΕ ΑΝΤΙΚΕΙΜΕΝΟΣΤΡΕ- ΦΕΙΣ ΜΕΘΟΔΟΥΣ. [Internet] [Thesis]. Πανεπιστήμιο Πατρών; University of Patras; 1998. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/10442/hedi/11016.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Μαριάτος �. ΣΥΣΧΕΔΙΑΣΗ ΣΥΣΤΗΜΑΤΩΝ ΥΛΙΚΟΥ-ΛΟΓΙΣΜΙΚΟΥ ΒΑΣΙΣΜΕΝΗ ΣΕ ΑΝΤΙΚΕΙΜΕΝΟΣΤΡΕ- ΦΕΙΣ ΜΕΘΟΔΟΥΣ. [Thesis]. Πανεπιστήμιο Πατρών; University of Patras; 1998. Available from: http://hdl.handle.net/10442/hedi/11016

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Portland State University

12. Yang, Lian. The object-oriented design of a hardware description language analyser for the DIADES silicon compiler system.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 1990, Portland State University

URL: https://pdxscholar.library.pdx.edu/open_access_etds/4260

This thesis is one of the first to introduce a systematic and general Source Language Analysis System (called SLA) for a high -level synthesis system. Advisors/Committee Members: Marek A. Perkowski.

Subjects/Keywords: Object-oriented programming (Computer science); Computer hardware description languages; Silicon compilers; DIADES (Computer program); Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yang, L. (1990). The object-oriented design of a hardware description language analyser for the DIADES silicon compiler system. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/4260

Chicago Manual of Style (16^th Edition):

Yang, Lian. “The object-oriented design of a hardware description language analyser for the DIADES silicon compiler system.” 1990. Masters Thesis, Portland State University. Accessed April 13, 2021. https://pdxscholar.library.pdx.edu/open_access_etds/4260.

MLA Handbook (7^th Edition):

Yang, Lian. “The object-oriented design of a hardware description language analyser for the DIADES silicon compiler system.” 1990. Web. 13 Apr 2021.

Vancouver:

Yang L. The object-oriented design of a hardware description language analyser for the DIADES silicon compiler system. [Internet] [Masters thesis]. Portland State University; 1990. [cited 2021 Apr 13]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4260.

Council of Science Editors:

Yang L. The object-oriented design of a hardware description language analyser for the DIADES silicon compiler system. [Masters Thesis]. Portland State University; 1990. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4260

13. Ferreira, Luciano. Um conjunto de classes para simulacao interativa visual de processadores no ambiente simoo.

Degree: 1998, Brazil

URL: http://hdl.handle.net/10183/26386

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O Projeto T&D-Bench (Teaching and Design Workbench) tern como objetivo fornecer um ambiente didático para fins de avaliação de desempenho de processadores utilizando modelagem e… (more)

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O Projeto T&D-Bench (Teaching and Design Workbench) tern como objetivo fornecer um ambiente didático para fins de avaliação de desempenho de processadores utilizando modelagem e simulação interativas visuais. A aplicação dos conceitos de orientação a objetos (abstração, encapsulamento, herança e polimorfismo) em modelagem de hardware vem sendo amplamente discutida na literatura. Entre os benefícios que este paradigma traz para os modelos de hardware pode-se citar: maior responsabilidade dos modelos, melhor documentação e facilidade de manutenção. O ambiente SIMOO é composto por uma biblioteca de classes e por uma ferramenta gráfica (MET - Model Edition Tool). Este ambiente, utilizado como plataforma para o desenvolvimento deste trabalho, é um ambiente genérico para modelagem e simulação de sistema discretos no qual os modelos sAo construídos de maneira hierárquica e utilizam os conceitos de orientação a objetos como metodologia de projeto e implementação. Este trabalho é a primeira etapa de desenvolvimento do projeto T&D-Bench e iniciou com a modelagem dos processadores Intel 8051 e DLX. Com isso foi possível identificar componentes de arquitetura de processadores que pudessem ser generalizados. As classes genéricas, juntamente com um conjunto de classes para visualização e interação implementadas especialmente para atender as necessidades iniciais do projeto T&D-Bench, foram utilizadas para refazer os modelos dos processadores citados anteriormente e para servir como base para a modelagem do processador PowerPC. Com isso, pode-se fazer uma analise sobre a utilização do paradigma de orientação a objetos em modelagem de processadores e sobre a utilização do ambiente SIMOO para modelagem de hardware. Este trabalho também ajudou na validação do ambiente SIMOO.

The goal of the T&D-Bench (Teaching and Design Workbench) project is to supply a didactic environment for evaluating the performance of processors by using visual interactive modelling and simulation. The application of object-orientation concepts (abstraction, encapsulation, inheritance and polymorphism) in hardware design is being discussed thoroughly in the literature. Among the benefits that this paradigm brings to the hardware modeling we can mention: greater model reusability, better documentation and easier maintenance. The SIMOO environment is composed by a library of classes and a graphic tool (MET - Model Edition Tool). This environment, used as platform for the development of this work, is a generic environment for design and simulation of discrete systems, in which the models are built in a hierarchical way and use the object-orientation concepts as project and implementation methodology. This work is the first stage of development of the T&D-Bench project and began with the design of the Intel 8051 and DLX processor models. This made possible to identify components of processor architectures that could be generalized. The generic classes, together with a set of classes for visualization and interaction specially implemented to assist T&D-Bench's…

Advisors/Committee Members: Wagner, Flavio Rech.

Subjects/Keywords: Sistemas digitais; Simulacao orientada : Objetos; Modelagem : Hardware; Visual interactive simulation; Object oriented simulation SIMOO environment; Processors architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ferreira, L. (1998). Um conjunto de classes para simulacao interativa visual de processadores no ambiente simoo. (Masters Thesis). Brazil. Retrieved from http://hdl.handle.net/10183/26386

Chicago Manual of Style (16^th Edition):

Ferreira, Luciano. “Um conjunto de classes para simulacao interativa visual de processadores no ambiente simoo.” 1998. Masters Thesis, Brazil. Accessed April 13, 2021. http://hdl.handle.net/10183/26386.

MLA Handbook (7^th Edition):

Ferreira, Luciano. “Um conjunto de classes para simulacao interativa visual de processadores no ambiente simoo.” 1998. Web. 13 Apr 2021.

Vancouver:

Ferreira L. Um conjunto de classes para simulacao interativa visual de processadores no ambiente simoo. [Internet] [Masters thesis]. Brazil; 1998. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/10183/26386.

Council of Science Editors:

Ferreira L. Um conjunto de classes para simulacao interativa visual de processadores no ambiente simoo. [Masters Thesis]. Brazil; 1998. Available from: http://hdl.handle.net/10183/26386

14. Medeiros, Sergio Queiroz de. Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC.

Degree: 2006, Federal University of Rio Grande do Norte

URL: https://repositorio.ufrn.br/jspui/handle/123456789/18072

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New programming language paradigms have commonly been tested and eventually incorporated into hardware description languages. Recently, aspect-oriented programming (AOP) has shown successful in improving the… (more)

Subjects/Keywords: Linguagem de programação; Programação orientada a aspectos (POA); Java; Sistema hardware; SystemC; Programming language; Aspect-oriented programming (AOP); Java; Hardware system; SystemC; CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Medeiros, S. Q. d. (2006). Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC. (Masters Thesis). Federal University of Rio Grande do Norte. Retrieved from https://repositorio.ufrn.br/jspui/handle/123456789/18072

Chicago Manual of Style (16^th Edition):

Medeiros, Sergio Queiroz de. “Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC.” 2006. Masters Thesis, Federal University of Rio Grande do Norte. Accessed April 13, 2021. https://repositorio.ufrn.br/jspui/handle/123456789/18072.

MLA Handbook (7^th Edition):

Medeiros, Sergio Queiroz de. “Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC.” 2006. Web. 13 Apr 2021.

Vancouver:

Medeiros SQd. Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC. [Internet] [Masters thesis]. Federal University of Rio Grande do Norte; 2006. [cited 2021 Apr 13]. Available from: https://repositorio.ufrn.br/jspui/handle/123456789/18072.

Council of Science Editors:

Medeiros SQd. Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC. [Masters Thesis]. Federal University of Rio Grande do Norte; 2006. Available from: https://repositorio.ufrn.br/jspui/handle/123456789/18072

Vrije Universiteit Amsterdam

15. Heman, S.A.B.C. Updating Compressed Column-Stores .

Degree: 2015, Vrije Universiteit Amsterdam

URL: http://hdl.handle.net/1871/53448

Subjects/Keywords: database management systems; column oriented database; column-store; large-scale data management; data compression; update handling; transaction management; hardware conscious algorithms; vectorized execution; high-performance computing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Heman, S. A. B. C. (2015). Updating Compressed Column-Stores . (Doctoral Dissertation). Vrije Universiteit Amsterdam. Retrieved from http://hdl.handle.net/1871/53448

Chicago Manual of Style (16^th Edition):

Heman, S A B C. “Updating Compressed Column-Stores .” 2015. Doctoral Dissertation, Vrije Universiteit Amsterdam. Accessed April 13, 2021. http://hdl.handle.net/1871/53448.

MLA Handbook (7^th Edition):

Heman, S A B C. “Updating Compressed Column-Stores .” 2015. Web. 13 Apr 2021.

Vancouver:

Heman SABC. Updating Compressed Column-Stores . [Internet] [Doctoral dissertation]. Vrije Universiteit Amsterdam; 2015. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/1871/53448.

Council of Science Editors:

Heman SABC. Updating Compressed Column-Stores . [Doctoral Dissertation]. Vrije Universiteit Amsterdam; 2015. Available from: http://hdl.handle.net/1871/53448

16. Fountoukis, Spyridon. Μελέτη μεθοδολογιών παραλληλισμού για την υλισμική απεικόνιση της άλγεβρας δυαδικών σχέσεων και κανόνων από δένδρα αποφάσεων.

Degree: 2005, National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ)

URL: http://hdl.handle.net/10442/hedi/21344

► During the operation of an object oriented information system, the objects derived are holding references one of another. These objects can be viewed as interconnected… (more)

▼ During the operation of an object oriented information system, the objects derived are holding references one of another. These objects can be viewed as interconnected forming relationships amongst them. A set of interconnected objects can also be considered as a set of pairs of objects, since the pairing implies a relation (connection) between the pair members. A binary relation is defined as a set of such object pairs. The algebra of binary relations (Tarski 1941, Chin 1951, Jonsson 1951, Jonsson 1952, Tarksi 1987, Givant 1994) can provide an algebraic framework (Sarathy 1993, Gyssens 1994a, Van den Bussche 2001) for manipulating object oriented databases. Previous attempts to use the algebra of binary relations for object manipulation purposes resulted in graph-oriented systems, where graphs were used for querying, browsing, updating and restructuring object databases (Gyssens 1990, Gyssens 1994b, Sarathy 1993) or architectures of software systems (Hold 1998). In this dissertation, instead of using graphs, an extension to the OQL of the ODMG’s object data standard 3.0 for incorporating binary relational expressions for query declarations is proposed. In this proposal, the introduction of simple and multiple merged chains of binary relations in query declarations extends the concept of relation composition, which is defined by the binary relational algebra. A Semi- Dewavefront-like Algorithm, which is mapped on a Bidirectional Multi- Functional Engine-BMFE is also introduced for efficient query execution purposes. This algorithm (and engine) processes the simple and multiple merged chains of binary relations introduced in the OQL extension and declared in queries. The basic elements of the architecture of this engine can be of two types of array processors, a synchronous Square Systolic Device (for Wavefront-like Computations) - S2DWC and an asynchronous Bi-directional Parallel Cubic Engine - BPCE. These array processors are the mappings of the semi-group structure of the binary relational algebra. The multifunctional engine is an extension of this mapping, since it processes, across multiple directions, multiple relations structured as simple or multiple merged chains. These systems were designed and extensively tested using environments provided by suitable VHDL tools and were FPGA implemented virtually producing hybrid systems, composed by both software and hardware (middleware). Decision trees or rules that are derived from machine learning algorithms can be further processed, especially if they are of special forms that serve concrete needs. Data accessing via decision trees is also investigated in this dissertation, through a proposed algorithm for the extraction of rules from decision trees with complex nominal data that could be even in the form of free text. The goal of the algorithm is to process a decision tree generated using the classification algorithm ID3, which processed data in natural language expressions form and to extract rules expressed in natural language. In this case, the algorithm’s input…

Subjects/Keywords: Αντικείμενα; Αντικειμενοστρεφείς βάσεις δεδομένων; Παράλληλη επεξεργασία; Υλισμική απεικόνιση; Άλγεβρα δυαδικών σχέσεων; Κυματομετώπη; Συστολικές διατάξεις; Δένδρα αποφάσεων; Objects; Object oriented databases; Parallel procesisng; Hardware mapping; Binary relations algebra; Wavefront; Systolic arrays; Decision trees

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Fountoukis, S. (2005). Μελέτη μεθοδολογιών παραλληλισμού για την υλισμική απεικόνιση της άλγεβρας δυαδικών σχέσεων και κανόνων από δένδρα αποφάσεων. (Thesis). National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ). Retrieved from http://hdl.handle.net/10442/hedi/21344

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Fountoukis, Spyridon. “Μελέτη μεθοδολογιών παραλληλισμού για την υλισμική απεικόνιση της άλγεβρας δυαδικών σχέσεων και κανόνων από δένδρα αποφάσεων.” 2005. Thesis, National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ). Accessed April 13, 2021. http://hdl.handle.net/10442/hedi/21344.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Fountoukis, Spyridon. “Μελέτη μεθοδολογιών παραλληλισμού για την υλισμική απεικόνιση της άλγεβρας δυαδικών σχέσεων και κανόνων από δένδρα αποφάσεων.” 2005. Web. 13 Apr 2021.

Vancouver:

Fountoukis S. Μελέτη μεθοδολογιών παραλληλισμού για την υλισμική απεικόνιση της άλγεβρας δυαδικών σχέσεων και κανόνων από δένδρα αποφάσεων. [Internet] [Thesis]. National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ); 2005. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/10442/hedi/21344.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fountoukis S. Μελέτη μεθοδολογιών παραλληλισμού για την υλισμική απεικόνιση της άλγεβρας δυαδικών σχέσεων και κανόνων από δένδρα αποφάσεων. [Thesis]. National and Kapodistrian University of Athens; Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών (ΕΚΠΑ); 2005. Available from: http://hdl.handle.net/10442/hedi/21344

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Mohammadi, Danyal. Real-Time Fault Detection and Reconfiguration of a Three-Phase Electric Motor Drive.

Degree: 2019, Boise State University

URL: https://scholarworks.boisestate.edu/td/1553

► Variable-frequency drives (VFDs) are widely used for control of electrical machines such as induction motors (IMs) or permanent-magnet synchronous motors (PMSMs). Similar to other electrical… (more)

Subjects/Keywords: field-oriented control; electric motor drives; fault detection; fault diagnosis; open-switch fault; three-phase inverter; fice-phase inverter; induction motor; PMSM; Controls and Control Theory; Electrical and Electronics; Power and Energy; VLSI and Circuits, Embedded and Hardware Systems

…80 5.2 Literature Review of Hardware/Software codesign… …84 5.5 5.4.1 Hardware… …77 5.1 Hardware platform setup parameter values… …2.2 Schematic of the field-oriented control with Space-Vector PWM . . . . . . 18 2.3… …Support Vector Machine VFD – Variable Frequency Drive FOC – Field-Oriented Control DC – Direct…

11 more images…

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Mohammadi, D. (2019). Real-Time Fault Detection and Reconfiguration of a Three-Phase Electric Motor Drive. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/1553

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Mohammadi, Danyal. “Real-Time Fault Detection and Reconfiguration of a Three-Phase Electric Motor Drive.” 2019. Thesis, Boise State University. Accessed April 13, 2021. https://scholarworks.boisestate.edu/td/1553.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Mohammadi, Danyal. “Real-Time Fault Detection and Reconfiguration of a Three-Phase Electric Motor Drive.” 2019. Web. 13 Apr 2021.

Vancouver:

Mohammadi D. Real-Time Fault Detection and Reconfiguration of a Three-Phase Electric Motor Drive. [Internet] [Thesis]. Boise State University; 2019. [cited 2021 Apr 13]. Available from: https://scholarworks.boisestate.edu/td/1553.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mohammadi D. Real-Time Fault Detection and Reconfiguration of a Three-Phase Electric Motor Drive. [Thesis]. Boise State University; 2019. Available from: https://scholarworks.boisestate.edu/td/1553

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Wobker, Hilmar. Efficient multilevel solvers and high performance computing techniques for the finite element simulation of large-scale elasticity problems.

Degree: 2010, Technische Universität Dortmund

URL: http://hdl.handle.net/2003/26998

► Bei der Simulation realistischer strukturmechanischer Probleme können Gleichungssysteme mit mehreren hundert Millionen Unbekannten entstehen. Für die effiziente Lösung solcher Systeme sind parallele Multilevel-Methoden unerlässlich, die… (more)

▼ Bei der Simulation realistischer strukturmechanischer Probleme können Gleichungssysteme mit mehreren hundert Millionen Unbekannten entstehen. Für die effiziente Lösung solcher Systeme sind parallele Multilevel-Methoden unerlässlich, die in der Lage sind, die Leistung moderner Hardware-Technologien auszuschöpfen. Die Finite-Elemente- und Löser-Toolbox FEAST, die auf die Behandlung skalarer Gleichungen ausgelegt ist, verfolgt genau dieses Ziel. FEAST kombiniert Hardware-orientierte Implementierungstechniken mit einer Multilevel-Gebietszerlegungsmethode namens ScaRC. In der vorliegenden Arbeit wird ein Konzept entwickelt, multivariate Elastizitätsprobleme basierend auf der FEAST-Bibliothek zu lösen. Die generelle Herangehensweise besteht darin, die Lösung multivariater Probleme auf die Lösung einer Reihe von skalaren Problemen zurückzuführen. Dieser Ansatz ermöglicht eine strikte Trennung von skalaren "low level" Kernfunktionalitäten (in Form der FEAST-Bibliothek) und multivariatem "high level" Anwendungscode (in Form des Elastizitätsproblems), was aus Sicht der Softwareentwicklungstechnik sehr vorteilhaft ist: Alle Bemühungen zur Verbesserung der Hardware-Effizienz, sowie Anpassungen an zukünftige technologische Entwicklungen können auf skalare Operationen beschränkt werden, während die multivariate Anwendung automatisch von diesen Erweiterungen profitiert. Im ersten Teil der Arbeit werden substantielle Verbesserungen der skalaren ScaRC-Löser entwickelt, die dann als essentielle Bausteine zur Lösung multivariater Elastizitätsprobleme eingesetzt werden. Ausführliche numerische Untersuchungen zeigen, wie sich die Effizienz der skalaren FEAST-Bibliothek auf den multivariaten Lösungsprozess überträgt. Die Löserstrategie wird dann auf nichtlineare Probleme der Elastizität mit finiter Deformation angewandt. Durch Einsatz einer Liniensuche-Methode wird die Robustheit des Newton-Raphson-Verfahrens signifikant erhöht. Es werden verschiedene Strategien miteinander verglichen, wie genau die linearen Probleme innerhalb der nichtlinearen Iteration zu lösen sind. Zur Behandlung der wichtigen Klasse von (fast) inkompressiblen Materialien wird eine gemischte Verschiebung/Druck-Formulierung gewählt, die mit Hilfe von stabilisierten bilinearen finiten Elementen (Q1/Q1) diskretisiert wird. Eine erweiterte Version der klassischen "Druck-Poisson"-Stabilisierung wird präsentiert, die auch für hochgradig irreguläre Gitter geeignet ist. Es werden Vor- und Nachteile der Q1/Q1-Diskretisierung erörtert, insbesondere in Bezug auf zeitabhängige Rechnungen. Zwei Löser-Klassen zur Behandlung der entstehenden Sattelpunkt-Probleme werden beschrieben und miteinander verglichen: einerseits verschiedene Arten von (beschleunigten) entkoppelten Lösern (Uzawa, Druck-Schurkomplement-Methoden, Block-Vorkonditionierer), andererseits gekoppelte Mehrgitter-Verfahren mit Vanka-Glättern. Effiziente Schurkomplement-Vorkonditionierer, die für die erste Löser-Klasse notwendig sind, werden im Rahmen statischer und zeitabhängiger Probleme besprochen. Die zentrale… Advisors/Committee Members: Turek, S..

Subjects/Keywords: Adaptive coarse grid correction; Adaptive Grobgitterkorrektur; Damped Newton-Raphson; Domain decomposition; Elasticity; Elastizität; Elastodynamic; Elastodynamisch; Elastostatic; Elastostatisch; Equal-order finite elements; FEAST; FEAST; Festkörpermechanik; Finite deformation; Finite Deformation; Finite-Elemente-Methode; Finite element method; Gebietszerlegung; Gedämpftes Newton-Raphson; Gemischte Formulierung; Globales Newton-Raphson; Global Newton-Raphson; Große Deformation; Großskalig; Hardware-oriented; Hardware-orientiert; High performance computing; Incompressible material; Inexact Newton-Raphson; Inexaktes Newton-Raphson; Inkompressibles Material; Irreguläres Gitter; Irregular grids; Iterativer Löser; Iterative solver; Large deformation; Large-scale; LBB stabilisation; LBB Stabilisierung; Line-search; Liniensuche; Mehrgitter; Mehrgitter-Krylov; Minimale Überlappung; Minimal overlap; Mixed formulation; Multigrid; Multigrid-Krylov; Multilevel; Multilevel; Newton-Raphson; Nicht-konformes Mehrgitter; Nonconforming multigrid; Parallel computing; Parallele Effizienz; Parallel efficiency; Paralleles Rechnen; Saddle point problem; Sattelpunkt-Problem; ScaRC; ScaRC; Schubversteifung; Schur complement preconditioning; Schurkomplement-Vorkonditionierer; Shear locking; Solid mechanics; Structural mechanics; Strukturmechanik; Transient; Vanka; Vanka; Volume locking; Volumenversteifung; Zeitabhängig; 510

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wobker, H. (2010). Efficient multilevel solvers and high performance computing techniques for the finite element simulation of large-scale elasticity problems. (Thesis). Technische Universität Dortmund. Retrieved from http://hdl.handle.net/2003/26998

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wobker, Hilmar. “Efficient multilevel solvers and high performance computing techniques for the finite element simulation of large-scale elasticity problems.” 2010. Thesis, Technische Universität Dortmund. Accessed April 13, 2021. http://hdl.handle.net/2003/26998.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wobker, Hilmar. “Efficient multilevel solvers and high performance computing techniques for the finite element simulation of large-scale elasticity problems.” 2010. Web. 13 Apr 2021.

Vancouver:

Wobker H. Efficient multilevel solvers and high performance computing techniques for the finite element simulation of large-scale elasticity problems. [Internet] [Thesis]. Technische Universität Dortmund; 2010. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2003/26998.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wobker H. Efficient multilevel solvers and high performance computing techniques for the finite element simulation of large-scale elasticity problems. [Thesis]. Technische Universität Dortmund; 2010. Available from: http://hdl.handle.net/2003/26998

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Wobker, Hilmar. Efficient multilevel solvers and high performance computing techniques for the finite element simulation of large-scale elasticity problems.

Degree: 2010, Technische Universität Dortmund

URL: http://dx.doi.org/10.17877/DE290R-497

► In the simulation of realistic solid mechanical problems, linear equation systems with hundreds of million unknowns can arise. For the efficient solution of such systems,… (more)

▼ In the simulation of realistic solid mechanical problems, linear equation systems with hundreds of million unknowns can arise. For the efficient solution of such systems, parallel multilevel methods are mandatory that are able to exploit the capabilities of modern hardware technologies. The finite element and solution toolbox FEAST, which is designed to solve scalar equations, pursues exactly this goal. It combines hardware-oriented implementation techniques with a multilevel domain decomposition method called ScaRC that achieves high numerical and parallel efficiency. In this thesis a concept is developed to solve multivariate elasticity problems based on the FEAST library. The general strategy is to reduce the solution of multivariate problems to the solution of a series of scalar problems. This approach facilitates a strict separation of 'low level' scalar kernel functionalities (in the form of the FEAST library) and 'high level' multivariate application code (in the form of the elasticity problem), which is very attractive from a software-engineering point of view: All efforts to improve hardware-efficiency and adaptations to future technology trends can be restricted to scalar operations, and the multivariate application automatically benefits from these enhancements. In the first part of the thesis, substantial improvements of the scalar ScaRC solvers are developed, which are then used as essential building blocks for the efficient solution of multivariate elasticity problems. Extensive numerical studies demonstrate how the efficiency of the scalar FEAST library transfers to the multivariate solution process. The solver strategy is then applied to treat nonlinear problems of finite deformation elasticity. A line-search method is used to significantly increase the robustness of the Newton-Raphson method, and different strategies are compared how to choose the accuracy of the linear system solves within the nonlinear iteration. In order to treat the important class of (nearly) incompressible material, a mixed displacement/pressure formulation is used which is discretised with stabilised bilinear finite elements (Q1/Q1). An enhanced version of the classical 'pressure Poisson' stabilisation is presented which is suitable for highly irregular meshes. Advantages and disadvantages of the Q1/Q1 discretisation are discussed, especially in the context of transient computations. Two solver classes for the resulting saddle point systems are described and compared: on the one hand various kinds of (accelerated) segregated solvers (Uzawa, pressure Schur complement methods, block preconditioners), and on the other hand coupled multigrid solvers with Vanka-smoothers. Efficient Schur complement preconditioners, which are required for the former class, are discussed for the static and the transient case. The main strategy to reduce the solution of multivariate systems to the solution of scalar systems is only applicable in the case of segregated methods. It is shown that for the class of elasticity problems considered in this… Advisors/Committee Members: Turek, S. (advisor), Suttmeier, F.-T. (referee).

Subjects/Keywords: Iterativer Löser; Multilevel; Mehrgitter; Gebietszerlegung; Mehrgitter-Krylov; Nicht-konformes Mehrgitter; ScaRC; Adaptive Grobgitterkorrektur; Minimale Überlappung; Sattelpunkt-Problem; Schurkomplement-Vorkonditionierer; Vanka; Gedämpftes Newton-Raphson; Globales Newton-Raphson; Inexaktes Newton-Raphson; Liniensuche; FEAST; Hardware-orientiert; Großskalig; Paralleles Rechnen; Parallele Effizienz; Finite-Elemente-Methode; Gemischte Formulierung; LBB Stabilisierung; Irreguläres Gitter; Festkörpermechanik; Strukturmechanik; Elastizität; Elastostatisch; Elastodynamisch; Zeitabhängig; Inkompressibles Material; Finite Deformation; Große Deformation; Volumenversteifung; Schubversteifung; Iterative solver; Multilevel; Multigrid; Domain decomposition; Multigrid-Krylov; Nonconforming multigrid; ScaRC; Adaptive coarse grid correction; Minimal overlap; Saddle point problem; Schur complement preconditioning; Vanka; Newton-Raphson; Damped Newton-Raphson; Global Newton-Raphson; Inexact Newton-Raphson; Line-search; FEAST; High performance computing; Hardware-oriented; Large-scale; Parallel computing; Parallel efficiency; Finite element method; Mixed formulation; LBB stabilisation; Equal-order finite elements; Irregular grids; Solid mechanics; Structural mechanics; Elasticity; Elastostatic; Elastodynamic; Transient; Incompressible material; Finite deformation; Large deformation; Volume locking; Shear locking; 510

Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wobker, H. (2010). Efficient multilevel solvers and high performance computing techniques for the finite element simulation of large-scale elasticity problems. (Doctoral Dissertation). Technische Universität Dortmund. Retrieved from http://dx.doi.org/10.17877/DE290R-497

Chicago Manual of Style (16^th Edition):

Wobker, Hilmar. “Efficient multilevel solvers and high performance computing techniques for the finite element simulation of large-scale elasticity problems.” 2010. Doctoral Dissertation, Technische Universität Dortmund. Accessed April 13, 2021. http://dx.doi.org/10.17877/DE290R-497.

MLA Handbook (7^th Edition):

Wobker, Hilmar. “Efficient multilevel solvers and high performance computing techniques for the finite element simulation of large-scale elasticity problems.” 2010. Web. 13 Apr 2021.

Vancouver:

Wobker H. Efficient multilevel solvers and high performance computing techniques for the finite element simulation of large-scale elasticity problems. [Internet] [Doctoral dissertation]. Technische Universität Dortmund; 2010. [cited 2021 Apr 13]. Available from: http://dx.doi.org/10.17877/DE290R-497.

Council of Science Editors:

Wobker H. Efficient multilevel solvers and high performance computing techniques for the finite element simulation of large-scale elasticity problems. [Doctoral Dissertation]. Technische Universität Dortmund; 2010. Available from: http://dx.doi.org/10.17877/DE290R-497

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