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You searched for subject:(Hardware Systems). Showing records 1 – 30 of 603 total matches.

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University of Arkansas

1. Ding, Hongyuan. Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking.

Degree: PhD, 2017, University of Arkansas

  With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance… (more)

Subjects/Keywords: FPGA; Hardware Abstraction; Hardware Acceleration; Hardware Multitasking; MPSoC; OpenCL; Hardware Systems

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APA (6th Edition):

Ding, H. (2017). Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1985

Chicago Manual of Style (16th Edition):

Ding, Hongyuan. “Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking.” 2017. Doctoral Dissertation, University of Arkansas. Accessed September 19, 2019. https://scholarworks.uark.edu/etd/1985.

MLA Handbook (7th Edition):

Ding, Hongyuan. “Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking.” 2017. Web. 19 Sep 2019.

Vancouver:

Ding H. Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking. [Internet] [Doctoral dissertation]. University of Arkansas; 2017. [cited 2019 Sep 19]. Available from: https://scholarworks.uark.edu/etd/1985.

Council of Science Editors:

Ding H. Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking. [Doctoral Dissertation]. University of Arkansas; 2017. Available from: https://scholarworks.uark.edu/etd/1985


Cal Poly

2. Day, Steven M. A Graphical Approach to Testing Real-Time Embedded Devices.

Degree: MS, Computer Science, 2009, Cal Poly

 Software Testing is both a vital and expensive part of the software development lifecycle. Improving the testing process has the potential for large returns. Current… (more)

Subjects/Keywords: Hardware Systems

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APA (6th Edition):

Day, S. M. (2009). A Graphical Approach to Testing Real-Time Embedded Devices. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/114 ; 10.15368/theses.2009.70

Chicago Manual of Style (16th Edition):

Day, Steven M. “A Graphical Approach to Testing Real-Time Embedded Devices.” 2009. Masters Thesis, Cal Poly. Accessed September 19, 2019. https://digitalcommons.calpoly.edu/theses/114 ; 10.15368/theses.2009.70.

MLA Handbook (7th Edition):

Day, Steven M. “A Graphical Approach to Testing Real-Time Embedded Devices.” 2009. Web. 19 Sep 2019.

Vancouver:

Day SM. A Graphical Approach to Testing Real-Time Embedded Devices. [Internet] [Masters thesis]. Cal Poly; 2009. [cited 2019 Sep 19]. Available from: https://digitalcommons.calpoly.edu/theses/114 ; 10.15368/theses.2009.70.

Council of Science Editors:

Day SM. A Graphical Approach to Testing Real-Time Embedded Devices. [Masters Thesis]. Cal Poly; 2009. Available from: https://digitalcommons.calpoly.edu/theses/114 ; 10.15368/theses.2009.70


University of Arkansas

3. McGeehan, Brendan. Hardware IP Classification through Weighted Characteristics.

Degree: MSCmpE, 2019, University of Arkansas

  Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) due to the many benefits it can bring to a company. For… (more)

Subjects/Keywords: Classifcation; Hardware; Trojans; Hardware Systems; Information Security; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

McGeehan, B. (2019). Hardware IP Classification through Weighted Characteristics. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3166

Chicago Manual of Style (16th Edition):

McGeehan, Brendan. “Hardware IP Classification through Weighted Characteristics.” 2019. Masters Thesis, University of Arkansas. Accessed September 19, 2019. https://scholarworks.uark.edu/etd/3166.

MLA Handbook (7th Edition):

McGeehan, Brendan. “Hardware IP Classification through Weighted Characteristics.” 2019. Web. 19 Sep 2019.

Vancouver:

McGeehan B. Hardware IP Classification through Weighted Characteristics. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2019 Sep 19]. Available from: https://scholarworks.uark.edu/etd/3166.

Council of Science Editors:

McGeehan B. Hardware IP Classification through Weighted Characteristics. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3166


University of Arkansas

4. Weaver, Lucas. Hardware Trojan Detection via Golden Reference Library Matching.

Degree: MSCmpE, 2016, University of Arkansas

  Due to the proliferation of hardware Trojans in third party Intellectual Property (IP) designs, the issue of hardware security has risen to the forefront… (more)

Subjects/Keywords: Applied sciences; Golden reference library; Hardware security; Hardware trojan; Hardware Systems; Information Security

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APA (6th Edition):

Weaver, L. (2016). Hardware Trojan Detection via Golden Reference Library Matching. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1460

Chicago Manual of Style (16th Edition):

Weaver, Lucas. “Hardware Trojan Detection via Golden Reference Library Matching.” 2016. Masters Thesis, University of Arkansas. Accessed September 19, 2019. https://scholarworks.uark.edu/etd/1460.

MLA Handbook (7th Edition):

Weaver, Lucas. “Hardware Trojan Detection via Golden Reference Library Matching.” 2016. Web. 19 Sep 2019.

Vancouver:

Weaver L. Hardware Trojan Detection via Golden Reference Library Matching. [Internet] [Masters thesis]. University of Arkansas; 2016. [cited 2019 Sep 19]. Available from: https://scholarworks.uark.edu/etd/1460.

Council of Science Editors:

Weaver L. Hardware Trojan Detection via Golden Reference Library Matching. [Masters Thesis]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/1460


Virginia Commonwealth University

5. Khairullah, Shawkat Sabah. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.

Degree: PhD, Electrical & Computer Engineering, 2018, Virginia Commonwealth University

  Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes.… (more)

Subjects/Keywords: Computer and Systems Architecture; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Khairullah, S. S. (2018). Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. (Doctoral Dissertation). Virginia Commonwealth University. Retrieved from https://scholarscompass.vcu.edu/etd/5671

Chicago Manual of Style (16th Edition):

Khairullah, Shawkat Sabah. “Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.” 2018. Doctoral Dissertation, Virginia Commonwealth University. Accessed September 19, 2019. https://scholarscompass.vcu.edu/etd/5671.

MLA Handbook (7th Edition):

Khairullah, Shawkat Sabah. “Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices.” 2018. Web. 19 Sep 2019.

Vancouver:

Khairullah SS. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. [Internet] [Doctoral dissertation]. Virginia Commonwealth University; 2018. [cited 2019 Sep 19]. Available from: https://scholarscompass.vcu.edu/etd/5671.

Council of Science Editors:

Khairullah SS. Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices. [Doctoral Dissertation]. Virginia Commonwealth University; 2018. Available from: https://scholarscompass.vcu.edu/etd/5671


EPFL

6. Porobic, Danica. High Performance Transaction Processing on Non-Uniform Hardware Topologies.

Degree: 2016, EPFL

 Transaction processing is a mission critical enterprise application that runs on high-end servers. Traditionally, transaction processing systems have been designed for uniform core-to-core communication latencies.… (more)

Subjects/Keywords: Database management systems; Transaction processing systems; Multisocket multicore hardware; Hardware Islands; Non-uniform hardware topologies; Distributed transaction processing systems

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APA (6th Edition):

Porobic, D. (2016). High Performance Transaction Processing on Non-Uniform Hardware Topologies. (Thesis). EPFL. Retrieved from http://infoscience.epfl.ch/record/219117

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Porobic, Danica. “High Performance Transaction Processing on Non-Uniform Hardware Topologies.” 2016. Thesis, EPFL. Accessed September 19, 2019. http://infoscience.epfl.ch/record/219117.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Porobic, Danica. “High Performance Transaction Processing on Non-Uniform Hardware Topologies.” 2016. Web. 19 Sep 2019.

Vancouver:

Porobic D. High Performance Transaction Processing on Non-Uniform Hardware Topologies. [Internet] [Thesis]. EPFL; 2016. [cited 2019 Sep 19]. Available from: http://infoscience.epfl.ch/record/219117.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Porobic D. High Performance Transaction Processing on Non-Uniform Hardware Topologies. [Thesis]. EPFL; 2016. Available from: http://infoscience.epfl.ch/record/219117

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

7. Pahlavan Yali, Moein. FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 The quick growth of embedded systems and their increasing computing power has made them suitable for a wider range of applications. Despite the increasing performance… (more)

Subjects/Keywords: Embedded Systems; FPGA; Hardware Accelerator; Performance Model

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APA (6th Edition):

Pahlavan Yali, M. (2015). FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51193

Chicago Manual of Style (16th Edition):

Pahlavan Yali, Moein. “FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems.” 2015. Masters Thesis, Virginia Tech. Accessed September 19, 2019. http://hdl.handle.net/10919/51193.

MLA Handbook (7th Edition):

Pahlavan Yali, Moein. “FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems.” 2015. Web. 19 Sep 2019.

Vancouver:

Pahlavan Yali M. FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/10919/51193.

Council of Science Editors:

Pahlavan Yali M. FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51193


University of Tennessee – Knoxville

8. Tham, Kevin Vun Kiat. PVT Compensation for Single-Slope Measurement Systems.

Degree: MS, Electrical Engineering, 2011, University of Tennessee – Knoxville

  A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6th Edition):

Tham, K. V. K. (2011). PVT Compensation for Single-Slope Measurement Systems. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tham, Kevin Vun Kiat. “PVT Compensation for Single-Slope Measurement Systems.” 2011. Thesis, University of Tennessee – Knoxville. Accessed September 19, 2019. https://trace.tennessee.edu/utk_gradthes/915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tham, Kevin Vun Kiat. “PVT Compensation for Single-Slope Measurement Systems.” 2011. Web. 19 Sep 2019.

Vancouver:

Tham KVK. PVT Compensation for Single-Slope Measurement Systems. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2019 Sep 19]. Available from: https://trace.tennessee.edu/utk_gradthes/915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tham KVK. PVT Compensation for Single-Slope Measurement Systems. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

9. Kilambi, Supriya. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.

Degree: MS, Computer Engineering, 2011, University of Tennessee – Knoxville

 This thesis presents the low power design of a 916MHz Gilbert cell mixer and a Class-A power amplifier for the Bioluminescent Bioreporter Integrated Circuit (BBIC)… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6th Edition):

Kilambi, S. (2011). Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/888

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kilambi, Supriya. “Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.” 2011. Thesis, University of Tennessee – Knoxville. Accessed September 19, 2019. https://trace.tennessee.edu/utk_gradthes/888.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kilambi, Supriya. “Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter.” 2011. Web. 19 Sep 2019.

Vancouver:

Kilambi S. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2019 Sep 19]. Available from: https://trace.tennessee.edu/utk_gradthes/888.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kilambi S. Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/888

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

10. Mudhasani, Shanthan. GPU-based Implementation of the Variational Path Integral Method.

Degree: MS, Electrical Engineering, 2011, University of Tennessee – Knoxville

  Any system in the world constitutes particles like electrons. To analyze the behaviors of these systems the behavior of these particles must be predicted.… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6th Edition):

Mudhasani, S. (2011). GPU-based Implementation of the Variational Path Integral Method. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mudhasani, Shanthan. “GPU-based Implementation of the Variational Path Integral Method.” 2011. Thesis, University of Tennessee – Knoxville. Accessed September 19, 2019. https://trace.tennessee.edu/utk_gradthes/932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mudhasani, Shanthan. “GPU-based Implementation of the Variational Path Integral Method.” 2011. Web. 19 Sep 2019.

Vancouver:

Mudhasani S. GPU-based Implementation of the Variational Path Integral Method. [Internet] [Thesis]. University of Tennessee – Knoxville; 2011. [cited 2019 Sep 19]. Available from: https://trace.tennessee.edu/utk_gradthes/932.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mudhasani S. GPU-based Implementation of the Variational Path Integral Method. [Thesis]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_gradthes/932

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Cal Poly

11. Zaveri, Jainish K. ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY.

Degree: MS, Electrical Engineering, 2018, Cal Poly

  Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These… (more)

Subjects/Keywords: VLSI and Circuits; Embedded and Hardware Systems

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APA (6th Edition):

Zaveri, J. K. (2018). ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1940

Chicago Manual of Style (16th Edition):

Zaveri, Jainish K. “ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY.” 2018. Masters Thesis, Cal Poly. Accessed September 19, 2019. https://digitalcommons.calpoly.edu/theses/1940.

MLA Handbook (7th Edition):

Zaveri, Jainish K. “ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY.” 2018. Web. 19 Sep 2019.

Vancouver:

Zaveri JK. ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY. [Internet] [Masters thesis]. Cal Poly; 2018. [cited 2019 Sep 19]. Available from: https://digitalcommons.calpoly.edu/theses/1940.

Council of Science Editors:

Zaveri JK. ASIC DESIGN OF RF ENERGY HARVESTER USING 0.13UM CMOS TECHNOLOGY. [Masters Thesis]. Cal Poly; 2018. Available from: https://digitalcommons.calpoly.edu/theses/1940


University of Ottawa

12. Necsulescu, Philip I. Automatic Generation of Hardware for Custom Instructions .

Degree: 2011, University of Ottawa

 The Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of… (more)

Subjects/Keywords: FPGA; Instruction Set Extension; ISE; Custom Instruction; Automatic Hardware Generation; Assisted Hardware Generation; VHDL; Embedded Systems; Custom Hardware

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APA (6th Edition):

Necsulescu, P. I. (2011). Automatic Generation of Hardware for Custom Instructions . (Thesis). University of Ottawa. Retrieved from http://hdl.handle.net/10393/20153

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Necsulescu, Philip I. “Automatic Generation of Hardware for Custom Instructions .” 2011. Thesis, University of Ottawa. Accessed September 19, 2019. http://hdl.handle.net/10393/20153.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Necsulescu, Philip I. “Automatic Generation of Hardware for Custom Instructions .” 2011. Web. 19 Sep 2019.

Vancouver:

Necsulescu PI. Automatic Generation of Hardware for Custom Instructions . [Internet] [Thesis]. University of Ottawa; 2011. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/10393/20153.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Necsulescu PI. Automatic Generation of Hardware for Custom Instructions . [Thesis]. University of Ottawa; 2011. Available from: http://hdl.handle.net/10393/20153

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

13. Yang, Depeng. Turbo Bayesian Compressed Sensing.

Degree: 2011, University of Tennessee – Knoxville

 Compressed sensing (CS) theory specifies a new signal acquisition approach, potentially allowing the acquisition of signals at a much lower data rate than the Nyquist… (more)

Subjects/Keywords: Compressed Sensing; Hardware Implementation; FPGA; GPU; Signal Processing; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Yang, D. (2011). Turbo Bayesian Compressed Sensing. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/1145

Chicago Manual of Style (16th Edition):

Yang, Depeng. “Turbo Bayesian Compressed Sensing.” 2011. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed September 19, 2019. https://trace.tennessee.edu/utk_graddiss/1145.

MLA Handbook (7th Edition):

Yang, Depeng. “Turbo Bayesian Compressed Sensing.” 2011. Web. 19 Sep 2019.

Vancouver:

Yang D. Turbo Bayesian Compressed Sensing. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2011. [cited 2019 Sep 19]. Available from: https://trace.tennessee.edu/utk_graddiss/1145.

Council of Science Editors:

Yang D. Turbo Bayesian Compressed Sensing. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2011. Available from: https://trace.tennessee.edu/utk_graddiss/1145


University of Arkansas

14. Le, Thao Phuong. Securing Soft IPs against Hardware Trojan Insertion.

Degree: PhD, 2018, University of Arkansas

  Due to the increasing complexity of hardware designs, third-party hardware Intellectual Property (IP) blocks are often incorporated in order to alleviate the burden on… (more)

Subjects/Keywords: Asset; Golden Reference; Hardware Trojan; Security; Digital Communications and Networking; Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Le, T. P. (2018). Securing Soft IPs against Hardware Trojan Insertion. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2694

Chicago Manual of Style (16th Edition):

Le, Thao Phuong. “Securing Soft IPs against Hardware Trojan Insertion.” 2018. Doctoral Dissertation, University of Arkansas. Accessed September 19, 2019. https://scholarworks.uark.edu/etd/2694.

MLA Handbook (7th Edition):

Le, Thao Phuong. “Securing Soft IPs against Hardware Trojan Insertion.” 2018. Web. 19 Sep 2019.

Vancouver:

Le TP. Securing Soft IPs against Hardware Trojan Insertion. [Internet] [Doctoral dissertation]. University of Arkansas; 2018. [cited 2019 Sep 19]. Available from: https://scholarworks.uark.edu/etd/2694.

Council of Science Editors:

Le TP. Securing Soft IPs against Hardware Trojan Insertion. [Doctoral Dissertation]. University of Arkansas; 2018. Available from: https://scholarworks.uark.edu/etd/2694

15. Merchant, Murtaza. Testing and Validation of a Prototype Gpgpu Design for FPGAs.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

  Due to their suitability for highly parallel and pipelined computation, field programmable gate arrays (FPGAs) and general-purpose graphics processing units (GPGPUs) have emerged as… (more)

Subjects/Keywords: GPGPU; FPGA; hardware acceleration; CUDA compatible; scalable; flexible; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Merchant, M. (2013). Testing and Validation of a Prototype Gpgpu Design for FPGAs. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1012

Chicago Manual of Style (16th Edition):

Merchant, Murtaza. “Testing and Validation of a Prototype Gpgpu Design for FPGAs.” 2013. Masters Thesis, University of Massachusetts. Accessed September 19, 2019. https://scholarworks.umass.edu/theses/1012.

MLA Handbook (7th Edition):

Merchant, Murtaza. “Testing and Validation of a Prototype Gpgpu Design for FPGAs.” 2013. Web. 19 Sep 2019.

Vancouver:

Merchant M. Testing and Validation of a Prototype Gpgpu Design for FPGAs. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2019 Sep 19]. Available from: https://scholarworks.umass.edu/theses/1012.

Council of Science Editors:

Merchant M. Testing and Validation of a Prototype Gpgpu Design for FPGAs. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1012

16. zhang, xiangyu. ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS.

Degree: 2017, University of Massachusetts

  This study comprises two tasks. The first is to implement gate-level circuit camouflage techniques. The second is to implement the Oracle-guided incremental de-camouflage algorithm… (more)

Subjects/Keywords: Reverse engineer; Algorithm; Hardware; Camouflage; Digital Circuits; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

zhang, x. (2017). ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

zhang, xiangyu. “ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS.” 2017. Thesis, University of Massachusetts. Accessed September 19, 2019. https://scholarworks.umass.edu/masters_theses_2/551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

zhang, xiangyu. “ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS.” 2017. Web. 19 Sep 2019.

Vancouver:

zhang x. ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS. [Internet] [Thesis]. University of Massachusetts; 2017. [cited 2019 Sep 19]. Available from: https://scholarworks.umass.edu/masters_theses_2/551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

zhang x. ORACLE GUIDED INCREMENTAL SAT SOLVING TO REVERSE ENGINEER CAMOUFLAGED CIRCUITS. [Thesis]. University of Massachusetts; 2017. Available from: https://scholarworks.umass.edu/masters_theses_2/551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Colorado

17. Ismail, Ali Yasser. Cloud RTR: Cloud Infrastructure for Apps with Hardware.

Degree: MS, Electrical, Computer & Energy Engineering, 2015, University of Colorado

  There has been a great deal of innovation in the software space for smart phones, however, there has been virtually no room to innovate… (more)

Subjects/Keywords: mobware; field programmable gate array; mobile phone; software; hardware; software architecture; Computer and Systems Architecture; Hardware Systems; Systems Architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ismail, A. Y. (2015). Cloud RTR: Cloud Infrastructure for Apps with Hardware. (Masters Thesis). University of Colorado. Retrieved from https://scholar.colorado.edu/ecen_gradetds/109

Chicago Manual of Style (16th Edition):

Ismail, Ali Yasser. “Cloud RTR: Cloud Infrastructure for Apps with Hardware.” 2015. Masters Thesis, University of Colorado. Accessed September 19, 2019. https://scholar.colorado.edu/ecen_gradetds/109.

MLA Handbook (7th Edition):

Ismail, Ali Yasser. “Cloud RTR: Cloud Infrastructure for Apps with Hardware.” 2015. Web. 19 Sep 2019.

Vancouver:

Ismail AY. Cloud RTR: Cloud Infrastructure for Apps with Hardware. [Internet] [Masters thesis]. University of Colorado; 2015. [cited 2019 Sep 19]. Available from: https://scholar.colorado.edu/ecen_gradetds/109.

Council of Science Editors:

Ismail AY. Cloud RTR: Cloud Infrastructure for Apps with Hardware. [Masters Thesis]. University of Colorado; 2015. Available from: https://scholar.colorado.edu/ecen_gradetds/109


Virginia Tech

18. Farag, Mohammed Morsy Naeem. Architectural Enhancements to Increase Trust in Cyber-Physical Systems Containing Untrusted Software and Hardware.

Degree: PhD, Electrical and Computer Engineering, 2012, Virginia Tech

 Embedded electronics are widely employed in cyber-physical systems (CPSes), which tightly integrate and coordinate computational and physical elements. CPSes are extensively deployed in security-critical applications… (more)

Subjects/Keywords: Hardware Trojans; Reconfigurable Hardware; Embedded Systems Security; Cognitive Radio; Trusted Computing; Cyber-Physical Systems; Process Control Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Farag, M. M. N. (2012). Architectural Enhancements to Increase Trust in Cyber-Physical Systems Containing Untrusted Software and Hardware. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/29084

Chicago Manual of Style (16th Edition):

Farag, Mohammed Morsy Naeem. “Architectural Enhancements to Increase Trust in Cyber-Physical Systems Containing Untrusted Software and Hardware.” 2012. Doctoral Dissertation, Virginia Tech. Accessed September 19, 2019. http://hdl.handle.net/10919/29084.

MLA Handbook (7th Edition):

Farag, Mohammed Morsy Naeem. “Architectural Enhancements to Increase Trust in Cyber-Physical Systems Containing Untrusted Software and Hardware.” 2012. Web. 19 Sep 2019.

Vancouver:

Farag MMN. Architectural Enhancements to Increase Trust in Cyber-Physical Systems Containing Untrusted Software and Hardware. [Internet] [Doctoral dissertation]. Virginia Tech; 2012. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/10919/29084.

Council of Science Editors:

Farag MMN. Architectural Enhancements to Increase Trust in Cyber-Physical Systems Containing Untrusted Software and Hardware. [Doctoral Dissertation]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/29084

19. Gorman, Cory. Design of an Open-Source Sata Core for Virtex-4 FPGAs.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

  Many hard drives manufactured today use the Serial ATA (SATA) protocol to communicate with the host machine, typically a PC. SATA is a much… (more)

Subjects/Keywords: SATA; FPGA; Virtex-4; Hardware; Storage; High Speed Serial I/O; Data Storage Systems; Hardware Systems; Systems and Communications

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gorman, C. (2013). Design of an Open-Source Sata Core for Virtex-4 FPGAs. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1125

Chicago Manual of Style (16th Edition):

Gorman, Cory. “Design of an Open-Source Sata Core for Virtex-4 FPGAs.” 2013. Masters Thesis, University of Massachusetts. Accessed September 19, 2019. https://scholarworks.umass.edu/theses/1125.

MLA Handbook (7th Edition):

Gorman, Cory. “Design of an Open-Source Sata Core for Virtex-4 FPGAs.” 2013. Web. 19 Sep 2019.

Vancouver:

Gorman C. Design of an Open-Source Sata Core for Virtex-4 FPGAs. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2019 Sep 19]. Available from: https://scholarworks.umass.edu/theses/1125.

Council of Science Editors:

Gorman C. Design of an Open-Source Sata Core for Virtex-4 FPGAs. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1125


University of Waterloo

20. Hassan, Mohamed. Predictable Shared Memory Resources for Multi-Core Real-Time Systems.

Degree: 2017, University of Waterloo

 A major challenge in multi-core real-time systems is the interference problem on the shared hardware components amongst cores. Examples of these shared components include buses,… (more)

Subjects/Keywords: Real-time; Embedded Systems; Comptuer Hardware; Memory Systems; DRAM; Timing analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hassan, M. (2017). Predictable Shared Memory Resources for Multi-Core Real-Time Systems. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/11676

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hassan, Mohamed. “Predictable Shared Memory Resources for Multi-Core Real-Time Systems.” 2017. Thesis, University of Waterloo. Accessed September 19, 2019. http://hdl.handle.net/10012/11676.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hassan, Mohamed. “Predictable Shared Memory Resources for Multi-Core Real-Time Systems.” 2017. Web. 19 Sep 2019.

Vancouver:

Hassan M. Predictable Shared Memory Resources for Multi-Core Real-Time Systems. [Internet] [Thesis]. University of Waterloo; 2017. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/10012/11676.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hassan M. Predictable Shared Memory Resources for Multi-Core Real-Time Systems. [Thesis]. University of Waterloo; 2017. Available from: http://hdl.handle.net/10012/11676

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Liu, Xiaobin. ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY.

Degree: 2015, University of Massachusetts

  With the rapid growth in consumer electronics, people expect thin, smart and powerful devices, e.g. Google Glass and other wearable devices. However, as portable… (more)

Subjects/Keywords: CGRA; MRAM; time-scheduled interconnect; Computer and Systems Architecture; Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, X. (2015). ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Xiaobin. “ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY.” 2015. Thesis, University of Massachusetts. Accessed September 19, 2019. https://scholarworks.umass.edu/masters_theses_2/159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Xiaobin. “ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY.” 2015. Web. 19 Sep 2019.

Vancouver:

Liu X. ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY. [Internet] [Thesis]. University of Massachusetts; 2015. [cited 2019 Sep 19]. Available from: https://scholarworks.umass.edu/masters_theses_2/159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu X. ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY. [Thesis]. University of Massachusetts; 2015. Available from: https://scholarworks.umass.edu/masters_theses_2/159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

22. Vanguri, Phani Bharadwaj. An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm.

Degree: MS, Computer Engineering, 2010, University of Tennessee – Knoxville

 Mathematical and statistical modeling of biological systems is a desired goal for many years. Many biochemical models are often evaluated using a deterministic approach, which… (more)

Subjects/Keywords: stochastic; FPGA; vlsi; simulation; algorithm; hpc; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vanguri, P. B. (2010). An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/837

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vanguri, Phani Bharadwaj. “An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm.” 2010. Thesis, University of Tennessee – Knoxville. Accessed September 19, 2019. https://trace.tennessee.edu/utk_gradthes/837.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vanguri, Phani Bharadwaj. “An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm.” 2010. Web. 19 Sep 2019.

Vancouver:

Vanguri PB. An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm. [Internet] [Thesis]. University of Tennessee – Knoxville; 2010. [cited 2019 Sep 19]. Available from: https://trace.tennessee.edu/utk_gradthes/837.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vanguri PB. An FPGA Based Implementation of the Exact Stochastic Simulation Algorithm. [Thesis]. University of Tennessee – Knoxville; 2010. Available from: https://trace.tennessee.edu/utk_gradthes/837

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. Vyas, Shrikant S. Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems.

Degree: 2016, University of Massachusetts

  With the importance of data security at its peak today, many reconfigurable systems are used to provide security. This protection is often provided by… (more)

Subjects/Keywords: Physical Unclonable Functions; FPGAs; Error Correction; Variation Aware; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Vyas, S. S. (2016). Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/452

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vyas, Shrikant S. “Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems.” 2016. Thesis, University of Massachusetts. Accessed September 19, 2019. https://scholarworks.umass.edu/masters_theses_2/452.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vyas, Shrikant S. “Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems.” 2016. Web. 19 Sep 2019.

Vancouver:

Vyas SS. Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems. [Internet] [Thesis]. University of Massachusetts; 2016. [cited 2019 Sep 19]. Available from: https://scholarworks.umass.edu/masters_theses_2/452.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vyas SS. Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems. [Thesis]. University of Massachusetts; 2016. Available from: https://scholarworks.umass.edu/masters_theses_2/452

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Michigan Technological University

24. Liu, Lin. DESIGN AUTOMATION FOR CARBON NANOTUBE CIRCUITS CONSIDERING PERFORMANCE AND SECURITY OPTIMIZATION.

Degree: PhD, Department of Electrical and Computer Engineering, 2017, Michigan Technological University

  As prevailing copper interconnect technology advances to its fundamental physical limit, interconnect delay due to ever-increasing wire resistivity has greatly limited the circuit miniaturization.… (more)

Subjects/Keywords: Carbon Nanotubes; Timing Optimization; Buffer Insertion; Physical Unclonable Functions; Hardware Security; Machine Learning; Hardware Systems; Nanotechnology Fabrication; Other Computer Engineering; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, L. (2017). DESIGN AUTOMATION FOR CARBON NANOTUBE CIRCUITS CONSIDERING PERFORMANCE AND SECURITY OPTIMIZATION. (Doctoral Dissertation). Michigan Technological University. Retrieved from http://digitalcommons.mtu.edu/etdr/350

Chicago Manual of Style (16th Edition):

Liu, Lin. “DESIGN AUTOMATION FOR CARBON NANOTUBE CIRCUITS CONSIDERING PERFORMANCE AND SECURITY OPTIMIZATION.” 2017. Doctoral Dissertation, Michigan Technological University. Accessed September 19, 2019. http://digitalcommons.mtu.edu/etdr/350.

MLA Handbook (7th Edition):

Liu, Lin. “DESIGN AUTOMATION FOR CARBON NANOTUBE CIRCUITS CONSIDERING PERFORMANCE AND SECURITY OPTIMIZATION.” 2017. Web. 19 Sep 2019.

Vancouver:

Liu L. DESIGN AUTOMATION FOR CARBON NANOTUBE CIRCUITS CONSIDERING PERFORMANCE AND SECURITY OPTIMIZATION. [Internet] [Doctoral dissertation]. Michigan Technological University; 2017. [cited 2019 Sep 19]. Available from: http://digitalcommons.mtu.edu/etdr/350.

Council of Science Editors:

Liu L. DESIGN AUTOMATION FOR CARBON NANOTUBE CIRCUITS CONSIDERING PERFORMANCE AND SECURITY OPTIMIZATION. [Doctoral Dissertation]. Michigan Technological University; 2017. Available from: http://digitalcommons.mtu.edu/etdr/350

25. Cutitaru, Mihail T. IDPAL – A Partially-Adiabatic Energy-Efficient Logic Family: Theory and Applications to Secure Computing.

Degree: PhD, Electrical/Computer Engineering, 2014, Old Dominion University

  Low-power circuits and issues associated with them have gained a significant amount of attention in recent years due to the boom in portable electronic… (more)

Subjects/Keywords: Adiabatic circuits; Hardware security; IDPAL; Low-power circuits; Power analysis attacks; Computer Engineering; Hardware Systems; Power and Energy; Theory and Algorithms; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cutitaru, M. T. (2014). IDPAL – A Partially-Adiabatic Energy-Efficient Logic Family: Theory and Applications to Secure Computing. (Doctoral Dissertation). Old Dominion University. Retrieved from 9781321298994 ; https://digitalcommons.odu.edu/ece_etds/63

Chicago Manual of Style (16th Edition):

Cutitaru, Mihail T. “IDPAL – A Partially-Adiabatic Energy-Efficient Logic Family: Theory and Applications to Secure Computing.” 2014. Doctoral Dissertation, Old Dominion University. Accessed September 19, 2019. 9781321298994 ; https://digitalcommons.odu.edu/ece_etds/63.

MLA Handbook (7th Edition):

Cutitaru, Mihail T. “IDPAL – A Partially-Adiabatic Energy-Efficient Logic Family: Theory and Applications to Secure Computing.” 2014. Web. 19 Sep 2019.

Vancouver:

Cutitaru MT. IDPAL – A Partially-Adiabatic Energy-Efficient Logic Family: Theory and Applications to Secure Computing. [Internet] [Doctoral dissertation]. Old Dominion University; 2014. [cited 2019 Sep 19]. Available from: 9781321298994 ; https://digitalcommons.odu.edu/ece_etds/63.

Council of Science Editors:

Cutitaru MT. IDPAL – A Partially-Adiabatic Energy-Efficient Logic Family: Theory and Applications to Secure Computing. [Doctoral Dissertation]. Old Dominion University; 2014. Available from: 9781321298994 ; https://digitalcommons.odu.edu/ece_etds/63


University of California – San Diego

26. Bhaskaran, Meenakshi Sundaram. Micro-Architecture and Systems Support for Emerging Non-Volatile Memories.

Degree: Computer Science, 2016, University of California – San Diego

 Emerging non-volatile memory technologies such as phase-change memory, resistive random access memory, spin-torque transfer memory and 3D XPoint memory promise to significantly increase the I/O… (more)

Subjects/Keywords: Computer science; Hardware/Software Design; Microarchitecture; Non-Volatile Memory; Storage Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bhaskaran, M. S. (2016). Micro-Architecture and Systems Support for Emerging Non-Volatile Memories. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/07c1z320

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bhaskaran, Meenakshi Sundaram. “Micro-Architecture and Systems Support for Emerging Non-Volatile Memories.” 2016. Thesis, University of California – San Diego. Accessed September 19, 2019. http://www.escholarship.org/uc/item/07c1z320.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bhaskaran, Meenakshi Sundaram. “Micro-Architecture and Systems Support for Emerging Non-Volatile Memories.” 2016. Web. 19 Sep 2019.

Vancouver:

Bhaskaran MS. Micro-Architecture and Systems Support for Emerging Non-Volatile Memories. [Internet] [Thesis]. University of California – San Diego; 2016. [cited 2019 Sep 19]. Available from: http://www.escholarship.org/uc/item/07c1z320.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bhaskaran MS. Micro-Architecture and Systems Support for Emerging Non-Volatile Memories. [Thesis]. University of California – San Diego; 2016. Available from: http://www.escholarship.org/uc/item/07c1z320

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Edinburgh

27. Hudson, Stephen. A hardware implementation of a knowledge manipulation system for real time engineering applications.

Degree: 1990, University of Edinburgh

Subjects/Keywords: 621.39; Hardware for expert systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hudson, S. (1990). A hardware implementation of a knowledge manipulation system for real time engineering applications. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/14130

Chicago Manual of Style (16th Edition):

Hudson, Stephen. “A hardware implementation of a knowledge manipulation system for real time engineering applications.” 1990. Doctoral Dissertation, University of Edinburgh. Accessed September 19, 2019. http://hdl.handle.net/1842/14130.

MLA Handbook (7th Edition):

Hudson, Stephen. “A hardware implementation of a knowledge manipulation system for real time engineering applications.” 1990. Web. 19 Sep 2019.

Vancouver:

Hudson S. A hardware implementation of a knowledge manipulation system for real time engineering applications. [Internet] [Doctoral dissertation]. University of Edinburgh; 1990. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1842/14130.

Council of Science Editors:

Hudson S. A hardware implementation of a knowledge manipulation system for real time engineering applications. [Doctoral Dissertation]. University of Edinburgh; 1990. Available from: http://hdl.handle.net/1842/14130


University of Edinburgh

28. Traub, Niklas Gerard. A formal approach to hardware analysis.

Degree: 1986, University of Edinburgh

Subjects/Keywords: 621.39; Hardware systems implementation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Traub, N. G. (1986). A formal approach to hardware analysis. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/14570

Chicago Manual of Style (16th Edition):

Traub, Niklas Gerard. “A formal approach to hardware analysis.” 1986. Doctoral Dissertation, University of Edinburgh. Accessed September 19, 2019. http://hdl.handle.net/1842/14570.

MLA Handbook (7th Edition):

Traub, Niklas Gerard. “A formal approach to hardware analysis.” 1986. Web. 19 Sep 2019.

Vancouver:

Traub NG. A formal approach to hardware analysis. [Internet] [Doctoral dissertation]. University of Edinburgh; 1986. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1842/14570.

Council of Science Editors:

Traub NG. A formal approach to hardware analysis. [Doctoral Dissertation]. University of Edinburgh; 1986. Available from: http://hdl.handle.net/1842/14570


Michigan Technological University

29. Beyers, Nathan. Simulation of Scalability for Autonomous Mobile Microgrids.

Degree: MS, Department of Mechanical Engineering-Engineering Mechanics, 2016, Michigan Technological University

  Microgrids are small-scale, decentralized systems for generation, storage, and management of electricity to provide power within a local area. By establishing these microgrids using… (more)

Subjects/Keywords: Autonomous; Microgrid; Robotics; Navigation; Simulation; Hardware; Electro-Mechanical Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Beyers, N. (2016). Simulation of Scalability for Autonomous Mobile Microgrids. (Masters Thesis). Michigan Technological University. Retrieved from http://digitalcommons.mtu.edu/etdr/124

Chicago Manual of Style (16th Edition):

Beyers, Nathan. “Simulation of Scalability for Autonomous Mobile Microgrids.” 2016. Masters Thesis, Michigan Technological University. Accessed September 19, 2019. http://digitalcommons.mtu.edu/etdr/124.

MLA Handbook (7th Edition):

Beyers, Nathan. “Simulation of Scalability for Autonomous Mobile Microgrids.” 2016. Web. 19 Sep 2019.

Vancouver:

Beyers N. Simulation of Scalability for Autonomous Mobile Microgrids. [Internet] [Masters thesis]. Michigan Technological University; 2016. [cited 2019 Sep 19]. Available from: http://digitalcommons.mtu.edu/etdr/124.

Council of Science Editors:

Beyers N. Simulation of Scalability for Autonomous Mobile Microgrids. [Masters Thesis]. Michigan Technological University; 2016. Available from: http://digitalcommons.mtu.edu/etdr/124


Penn State University

30. Cotter, Matthew Joseph. Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline.

Degree: PhD, Computer Science and Engineering, 2015, Penn State University

 The machine vision community has expended tremendous effort in the research and development of algorithms in an effort to develop a system that is capable… (more)

Subjects/Keywords: Configurable Systems; Vision Algorithms; Intelligent Vision; Hardware Accelerators

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cotter, M. J. (2015). Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/24792

Chicago Manual of Style (16th Edition):

Cotter, Matthew Joseph. “Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline.” 2015. Doctoral Dissertation, Penn State University. Accessed September 19, 2019. https://etda.libraries.psu.edu/catalog/24792.

MLA Handbook (7th Edition):

Cotter, Matthew Joseph. “Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline.” 2015. Web. 19 Sep 2019.

Vancouver:

Cotter MJ. Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline. [Internet] [Doctoral dissertation]. Penn State University; 2015. [cited 2019 Sep 19]. Available from: https://etda.libraries.psu.edu/catalog/24792.

Council of Science Editors:

Cotter MJ. Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline. [Doctoral Dissertation]. Penn State University; 2015. Available from: https://etda.libraries.psu.edu/catalog/24792

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