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Dept: Electrical Engineering

You searched for subject:(HOUSING DESIGN ARCHITECTURE ). Showing records 1 – 30 of 488 total matches.

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1. Patel, Rakesh B. Design and comparative analysis of mac architecture using soft computational paradigms; -.

Degree: Electrical Engineering, 2013, Maharaja Sayajirao University of Baroda

Abstract avalible

Bibliography p.122 - 134 and Appendix p.135 - 153

Advisors/Committee Members: Shah, Satish K.

Subjects/Keywords: architecture; comparative; Design

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APA (6th Edition):

Patel, R. B. (2013). Design and comparative analysis of mac architecture using soft computational paradigms; -. (Thesis). Maharaja Sayajirao University of Baroda. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/36695

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Patel, Rakesh B. “Design and comparative analysis of mac architecture using soft computational paradigms; -.” 2013. Thesis, Maharaja Sayajirao University of Baroda. Accessed October 18, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/36695.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Patel, Rakesh B. “Design and comparative analysis of mac architecture using soft computational paradigms; -.” 2013. Web. 18 Oct 2019.

Vancouver:

Patel RB. Design and comparative analysis of mac architecture using soft computational paradigms; -. [Internet] [Thesis]. Maharaja Sayajirao University of Baroda; 2013. [cited 2019 Oct 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/36695.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Patel RB. Design and comparative analysis of mac architecture using soft computational paradigms; -. [Thesis]. Maharaja Sayajirao University of Baroda; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/36695

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

2. Sharma, Vyoma. Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  Arithmetic Square Root is one of the most complex but nevertheless widely used operations in modern computing. A primary reason for the complexity is… (more)

Subjects/Keywords: Logic design; Circuits; Design methodology; Hardware description languages; Computer architecture; Calculators

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APA (6th Edition):

Sharma, V. (2017). Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9703

Chicago Manual of Style (16th Edition):

Sharma, Vyoma. “Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed October 18, 2019. https://scholarworks.rit.edu/theses/9703.

MLA Handbook (7th Edition):

Sharma, Vyoma. “Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm.” 2017. Web. 18 Oct 2019.

Vancouver:

Sharma V. Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2019 Oct 18]. Available from: https://scholarworks.rit.edu/theses/9703.

Council of Science Editors:

Sharma V. Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9703


NSYSU

3. Wu, Cheng-tao. Software Implementation of a Configurable Design of Control Units of Pipeline Processors.

Degree: Master, Electrical Engineering, 2014, NSYSU

 CPU(Central Processing Unit) is one of the important parts in an electric computer. Controller definitely plays an important role in the CPU. Different processor architectures… (more)

Subjects/Keywords: Verilog; computer aided design; architecture description language; controller; pipeline processor

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APA (6th Edition):

Wu, C. (2014). Software Implementation of a Configurable Design of Control Units of Pipeline Processors. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Cheng-tao. “Software Implementation of a Configurable Design of Control Units of Pipeline Processors.” 2014. Thesis, NSYSU. Accessed October 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Cheng-tao. “Software Implementation of a Configurable Design of Control Units of Pipeline Processors.” 2014. Web. 18 Oct 2019.

Vancouver:

Wu C. Software Implementation of a Configurable Design of Control Units of Pipeline Processors. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Oct 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. Software Implementation of a Configurable Design of Control Units of Pipeline Processors. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0114114-151336

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

4. Zheng, Nan. Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing.

Degree: PhD, Electrical Engineering, 2017, University of Michigan

 The development of computing systems based on the conventional von Neumann architecture has slowed down in the past decade as complementary metal-oxide-semiconductor (CMOS) technology scaling… (more)

Subjects/Keywords: Neuromorphic computing; Neural network; Machine learning; Low-power circuit; Hardware architecture; Algorithm-architecture co-design; Computer Science; Electrical Engineering; Engineering; Science

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APA (6th Edition):

Zheng, N. (2017). Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/144149

Chicago Manual of Style (16th Edition):

Zheng, Nan. “Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing.” 2017. Doctoral Dissertation, University of Michigan. Accessed October 18, 2019. http://hdl.handle.net/2027.42/144149.

MLA Handbook (7th Edition):

Zheng, Nan. “Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing.” 2017. Web. 18 Oct 2019.

Vancouver:

Zheng N. Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/2027.42/144149.

Council of Science Editors:

Zheng N. Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/144149


UCLA

5. Ren, Fengbo. A Scalable VLSI Architecture for Real-Time and Energy-Ecient Sparse Approximation in Compressive Sensing Systems.

Degree: Electrical Engineering, 2014, UCLA

 Digital electronic industry today relies on Nyquist sampling theorem, which requires to double the size (sampling rate) of the signal representation on the Fourier basis… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; Compressive Sensing; Energy-Efficient Design; Integrated Circuit; Sparse Approximation; VLSI Architecture; Wireless Health

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APA (6th Edition):

Ren, F. (2014). A Scalable VLSI Architecture for Real-Time and Energy-Ecient Sparse Approximation in Compressive Sensing Systems. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/73p6w2zv

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ren, Fengbo. “A Scalable VLSI Architecture for Real-Time and Energy-Ecient Sparse Approximation in Compressive Sensing Systems.” 2014. Thesis, UCLA. Accessed October 18, 2019. http://www.escholarship.org/uc/item/73p6w2zv.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ren, Fengbo. “A Scalable VLSI Architecture for Real-Time and Energy-Ecient Sparse Approximation in Compressive Sensing Systems.” 2014. Web. 18 Oct 2019.

Vancouver:

Ren F. A Scalable VLSI Architecture for Real-Time and Energy-Ecient Sparse Approximation in Compressive Sensing Systems. [Internet] [Thesis]. UCLA; 2014. [cited 2019 Oct 18]. Available from: http://www.escholarship.org/uc/item/73p6w2zv.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ren F. A Scalable VLSI Architecture for Real-Time and Energy-Ecient Sparse Approximation in Compressive Sensing Systems. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/73p6w2zv

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


The Ohio State University

6. Fisher, John Sheridan. Application of model driven architecture design methodologies to mixed-signal system design projects.

Degree: PhD, Electrical Engineering, 2006, The Ohio State University

 Mixed-signal system design is a complex task with many levels of deliverables, including layout, schematics, simulation results, functional models, design specifications, and process design kits.… (more)

Subjects/Keywords: model driven architecture; mixed-signal design methodologies; mixed-signal verification; process design kit development; design reuse; library development

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APA (6th Edition):

Fisher, J. S. (2006). Application of model driven architecture design methodologies to mixed-signal system design projects. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1143218375

Chicago Manual of Style (16th Edition):

Fisher, John Sheridan. “Application of model driven architecture design methodologies to mixed-signal system design projects.” 2006. Doctoral Dissertation, The Ohio State University. Accessed October 18, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1143218375.

MLA Handbook (7th Edition):

Fisher, John Sheridan. “Application of model driven architecture design methodologies to mixed-signal system design projects.” 2006. Web. 18 Oct 2019.

Vancouver:

Fisher JS. Application of model driven architecture design methodologies to mixed-signal system design projects. [Internet] [Doctoral dissertation]. The Ohio State University; 2006. [cited 2019 Oct 18]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1143218375.

Council of Science Editors:

Fisher JS. Application of model driven architecture design methodologies to mixed-signal system design projects. [Doctoral Dissertation]. The Ohio State University; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1143218375

7. Park, Yongjun. Libra: Achieving Efficient Instruction- and Data- Parallel Execution for Mobile Applications.

Degree: PhD, Electrical Engineering, 2013, University of Michigan

 Mobile computing as exemplified by the smart phone has become an integral part of our daily lives. The next generation of these devices will be… (more)

Subjects/Keywords: Compiler; SIMD Architecture; Energy Efficient Design; Electrical Engineering; Engineering

…6.2.2 Baseline Architecture . . . . . . . . . . . . . . . . . . . . 6.2.3 Limitations for… …6.3 Libra Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Overview… …vectorization at different granularities. . . . . . . . . . 2.3 Baseline SIMD architecture… …Energy comparison for the SGLP on the 32-wide SIMD architecture and ILP on the 4 way 8-wide… …VLIW architecture. . . . . . . . . . . . . . . . Overview of a 4x4 CGRA… 

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APA (6th Edition):

Park, Y. (2013). Libra: Achieving Efficient Instruction- and Data- Parallel Execution for Mobile Applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/99840

Chicago Manual of Style (16th Edition):

Park, Yongjun. “Libra: Achieving Efficient Instruction- and Data- Parallel Execution for Mobile Applications.” 2013. Doctoral Dissertation, University of Michigan. Accessed October 18, 2019. http://hdl.handle.net/2027.42/99840.

MLA Handbook (7th Edition):

Park, Yongjun. “Libra: Achieving Efficient Instruction- and Data- Parallel Execution for Mobile Applications.” 2013. Web. 18 Oct 2019.

Vancouver:

Park Y. Libra: Achieving Efficient Instruction- and Data- Parallel Execution for Mobile Applications. [Internet] [Doctoral dissertation]. University of Michigan; 2013. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/2027.42/99840.

Council of Science Editors:

Park Y. Libra: Achieving Efficient Instruction- and Data- Parallel Execution for Mobile Applications. [Doctoral Dissertation]. University of Michigan; 2013. Available from: http://hdl.handle.net/2027.42/99840


Cal Poly

8. Lee, Chris Y. Full Custom VLSI Design of On-Line Stability Checkers.

Degree: MS, Electrical Engineering, 2011, Cal Poly

  A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital… (more)

Subjects/Keywords: ASIC; logic design; digital simulation; error analysis; sequential logic circuit fault testing; Computer and Systems Architecture; Digital Circuits; Electronic Devices and Semiconductor Manufacturing; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Lee, C. Y. (2011). Full Custom VLSI Design of On-Line Stability Checkers. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/607 ; 10.15368/theses.2011.165

Chicago Manual of Style (16th Edition):

Lee, Chris Y. “Full Custom VLSI Design of On-Line Stability Checkers.” 2011. Masters Thesis, Cal Poly. Accessed October 18, 2019. https://digitalcommons.calpoly.edu/theses/607 ; 10.15368/theses.2011.165.

MLA Handbook (7th Edition):

Lee, Chris Y. “Full Custom VLSI Design of On-Line Stability Checkers.” 2011. Web. 18 Oct 2019.

Vancouver:

Lee CY. Full Custom VLSI Design of On-Line Stability Checkers. [Internet] [Masters thesis]. Cal Poly; 2011. [cited 2019 Oct 18]. Available from: https://digitalcommons.calpoly.edu/theses/607 ; 10.15368/theses.2011.165.

Council of Science Editors:

Lee CY. Full Custom VLSI Design of On-Line Stability Checkers. [Masters Thesis]. Cal Poly; 2011. Available from: https://digitalcommons.calpoly.edu/theses/607 ; 10.15368/theses.2011.165


University of Michigan

9. Li, Ziyun. Energy-Efficient, Mobile Computer Vision and Machine Learning Processors.

Degree: PhD, Electrical Engineering, 2019, University of Michigan

 Technology scaling has driven computing devices to be faster, cheaper, and smaller while consuming less power in past decades. However, as technology scaling has become… (more)

Subjects/Keywords: Machine Learning Processor; SLAM & Autonomous Navigation; High-performance, Low-power VLSI; Real-time Machine Vision; Algorithm, Software and Hardware Co-design; Digital Architecture and System; Electrical Engineering; Engineering

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APA (6th Edition):

Li, Z. (2019). Energy-Efficient, Mobile Computer Vision and Machine Learning Processors. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/151423

Chicago Manual of Style (16th Edition):

Li, Ziyun. “Energy-Efficient, Mobile Computer Vision and Machine Learning Processors.” 2019. Doctoral Dissertation, University of Michigan. Accessed October 18, 2019. http://hdl.handle.net/2027.42/151423.

MLA Handbook (7th Edition):

Li, Ziyun. “Energy-Efficient, Mobile Computer Vision and Machine Learning Processors.” 2019. Web. 18 Oct 2019.

Vancouver:

Li Z. Energy-Efficient, Mobile Computer Vision and Machine Learning Processors. [Internet] [Doctoral dissertation]. University of Michigan; 2019. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/2027.42/151423.

Council of Science Editors:

Li Z. Energy-Efficient, Mobile Computer Vision and Machine Learning Processors. [Doctoral Dissertation]. University of Michigan; 2019. Available from: http://hdl.handle.net/2027.42/151423


Linköping University

10. Boivie, Victor. Network Processor specific Multithreading tradeoffs.

Degree: Electrical Engineering, 2005, Linköping University

  Multithreading is a processor technique that can effectively hide long latencies that can occur due to memory accesses, coprocessor operations and similar. While this… (more)

Subjects/Keywords: Datorteknik; multithreading; network processors; computer architecture; system level design exploration; Datorteknik; Computer Engineering; Datorteknik

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APA (6th Edition):

Boivie, V. (2005). Network Processor specific Multithreading tradeoffs. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2940

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Boivie, Victor. “Network Processor specific Multithreading tradeoffs.” 2005. Thesis, Linköping University. Accessed October 18, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2940.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Boivie, Victor. “Network Processor specific Multithreading tradeoffs.” 2005. Web. 18 Oct 2019.

Vancouver:

Boivie V. Network Processor specific Multithreading tradeoffs. [Internet] [Thesis]. Linköping University; 2005. [cited 2019 Oct 18]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2940.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Boivie V. Network Processor specific Multithreading tradeoffs. [Thesis]. Linköping University; 2005. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2940

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Radivojević Zaharije. Methodology for designing simulators of computer architecture and organization.

Degree: PhD, Electrical Engineering, 2012, University of Belgrade

 This paper presents methodological approach to the computer architecture and organization simulator design. The methodological approach should help students to bridge the gap between theory… (more)

Subjects/Keywords: Simulator design; Computer architecture and organization; Concurrent programming; Distributed programming; General purpose discrete event simulator; Analytical model; Projektovanje simulatora; Arhitektura i organizacija računara; Konkurentno programiranje; Distribuirano programiranje; Simulatori diskretnih događaja opšte namene; Analitički model

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APA (6th Edition):

Zaharije, R. (2012). Methodology for designing simulators of computer architecture and organization. (Doctoral Dissertation). University of Belgrade. Retrieved from http://dx.doi.org/10.2298/BG20120604RADIVOJEVIC ; http://eteze.bg.ac.rs/application/showtheses?thesesId=232 ; https://fedorabg.bg.ac.rs/fedora/get/o:5498/bdef:Content/get ; http://vbs.rs/scripts/cobiss?command=SEARCH&base=99999&select=ID=43466255

Chicago Manual of Style (16th Edition):

Zaharije, Radivojević. “Methodology for designing simulators of computer architecture and organization.” 2012. Doctoral Dissertation, University of Belgrade. Accessed October 18, 2019. http://dx.doi.org/10.2298/BG20120604RADIVOJEVIC ; http://eteze.bg.ac.rs/application/showtheses?thesesId=232 ; https://fedorabg.bg.ac.rs/fedora/get/o:5498/bdef:Content/get ; http://vbs.rs/scripts/cobiss?command=SEARCH&base=99999&select=ID=43466255.

MLA Handbook (7th Edition):

Zaharije, Radivojević. “Methodology for designing simulators of computer architecture and organization.” 2012. Web. 18 Oct 2019.

Vancouver:

Zaharije R. Methodology for designing simulators of computer architecture and organization. [Internet] [Doctoral dissertation]. University of Belgrade; 2012. [cited 2019 Oct 18]. Available from: http://dx.doi.org/10.2298/BG20120604RADIVOJEVIC ; http://eteze.bg.ac.rs/application/showtheses?thesesId=232 ; https://fedorabg.bg.ac.rs/fedora/get/o:5498/bdef:Content/get ; http://vbs.rs/scripts/cobiss?command=SEARCH&base=99999&select=ID=43466255.

Council of Science Editors:

Zaharije R. Methodology for designing simulators of computer architecture and organization. [Doctoral Dissertation]. University of Belgrade; 2012. Available from: http://dx.doi.org/10.2298/BG20120604RADIVOJEVIC ; http://eteze.bg.ac.rs/application/showtheses?thesesId=232 ; https://fedorabg.bg.ac.rs/fedora/get/o:5498/bdef:Content/get ; http://vbs.rs/scripts/cobiss?command=SEARCH&base=99999&select=ID=43466255


Linköping University

12. Alfredsson, Jon. Design of a parallel A/D converter system on PCB : For high-speed sampling and timing error correction.

Degree: Electrical Engineering, 2002, Linköping University

  The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master… (more)

Subjects/Keywords: Electronics; Analog-to-digital converter; ADC; A/D; sampling system; high speed; timing error; estimation algorithm; time interleaving; parallel architecture; PCB design; conveter; undersampling; Elektronik; Electronics; Elektronik

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APA (6th Edition):

Alfredsson, J. (2002). Design of a parallel A/D converter system on PCB : For high-speed sampling and timing error correction. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1201

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alfredsson, Jon. “Design of a parallel A/D converter system on PCB : For high-speed sampling and timing error correction.” 2002. Thesis, Linköping University. Accessed October 18, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1201.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alfredsson, Jon. “Design of a parallel A/D converter system on PCB : For high-speed sampling and timing error correction.” 2002. Web. 18 Oct 2019.

Vancouver:

Alfredsson J. Design of a parallel A/D converter system on PCB : For high-speed sampling and timing error correction. [Internet] [Thesis]. Linköping University; 2002. [cited 2019 Oct 18]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1201.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alfredsson J. Design of a parallel A/D converter system on PCB : For high-speed sampling and timing error correction. [Thesis]. Linköping University; 2002. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1201

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Lowell, Nicholas Stephen. Model-based Software Design Tools for the Cell Processor.

Degree: MS, Electrical Engineering, 2009, Vanderbilt University

 This thesis presents a multi-core architecture, the Cell processor, and an updated model-based tool suite named the Signal Processing Platform (SPP) that supports development of… (more)

Subjects/Keywords: domain specific modeling language; automatic target recognition; model-based design; multi-core architecture; dataflow modeling; code generation; cell processor

Design of mult_difft_calc_mean_psr_core ............................................... 41 23… …the language. I have adopted the Cell Broadband Engine Architecture (or, Cell)—the… …multi-core architecture resulting from the collaborative efforts of IBM, Sony, and Toshiba—and… …the Cell architecture. Chapter four introduces the SPP tool chain—the modeling language… …cores. The architecture may require the cores to share as much as cache, memory, and busses… 

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APA (6th Edition):

Lowell, N. S. (2009). Model-based Software Design Tools for the Cell Processor. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-03302009-113308/ ;

Chicago Manual of Style (16th Edition):

Lowell, Nicholas Stephen. “Model-based Software Design Tools for the Cell Processor.” 2009. Masters Thesis, Vanderbilt University. Accessed October 18, 2019. http://etd.library.vanderbilt.edu//available/etd-03302009-113308/ ;.

MLA Handbook (7th Edition):

Lowell, Nicholas Stephen. “Model-based Software Design Tools for the Cell Processor.” 2009. Web. 18 Oct 2019.

Vancouver:

Lowell NS. Model-based Software Design Tools for the Cell Processor. [Internet] [Masters thesis]. Vanderbilt University; 2009. [cited 2019 Oct 18]. Available from: http://etd.library.vanderbilt.edu//available/etd-03302009-113308/ ;.

Council of Science Editors:

Lowell NS. Model-based Software Design Tools for the Cell Processor. [Masters Thesis]. Vanderbilt University; 2009. Available from: http://etd.library.vanderbilt.edu//available/etd-03302009-113308/ ;


UCLA

14. Zhou, Peipei. A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture).

Degree: Electrical Engineering, 2014, UCLA

 Future processor will not be limited by the transistor resources, but will be mainly constrained by energy efficiency. Reconfigurable architecture offers higher energy efficiency than… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; Computer science; CGRA; composable architecture; computer architecture; full pipeline; reconfigurable architecture

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APA (6th Edition):

Zhou, P. (2014). A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture). (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9446s3nx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhou, Peipei. “A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture).” 2014. Thesis, UCLA. Accessed October 18, 2019. http://www.escholarship.org/uc/item/9446s3nx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhou, Peipei. “A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture).” 2014. Web. 18 Oct 2019.

Vancouver:

Zhou P. A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture). [Internet] [Thesis]. UCLA; 2014. [cited 2019 Oct 18]. Available from: http://www.escholarship.org/uc/item/9446s3nx.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhou P. A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture). [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/9446s3nx

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Pashupathy Manjula Devi, Namratha. Configurable Verification of RISC Processors.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  The Verification methodology of modern processor designs is an enormous challenge. As processor design complexity increases, an elaborate and sophisticated verification environment has to… (more)

Subjects/Keywords: RISC; Processor; RISC processor verification; Harvard architecture; von Neumann architecture; SystemVerilog; Micro-architecture; Instruction Set Architecture

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APA (6th Edition):

Pashupathy Manjula Devi, N. (2017). Configurable Verification of RISC Processors. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9420

Chicago Manual of Style (16th Edition):

Pashupathy Manjula Devi, Namratha. “Configurable Verification of RISC Processors.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed October 18, 2019. https://scholarworks.rit.edu/theses/9420.

MLA Handbook (7th Edition):

Pashupathy Manjula Devi, Namratha. “Configurable Verification of RISC Processors.” 2017. Web. 18 Oct 2019.

Vancouver:

Pashupathy Manjula Devi N. Configurable Verification of RISC Processors. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2019 Oct 18]. Available from: https://scholarworks.rit.edu/theses/9420.

Council of Science Editors:

Pashupathy Manjula Devi N. Configurable Verification of RISC Processors. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9420


Rochester Institute of Technology

16. Lima, Thiago Pinheiro Felix da Silva e. Reconfigurable Model for RISC Processors.

Degree: MS, Electrical Engineering, 2016, Rochester Institute of Technology

  The instruction set of a processor is embodied in the particular micro-architecture representing the processor hardware. Verifying proper operation of the instruction set for… (more)

Subjects/Keywords: RISC; Processor; SystemC; SystemVerilog; Micro-architecture; Instruction Set Architecture​

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lima, T. P. F. d. S. e. (2016). Reconfigurable Model for RISC Processors. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9326

Chicago Manual of Style (16th Edition):

Lima, Thiago Pinheiro Felix da Silva e. “Reconfigurable Model for RISC Processors.” 2016. Masters Thesis, Rochester Institute of Technology. Accessed October 18, 2019. https://scholarworks.rit.edu/theses/9326.

MLA Handbook (7th Edition):

Lima, Thiago Pinheiro Felix da Silva e. “Reconfigurable Model for RISC Processors.” 2016. Web. 18 Oct 2019.

Vancouver:

Lima TPFdSe. Reconfigurable Model for RISC Processors. [Internet] [Masters thesis]. Rochester Institute of Technology; 2016. [cited 2019 Oct 18]. Available from: https://scholarworks.rit.edu/theses/9326.

Council of Science Editors:

Lima TPFdSe. Reconfigurable Model for RISC Processors. [Masters Thesis]. Rochester Institute of Technology; 2016. Available from: https://scholarworks.rit.edu/theses/9326


NSYSU

17. Wu, Chien-chan. Software Implementation of a Configurable Design of Interconnection Routers.

Degree: Master, Electrical Engineering, 2013, NSYSU

 In the development process of hardware system designs, effective design integration and design reuse can reduce system development time. Our previous research on configurable design(more)

Subjects/Keywords: system design; configurable design; router; automatic generation

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APA (6th Edition):

Wu, C. (2013). Software Implementation of a Configurable Design of Interconnection Routers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622113-175410

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Chien-chan. “Software Implementation of a Configurable Design of Interconnection Routers.” 2013. Thesis, NSYSU. Accessed October 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622113-175410.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Chien-chan. “Software Implementation of a Configurable Design of Interconnection Routers.” 2013. Web. 18 Oct 2019.

Vancouver:

Wu C. Software Implementation of a Configurable Design of Interconnection Routers. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Oct 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622113-175410.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. Software Implementation of a Configurable Design of Interconnection Routers. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622113-175410

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Cal Poly

18. Lin, Yu-wei. Benchmarked Hard Disk Drive Performance Characterization and Optimization Based on Design of Experiments Techniques.

Degree: MS, Electrical Engineering, 2010, Cal Poly

 This paper describes an experimental study offered by Designs of Experiments (DOE) within the defined factor domains to evaluate the factor effects of simultaneous characteristics… (more)

Subjects/Keywords: design of experiments

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, Y. (2010). Benchmarked Hard Disk Drive Performance Characterization and Optimization Based on Design of Experiments Techniques. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/350 ; 10.15368/theses.2010.116

Chicago Manual of Style (16th Edition):

Lin, Yu-wei. “Benchmarked Hard Disk Drive Performance Characterization and Optimization Based on Design of Experiments Techniques.” 2010. Masters Thesis, Cal Poly. Accessed October 18, 2019. https://digitalcommons.calpoly.edu/theses/350 ; 10.15368/theses.2010.116.

MLA Handbook (7th Edition):

Lin, Yu-wei. “Benchmarked Hard Disk Drive Performance Characterization and Optimization Based on Design of Experiments Techniques.” 2010. Web. 18 Oct 2019.

Vancouver:

Lin Y. Benchmarked Hard Disk Drive Performance Characterization and Optimization Based on Design of Experiments Techniques. [Internet] [Masters thesis]. Cal Poly; 2010. [cited 2019 Oct 18]. Available from: https://digitalcommons.calpoly.edu/theses/350 ; 10.15368/theses.2010.116.

Council of Science Editors:

Lin Y. Benchmarked Hard Disk Drive Performance Characterization and Optimization Based on Design of Experiments Techniques. [Masters Thesis]. Cal Poly; 2010. Available from: https://digitalcommons.calpoly.edu/theses/350 ; 10.15368/theses.2010.116


University of Tennessee – Knoxville

19. Li, Jie. Wireless Power System Design for Maximum Efficiency.

Degree: MS, Electrical Engineering, 2018, University of Tennessee – Knoxville

 With the potential of cutting the last cord, wireless power transfer (WPT) using magnetic resonant coupling is gaining increasing popularity. Evolved from the inductive WPT… (more)

Subjects/Keywords: wireless power transfer; coil design; converter design; system design

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APA (6th Edition):

Li, J. (2018). Wireless Power System Design for Maximum Efficiency. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/5110

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Jie. “Wireless Power System Design for Maximum Efficiency.” 2018. Thesis, University of Tennessee – Knoxville. Accessed October 18, 2019. https://trace.tennessee.edu/utk_gradthes/5110.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Jie. “Wireless Power System Design for Maximum Efficiency.” 2018. Web. 18 Oct 2019.

Vancouver:

Li J. Wireless Power System Design for Maximum Efficiency. [Internet] [Thesis]. University of Tennessee – Knoxville; 2018. [cited 2019 Oct 18]. Available from: https://trace.tennessee.edu/utk_gradthes/5110.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li J. Wireless Power System Design for Maximum Efficiency. [Thesis]. University of Tennessee – Knoxville; 2018. Available from: https://trace.tennessee.edu/utk_gradthes/5110

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. Thibodeaux, Ryan. The Specification and Implementation of a Model of Computation.

Degree: MS, Electrical Engineering, 2008, Vanderbilt University

 Separating a complex software system into individual components with well-defined interfaces is a common practice in software engineering intended to simplify reasoning about the system.… (more)

Subjects/Keywords: Model-Driven Development; Models of Computation; Time-Triggered Systems; Platform Modeling; Model-driven software architecture; Embedded computer systems  – Design and construction

…bus . . . . 19 8. System architecture of a single node… …Triggered Architecture TTP Time-Triggered Protocol VM Virtual Machine viii CHAPTER I… …computational model of software only complicates the design process for embedded systems. Consequently… …some of the design challenges. Ultimately, any approach intended to design, model, and… …design of software systems, partitioning a functional software specification into distinct… 

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APA (6th Edition):

Thibodeaux, R. (2008). The Specification and Implementation of a Model of Computation. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-02142008-101147/ ;

Chicago Manual of Style (16th Edition):

Thibodeaux, Ryan. “The Specification and Implementation of a Model of Computation.” 2008. Masters Thesis, Vanderbilt University. Accessed October 18, 2019. http://etd.library.vanderbilt.edu/available/etd-02142008-101147/ ;.

MLA Handbook (7th Edition):

Thibodeaux, Ryan. “The Specification and Implementation of a Model of Computation.” 2008. Web. 18 Oct 2019.

Vancouver:

Thibodeaux R. The Specification and Implementation of a Model of Computation. [Internet] [Masters thesis]. Vanderbilt University; 2008. [cited 2019 Oct 18]. Available from: http://etd.library.vanderbilt.edu/available/etd-02142008-101147/ ;.

Council of Science Editors:

Thibodeaux R. The Specification and Implementation of a Model of Computation. [Masters Thesis]. Vanderbilt University; 2008. Available from: http://etd.library.vanderbilt.edu/available/etd-02142008-101147/ ;


NSYSU

21. Luo, Ming. Software Design of an Architecture Description Language Simulator.

Degree: Master, Electrical Engineering, 2011, NSYSU

 In system-on-chips, system architecture designs greatly affect cost, performance, and power consumption of the systems. In system design time, we thus need to perform system… (more)

Subjects/Keywords: Architecture Description Language; simulator; parser; decoder; interpreter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Luo, M. (2011). Software Design of an Architecture Description Language Simulator. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0221111-162645

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Luo, Ming. “Software Design of an Architecture Description Language Simulator.” 2011. Thesis, NSYSU. Accessed October 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0221111-162645.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Luo, Ming. “Software Design of an Architecture Description Language Simulator.” 2011. Web. 18 Oct 2019.

Vancouver:

Luo M. Software Design of an Architecture Description Language Simulator. [Internet] [Thesis]. NSYSU; 2011. [cited 2019 Oct 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0221111-162645.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Luo M. Software Design of an Architecture Description Language Simulator. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0221111-162645

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

22. Kim, Sangmin. Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes.

Degree: PhD, Electrical Engineering, 2010, University of Minnesota

 This thesis proposes efficient algorithm and architecture aspects for binary and nonbinary low- density parity-check (LDPC) codes by developing optimal quantization approaches, decoding algorithms, decoding… (more)

Subjects/Keywords: Architecture; Decoding; LDPC; VLSI; Electrical Engineering

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APA (6th Edition):

Kim, S. (2010). Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/96825

Chicago Manual of Style (16th Edition):

Kim, Sangmin. “Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes.” 2010. Doctoral Dissertation, University of Minnesota. Accessed October 18, 2019. http://purl.umn.edu/96825.

MLA Handbook (7th Edition):

Kim, Sangmin. “Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes.” 2010. Web. 18 Oct 2019.

Vancouver:

Kim S. Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes. [Internet] [Doctoral dissertation]. University of Minnesota; 2010. [cited 2019 Oct 18]. Available from: http://purl.umn.edu/96825.

Council of Science Editors:

Kim S. Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes. [Doctoral Dissertation]. University of Minnesota; 2010. Available from: http://purl.umn.edu/96825


University of Connecticut

23. Ahmad, Masab. Understanding Concurrency for Graph Workloads in Large Scale Multicores.

Degree: MS, Electrical Engineering, 2016, University of Connecticut

  Algorithms operating on a graph setting are known to be highly irregular and un- structured. This leads to workload imbalance and data locality challenge… (more)

Subjects/Keywords: Computer Architecture; Graph Algorithms; Workload Characterization

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APA (6th Edition):

Ahmad, M. (2016). Understanding Concurrency for Graph Workloads in Large Scale Multicores. (Masters Thesis). University of Connecticut. Retrieved from https://opencommons.uconn.edu/gs_theses/1018

Chicago Manual of Style (16th Edition):

Ahmad, Masab. “Understanding Concurrency for Graph Workloads in Large Scale Multicores.” 2016. Masters Thesis, University of Connecticut. Accessed October 18, 2019. https://opencommons.uconn.edu/gs_theses/1018.

MLA Handbook (7th Edition):

Ahmad, Masab. “Understanding Concurrency for Graph Workloads in Large Scale Multicores.” 2016. Web. 18 Oct 2019.

Vancouver:

Ahmad M. Understanding Concurrency for Graph Workloads in Large Scale Multicores. [Internet] [Masters thesis]. University of Connecticut; 2016. [cited 2019 Oct 18]. Available from: https://opencommons.uconn.edu/gs_theses/1018.

Council of Science Editors:

Ahmad M. Understanding Concurrency for Graph Workloads in Large Scale Multicores. [Masters Thesis]. University of Connecticut; 2016. Available from: https://opencommons.uconn.edu/gs_theses/1018


Rochester Institute of Technology

24. Opong-Mensah, Kwadwo. Pulsar: Design and Simulation Methodology for Dynamic Bandwidth Allocation in Photonic Network-on-Chip Architectures in Heterogeneous Multicore Systems.

Degree: MS, Electrical Engineering, 2015, Rochester Institute of Technology

  As the computing industry moved toward faster and more energy-efficient solutions, multicore computers proved to be dependable. Soon after, the Network-on-Chip (NoC) paradigm made… (more)

Subjects/Keywords: Cache coherence; Communication; Computer architecture; Network; Photonics

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APA (6th Edition):

Opong-Mensah, K. (2015). Pulsar: Design and Simulation Methodology for Dynamic Bandwidth Allocation in Photonic Network-on-Chip Architectures in Heterogeneous Multicore Systems. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8824

Chicago Manual of Style (16th Edition):

Opong-Mensah, Kwadwo. “Pulsar: Design and Simulation Methodology for Dynamic Bandwidth Allocation in Photonic Network-on-Chip Architectures in Heterogeneous Multicore Systems.” 2015. Masters Thesis, Rochester Institute of Technology. Accessed October 18, 2019. https://scholarworks.rit.edu/theses/8824.

MLA Handbook (7th Edition):

Opong-Mensah, Kwadwo. “Pulsar: Design and Simulation Methodology for Dynamic Bandwidth Allocation in Photonic Network-on-Chip Architectures in Heterogeneous Multicore Systems.” 2015. Web. 18 Oct 2019.

Vancouver:

Opong-Mensah K. Pulsar: Design and Simulation Methodology for Dynamic Bandwidth Allocation in Photonic Network-on-Chip Architectures in Heterogeneous Multicore Systems. [Internet] [Masters thesis]. Rochester Institute of Technology; 2015. [cited 2019 Oct 18]. Available from: https://scholarworks.rit.edu/theses/8824.

Council of Science Editors:

Opong-Mensah K. Pulsar: Design and Simulation Methodology for Dynamic Bandwidth Allocation in Photonic Network-on-Chip Architectures in Heterogeneous Multicore Systems. [Masters Thesis]. Rochester Institute of Technology; 2015. Available from: https://scholarworks.rit.edu/theses/8824


Florida International University

25. Hariri, Abla. Secure Large Scale Penetration of Electric Vehicles in the Power Grid.

Degree: PhD, Electrical Engineering, 2018, Florida International University

  As part of the approaches used to meet climate goals set by international environmental agreements, policies are being applied worldwide for promoting the uptake… (more)

Subjects/Keywords: computer and systems architecture; electrical and electronics; Computer and Systems Architecture; Electrical and Electronics

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APA (6th Edition):

Hariri, A. (2018). Secure Large Scale Penetration of Electric Vehicles in the Power Grid. (Doctoral Dissertation). Florida International University. Retrieved from https://digitalcommons.fiu.edu/etd/3848 ; FIDC007054

Chicago Manual of Style (16th Edition):

Hariri, Abla. “Secure Large Scale Penetration of Electric Vehicles in the Power Grid.” 2018. Doctoral Dissertation, Florida International University. Accessed October 18, 2019. https://digitalcommons.fiu.edu/etd/3848 ; FIDC007054.

MLA Handbook (7th Edition):

Hariri, Abla. “Secure Large Scale Penetration of Electric Vehicles in the Power Grid.” 2018. Web. 18 Oct 2019.

Vancouver:

Hariri A. Secure Large Scale Penetration of Electric Vehicles in the Power Grid. [Internet] [Doctoral dissertation]. Florida International University; 2018. [cited 2019 Oct 18]. Available from: https://digitalcommons.fiu.edu/etd/3848 ; FIDC007054.

Council of Science Editors:

Hariri A. Secure Large Scale Penetration of Electric Vehicles in the Power Grid. [Doctoral Dissertation]. Florida International University; 2018. Available from: https://digitalcommons.fiu.edu/etd/3848 ; FIDC007054


Rochester Institute of Technology

26. Mange, Krunal. Configurable Random Instruction Generator for RISC Processors.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  Processors have evolved and grown more complex to serve enormous computational needs. Even though modern-day processors share same dna with processors half century ago,… (more)

Subjects/Keywords: RISC; Processor; RISC processor verification; Harvard architecture; von Neumann architecture; System verilog

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APA (6th Edition):

Mange, K. (2017). Configurable Random Instruction Generator for RISC Processors. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9707

Chicago Manual of Style (16th Edition):

Mange, Krunal. “Configurable Random Instruction Generator for RISC Processors.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed October 18, 2019. https://scholarworks.rit.edu/theses/9707.

MLA Handbook (7th Edition):

Mange, Krunal. “Configurable Random Instruction Generator for RISC Processors.” 2017. Web. 18 Oct 2019.

Vancouver:

Mange K. Configurable Random Instruction Generator for RISC Processors. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2019 Oct 18]. Available from: https://scholarworks.rit.edu/theses/9707.

Council of Science Editors:

Mange K. Configurable Random Instruction Generator for RISC Processors. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9707


University of Southern California

27. Zhao, Lihang. Hardware techniques for efficient communication in transactional systems.

Degree: PhD, Electrical Engineering, 2014, University of Southern California

 The architectural challenges for reaching extreme‐scale computing necessitate major progress in designing high performance and energy‐efficient hardware building blocks, such as microprocessors. The chip multiprocessor… (more)

Subjects/Keywords: computer architecture; parallel architecture; microprocessor; parallel programming; transactional memory; on‐chip network; energy efficiency

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APA (6th Edition):

Zhao, L. (2014). Hardware techniques for efficient communication in transactional systems. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/427031/rec/3121

Chicago Manual of Style (16th Edition):

Zhao, Lihang. “Hardware techniques for efficient communication in transactional systems.” 2014. Doctoral Dissertation, University of Southern California. Accessed October 18, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/427031/rec/3121.

MLA Handbook (7th Edition):

Zhao, Lihang. “Hardware techniques for efficient communication in transactional systems.” 2014. Web. 18 Oct 2019.

Vancouver:

Zhao L. Hardware techniques for efficient communication in transactional systems. [Internet] [Doctoral dissertation]. University of Southern California; 2014. [cited 2019 Oct 18]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/427031/rec/3121.

Council of Science Editors:

Zhao L. Hardware techniques for efficient communication in transactional systems. [Doctoral Dissertation]. University of Southern California; 2014. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/427031/rec/3121


Vanderbilt University

28. Shetler, Kevin Joseph. Temperature and Total Ionizing Dose Characterization of a Voltage Reference in a 180 nm CMOS Technology.

Degree: MS, Electrical Engineering, 2016, Vanderbilt University

 A voltage reference is a critical component of analog and mixed signal systems because it provides a global signal used for a variety of system… (more)

Subjects/Keywords: TID; radiation-hardened-by-design

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APA (6th Edition):

Shetler, K. J. (2016). Temperature and Total Ionizing Dose Characterization of a Voltage Reference in a 180 nm CMOS Technology. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-04082016-164141/ ;

Chicago Manual of Style (16th Edition):

Shetler, Kevin Joseph. “Temperature and Total Ionizing Dose Characterization of a Voltage Reference in a 180 nm CMOS Technology.” 2016. Masters Thesis, Vanderbilt University. Accessed October 18, 2019. http://etd.library.vanderbilt.edu/available/etd-04082016-164141/ ;.

MLA Handbook (7th Edition):

Shetler, Kevin Joseph. “Temperature and Total Ionizing Dose Characterization of a Voltage Reference in a 180 nm CMOS Technology.” 2016. Web. 18 Oct 2019.

Vancouver:

Shetler KJ. Temperature and Total Ionizing Dose Characterization of a Voltage Reference in a 180 nm CMOS Technology. [Internet] [Masters thesis]. Vanderbilt University; 2016. [cited 2019 Oct 18]. Available from: http://etd.library.vanderbilt.edu/available/etd-04082016-164141/ ;.

Council of Science Editors:

Shetler KJ. Temperature and Total Ionizing Dose Characterization of a Voltage Reference in a 180 nm CMOS Technology. [Masters Thesis]. Vanderbilt University; 2016. Available from: http://etd.library.vanderbilt.edu/available/etd-04082016-164141/ ;


Rochester Institute of Technology

29. Connor, John. The RIT IEEE-488 buffer design.

Degree: Electrical Engineering, 1992, Rochester Institute of Technology

 This document describes the design of an NMOS ASIC used to control an RIT IEEE-488 Buffer previously designed by the author. Past designs used discrete… (more)

Subjects/Keywords: Buffer design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Connor, J. (1992). The RIT IEEE-488 buffer design. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/5570

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Connor, John. “The RIT IEEE-488 buffer design.” 1992. Thesis, Rochester Institute of Technology. Accessed October 18, 2019. https://scholarworks.rit.edu/theses/5570.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Connor, John. “The RIT IEEE-488 buffer design.” 1992. Web. 18 Oct 2019.

Vancouver:

Connor J. The RIT IEEE-488 buffer design. [Internet] [Thesis]. Rochester Institute of Technology; 1992. [cited 2019 Oct 18]. Available from: https://scholarworks.rit.edu/theses/5570.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Connor J. The RIT IEEE-488 buffer design. [Thesis]. Rochester Institute of Technology; 1992. Available from: https://scholarworks.rit.edu/theses/5570

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Cal Poly

30. Furlan, Carmelo C. Analysis of Hardware Sorting Units in Processor Design.

Degree: MS, Electrical Engineering, 2019, Cal Poly

  Sorting is often computationally intensive and can cause the application in which it is used to run slowly. To date, the quickest software sorting… (more)

Subjects/Keywords: Sorting Units; Processor Design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Furlan, C. C. (2019). Analysis of Hardware Sorting Units in Processor Design. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/2020

Chicago Manual of Style (16th Edition):

Furlan, Carmelo C. “Analysis of Hardware Sorting Units in Processor Design.” 2019. Masters Thesis, Cal Poly. Accessed October 18, 2019. https://digitalcommons.calpoly.edu/theses/2020.

MLA Handbook (7th Edition):

Furlan, Carmelo C. “Analysis of Hardware Sorting Units in Processor Design.” 2019. Web. 18 Oct 2019.

Vancouver:

Furlan CC. Analysis of Hardware Sorting Units in Processor Design. [Internet] [Masters thesis]. Cal Poly; 2019. [cited 2019 Oct 18]. Available from: https://digitalcommons.calpoly.edu/theses/2020.

Council of Science Editors:

Furlan CC. Analysis of Hardware Sorting Units in Processor Design. [Masters Thesis]. Cal Poly; 2019. Available from: https://digitalcommons.calpoly.edu/theses/2020

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