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You searched for subject:(H CHSTINTEGRIERTE SCHALTUNGEN VLSI MIKROELEKTRONIK ). Showing records 1 – 30 of 6077 total matches.

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ETH Zürich

1. Muttersbach, Jens. Globally-asynchronous locally-synchronous architectures for VLSI systems.

Degree: 2001, ETH Zürich

Subjects/Keywords: HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); SCHALTKREISENTWURF (MIKROELEKTRONIK); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); CIRCUIT DESIGN (MICROELECTRONICS); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Muttersbach, J. (2001). Globally-asynchronous locally-synchronous architectures for VLSI systems. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/145308

Chicago Manual of Style (16th Edition):

Muttersbach, Jens. “Globally-asynchronous locally-synchronous architectures for VLSI systems.” 2001. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/145308.

MLA Handbook (7th Edition):

Muttersbach, Jens. “Globally-asynchronous locally-synchronous architectures for VLSI systems.” 2001. Web. 14 Dec 2019.

Vancouver:

Muttersbach J. Globally-asynchronous locally-synchronous architectures for VLSI systems. [Internet] [Doctoral dissertation]. ETH Zürich; 2001. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/145308.

Council of Science Editors:

Muttersbach J. Globally-asynchronous locally-synchronous architectures for VLSI systems. [Doctoral Dissertation]. ETH Zürich; 2001. Available from: http://hdl.handle.net/20.500.11850/145308


ETH Zürich

2. Sailer, Thomas Michael. Decision feedback equalization for powerline and HIPERLAN.

Degree: 2001, ETH Zürich

Subjects/Keywords: FEEDBACK-KANÄLE (INFORMATIONSTHEORIE); SCHALTKREISENTWURF (MIKROELEKTRONIK); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); FEEDBACK CHANNELS (INFORMATION THEORY); CIRCUIT DESIGN (MICROELECTRONICS); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); info:eu-repo/classification/ddc/510; info:eu-repo/classification/ddc/621.3; Mathematics; Electric engineering

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APA (6th Edition):

Sailer, T. M. (2001). Decision feedback equalization for powerline and HIPERLAN. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/145038

Chicago Manual of Style (16th Edition):

Sailer, Thomas Michael. “Decision feedback equalization for powerline and HIPERLAN.” 2001. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/145038.

MLA Handbook (7th Edition):

Sailer, Thomas Michael. “Decision feedback equalization for powerline and HIPERLAN.” 2001. Web. 14 Dec 2019.

Vancouver:

Sailer TM. Decision feedback equalization for powerline and HIPERLAN. [Internet] [Doctoral dissertation]. ETH Zürich; 2001. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/145038.

Council of Science Editors:

Sailer TM. Decision feedback equalization for powerline and HIPERLAN. [Doctoral Dissertation]. ETH Zürich; 2001. Available from: http://hdl.handle.net/20.500.11850/145038


ETH Zürich

3. Benkeser, Christian. Power Efficiency and the Mapping of Communication Algorithms into VLSI.

Degree: 2010, ETH Zürich

Subjects/Keywords: MOBILTELEFONE + HANDY (MOBILKOMMUNIKATION); ENERGIEVERLUSTE + WIRKUNGSGRAD + LEISTUNGSVERLUSTE (ELEKTROTECHNIK); DIGITALE INTEGRIERTE SCHALTUNGEN (MIKROELEKTRONIK); MOBILE TELEPHONES + CELLULAR TELEPHONES (MOBILE COMMUNICATIONS); DIGITAL INTEGRATED CIRCUITS (MICROELECTRONICS); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); ENERGY LOSSES + EFFICIENCY + POWER LOSSES (ELECTRICAL ENGINEERING); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Benkeser, C. (2010). Power Efficiency and the Mapping of Communication Algorithms into VLSI. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/29939

Chicago Manual of Style (16th Edition):

Benkeser, Christian. “Power Efficiency and the Mapping of Communication Algorithms into VLSI.” 2010. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/29939.

MLA Handbook (7th Edition):

Benkeser, Christian. “Power Efficiency and the Mapping of Communication Algorithms into VLSI.” 2010. Web. 14 Dec 2019.

Vancouver:

Benkeser C. Power Efficiency and the Mapping of Communication Algorithms into VLSI. [Internet] [Doctoral dissertation]. ETH Zürich; 2010. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/29939.

Council of Science Editors:

Benkeser C. Power Efficiency and the Mapping of Communication Algorithms into VLSI. [Doctoral Dissertation]. ETH Zürich; 2010. Available from: http://hdl.handle.net/20.500.11850/29939


ETH Zürich

4. Mächler, Patrick. VLSI architectures for compressive sensing and sparse signal recovery.

Degree: 2012, ETH Zürich

Subjects/Keywords: DIGITALE SIGNALVERARBEITUNG, DSV (NACHRICHTENTECHNIK); VLSI; DIGITAL SIGNAL PROCESSING, DSP (TELECOMMUNICATIONS); DIGITALE SIGNALÜBERTRAGUNG (NACHRICHTENTECHNIK); Digitale Signalverarbeitung; Höchstintegrierte Schaltungen; DIGITAL SIGNAL TRANSMISSION (TELECOMMUNICATIONS); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); Digitale Signalübertragung; HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); DSV; info:eu-repo/classification/ddc/621.3; info:eu-repo/classification/ddc/621.3; Electric engineering; Electric engineering

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APA (6th Edition):

Mächler, P. (2012). VLSI architectures for compressive sensing and sparse signal recovery. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/65163

Chicago Manual of Style (16th Edition):

Mächler, Patrick. “VLSI architectures for compressive sensing and sparse signal recovery.” 2012. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/65163.

MLA Handbook (7th Edition):

Mächler, Patrick. “VLSI architectures for compressive sensing and sparse signal recovery.” 2012. Web. 14 Dec 2019.

Vancouver:

Mächler P. VLSI architectures for compressive sensing and sparse signal recovery. [Internet] [Doctoral dissertation]. ETH Zürich; 2012. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/65163.

Council of Science Editors:

Mächler P. VLSI architectures for compressive sensing and sparse signal recovery. [Doctoral Dissertation]. ETH Zürich; 2012. Available from: http://hdl.handle.net/20.500.11850/65163


ETH Zürich

5. Bartolozzi, Chiara. Selective attention in silicon: from the design of an analog VLSI synapse to the implementation of a multi-chip system.

Degree: 2007, ETH Zürich

Subjects/Keywords: HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); MULTICHIP MODULE, MCM (MIKROELEKTRONIK); ECHTZEITSYSTEME + EINGEBETTETE SYSTEME (BETRIEBSSYSTEME); SCHALTKREISENTWURF (MIKROELEKTRONIK); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); MULTICHIP MODULES, MCM (MICROELECTRONICS); REAL-TIME SYSTEMS + EMBEDDED SYSTEMS (OPERATING SYSTEMS); CIRCUIT DESIGN (MICROELECTRONICS); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Bartolozzi, C. (2007). Selective attention in silicon: from the design of an analog VLSI synapse to the implementation of a multi-chip system. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/150088

Chicago Manual of Style (16th Edition):

Bartolozzi, Chiara. “Selective attention in silicon: from the design of an analog VLSI synapse to the implementation of a multi-chip system.” 2007. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/150088.

MLA Handbook (7th Edition):

Bartolozzi, Chiara. “Selective attention in silicon: from the design of an analog VLSI synapse to the implementation of a multi-chip system.” 2007. Web. 14 Dec 2019.

Vancouver:

Bartolozzi C. Selective attention in silicon: from the design of an analog VLSI synapse to the implementation of a multi-chip system. [Internet] [Doctoral dissertation]. ETH Zürich; 2007. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/150088.

Council of Science Editors:

Bartolozzi C. Selective attention in silicon: from the design of an analog VLSI synapse to the implementation of a multi-chip system. [Doctoral Dissertation]. ETH Zürich; 2007. Available from: http://hdl.handle.net/20.500.11850/150088


ETH Zürich

6. Henzen, Luca. VLSI Circuits for Cryptographic Authentication.

Degree: 2010, ETH Zürich

Subjects/Keywords: CRYPTOGRAPHY (INFORMATION THEORY); PERSONENIDENTIFIZIERUNG (INFORMATIONSTHEORIE); PERSONAL IDENTITY VERIFICATION (INFORMATION THEORY); KRYPTOGRAPHIE (INFORMATIONSTHEORIE); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); info:eu-repo/classification/ddc/621.3; info:eu-repo/classification/ddc/510; Electric engineering; Mathematics

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APA (6th Edition):

Henzen, L. (2010). VLSI Circuits for Cryptographic Authentication. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/29393

Chicago Manual of Style (16th Edition):

Henzen, Luca. “VLSI Circuits for Cryptographic Authentication.” 2010. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/29393.

MLA Handbook (7th Edition):

Henzen, Luca. “VLSI Circuits for Cryptographic Authentication.” 2010. Web. 14 Dec 2019.

Vancouver:

Henzen L. VLSI Circuits for Cryptographic Authentication. [Internet] [Doctoral dissertation]. ETH Zürich; 2010. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/29393.

Council of Science Editors:

Henzen L. VLSI Circuits for Cryptographic Authentication. [Doctoral Dissertation]. ETH Zürich; 2010. Available from: http://hdl.handle.net/20.500.11850/29393


ETH Zürich

7. Rasche, Christoph Albrecht. Analog VLSI circuits for emulating computational features of pyramidal cells.

Degree: 1999, ETH Zürich

Subjects/Keywords: NEURONALE NETZWERKE (COMPUTERSYSTEME); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); NEURAL NETWORKS (COMPUTER SYSTEMS); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/621.3; Data processing, computer science; Electric engineering

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APA (6th Edition):

Rasche, C. A. (1999). Analog VLSI circuits for emulating computational features of pyramidal cells. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/144242

Chicago Manual of Style (16th Edition):

Rasche, Christoph Albrecht. “Analog VLSI circuits for emulating computational features of pyramidal cells.” 1999. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/144242.

MLA Handbook (7th Edition):

Rasche, Christoph Albrecht. “Analog VLSI circuits for emulating computational features of pyramidal cells.” 1999. Web. 14 Dec 2019.

Vancouver:

Rasche CA. Analog VLSI circuits for emulating computational features of pyramidal cells. [Internet] [Doctoral dissertation]. ETH Zürich; 1999. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/144242.

Council of Science Editors:

Rasche CA. Analog VLSI circuits for emulating computational features of pyramidal cells. [Doctoral Dissertation]. ETH Zürich; 1999. Available from: http://hdl.handle.net/20.500.11850/144242


ETH Zürich

8. Chicca, Elisabetta. A neuromorphic VLSI system for modeling spike-based cooperative competitive neural networks.

Degree: 2006, ETH Zürich

Subjects/Keywords: HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); NEURONALE NETZWERKE + KONNEKTIONISMUS (KÜNSTLICHE INTELLIGENZ); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); NEURAL NETWORKS + CONNECTIONISM (ARTIFICIAL INTELLIGENCE); info:eu-repo/classification/ddc/004; Data processing, computer science

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APA (6th Edition):

Chicca, E. (2006). A neuromorphic VLSI system for modeling spike-based cooperative competitive neural networks. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/149527

Chicago Manual of Style (16th Edition):

Chicca, Elisabetta. “A neuromorphic VLSI system for modeling spike-based cooperative competitive neural networks.” 2006. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/149527.

MLA Handbook (7th Edition):

Chicca, Elisabetta. “A neuromorphic VLSI system for modeling spike-based cooperative competitive neural networks.” 2006. Web. 14 Dec 2019.

Vancouver:

Chicca E. A neuromorphic VLSI system for modeling spike-based cooperative competitive neural networks. [Internet] [Doctoral dissertation]. ETH Zürich; 2006. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/149527.

Council of Science Editors:

Chicca E. A neuromorphic VLSI system for modeling spike-based cooperative competitive neural networks. [Doctoral Dissertation]. ETH Zürich; 2006. Available from: http://hdl.handle.net/20.500.11850/149527


ETH Zürich

9. Burg, Andreas P. VLSI circuits for MIMO communication systems.

Degree: 2006, ETH Zürich

Subjects/Keywords: HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); MULTI-INPUT, MULTI-OUTPUT, MIMO (NACHRICHTENTECHNIK); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); MULTI-INPUT, MULTI-OUTPUT, MIMO (TELECOMMUNICATIONS); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Burg, A. P. (2006). VLSI circuits for MIMO communication systems. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/149127

Chicago Manual of Style (16th Edition):

Burg, Andreas P. “VLSI circuits for MIMO communication systems.” 2006. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/149127.

MLA Handbook (7th Edition):

Burg, Andreas P. “VLSI circuits for MIMO communication systems.” 2006. Web. 14 Dec 2019.

Vancouver:

Burg AP. VLSI circuits for MIMO communication systems. [Internet] [Doctoral dissertation]. ETH Zürich; 2006. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/149127.

Council of Science Editors:

Burg AP. VLSI circuits for MIMO communication systems. [Doctoral Dissertation]. ETH Zürich; 2006. Available from: http://hdl.handle.net/20.500.11850/149127


ETH Zürich

10. Jacomet, Marcel. Layoutabhängige Fehleranalyse und Testsynthese integrierter CMOS Schaltungen.

Degree: 1990, ETH Zürich

Subjects/Keywords: KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); SIGNATURANALYSE, KOMPLEXE SCHALTUNGEN (MIKROELEKTRONIK); DEFEKTERKENNUNG + FEHLERERKENNUNG (ELEKTROTECHNIK); LAYOUTS/MIKROELEKTRONIK; HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); PRODUKTION (BETRIEBSWIRTSCHAFT); QUALITÄTSKONTROLLE + FERTIGUNGSPRÜFUNG; COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); SIGNATURE ANALYSIS, COMPLEX CIRCUITS (MICROELECTRONICS); DEFECT RECOGNITION + FAULT RECOGNITION (ELECTRICAL ENGINEERING); LAYOUTS/MICROELECTRONICS; VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); PRODUCTION (BUSINESS ECONOMICS); QUALITY CONTROL + PRODUCTION INSPECTION; info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Jacomet, M. (1990). Layoutabhängige Fehleranalyse und Testsynthese integrierter CMOS Schaltungen. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/139941

Chicago Manual of Style (16th Edition):

Jacomet, Marcel. “Layoutabhängige Fehleranalyse und Testsynthese integrierter CMOS Schaltungen.” 1990. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/139941.

MLA Handbook (7th Edition):

Jacomet, Marcel. “Layoutabhängige Fehleranalyse und Testsynthese integrierter CMOS Schaltungen.” 1990. Web. 14 Dec 2019.

Vancouver:

Jacomet M. Layoutabhängige Fehleranalyse und Testsynthese integrierter CMOS Schaltungen. [Internet] [Doctoral dissertation]. ETH Zürich; 1990. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/139941.

Council of Science Editors:

Jacomet M. Layoutabhängige Fehleranalyse und Testsynthese integrierter CMOS Schaltungen. [Doctoral Dissertation]. ETH Zürich; 1990. Available from: http://hdl.handle.net/20.500.11850/139941


ETH Zürich

11. Lustenberger, Felix. On the design of analog VLSI iterative decoders.

Degree: 2000, ETH Zürich

Subjects/Keywords: SCHALTKREISENTWURF (MIKROELEKTRONIK); DECODIERUNG (INFORMATIONSTHEORIE); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); VITERBI-ALGORITHMEN (INFORMATIONSTHEORIE); CIRCUIT DESIGN (MICROELECTRONICS); DECODING (INFORMATION THEORY); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); VITERBI ALGORITHMS (INFORMATION THEORY); info:eu-repo/classification/ddc/510; info:eu-repo/classification/ddc/621.3; Mathematics; Electric engineering

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APA (6th Edition):

Lustenberger, F. (2000). On the design of analog VLSI iterative decoders. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/144863

Chicago Manual of Style (16th Edition):

Lustenberger, Felix. “On the design of analog VLSI iterative decoders.” 2000. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/144863.

MLA Handbook (7th Edition):

Lustenberger, Felix. “On the design of analog VLSI iterative decoders.” 2000. Web. 14 Dec 2019.

Vancouver:

Lustenberger F. On the design of analog VLSI iterative decoders. [Internet] [Doctoral dissertation]. ETH Zürich; 2000. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/144863.

Council of Science Editors:

Lustenberger F. On the design of analog VLSI iterative decoders. [Doctoral Dissertation]. ETH Zürich; 2000. Available from: http://hdl.handle.net/20.500.11850/144863


ETH Zürich

12. Wassner, Jürgen. Data statistics and low-power digital VLSI.

Degree: 2001, ETH Zürich

Subjects/Keywords: HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); TRANSISTOREN/TEGFET, VFET, MODFET, MOSFET, MESFET, SGFET, ISFET, MISFET, HFET, JFET, CIGFET, POSFET (ELEKTRONIK); DIGITALE INTEGRIERTE SCHALTUNGEN (MIKROELEKTRONIK); KLEINE LEISTUNG (ELEKTROTECHNIK); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); TRANSISTORS/TEGFET, VFET, MODFET, MOSFET, MESFET, SGFET, ISFET, MISFET, HFET, JFET, CIGFET, POSFET (ELECTRONICS); DIGITAL INTEGRATED CIRCUITS (MICROELECTRONICS); LOW POWER (ELECTRICAL ENGINEERING); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Wassner, J. (2001). Data statistics and low-power digital VLSI. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/145500

Chicago Manual of Style (16th Edition):

Wassner, Jürgen. “Data statistics and low-power digital VLSI.” 2001. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/145500.

MLA Handbook (7th Edition):

Wassner, Jürgen. “Data statistics and low-power digital VLSI.” 2001. Web. 14 Dec 2019.

Vancouver:

Wassner J. Data statistics and low-power digital VLSI. [Internet] [Doctoral dissertation]. ETH Zürich; 2001. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/145500.

Council of Science Editors:

Wassner J. Data statistics and low-power digital VLSI. [Doctoral Dissertation]. ETH Zürich; 2001. Available from: http://hdl.handle.net/20.500.11850/145500


ETH Zürich

13. Roth, Christoph. VLSI Design, Optimization, and Implementation of Channel Decoding in Wireless Systems.

Degree: 2015, ETH Zürich

Subjects/Keywords: SOURCE CODING + CHANNEL CODING (INFORMATION THEORY); MOBILFUNKNETZE + DRAHTLOSE NACHRICHTENNETZE (NACHRICHTENTECHNIK); DECODING (INFORMATION THEORY); DECODIERUNG (INFORMATIONSTHEORIE); MOBILE RADIO NETWORKS + WIRELESS COMMUNICATIONS NETWORKS (TELECOMMUNICATIONS); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); QUELLCODIERUNG + KANALCODIERUNG (INFORMATIONSTHEORIE); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); info:eu-repo/classification/ddc/621.3; info:eu-repo/classification/ddc/621.3; Electric engineering; Electric engineering

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APA (6th Edition):

Roth, C. (2015). VLSI Design, Optimization, and Implementation of Channel Decoding in Wireless Systems. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/103524

Chicago Manual of Style (16th Edition):

Roth, Christoph. “VLSI Design, Optimization, and Implementation of Channel Decoding in Wireless Systems.” 2015. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/103524.

MLA Handbook (7th Edition):

Roth, Christoph. “VLSI Design, Optimization, and Implementation of Channel Decoding in Wireless Systems.” 2015. Web. 14 Dec 2019.

Vancouver:

Roth C. VLSI Design, Optimization, and Implementation of Channel Decoding in Wireless Systems. [Internet] [Doctoral dissertation]. ETH Zürich; 2015. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/103524.

Council of Science Editors:

Roth C. VLSI Design, Optimization, and Implementation of Channel Decoding in Wireless Systems. [Doctoral Dissertation]. ETH Zürich; 2015. Available from: http://hdl.handle.net/20.500.11850/103524

14. Mühlberghuber, Michael. Security Considerations for VLSI-Based Symmetric Encryption Devices.

Degree: 2016, ETH Zürich

Subjects/Keywords: CODIERUNG (INFORMATIONSTHEORIE); DATA SECURITY + DATA PROTECTION (OPERATING SYSTEMS); DECODING (INFORMATION THEORY); DECODIERUNG (INFORMATIONSTHEORIE); CODING (INFORMATION THEORY); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); DATENSICHERHEIT + DATENSCHUTZ (BETRIEBSSYSTEME); info:eu-repo/classification/ddc/510; info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/621.3; Mathematics; Data processing, computer science; Electric engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mühlberghuber, M. (2016). Security Considerations for VLSI-Based Symmetric Encryption Devices. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/124591

Chicago Manual of Style (16th Edition):

Mühlberghuber, Michael. “Security Considerations for VLSI-Based Symmetric Encryption Devices.” 2016. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/124591.

MLA Handbook (7th Edition):

Mühlberghuber, Michael. “Security Considerations for VLSI-Based Symmetric Encryption Devices.” 2016. Web. 14 Dec 2019.

Vancouver:

Mühlberghuber M. Security Considerations for VLSI-Based Symmetric Encryption Devices. [Internet] [Doctoral dissertation]. ETH Zürich; 2016. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/124591.

Council of Science Editors:

Mühlberghuber M. Security Considerations for VLSI-Based Symmetric Encryption Devices. [Doctoral Dissertation]. ETH Zürich; 2016. Available from: http://hdl.handle.net/20.500.11850/124591


ETH Zürich

15. Dragas, Jelena. VLSI Hardware Devices for Acquisition and Processing of Multielectrode Neuronal Signals.

Degree: 2016, ETH Zürich

Subjects/Keywords: HUMAN-COMPUTER INTERACTION, HCI; SCHNITTSTELLEN (HARDWARE); INTERFACES (HARDWARE); ELEKTRISCHE PHÄNOMENE IM GEHIRN + HIRNSTRÖME (NEUROLOGIE); ELECTRICAL PHENOMENA IN THE BRAIN + BRAIN WAVES (NEUROLOGY); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); info:eu-repo/classification/ddc/621.3; info:eu-repo/classification/ddc/004; Electric engineering; Data processing, computer science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dragas, J. (2016). VLSI Hardware Devices for Acquisition and Processing of Multielectrode Neuronal Signals. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/127882

Chicago Manual of Style (16th Edition):

Dragas, Jelena. “VLSI Hardware Devices for Acquisition and Processing of Multielectrode Neuronal Signals.” 2016. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/127882.

MLA Handbook (7th Edition):

Dragas, Jelena. “VLSI Hardware Devices for Acquisition and Processing of Multielectrode Neuronal Signals.” 2016. Web. 14 Dec 2019.

Vancouver:

Dragas J. VLSI Hardware Devices for Acquisition and Processing of Multielectrode Neuronal Signals. [Internet] [Doctoral dissertation]. ETH Zürich; 2016. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/127882.

Council of Science Editors:

Dragas J. VLSI Hardware Devices for Acquisition and Processing of Multielectrode Neuronal Signals. [Doctoral Dissertation]. ETH Zürich; 2016. Available from: http://hdl.handle.net/20.500.11850/127882


ETH Zürich

16. Sonnleithner, Daniel Eduard. Neuromorphic implementation of a saliency-based visual selective attention system.

Degree: 2013, ETH Zürich

Subjects/Keywords: NEURONALE NETZWERKE + NEUROMORPHE SYSTEME (NEUROLOGIE); COMPUTERVISION (KÜNSTLICHE INTELLIGENZ); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); NEURAL NETWORKS + NEUROMORPHIC SYSTEMS (NEUROLOGY); COMPUTER VISION + SCENE UNDERSTANDING (ARTIFICIAL INTELLIGENCE); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/621.3; info:eu-repo/classification/ddc/621.3; Data processing, computer science; Electric engineering; Electric engineering

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APA (6th Edition):

Sonnleithner, D. E. (2013). Neuromorphic implementation of a saliency-based visual selective attention system. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/154483

Chicago Manual of Style (16th Edition):

Sonnleithner, Daniel Eduard. “Neuromorphic implementation of a saliency-based visual selective attention system.” 2013. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/154483.

MLA Handbook (7th Edition):

Sonnleithner, Daniel Eduard. “Neuromorphic implementation of a saliency-based visual selective attention system.” 2013. Web. 14 Dec 2019.

Vancouver:

Sonnleithner DE. Neuromorphic implementation of a saliency-based visual selective attention system. [Internet] [Doctoral dissertation]. ETH Zürich; 2013. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/154483.

Council of Science Editors:

Sonnleithner DE. Neuromorphic implementation of a saliency-based visual selective attention system. [Doctoral Dissertation]. ETH Zürich; 2013. Available from: http://hdl.handle.net/20.500.11850/154483


ETH Zürich

17. Fasnacht, Daniel Bernhard. Experimentation Platforms for Neuromorphic Event-Based Multi-Chip Systems.

Degree: 2016, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); NEURAL NETWORKS + NEUROMORPHIC SYSTEMS (NEUROLOGY); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); NEURONALE NETZWERKE + NEUROMORPHE SYSTEME (NEUROLOGIE); NEURONALE NETZWERKE (COMPUTERSYSTEME); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); NEURAL NETWORKS (COMPUTER SYSTEMS); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; Data processing, computer science; Data processing, computer science

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APA (6th Edition):

Fasnacht, D. B. (2016). Experimentation Platforms for Neuromorphic Event-Based Multi-Chip Systems. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/123065

Chicago Manual of Style (16th Edition):

Fasnacht, Daniel Bernhard. “Experimentation Platforms for Neuromorphic Event-Based Multi-Chip Systems.” 2016. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/123065.

MLA Handbook (7th Edition):

Fasnacht, Daniel Bernhard. “Experimentation Platforms for Neuromorphic Event-Based Multi-Chip Systems.” 2016. Web. 14 Dec 2019.

Vancouver:

Fasnacht DB. Experimentation Platforms for Neuromorphic Event-Based Multi-Chip Systems. [Internet] [Doctoral dissertation]. ETH Zürich; 2016. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/123065.

Council of Science Editors:

Fasnacht DB. Experimentation Platforms for Neuromorphic Event-Based Multi-Chip Systems. [Doctoral Dissertation]. ETH Zürich; 2016. Available from: http://hdl.handle.net/20.500.11850/123065


ETH Zürich

18. Huang, Kai. Towards Many-Core Real-Time Embedded Systems: Software Design of Streaming Systems at System Level.

Degree: 2010, ETH Zürich

Subjects/Keywords: MULTIPLE DATA STREAM ARCHITECTURES + MULTIPROCESSORS (COMPUTER SYSTEMS); REAL-TIME SYSTEMS + EMBEDDED SYSTEMS (COMPUTER SYSTEMS); MULTIPLE-DATA-STREAM-ARCHITEKTUREN + MULTIPROZESSOREN (COMPUTERSYSTEME); ECHTZEITSYSTEME + EINGEBETTETE SYSTEME (COMPUTERSYSTEME); SYSTEMPROGRAMMIERUNG (BETRIEBSSYSTEME); SYSTEMS PROGRAMMING (OPERATING SYSTEMS); VERY LARGE SCALE INTEGRATED CIRCUITS, VLSI (MICROELECTRONICS); HÖCHSTINTEGRIERTE SCHALTUNGEN, VLSI (MIKROELEKTRONIK); info:eu-repo/classification/ddc/004; info:eu-repo/classification/ddc/004; Data processing, computer science; Data processing, computer science

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APA (6th Edition):

Huang, K. (2010). Towards Many-Core Real-Time Embedded Systems: Software Design of Streaming Systems at System Level. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/27972

Chicago Manual of Style (16th Edition):

Huang, Kai. “Towards Many-Core Real-Time Embedded Systems: Software Design of Streaming Systems at System Level.” 2010. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/27972.

MLA Handbook (7th Edition):

Huang, Kai. “Towards Many-Core Real-Time Embedded Systems: Software Design of Streaming Systems at System Level.” 2010. Web. 14 Dec 2019.

Vancouver:

Huang K. Towards Many-Core Real-Time Embedded Systems: Software Design of Streaming Systems at System Level. [Internet] [Doctoral dissertation]. ETH Zürich; 2010. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/27972.

Council of Science Editors:

Huang K. Towards Many-Core Real-Time Embedded Systems: Software Design of Streaming Systems at System Level. [Doctoral Dissertation]. ETH Zürich; 2010. Available from: http://hdl.handle.net/20.500.11850/27972


Universidade do Rio Grande do Sul

19. Zatt, Bruno. Modelagem de hardware para codificação de vídeo e arquitetura de compensação de movimento segundo o padrão H.264/AVC.

Degree: 2008, Universidade do Rio Grande do Sul

Esta dissertação é composta de duas partes principais em que apresenta, em sua primeira parte, o desenvolvimento de uma arquitetura de hardware para compensação de… (more)

Subjects/Keywords: H.264/AVC; Microeletrônica; Vlsi; Video codin; Codificacao : Video digital; VLSI architectures; Modeling in systemC; Sistemas digitais

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APA (6th Edition):

Zatt, B. (2008). Modelagem de hardware para codificação de vídeo e arquitetura de compensação de movimento segundo o padrão H.264/AVC. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/16133

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zatt, Bruno. “Modelagem de hardware para codificação de vídeo e arquitetura de compensação de movimento segundo o padrão H.264/AVC.” 2008. Thesis, Universidade do Rio Grande do Sul. Accessed December 14, 2019. http://hdl.handle.net/10183/16133.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zatt, Bruno. “Modelagem de hardware para codificação de vídeo e arquitetura de compensação de movimento segundo o padrão H.264/AVC.” 2008. Web. 14 Dec 2019.

Vancouver:

Zatt B. Modelagem de hardware para codificação de vídeo e arquitetura de compensação de movimento segundo o padrão H.264/AVC. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2008. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/10183/16133.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zatt B. Modelagem de hardware para codificação de vídeo e arquitetura de compensação de movimento segundo o padrão H.264/AVC. [Thesis]. Universidade do Rio Grande do Sul; 2008. Available from: http://hdl.handle.net/10183/16133

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ETH Zürich

20. Flückiger, Ralf. Monolithic Microwave Integrated Circuits Based on InP/GaAsSb Double Heterojunction Bipolar Transistors.

Degree: 2015, ETH Zürich

Subjects/Keywords: BIPOLAR TRANSISTORS (ELECTRONICS); BIPOLARE TRANSISTOREN (ELEKTRONIK); MICROWAVE INTEGRATED CIRCUITS, MIC (MICROELECTRONICS); MIKROWELLEN-INTEGRIERTE SCHALTUNGEN, MIC (MIKROELEKTRONIK); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Flückiger, R. (2015). Monolithic Microwave Integrated Circuits Based on InP/GaAsSb Double Heterojunction Bipolar Transistors. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/112217

Chicago Manual of Style (16th Edition):

Flückiger, Ralf. “Monolithic Microwave Integrated Circuits Based on InP/GaAsSb Double Heterojunction Bipolar Transistors.” 2015. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/112217.

MLA Handbook (7th Edition):

Flückiger, Ralf. “Monolithic Microwave Integrated Circuits Based on InP/GaAsSb Double Heterojunction Bipolar Transistors.” 2015. Web. 14 Dec 2019.

Vancouver:

Flückiger R. Monolithic Microwave Integrated Circuits Based on InP/GaAsSb Double Heterojunction Bipolar Transistors. [Internet] [Doctoral dissertation]. ETH Zürich; 2015. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/112217.

Council of Science Editors:

Flückiger R. Monolithic Microwave Integrated Circuits Based on InP/GaAsSb Double Heterojunction Bipolar Transistors. [Doctoral Dissertation]. ETH Zürich; 2015. Available from: http://hdl.handle.net/20.500.11850/112217


Universidade do Rio Grande do Sul

21. Martins, André Luis Del Mestre. Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC.

Degree: 2011, Universidade do Rio Grande do Sul

O codificador aritmético binário adaptativo ao contexto adotado (CABAC – Context-based Adaptive Binary Arithmetic Coding) pelo padrão H.264/AVC a partir de perfil Main é o… (more)

Subjects/Keywords: Microeletrônica; Binarization and context modeling; Entropy encoding; Vlsi; Compressao : Video; VLSI dedicated architecture; Context-based adaptive binary arithmetic coding; H.264/AVC video compression

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Martins, A. L. D. M. (2011). Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/28742

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Martins, André Luis Del Mestre. “Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC.” 2011. Thesis, Universidade do Rio Grande do Sul. Accessed December 14, 2019. http://hdl.handle.net/10183/28742.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Martins, André Luis Del Mestre. “Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC.” 2011. Web. 14 Dec 2019.

Vancouver:

Martins ALDM. Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2011. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/10183/28742.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Martins ALDM. Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC. [Thesis]. Universidade do Rio Grande do Sul; 2011. Available from: http://hdl.handle.net/10183/28742

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Sun, Chi-Chia. VLSI design concepts for iterative algorithms.

Degree: 2011, Technische Universität Dortmund

 Circuit design becomes more and more complicated, especially when the Very Large Scale Integration (VLSI) manufacturing technology node keeps shrinking down to nanoscale level. New… (more)

Subjects/Keywords: CORDIC algorithm; FPGA; H.264; Iterative algorithm; Jacobi method; MPEG-4; NoC; Parallel computing; QDCT; SMVM; VLSI; 620

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APA (6th Edition):

Sun, C. (2011). VLSI design concepts for iterative algorithms. (Thesis). Technische Universität Dortmund. Retrieved from http://hdl.handle.net/2003/27714

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sun, Chi-Chia. “VLSI design concepts for iterative algorithms.” 2011. Thesis, Technische Universität Dortmund. Accessed December 14, 2019. http://hdl.handle.net/2003/27714.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sun, Chi-Chia. “VLSI design concepts for iterative algorithms.” 2011. Web. 14 Dec 2019.

Vancouver:

Sun C. VLSI design concepts for iterative algorithms. [Internet] [Thesis]. Technische Universität Dortmund; 2011. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/2003/27714.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sun C. VLSI design concepts for iterative algorithms. [Thesis]. Technische Universität Dortmund; 2011. Available from: http://hdl.handle.net/2003/27714

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

23. Agostini, Luciano Volcan. Desenvolvimento de Arquiteturas de Alto Desempenho dedicadas à compressão de vídeo segundo o Padrão H.264/AVC.

Degree: 2007, Universidade do Rio Grande do Sul

A compressão de vídeo é essencial para aplicações que manipulam vídeos digitais, em função da enorme quantidade de informação necessária para representar um vídeo sem… (more)

Subjects/Keywords: Video coding; Sistemas digitais; Televisão digital; H.264/AVC standard; VLSI architectures; Codificacao : Video digital; Fpga

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APA (6th Edition):

Agostini, L. V. (2007). Desenvolvimento de Arquiteturas de Alto Desempenho dedicadas à compressão de vídeo segundo o Padrão H.264/AVC. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/12425

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Agostini, Luciano Volcan. “Desenvolvimento de Arquiteturas de Alto Desempenho dedicadas à compressão de vídeo segundo o Padrão H.264/AVC.” 2007. Thesis, Universidade do Rio Grande do Sul. Accessed December 14, 2019. http://hdl.handle.net/10183/12425.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Agostini, Luciano Volcan. “Desenvolvimento de Arquiteturas de Alto Desempenho dedicadas à compressão de vídeo segundo o Padrão H.264/AVC.” 2007. Web. 14 Dec 2019.

Vancouver:

Agostini LV. Desenvolvimento de Arquiteturas de Alto Desempenho dedicadas à compressão de vídeo segundo o Padrão H.264/AVC. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2007. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/10183/12425.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Agostini LV. Desenvolvimento de Arquiteturas de Alto Desempenho dedicadas à compressão de vídeo segundo o Padrão H.264/AVC. [Thesis]. Universidade do Rio Grande do Sul; 2007. Available from: http://hdl.handle.net/10183/12425

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


ETH Zürich

24. Schenkel, Michael. Substrate current effects in smart power ICs.

Degree: 2003, ETH Zürich

Subjects/Keywords: MIKROELEKTRONIK + INTEGRIERTE SCHALTUNGEN; LAYOUTS/MIKROELEKTRONIK; DOPPELT DIFFUNDIERTE TRANSISTOREN, DMOS (ELEKTRONIK); CHIPS + MIKROCHIPS (MIKROELEKTRONIK); HALBLEITERBAUELEMENTE + ELEKTRONISCHE BAUELEMENTE (ELEKTRONIK); SILICIUM (CHEMISCHE ELEMENTE); MICROELECTRONICS + INTEGRATED CIRCUITS; LAYOUTS/MICROELECTRONICS; DOUBLE DIFFUSED TRANSISTORS, DMOS (ELECTRONICS); CHIPS + MICROCHIPS (MICROELECTRONICS); SEMICONDUCTOR COMPONENTS + ELECTRONIC COMPONENTS (ELECTRONICS); SILICON (CHEMICAL ELEMENTS); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Schenkel, M. (2003). Substrate current effects in smart power ICs. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/147283

Chicago Manual of Style (16th Edition):

Schenkel, Michael. “Substrate current effects in smart power ICs.” 2003. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/147283.

MLA Handbook (7th Edition):

Schenkel, Michael. “Substrate current effects in smart power ICs.” 2003. Web. 14 Dec 2019.

Vancouver:

Schenkel M. Substrate current effects in smart power ICs. [Internet] [Doctoral dissertation]. ETH Zürich; 2003. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/147283.

Council of Science Editors:

Schenkel M. Substrate current effects in smart power ICs. [Doctoral Dissertation]. ETH Zürich; 2003. Available from: http://hdl.handle.net/20.500.11850/147283


ETH Zürich

25. Villiger, Thomas. Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems.

Degree: 2005, ETH Zürich

Subjects/Keywords: http://dx.doi.org/10.3929/ethz-a-004948731; KOMPLEMENTÄRE METALLOXID-HALBLEITERSCHALTUNGEN, CMOS (MIKROELEKTRONIK); SYSTEM ON A CHIP, SOC (MIKROELEKTRONIK); ASYNCHRONOUS INTEGRATED CIRCUITS (MICROELECTRONICS); SYSTEM ON A CHIP, SOC (MICROELECTRONICS); COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR CIRCUITS, CMOS (MICROELECTRONICS); ASYNCHRONE INTEGRIERTE SCHALTUNGEN (MIKROELEKTRONIK); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA (6th Edition):

Villiger, T. (2005). Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/87052

Chicago Manual of Style (16th Edition):

Villiger, Thomas. “Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems.” 2005. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/87052.

MLA Handbook (7th Edition):

Villiger, Thomas. “Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems.” 2005. Web. 14 Dec 2019.

Vancouver:

Villiger T. Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems. [Internet] [Doctoral dissertation]. ETH Zürich; 2005. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/87052.

Council of Science Editors:

Villiger T. Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems. [Doctoral Dissertation]. ETH Zürich; 2005. Available from: http://hdl.handle.net/20.500.11850/87052


ETH Zürich

26. Merkli, Patrick P. Message-passing algorithms and analog electronic circuits.

Degree: 2005, ETH Zürich

Subjects/Keywords: CODIERUNG (INFORMATIONSTHEORIE); ANALOG INTEGRATED CIRCUITS (MICROELECTRONICS); GRAPHENALGORITHMEN + GEOMETRISCHE ALGORITHMEN (GRAPHENTHEORIE); ANALOGE INTEGRIERTE SCHALTUNGEN (MIKROELEKTRONIK); CODING (INFORMATION THEORY); GRAPHENMODELLE (GRAPHENTHEORIE); GRAPH ALGORITHMS + GEOMETRIC ALGORITHMS (GRAPH THEORY); GRAPH MODELS (GRAPH THEORY); info:eu-repo/classification/ddc/621.3; Electric engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Merkli, P. P. (2005). Message-passing algorithms and analog electronic circuits. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/83020

Chicago Manual of Style (16th Edition):

Merkli, Patrick P. “Message-passing algorithms and analog electronic circuits.” 2005. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/83020.

MLA Handbook (7th Edition):

Merkli, Patrick P. “Message-passing algorithms and analog electronic circuits.” 2005. Web. 14 Dec 2019.

Vancouver:

Merkli PP. Message-passing algorithms and analog electronic circuits. [Internet] [Doctoral dissertation]. ETH Zürich; 2005. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/83020.

Council of Science Editors:

Merkli PP. Message-passing algorithms and analog electronic circuits. [Doctoral Dissertation]. ETH Zürich; 2005. Available from: http://hdl.handle.net/20.500.11850/83020


ETH Zürich

27. Papadopoulos, Dimitrios Filippos. A power efficient linear multi-mode CMOS radio transmitter.

Degree: 2008, ETH Zürich

Subjects/Keywords: MOBILKOMMUNIKATION + MOBILE NACHRICHTENTECHNIK (FUNKTECHNIK); MIKROELEKTRONIK + INTEGRIERTE SCHALTUNGEN; RADIOWELLEN (ELEKTROTECHNIK); MOBILE COMMUNICATIONS + CELLULAR COMMUNICATIONS (RADIO COMMUNICATIONS); MICROELECTRONICS + INTEGRATED CIRCUITS; RADIO FREQUENCIES (ELECTRICAL ENGINEERING); info:eu-repo/classification/ddc/621.3; info:eu-repo/classification/ddc/621.3; Electric engineering; Electric engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Papadopoulos, D. F. (2008). A power efficient linear multi-mode CMOS radio transmitter. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/150835

Chicago Manual of Style (16th Edition):

Papadopoulos, Dimitrios Filippos. “A power efficient linear multi-mode CMOS radio transmitter.” 2008. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/150835.

MLA Handbook (7th Edition):

Papadopoulos, Dimitrios Filippos. “A power efficient linear multi-mode CMOS radio transmitter.” 2008. Web. 14 Dec 2019.

Vancouver:

Papadopoulos DF. A power efficient linear multi-mode CMOS radio transmitter. [Internet] [Doctoral dissertation]. ETH Zürich; 2008. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/150835.

Council of Science Editors:

Papadopoulos DF. A power efficient linear multi-mode CMOS radio transmitter. [Doctoral Dissertation]. ETH Zürich; 2008. Available from: http://hdl.handle.net/20.500.11850/150835


ETH Zürich

28. Fröhlich, Jürg. Evolutionary Optimization for Computational Electromagnetics.

Degree: 1997, ETH Zürich

Subjects/Keywords: COMPUTER APPLICATIONS IN ELECTRICAL ENGINEERING, ELECTRONICS, MICROELECTRONICS, TELECOMMUNICATIONS; COMPUTERANWENDUNGEN/ELEKTROTECHNIK, ELEKTRONIK, MIKROELEKTRONIK, NACHRICHTENTECHNIK; EVOLUTIONARY ALGORITHMS (MATHEMATICAL PROGRAMMING); OPTOELEKTRONISCHE INTEGRIERTE SCHALTUNGEN (OPTOELEKTRONIK); SCHALTKREISENTWURF (MIKROELEKTRONIK); EVOLUTIONÄRE ALGORITHMEN (MATHEMATISCHE OPTIMIERUNG); OPTOELECTRONIC INTEGRATED CIRCUITS (OPTOELECTRONICS); CIRCUIT DESIGN (MICROELECTRONICS); info:eu-repo/classification/ddc/621.3; info:eu-repo/classification/ddc/510; Electric engineering; Mathematics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fröhlich, J. (1997). Evolutionary Optimization for Computational Electromagnetics. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/92780

Chicago Manual of Style (16th Edition):

Fröhlich, Jürg. “Evolutionary Optimization for Computational Electromagnetics.” 1997. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/92780.

MLA Handbook (7th Edition):

Fröhlich, Jürg. “Evolutionary Optimization for Computational Electromagnetics.” 1997. Web. 14 Dec 2019.

Vancouver:

Fröhlich J. Evolutionary Optimization for Computational Electromagnetics. [Internet] [Doctoral dissertation]. ETH Zürich; 1997. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/92780.

Council of Science Editors:

Fröhlich J. Evolutionary Optimization for Computational Electromagnetics. [Doctoral Dissertation]. ETH Zürich; 1997. Available from: http://hdl.handle.net/20.500.11850/92780


ETH Zürich

29. Brauner, Thomas. Active antenna radio frontends for multiple antenna communication systems.

Degree: 2004, ETH Zürich

Subjects/Keywords: RICHTANTENNEN (FUNKTECHNIK); EMPFÄNGER/FUNKTECHNIK; CHIPS + MIKROCHIPS (MIKROELEKTRONIK); BIPOLARE KOMPLEMENTÄRE MOS SCHALTUNGEN, BICMOS (MIKROELEKTRONIK); DIRECTIONAL AERIALS + DIRECTIONAL ANTENNAS (RADIO ENGINEERING); RECEIVERS/RADIO ENGINEERING; CHIPS + MICROCHIPS (MICROELECTRONICS); BICMOS, BIPOLAR-COMPLEMENTARY-MOS-CIRCUITS (MICROELECTRONICS); info:eu-repo/classification/ddc/621.3; info:eu-repo/classification/ddc/621.3; Electric engineering; Electric engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Brauner, T. (2004). Active antenna radio frontends for multiple antenna communication systems. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/148460

Chicago Manual of Style (16th Edition):

Brauner, Thomas. “Active antenna radio frontends for multiple antenna communication systems.” 2004. Doctoral Dissertation, ETH Zürich. Accessed December 14, 2019. http://hdl.handle.net/20.500.11850/148460.

MLA Handbook (7th Edition):

Brauner, Thomas. “Active antenna radio frontends for multiple antenna communication systems.” 2004. Web. 14 Dec 2019.

Vancouver:

Brauner T. Active antenna radio frontends for multiple antenna communication systems. [Internet] [Doctoral dissertation]. ETH Zürich; 2004. [cited 2019 Dec 14]. Available from: http://hdl.handle.net/20.500.11850/148460.

Council of Science Editors:

Brauner T. Active antenna radio frontends for multiple antenna communication systems. [Doctoral Dissertation]. ETH Zürich; 2004. Available from: http://hdl.handle.net/20.500.11850/148460


University of Georgia

30. Bahuman, Anil Lakshman. An evolutionary approach to standard cell design automation.

Degree: MS, Artificial Intelligence, 2001, University of Georgia

 The problem of designing the transistor-level layout of cells in a standard cell library is a multi-objective design optimization problem. Contemporary methods are optimization or… (more)

Subjects/Keywords: VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bahuman, A. L. (2001). An evolutionary approach to standard cell design automation. (Masters Thesis). University of Georgia. Retrieved from http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms

Chicago Manual of Style (16th Edition):

Bahuman, Anil Lakshman. “An evolutionary approach to standard cell design automation.” 2001. Masters Thesis, University of Georgia. Accessed December 14, 2019. http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms.

MLA Handbook (7th Edition):

Bahuman, Anil Lakshman. “An evolutionary approach to standard cell design automation.” 2001. Web. 14 Dec 2019.

Vancouver:

Bahuman AL. An evolutionary approach to standard cell design automation. [Internet] [Masters thesis]. University of Georgia; 2001. [cited 2019 Dec 14]. Available from: http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms.

Council of Science Editors:

Bahuman AL. An evolutionary approach to standard cell design automation. [Masters Thesis]. University of Georgia; 2001. Available from: http://purl.galileo.usg.edu/uga_etd/bahuman_anil_l_200112_ms

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