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You searched for subject:(Gigascale). Showing records 1 – 3 of 3 total matches.

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Georgia Tech

1. Ogunsola, Oluwafemi Olusegun. Prospects for Mirror-Enabled Polymer Pillar I/O Optical Interconnects for Gigascale Integration.

Degree: PhD, Electrical Engineering, 2006, Georgia Tech

Digital systems have derived performance benefits due to the scaling down of CMOS microprocessor feature sizes towards packing billions of transistors on a chip, or gigascale integration (GSI). This has placed immense bandwidth demands on chip-to-chip and chip-to-board interconnects. The present-day electrical interconnect may limit bandwidth as transmission rates grow. As such, optical interconnects have been proposed as a potential solution. A critical requirement for enabling chip-to-chip and chip-to-board optical interconnection is out-of-plane coupling for directing light between a chip and the board. Any solution for this problem must be compatible with conventional packaging and assembly requirements. This research addresses the prospects for integrating waveguides with mirrors and polymer pillar optical I/O interconnects to provide such a compatible, out-of-plane, chip-to-board packaging solution through the design, analysis, fabrication, and testing of its constituent parts and their ultimate integration. Advisors/Committee Members: Dr. James D. Meindl (Committee Chair), Dr. Thomas K. Gaylord (Committee Co-Chair), Dr. Gary S. May (Committee Member), Dr. Jeffrey A. Davis (Committee Member), Dr. Paul Kohl (Committee Member), Dr. Stephen E. Ralph (Committee Member).

Subjects/Keywords: Mirrors; Polymer pillars; Finite-difference time-domain; FDTD; Optical interconnects; Gigascale integration; Silicon; Optical interconnects; Finite differences Data processing; Digital integrated circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ogunsola, O. O. (2006). Prospects for Mirror-Enabled Polymer Pillar I/O Optical Interconnects for Gigascale Integration. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/14067

Chicago Manual of Style (16th Edition):

Ogunsola, Oluwafemi Olusegun. “Prospects for Mirror-Enabled Polymer Pillar I/O Optical Interconnects for Gigascale Integration.” 2006. Doctoral Dissertation, Georgia Tech. Accessed November 14, 2019. http://hdl.handle.net/1853/14067.

MLA Handbook (7th Edition):

Ogunsola, Oluwafemi Olusegun. “Prospects for Mirror-Enabled Polymer Pillar I/O Optical Interconnects for Gigascale Integration.” 2006. Web. 14 Nov 2019.

Vancouver:

Ogunsola OO. Prospects for Mirror-Enabled Polymer Pillar I/O Optical Interconnects for Gigascale Integration. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2019 Nov 14]. Available from: http://hdl.handle.net/1853/14067.

Council of Science Editors:

Ogunsola OO. Prospects for Mirror-Enabled Polymer Pillar I/O Optical Interconnects for Gigascale Integration. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/14067


Georgia Tech

2. Huang, Gang. Compact physical models for power supply noise and chip/package co-design in gigascale integration (GSI) and three-dimensional (3-D) integration systems.

Degree: PhD, Electrical and Computer Engineering, 2008, Georgia Tech

The objective of this dissertation is to derive a set of compact physical models addressing power integrity issues in high performance gigascale integration (GSI) systems and three-dimensional (3-D) systems. The aggressive scaling of CMOS integrated circuits makes the design of power distribution networks a serious challenge. This is because the supply current and clock frequency are increasing, which increases the power supply noise. The scaling of the supply voltage slowed down in recent years, but the logic on the integrated circuit (IC) still becomes more sensitive to any supply voltage change because of the decreasing clock cycle and therefore noise margin. Excessive power supply noise can lead to severe degradation of chip performance and even logic failure. Therefore, power supply noise modeling and power integrity validation are of great significance in GSI systems and 3-D systems. Compact physical models enable quick recognition of the power supply noise without doing dedicated simulations. In this dissertation, accurate and compact physical models for the power supply noise are derived for power hungry blocks, hot spots, 3-D chip stacks, and chip/package co-design. The impacts of noise on transmission line performance are also investigated using compact physical modeling schemes. The models can help designers gain sufficient physical insights into the complicated power delivery system and tradeoff various important chip and package design parameters during the early stages of design. The models are compared with commercial tools and display high accuracy. Advisors/Committee Members: Meindl, James D. (Committee Chair), Bakir, Muhannad S. (Committee Member), Davis, Jeffrey A. (Committee Member), Gaylord, Thomas K. (Committee Member), Kohl, Paul A. (Committee Member), Naeemi, Azad (Committee Member).

Subjects/Keywords: Gigascale integration (GSI); Three-dimensional integraton (3-D integration); Compact physical model; Power delivery; Chip/package co-design; Power supply noise; Current noise (Electricity); Microprocessors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, G. (2008). Compact physical models for power supply noise and chip/package co-design in gigascale integration (GSI) and three-dimensional (3-D) integration systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26619

Chicago Manual of Style (16th Edition):

Huang, Gang. “Compact physical models for power supply noise and chip/package co-design in gigascale integration (GSI) and three-dimensional (3-D) integration systems.” 2008. Doctoral Dissertation, Georgia Tech. Accessed November 14, 2019. http://hdl.handle.net/1853/26619.

MLA Handbook (7th Edition):

Huang, Gang. “Compact physical models for power supply noise and chip/package co-design in gigascale integration (GSI) and three-dimensional (3-D) integration systems.” 2008. Web. 14 Nov 2019.

Vancouver:

Huang G. Compact physical models for power supply noise and chip/package co-design in gigascale integration (GSI) and three-dimensional (3-D) integration systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2008. [cited 2019 Nov 14]. Available from: http://hdl.handle.net/1853/26619.

Council of Science Editors:

Huang G. Compact physical models for power supply noise and chip/package co-design in gigascale integration (GSI) and three-dimensional (3-D) integration systems. [Doctoral Dissertation]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/26619


Georgia Tech

3. Nugent, Steven Paul. A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC).

Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech

Future opportunities for gigascale integration will be governed by a hierarchy of theoretical and practical limits that can be codified as follows: fundamental, material, device, circuit, and system. An exponential increase in on-chip integration is driving System-on-Chip (SoC) methodologies as a dominant design solution for gigascale ICs. Therefore, a second generation generic systems simulator (GENESYS) is developed to address a need for rapid assessment of technology/architecture tradeoffs for multi-billion transistor SoCs while maintaining the depth of core modeling codified in the hierarchy of limits. A newly developed system methodology incorporates a hiearchical block-based model, a dual interconnect distribution for both local and global interconnects, a generic on-chip bus model, and cell placement algorithms. A comparison of simulation results for five commercial SoC implementations shows increased accuracy in predicting die size, clock frequency, and total power dissipation. ITRS projections for future technology requirments are applied with results indicating that increasing static power dissipation is a key impediment to making continued improvements in chip performance. Additionally, simulations of a generic chip multi-processor architecture utilizing several interconnect schemes shows that the most promising candidate for the future of on-chip global interconnect networks will be hierarchical bus structures providing a high degree of connectivity while maintaining high operating frequencies. Advisors/Committee Members: James D. Meindl (Committee Chair), D. S. Wills (Committee Co-Chair), Jeffrey A. Davis (Committee Member), Madhavan Swaminathan (Committee Member), Paul A. Kohl (Committee Member), William R. Callen (Committee Member).

Subjects/Keywords: Chip modeling; Performance modeling; Simulator; Gigascale; Chip modeling; GENESYS; Integrated circuits Very large scale integration Design and construction Computer simulation; System design Computer simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nugent, S. P. (2005). A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC). (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6885

Chicago Manual of Style (16th Edition):

Nugent, Steven Paul. “A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC).” 2005. Doctoral Dissertation, Georgia Tech. Accessed November 14, 2019. http://hdl.handle.net/1853/6885.

MLA Handbook (7th Edition):

Nugent, Steven Paul. “A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC).” 2005. Web. 14 Nov 2019.

Vancouver:

Nugent SP. A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC). [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2019 Nov 14]. Available from: http://hdl.handle.net/1853/6885.

Council of Science Editors:

Nugent SP. A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC). [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6885

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