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You searched for subject:(Gate). Showing records 1 – 30 of 1519 total matches.

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Delft University of Technology

1. De Man, S. (author). A proposal for improvement of mid-term capacity planning for gates and remote stand at Amsterdam Airport Schiphol (AAS).

Degree: 2011, Delft University of Technology

Transport and Logistics

Systems Engineering, Policy and Management

Technology, Policy and Management

Advisors/Committee Members: Ludema, M. (mentor).

Subjects/Keywords: gate capacity planning

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

De Man, S. (. (2011). A proposal for improvement of mid-term capacity planning for gates and remote stand at Amsterdam Airport Schiphol (AAS). (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:818dd141-ca25-45a3-b207-f142a8b2b637

Chicago Manual of Style (16th Edition):

De Man, S (author). “A proposal for improvement of mid-term capacity planning for gates and remote stand at Amsterdam Airport Schiphol (AAS).” 2011. Masters Thesis, Delft University of Technology. Accessed April 14, 2021. http://resolver.tudelft.nl/uuid:818dd141-ca25-45a3-b207-f142a8b2b637.

MLA Handbook (7th Edition):

De Man, S (author). “A proposal for improvement of mid-term capacity planning for gates and remote stand at Amsterdam Airport Schiphol (AAS).” 2011. Web. 14 Apr 2021.

Vancouver:

De Man S(. A proposal for improvement of mid-term capacity planning for gates and remote stand at Amsterdam Airport Schiphol (AAS). [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2021 Apr 14]. Available from: http://resolver.tudelft.nl/uuid:818dd141-ca25-45a3-b207-f142a8b2b637.

Council of Science Editors:

De Man S(. A proposal for improvement of mid-term capacity planning for gates and remote stand at Amsterdam Airport Schiphol (AAS). [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:818dd141-ca25-45a3-b207-f142a8b2b637


Nelson Mandela Metropolitan University

2. Potgieter, Juan-Pierre. Single event upset testing of flash based field programmable gate arrays.

Degree: Faculty of Engineering, the Built Environment and Information Technology, 2015, Nelson Mandela Metropolitan University

 In the last 50 years microelectronics have advanced at an exponential rate, causing microelectronic devices to shrink, have very low operating voltages and increased complexities;… (more)

Subjects/Keywords: Field programmable gate arrays

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APA (6th Edition):

Potgieter, J. (2015). Single event upset testing of flash based field programmable gate arrays. (Thesis). Nelson Mandela Metropolitan University. Retrieved from http://hdl.handle.net/10948/12520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Potgieter, Juan-Pierre. “Single event upset testing of flash based field programmable gate arrays.” 2015. Thesis, Nelson Mandela Metropolitan University. Accessed April 14, 2021. http://hdl.handle.net/10948/12520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Potgieter, Juan-Pierre. “Single event upset testing of flash based field programmable gate arrays.” 2015. Web. 14 Apr 2021.

Vancouver:

Potgieter J. Single event upset testing of flash based field programmable gate arrays. [Internet] [Thesis]. Nelson Mandela Metropolitan University; 2015. [cited 2021 Apr 14]. Available from: http://hdl.handle.net/10948/12520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Potgieter J. Single event upset testing of flash based field programmable gate arrays. [Thesis]. Nelson Mandela Metropolitan University; 2015. Available from: http://hdl.handle.net/10948/12520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

3. Zhao, Yichen. Design and FPGA implementation of digital transmission over severe ISI channels.

Degree: MS, Electrical and Computer Engineering, 2013, Oregon State University

 Inter-symbol interference is one of the major factors that make the realization of high-data-rate digital communications system complex. Current designs face two main challenges: how… (more)

Subjects/Keywords: ISI; Field programmable gate arrays

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APA (6th Edition):

Zhao, Y. (2013). Design and FPGA implementation of digital transmission over severe ISI channels. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39400

Chicago Manual of Style (16th Edition):

Zhao, Yichen. “Design and FPGA implementation of digital transmission over severe ISI channels.” 2013. Masters Thesis, Oregon State University. Accessed April 14, 2021. http://hdl.handle.net/1957/39400.

MLA Handbook (7th Edition):

Zhao, Yichen. “Design and FPGA implementation of digital transmission over severe ISI channels.” 2013. Web. 14 Apr 2021.

Vancouver:

Zhao Y. Design and FPGA implementation of digital transmission over severe ISI channels. [Internet] [Masters thesis]. Oregon State University; 2013. [cited 2021 Apr 14]. Available from: http://hdl.handle.net/1957/39400.

Council of Science Editors:

Zhao Y. Design and FPGA implementation of digital transmission over severe ISI channels. [Masters Thesis]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39400


University of Debrecen

4. Uba, Chukwudire. Building a Flux-gate Magnetometer .

Degree: DE – Természettudományi és Technológiai Kar – Fizikai Intézet, University of Debrecen

I built a flux-gate magnetometer Advisors/Committee Members: Daroczi, Lajos (advisor).

Subjects/Keywords: Flux-gate

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APA (6th Edition):

Uba, C. (n.d.). Building a Flux-gate Magnetometer . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/276650

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Uba, Chukwudire. “Building a Flux-gate Magnetometer .” Thesis, University of Debrecen. Accessed April 14, 2021. http://hdl.handle.net/2437/276650.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Uba, Chukwudire. “Building a Flux-gate Magnetometer .” Web. 14 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Uba C. Building a Flux-gate Magnetometer . [Internet] [Thesis]. University of Debrecen; [cited 2021 Apr 14]. Available from: http://hdl.handle.net/2437/276650.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Uba C. Building a Flux-gate Magnetometer . [Thesis]. University of Debrecen; Available from: http://hdl.handle.net/2437/276650

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Uppsala University

5. Herterich, Emmi. Sequential Holonomic Quantum Gates : Open Path Holonomy in Λ-configuration.

Degree: Materials Theory, 2016, Uppsala University

In the Λ-system, non-adiabatic holonomic quantum phases are used to construct holonomic quantum gates. An interesting approach would be to implement open path holonomies… (more)

Subjects/Keywords: Quantum Gate; Holonomy; Geometric Phase

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Herterich, E. (2016). Sequential Holonomic Quantum Gates : Open Path Holonomy in Λ-configuration. (Thesis). Uppsala University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-296137

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Herterich, Emmi. “Sequential Holonomic Quantum Gates : Open Path Holonomy in Λ-configuration.” 2016. Thesis, Uppsala University. Accessed April 14, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-296137.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Herterich, Emmi. “Sequential Holonomic Quantum Gates : Open Path Holonomy in Λ-configuration.” 2016. Web. 14 Apr 2021.

Vancouver:

Herterich E. Sequential Holonomic Quantum Gates : Open Path Holonomy in Λ-configuration. [Internet] [Thesis]. Uppsala University; 2016. [cited 2021 Apr 14]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-296137.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Herterich E. Sequential Holonomic Quantum Gates : Open Path Holonomy in Λ-configuration. [Thesis]. Uppsala University; 2016. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-296137

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

6. Borghart, jasper (author). Operational Gate Allocation Using a Sliding Time Window.

Degree: 2019, Delft University of Technology

The steady growth of air traffic volumes and the subsequent increase of congestion at major airports require airports to increase their operational efficiency. Inefficient or… (more)

Subjects/Keywords: Gate allocation; Airport; MILP; Aircraft

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APA (6th Edition):

Borghart, j. (. (2019). Operational Gate Allocation Using a Sliding Time Window. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:52904af0-09cb-4958-9658-691377864f80

Chicago Manual of Style (16th Edition):

Borghart, jasper (author). “Operational Gate Allocation Using a Sliding Time Window.” 2019. Masters Thesis, Delft University of Technology. Accessed April 14, 2021. http://resolver.tudelft.nl/uuid:52904af0-09cb-4958-9658-691377864f80.

MLA Handbook (7th Edition):

Borghart, jasper (author). “Operational Gate Allocation Using a Sliding Time Window.” 2019. Web. 14 Apr 2021.

Vancouver:

Borghart j(. Operational Gate Allocation Using a Sliding Time Window. [Internet] [Masters thesis]. Delft University of Technology; 2019. [cited 2021 Apr 14]. Available from: http://resolver.tudelft.nl/uuid:52904af0-09cb-4958-9658-691377864f80.

Council of Science Editors:

Borghart j(. Operational Gate Allocation Using a Sliding Time Window. [Masters Thesis]. Delft University of Technology; 2019. Available from: http://resolver.tudelft.nl/uuid:52904af0-09cb-4958-9658-691377864f80


Delft University of Technology

7. Yang, J. (author). Reliability study of the Floating Gate Based Embedded Non?Volatile Memory (eNVM).

Degree: 2010, Delft University of Technology

The task of this project is to investigate the reliability aspects of NXP 2T?FNFN?NOR embedded non?volatile memories (eNVM). The structure of the memory cell is… (more)

Subjects/Keywords: floating gate

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APA (6th Edition):

Yang, J. (. (2010). Reliability study of the Floating Gate Based Embedded Non?Volatile Memory (eNVM). (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:8cd415c3-1ca3-4974-982f-40b5508bd8e1

Chicago Manual of Style (16th Edition):

Yang, J (author). “Reliability study of the Floating Gate Based Embedded Non?Volatile Memory (eNVM).” 2010. Masters Thesis, Delft University of Technology. Accessed April 14, 2021. http://resolver.tudelft.nl/uuid:8cd415c3-1ca3-4974-982f-40b5508bd8e1.

MLA Handbook (7th Edition):

Yang, J (author). “Reliability study of the Floating Gate Based Embedded Non?Volatile Memory (eNVM).” 2010. Web. 14 Apr 2021.

Vancouver:

Yang J(. Reliability study of the Floating Gate Based Embedded Non?Volatile Memory (eNVM). [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2021 Apr 14]. Available from: http://resolver.tudelft.nl/uuid:8cd415c3-1ca3-4974-982f-40b5508bd8e1.

Council of Science Editors:

Yang J(. Reliability study of the Floating Gate Based Embedded Non?Volatile Memory (eNVM). [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:8cd415c3-1ca3-4974-982f-40b5508bd8e1


Delft University of Technology

8. Teengs, Pieter (author). Analysis of a rolling FRP lock gate: + stability during movement.

Degree: 2017, Delft University of Technology

 Fibre-reinforced polymers (FRPs) are becoming a more commonly used building material in many civil engineering applications including locks. One quality of FRPs is the fact… (more)

Subjects/Keywords: Rolling lock gate; FRP

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APA (6th Edition):

Teengs, P. (. (2017). Analysis of a rolling FRP lock gate: + stability during movement. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:9ae36c48-4548-4569-9769-c8e0ef353a1e

Chicago Manual of Style (16th Edition):

Teengs, Pieter (author). “Analysis of a rolling FRP lock gate: + stability during movement.” 2017. Masters Thesis, Delft University of Technology. Accessed April 14, 2021. http://resolver.tudelft.nl/uuid:9ae36c48-4548-4569-9769-c8e0ef353a1e.

MLA Handbook (7th Edition):

Teengs, Pieter (author). “Analysis of a rolling FRP lock gate: + stability during movement.” 2017. Web. 14 Apr 2021.

Vancouver:

Teengs P(. Analysis of a rolling FRP lock gate: + stability during movement. [Internet] [Masters thesis]. Delft University of Technology; 2017. [cited 2021 Apr 14]. Available from: http://resolver.tudelft.nl/uuid:9ae36c48-4548-4569-9769-c8e0ef353a1e.

Council of Science Editors:

Teengs P(. Analysis of a rolling FRP lock gate: + stability during movement. [Masters Thesis]. Delft University of Technology; 2017. Available from: http://resolver.tudelft.nl/uuid:9ae36c48-4548-4569-9769-c8e0ef353a1e


Georgia Tech

9. Wunderlich, Richard Bryan. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems.… (more)

Subjects/Keywords: Floating-gate; Reconfigurable; Digital; Analog processing; Field programmable gate arrays

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APA (6th Edition):

Wunderlich, R. B. (2014). Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51815

Chicago Manual of Style (16th Edition):

Wunderlich, Richard Bryan. “Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.” 2014. Doctoral Dissertation, Georgia Tech. Accessed April 14, 2021. http://hdl.handle.net/1853/51815.

MLA Handbook (7th Edition):

Wunderlich, Richard Bryan. “Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.” 2014. Web. 14 Apr 2021.

Vancouver:

Wunderlich RB. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2021 Apr 14]. Available from: http://hdl.handle.net/1853/51815.

Council of Science Editors:

Wunderlich RB. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51815


University of Tennessee – Knoxville

10. Long, Yu. Design and Analysis of a Fully-Integrated Resonant Gate Driver.

Degree: 2016, University of Tennessee – Knoxville

 Several decades ago the resonant gate driving technique was proposed. Given the recent rapid growth in GaN HEMT power device applications for high-frequency power applications,… (more)

Subjects/Keywords: Gate driver; resonant gate driver; GaN FET; Electrical and Electronics

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APA (6th Edition):

Long, Y. (2016). Design and Analysis of a Fully-Integrated Resonant Gate Driver. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/4147

Chicago Manual of Style (16th Edition):

Long, Yu. “Design and Analysis of a Fully-Integrated Resonant Gate Driver.” 2016. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed April 14, 2021. https://trace.tennessee.edu/utk_graddiss/4147.

MLA Handbook (7th Edition):

Long, Yu. “Design and Analysis of a Fully-Integrated Resonant Gate Driver.” 2016. Web. 14 Apr 2021.

Vancouver:

Long Y. Design and Analysis of a Fully-Integrated Resonant Gate Driver. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2016. [cited 2021 Apr 14]. Available from: https://trace.tennessee.edu/utk_graddiss/4147.

Council of Science Editors:

Long Y. Design and Analysis of a Fully-Integrated Resonant Gate Driver. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2016. Available from: https://trace.tennessee.edu/utk_graddiss/4147


Indian Institute of Science

11. Srivatsava, J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.

Degree: PhD, Faculty of Engineering, 2014, Indian Institute of Science

 For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology… (more)

Subjects/Keywords: Asymmetric Double Gate MOSFET; Asymmetric Double Gate Transistor - Compact Modeling; Transistor Performance; Common-Gate Asymmetric Double Gate MOSFET; Independent-gate Asymmetric Double Gate MOSFET; DG MOSFET; Double Gate MOSFET; Metal Oxide Semiconductor Field Effect Transistor; Electronic Engineering

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APA (6th Edition):

Srivatsava, J. (2014). Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/2346

Chicago Manual of Style (16th Edition):

Srivatsava, J. “Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.” 2014. Doctoral Dissertation, Indian Institute of Science. Accessed April 14, 2021. http://etd.iisc.ac.in/handle/2005/2346.

MLA Handbook (7th Edition):

Srivatsava, J. “Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.” 2014. Web. 14 Apr 2021.

Vancouver:

Srivatsava J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2014. [cited 2021 Apr 14]. Available from: http://etd.iisc.ac.in/handle/2005/2346.

Council of Science Editors:

Srivatsava J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. [Doctoral Dissertation]. Indian Institute of Science; 2014. Available from: http://etd.iisc.ac.in/handle/2005/2346


Universidade Federal de Mato Grosso do Sul

12. Corbelino, Luis Henrique Guimarães. Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA .

Degree: 2012, Universidade Federal de Mato Grosso do Sul

 Este trabalho aborda o desenvolvimento, a simulação e a implementação de um sistema automático para realizar o paralelismo entre gerador e a rede elétrica, além… (more)

Subjects/Keywords: Arranjos de Lógica Programável em Campo; Field Programmable Gate Arrays; Circuitos Gate Arrays; Gate Arrays Circuits; Energia Elétrica; Electric Power

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APA (6th Edition):

Corbelino, L. H. G. (2012). Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA . (Thesis). Universidade Federal de Mato Grosso do Sul. Retrieved from http://repositorio.cbc.ufms.br:8080/jspui/handle/123456789/1924

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Corbelino, Luis Henrique Guimarães. “Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA .” 2012. Thesis, Universidade Federal de Mato Grosso do Sul. Accessed April 14, 2021. http://repositorio.cbc.ufms.br:8080/jspui/handle/123456789/1924.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Corbelino, Luis Henrique Guimarães. “Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA .” 2012. Web. 14 Apr 2021.

Vancouver:

Corbelino LHG. Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA . [Internet] [Thesis]. Universidade Federal de Mato Grosso do Sul; 2012. [cited 2021 Apr 14]. Available from: http://repositorio.cbc.ufms.br:8080/jspui/handle/123456789/1924.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Corbelino LHG. Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA . [Thesis]. Universidade Federal de Mato Grosso do Sul; 2012. Available from: http://repositorio.cbc.ufms.br:8080/jspui/handle/123456789/1924

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Florida International University

13. Hamedi, Amirmasoud. Advanced Characterization of Hydraulic Structures for Flow Regime Control: Experimental Developement.

Degree: PhD, Civil Engineering, 2017, Florida International University

  A good understanding of flow in a number of hydraulic structures, such as energy dissipators, among others, is needed to effectively control upstream and… (more)

Subjects/Keywords: Hydraulic structures; gate; gate with an expansion; gate with a contraction; flow stability factor; flow stability number; efficiency index; Hydraulic Engineering

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APA (6th Edition):

Hamedi, A. (2017). Advanced Characterization of Hydraulic Structures for Flow Regime Control: Experimental Developement. (Doctoral Dissertation). Florida International University. Retrieved from https://digitalcommons.fiu.edu/etd/3369 ; 10.25148/etd.FIDC001966 ; FIDC001966

Chicago Manual of Style (16th Edition):

Hamedi, Amirmasoud. “Advanced Characterization of Hydraulic Structures for Flow Regime Control: Experimental Developement.” 2017. Doctoral Dissertation, Florida International University. Accessed April 14, 2021. https://digitalcommons.fiu.edu/etd/3369 ; 10.25148/etd.FIDC001966 ; FIDC001966.

MLA Handbook (7th Edition):

Hamedi, Amirmasoud. “Advanced Characterization of Hydraulic Structures for Flow Regime Control: Experimental Developement.” 2017. Web. 14 Apr 2021.

Vancouver:

Hamedi A. Advanced Characterization of Hydraulic Structures for Flow Regime Control: Experimental Developement. [Internet] [Doctoral dissertation]. Florida International University; 2017. [cited 2021 Apr 14]. Available from: https://digitalcommons.fiu.edu/etd/3369 ; 10.25148/etd.FIDC001966 ; FIDC001966.

Council of Science Editors:

Hamedi A. Advanced Characterization of Hydraulic Structures for Flow Regime Control: Experimental Developement. [Doctoral Dissertation]. Florida International University; 2017. Available from: https://digitalcommons.fiu.edu/etd/3369 ; 10.25148/etd.FIDC001966 ; FIDC001966


Delft University of Technology

14. van Lingen, Wouter (author). Modelling the Effects of Gate Pit-Stops on Apron Congestion.

Degree: 2019, Delft University of Technology

Demand for air traffic is growing worldwide. In order to accommodate this growth, existing infrastructure such as gates should be used more efficiently. One technique… (more)

Subjects/Keywords: Gate pit-stops; Gate utilization; Gate allocation; Apron movements; Apron delays; ETS; operations optimization; Aircraft taxiing; Aircraft towing

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APA (6th Edition):

van Lingen, W. (. (2019). Modelling the Effects of Gate Pit-Stops on Apron Congestion. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:d2f70dea-b9d5-40fc-87d9-29ffb3c0c72f

Chicago Manual of Style (16th Edition):

van Lingen, Wouter (author). “Modelling the Effects of Gate Pit-Stops on Apron Congestion.” 2019. Masters Thesis, Delft University of Technology. Accessed April 14, 2021. http://resolver.tudelft.nl/uuid:d2f70dea-b9d5-40fc-87d9-29ffb3c0c72f.

MLA Handbook (7th Edition):

van Lingen, Wouter (author). “Modelling the Effects of Gate Pit-Stops on Apron Congestion.” 2019. Web. 14 Apr 2021.

Vancouver:

van Lingen W(. Modelling the Effects of Gate Pit-Stops on Apron Congestion. [Internet] [Masters thesis]. Delft University of Technology; 2019. [cited 2021 Apr 14]. Available from: http://resolver.tudelft.nl/uuid:d2f70dea-b9d5-40fc-87d9-29ffb3c0c72f.

Council of Science Editors:

van Lingen W(. Modelling the Effects of Gate Pit-Stops on Apron Congestion. [Masters Thesis]. Delft University of Technology; 2019. Available from: http://resolver.tudelft.nl/uuid:d2f70dea-b9d5-40fc-87d9-29ffb3c0c72f

15. Corbelino, Luis Henrique Guimarães. Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA.

Degree: 2012, Brazil

Este trabalho aborda o desenvolvimento, a simulação e a implementação de um sistema automático para realizar o paralelismo entre gerador e a rede elétrica, além… (more)

Subjects/Keywords: Arranjos de Lógica Programável em Campo; Field Programmable Gate Arrays; Circuitos Gate Arrays; Gate Arrays Circuits; Energia Elétrica; Electric Power

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APA (6th Edition):

Corbelino, L. H. G. (2012). Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA. (Masters Thesis). Brazil. Retrieved from https://repositorio.ufms.br/handle/123456789/1924

Chicago Manual of Style (16th Edition):

Corbelino, Luis Henrique Guimarães. “Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA.” 2012. Masters Thesis, Brazil. Accessed April 14, 2021. https://repositorio.ufms.br/handle/123456789/1924.

MLA Handbook (7th Edition):

Corbelino, Luis Henrique Guimarães. “Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA.” 2012. Web. 14 Apr 2021.

Vancouver:

Corbelino LHG. Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA. [Internet] [Masters thesis]. Brazil; 2012. [cited 2021 Apr 14]. Available from: https://repositorio.ufms.br/handle/123456789/1924.

Council of Science Editors:

Corbelino LHG. Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA. [Masters Thesis]. Brazil; 2012. Available from: https://repositorio.ufms.br/handle/123456789/1924


NSYSU

16. Kuo, Yuan-Jui. Electrical Properties and Physical Mechanisms of Advanced MOSFETs.

Degree: PhD, Electro-Optical Engineering, 2010, NSYSU

 In this thesis, we investigate the electrical properties and reliability of novel metal-oxide-semiconductor field-effect transistors (MOSFETs) for 65 nm technology node and below. Roughly, we… (more)

Subjects/Keywords: MOSFETs; metal gate; strained silicon; high-k

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APA (6th Edition):

Kuo, Y. (2010). Electrical Properties and Physical Mechanisms of Advanced MOSFETs. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1220110-174355

Chicago Manual of Style (16th Edition):

Kuo, Yuan-Jui. “Electrical Properties and Physical Mechanisms of Advanced MOSFETs.” 2010. Doctoral Dissertation, NSYSU. Accessed April 14, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1220110-174355.

MLA Handbook (7th Edition):

Kuo, Yuan-Jui. “Electrical Properties and Physical Mechanisms of Advanced MOSFETs.” 2010. Web. 14 Apr 2021.

Vancouver:

Kuo Y. Electrical Properties and Physical Mechanisms of Advanced MOSFETs. [Internet] [Doctoral dissertation]. NSYSU; 2010. [cited 2021 Apr 14]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1220110-174355.

Council of Science Editors:

Kuo Y. Electrical Properties and Physical Mechanisms of Advanced MOSFETs. [Doctoral Dissertation]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1220110-174355

17. 久保, 敦子. モンテカルロシミュレーションを用いた完全データ収集ピンホールSPECTの性能評価 : Evaluation of pinhole SPECT acquisition with complete data-set using monte carlo simulation; モンテカルロ シミュレーション オ モチイタ カンゼン データ シュウシュウ ピンホール SPECT ノ セイノウ ヒョウカ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: ピンホールSPECT; GATE

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APA (6th Edition):

久保, . (n.d.). モンテカルロシミュレーションを用いた完全データ収集ピンホールSPECTの性能評価 : Evaluation of pinhole SPECT acquisition with complete data-set using monte carlo simulation; モンテカルロ シミュレーション オ モチイタ カンゼン データ シュウシュウ ピンホール SPECT ノ セイノウ ヒョウカ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/1364

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

久保, 敦子. “モンテカルロシミュレーションを用いた完全データ収集ピンホールSPECTの性能評価 : Evaluation of pinhole SPECT acquisition with complete data-set using monte carlo simulation; モンテカルロ シミュレーション オ モチイタ カンゼン データ シュウシュウ ピンホール SPECT ノ セイノウ ヒョウカ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed April 14, 2021. http://hdl.handle.net/10061/1364.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

久保, 敦子. “モンテカルロシミュレーションを用いた完全データ収集ピンホールSPECTの性能評価 : Evaluation of pinhole SPECT acquisition with complete data-set using monte carlo simulation; モンテカルロ シミュレーション オ モチイタ カンゼン データ シュウシュウ ピンホール SPECT ノ セイノウ ヒョウカ.” Web. 14 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

久保 . モンテカルロシミュレーションを用いた完全データ収集ピンホールSPECTの性能評価 : Evaluation of pinhole SPECT acquisition with complete data-set using monte carlo simulation; モンテカルロ シミュレーション オ モチイタ カンゼン データ シュウシュウ ピンホール SPECT ノ セイノウ ヒョウカ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2021 Apr 14]. Available from: http://hdl.handle.net/10061/1364.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

久保 . モンテカルロシミュレーションを用いた完全データ収集ピンホールSPECTの性能評価 : Evaluation of pinhole SPECT acquisition with complete data-set using monte carlo simulation; モンテカルロ シミュレーション オ モチイタ カンゼン データ シュウシュウ ピンホール SPECT ノ セイノウ ヒョウカ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/1364

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Dalhousie University

18. Saheb, Zina. TRANSIT AND DC MODEL OF FLOATING GATE TRANSISTOR IN 90NM CMOS TECHNOLOGY.

Degree: Master of Applied Science, Department of Electrical & Computer Engineering, 2013, Dalhousie University

 This thesis presents a new simulation model for floating gate transistor (FGMOS) in nanometer scale technology where the transistors suffer from non-negligible gate leakage current… (more)

Subjects/Keywords: CMOS transistor; 90nm technology; floating gate

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APA (6th Edition):

Saheb, Z. (2013). TRANSIT AND DC MODEL OF FLOATING GATE TRANSISTOR IN 90NM CMOS TECHNOLOGY. (Masters Thesis). Dalhousie University. Retrieved from http://hdl.handle.net/10222/31441

Chicago Manual of Style (16th Edition):

Saheb, Zina. “TRANSIT AND DC MODEL OF FLOATING GATE TRANSISTOR IN 90NM CMOS TECHNOLOGY.” 2013. Masters Thesis, Dalhousie University. Accessed April 14, 2021. http://hdl.handle.net/10222/31441.

MLA Handbook (7th Edition):

Saheb, Zina. “TRANSIT AND DC MODEL OF FLOATING GATE TRANSISTOR IN 90NM CMOS TECHNOLOGY.” 2013. Web. 14 Apr 2021.

Vancouver:

Saheb Z. TRANSIT AND DC MODEL OF FLOATING GATE TRANSISTOR IN 90NM CMOS TECHNOLOGY. [Internet] [Masters thesis]. Dalhousie University; 2013. [cited 2021 Apr 14]. Available from: http://hdl.handle.net/10222/31441.

Council of Science Editors:

Saheb Z. TRANSIT AND DC MODEL OF FLOATING GATE TRANSISTOR IN 90NM CMOS TECHNOLOGY. [Masters Thesis]. Dalhousie University; 2013. Available from: http://hdl.handle.net/10222/31441

19. Vartiainen, Juha J. Unitary Transformations for Quantum Computing.

Degree: 2005, Helsinki University of Technology

The last two decades have seen an enormous increase in the computational power of digital computers. This was due to the rapid technical development in… (more)

Subjects/Keywords: quantum computing; unitary transformations; gate decompositions

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APA (6th Edition):

Vartiainen, J. J. (2005). Unitary Transformations for Quantum Computing. (Thesis). Helsinki University of Technology. Retrieved from http://lib.tkk.fi/Diss/2005/isbn9512276127/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vartiainen, Juha J. “Unitary Transformations for Quantum Computing.” 2005. Thesis, Helsinki University of Technology. Accessed April 14, 2021. http://lib.tkk.fi/Diss/2005/isbn9512276127/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vartiainen, Juha J. “Unitary Transformations for Quantum Computing.” 2005. Web. 14 Apr 2021.

Vancouver:

Vartiainen JJ. Unitary Transformations for Quantum Computing. [Internet] [Thesis]. Helsinki University of Technology; 2005. [cited 2021 Apr 14]. Available from: http://lib.tkk.fi/Diss/2005/isbn9512276127/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vartiainen JJ. Unitary Transformations for Quantum Computing. [Thesis]. Helsinki University of Technology; 2005. Available from: http://lib.tkk.fi/Diss/2005/isbn9512276127/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Riverside

20. Wen, Hua. Towards Magneto-Logic Gates in Graphene.

Degree: Physics, 2014, University of California – Riverside

 Spintronics utilizes electron spin degree of freedom for novel information storage and processing beyond. The key components in spintronics includecreating, manipulating and detecting spins in… (more)

Subjects/Keywords: Physics; Graphene; Logic Gate; Spintronics; Spin valve

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APA (6th Edition):

Wen, H. (2014). Towards Magneto-Logic Gates in Graphene. (Thesis). University of California – Riverside. Retrieved from http://www.escholarship.org/uc/item/8x3346b7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wen, Hua. “Towards Magneto-Logic Gates in Graphene.” 2014. Thesis, University of California – Riverside. Accessed April 14, 2021. http://www.escholarship.org/uc/item/8x3346b7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wen, Hua. “Towards Magneto-Logic Gates in Graphene.” 2014. Web. 14 Apr 2021.

Vancouver:

Wen H. Towards Magneto-Logic Gates in Graphene. [Internet] [Thesis]. University of California – Riverside; 2014. [cited 2021 Apr 14]. Available from: http://www.escholarship.org/uc/item/8x3346b7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wen H. Towards Magneto-Logic Gates in Graphene. [Thesis]. University of California – Riverside; 2014. Available from: http://www.escholarship.org/uc/item/8x3346b7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

21. Mutukuda, Omesh. Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits.

Degree: 2010, Ryerson University

 Field Programmable Gate Arrays (FPGAs) are increasingly being used to implement large datapath-oriented application that are designed to process multiple-bit wide data. Studies have shown… (more)

Subjects/Keywords: Field programmable gate arrays; Integrated circuits

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APA (6th Edition):

Mutukuda, O. (2010). Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1868

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mutukuda, Omesh. “Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits.” 2010. Thesis, Ryerson University. Accessed April 14, 2021. https://digital.library.ryerson.ca/islandora/object/RULA%3A1868.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mutukuda, Omesh. “Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits.” 2010. Web. 14 Apr 2021.

Vancouver:

Mutukuda O. Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits. [Internet] [Thesis]. Ryerson University; 2010. [cited 2021 Apr 14]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1868.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mutukuda O. Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits. [Thesis]. Ryerson University; 2010. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1868

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Kyoto University / 京都大学

22. Zhao, Ming. Studies on High-k Gate Stacks by High-resolution Rutherford Backscattering Spectroscopy : 高分解能ラザフォード後方散乱法による高誘電率ゲートスタック構造に関する研究.

Degree: 博士(工学), 2008, Kyoto University / 京都大学

This thesis is on the study of the characterization of interfaces and surfaces of high-k stacks for the future microelectronics. The changes of the high-k… (more)

Subjects/Keywords: high-k gate stacks; high-resolution RBS

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APA (6th Edition):

Zhao, M. (2008). Studies on High-k Gate Stacks by High-resolution Rutherford Backscattering Spectroscopy : 高分解能ラザフォード後方散乱法による高誘電率ゲートスタック構造に関する研究. (Thesis). Kyoto University / 京都大学. Retrieved from http://hdl.handle.net/2433/57263 ; http://dx.doi.org/10.14989/doctor.k13814

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhao, Ming. “Studies on High-k Gate Stacks by High-resolution Rutherford Backscattering Spectroscopy : 高分解能ラザフォード後方散乱法による高誘電率ゲートスタック構造に関する研究.” 2008. Thesis, Kyoto University / 京都大学. Accessed April 14, 2021. http://hdl.handle.net/2433/57263 ; http://dx.doi.org/10.14989/doctor.k13814.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhao, Ming. “Studies on High-k Gate Stacks by High-resolution Rutherford Backscattering Spectroscopy : 高分解能ラザフォード後方散乱法による高誘電率ゲートスタック構造に関する研究.” 2008. Web. 14 Apr 2021.

Vancouver:

Zhao M. Studies on High-k Gate Stacks by High-resolution Rutherford Backscattering Spectroscopy : 高分解能ラザフォード後方散乱法による高誘電率ゲートスタック構造に関する研究. [Internet] [Thesis]. Kyoto University / 京都大学; 2008. [cited 2021 Apr 14]. Available from: http://hdl.handle.net/2433/57263 ; http://dx.doi.org/10.14989/doctor.k13814.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhao M. Studies on High-k Gate Stacks by High-resolution Rutherford Backscattering Spectroscopy : 高分解能ラザフォード後方散乱法による高誘電率ゲートスタック構造に関する研究. [Thesis]. Kyoto University / 京都大学; 2008. Available from: http://hdl.handle.net/2433/57263 ; http://dx.doi.org/10.14989/doctor.k13814

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. Srivastava, Viranjay Mohan. Analysis and design of double-pole four-throw RF switch by using novel MOSFET Technologies.

Degree: Electronics and Communication, 2013, Jaypee University of Information Technology, Solan

Recently, The Growing Demand Of Low-Power And Low-Cost Wireless Transceivers, Various Integrated Circuit (Ic) Technologies Are Competing To Integrate More Radio Frequency (Rf) Functions Onto… (more)

Subjects/Keywords: Double-Gate MOSFET; Radio Frequency; RF Switch

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APA (6th Edition):

Srivastava, V. M. (2013). Analysis and design of double-pole four-throw RF switch by using novel MOSFET Technologies. (Thesis). Jaypee University of Information Technology, Solan. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/11080

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Srivastava, Viranjay Mohan. “Analysis and design of double-pole four-throw RF switch by using novel MOSFET Technologies.” 2013. Thesis, Jaypee University of Information Technology, Solan. Accessed April 14, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/11080.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Srivastava, Viranjay Mohan. “Analysis and design of double-pole four-throw RF switch by using novel MOSFET Technologies.” 2013. Web. 14 Apr 2021.

Vancouver:

Srivastava VM. Analysis and design of double-pole four-throw RF switch by using novel MOSFET Technologies. [Internet] [Thesis]. Jaypee University of Information Technology, Solan; 2013. [cited 2021 Apr 14]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11080.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Srivastava VM. Analysis and design of double-pole four-throw RF switch by using novel MOSFET Technologies. [Thesis]. Jaypee University of Information Technology, Solan; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/11080

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Kumari, Vandana. Impact of sielectric pocket on dofferent gate geometry mosfet architecture for improved and digital performance modeling and simulation; -.

Degree: Electronic Science, 2013, University of Delhi

Abstract avlible

n.d.

Advisors/Committee Members: Gupta, Mridula and Saxena, Manoj.

Subjects/Keywords: dofferent gate; sielectric

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APA (6th Edition):

Kumari, V. (2013). Impact of sielectric pocket on dofferent gate geometry mosfet architecture for improved and digital performance modeling and simulation; -. (Thesis). University of Delhi. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/36139

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kumari, Vandana. “Impact of sielectric pocket on dofferent gate geometry mosfet architecture for improved and digital performance modeling and simulation; -.” 2013. Thesis, University of Delhi. Accessed April 14, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/36139.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kumari, Vandana. “Impact of sielectric pocket on dofferent gate geometry mosfet architecture for improved and digital performance modeling and simulation; -.” 2013. Web. 14 Apr 2021.

Vancouver:

Kumari V. Impact of sielectric pocket on dofferent gate geometry mosfet architecture for improved and digital performance modeling and simulation; -. [Internet] [Thesis]. University of Delhi; 2013. [cited 2021 Apr 14]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/36139.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kumari V. Impact of sielectric pocket on dofferent gate geometry mosfet architecture for improved and digital performance modeling and simulation; -. [Thesis]. University of Delhi; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/36139

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

25. Singh, Amrinder. Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor.

Degree: MS, Computer Engineering, 2011, Texas A&M University

 In nanometer technologies, process variation control and low power have emerged as the first order design goal after high performance. Process variations cause high variability… (more)

Subjects/Keywords: process variation; double gate; low power

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APA (6th Edition):

Singh, A. (2011). Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488

Chicago Manual of Style (16th Edition):

Singh, Amrinder. “Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor.” 2011. Masters Thesis, Texas A&M University. Accessed April 14, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488.

MLA Handbook (7th Edition):

Singh, Amrinder. “Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor.” 2011. Web. 14 Apr 2021.

Vancouver:

Singh A. Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor. [Internet] [Masters thesis]. Texas A&M University; 2011. [cited 2021 Apr 14]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488.

Council of Science Editors:

Singh A. Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor. [Masters Thesis]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488


Penn State University

26. Sircar, Sarmishtha. Studies of Gas Adsorption in Flexible Metal-organic Frameworks.

Degree: 2014, Penn State University

 Flexible Metal-Organic frameworks that exhibit a gate-opening (GO) adsorption mechanism have potential for gas separations and gas storage. The GO phenomenon occurs when molecular gates… (more)

Subjects/Keywords: Adsorption; Gate-Opening; Metal-Organic Frameworks

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APA (6th Edition):

Sircar, S. (2014). Studies of Gas Adsorption in Flexible Metal-organic Frameworks. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/21037

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sircar, Sarmishtha. “Studies of Gas Adsorption in Flexible Metal-organic Frameworks.” 2014. Thesis, Penn State University. Accessed April 14, 2021. https://submit-etda.libraries.psu.edu/catalog/21037.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sircar, Sarmishtha. “Studies of Gas Adsorption in Flexible Metal-organic Frameworks.” 2014. Web. 14 Apr 2021.

Vancouver:

Sircar S. Studies of Gas Adsorption in Flexible Metal-organic Frameworks. [Internet] [Thesis]. Penn State University; 2014. [cited 2021 Apr 14]. Available from: https://submit-etda.libraries.psu.edu/catalog/21037.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sircar S. Studies of Gas Adsorption in Flexible Metal-organic Frameworks. [Thesis]. Penn State University; 2014. Available from: https://submit-etda.libraries.psu.edu/catalog/21037

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Addis Ababa University

27. Solomon, Hailemichael. DEVELOPMENT OF FPGA BASED SYSTEM ON CHIP FOR LEVEL CROSSING MANAGEMENT SYSTEM IN CASE OF AALRT .

Degree: 2015, Addis Ababa University

 The purpose of this thesis is to develop an automatic railway gate system that uses the FPGA as a main function of design. The principle… (more)

Subjects/Keywords: Level crossing; FPGA; LabVIEW; Automatic gate control

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Solomon, H. (2015). DEVELOPMENT OF FPGA BASED SYSTEM ON CHIP FOR LEVEL CROSSING MANAGEMENT SYSTEM IN CASE OF AALRT . (Thesis). Addis Ababa University. Retrieved from http://etd.aau.edu.et/dspace/handle/123456789/7435

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Solomon, Hailemichael. “DEVELOPMENT OF FPGA BASED SYSTEM ON CHIP FOR LEVEL CROSSING MANAGEMENT SYSTEM IN CASE OF AALRT .” 2015. Thesis, Addis Ababa University. Accessed April 14, 2021. http://etd.aau.edu.et/dspace/handle/123456789/7435.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Solomon, Hailemichael. “DEVELOPMENT OF FPGA BASED SYSTEM ON CHIP FOR LEVEL CROSSING MANAGEMENT SYSTEM IN CASE OF AALRT .” 2015. Web. 14 Apr 2021.

Vancouver:

Solomon H. DEVELOPMENT OF FPGA BASED SYSTEM ON CHIP FOR LEVEL CROSSING MANAGEMENT SYSTEM IN CASE OF AALRT . [Internet] [Thesis]. Addis Ababa University; 2015. [cited 2021 Apr 14]. Available from: http://etd.aau.edu.et/dspace/handle/123456789/7435.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Solomon H. DEVELOPMENT OF FPGA BASED SYSTEM ON CHIP FOR LEVEL CROSSING MANAGEMENT SYSTEM IN CASE OF AALRT . [Thesis]. Addis Ababa University; 2015. Available from: http://etd.aau.edu.et/dspace/handle/123456789/7435

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Pontifical Catholic University of Rio de Janeiro

28. ALEXANDRE JOSE REIS SANTORO. [en] A DATAPATH GENERATING SYSTEM.

Degree: 2009, Pontifical Catholic University of Rio de Janeiro

[pt] Programas de computador já vem sendo utilizados há muito tempo no projeto de circuitos integrados, principalmente para verificação e simulação. Os anos 80 viram… (more)

Subjects/Keywords: [pt] VIA DE DADOS; [pt] GATE MATRIX

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

SANTORO, A. J. R. (2009). [en] A DATAPATH GENERATING SYSTEM. (Thesis). Pontifical Catholic University of Rio de Janeiro. Retrieved from http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14554

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

SANTORO, ALEXANDRE JOSE REIS. “[en] A DATAPATH GENERATING SYSTEM.” 2009. Thesis, Pontifical Catholic University of Rio de Janeiro. Accessed April 14, 2021. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14554.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

SANTORO, ALEXANDRE JOSE REIS. “[en] A DATAPATH GENERATING SYSTEM.” 2009. Web. 14 Apr 2021.

Vancouver:

SANTORO AJR. [en] A DATAPATH GENERATING SYSTEM. [Internet] [Thesis]. Pontifical Catholic University of Rio de Janeiro; 2009. [cited 2021 Apr 14]. Available from: http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14554.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

SANTORO AJR. [en] A DATAPATH GENERATING SYSTEM. [Thesis]. Pontifical Catholic University of Rio de Janeiro; 2009. Available from: http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14554

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Rovira i Virgili

29. Weidemann, Michaela Patricia. Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets.

Degree: Departament d'Enginyeria Electrònica, Elèctrica i Automàtica, 2011, Universitat Rovira i Virgili

 In this thesis the pinch-off behavior in nanoscale Multi-Gate MOSFETs was reviewed and with compact models described. For this a 2D approach with Schwarz-Christoffel conformal… (more)

Subjects/Keywords: Modeling; Nanoscale; Multi-gate; Mosfet; 621.3

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Weidemann, M. P. (2011). Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets. (Thesis). Universitat Rovira i Virgili. Retrieved from http://hdl.handle.net/10803/52800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Weidemann, Michaela Patricia. “Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets.” 2011. Thesis, Universitat Rovira i Virgili. Accessed April 14, 2021. http://hdl.handle.net/10803/52800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Weidemann, Michaela Patricia. “Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets.” 2011. Web. 14 Apr 2021.

Vancouver:

Weidemann MP. Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets. [Internet] [Thesis]. Universitat Rovira i Virgili; 2011. [cited 2021 Apr 14]. Available from: http://hdl.handle.net/10803/52800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Weidemann MP. Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets. [Thesis]. Universitat Rovira i Virgili; 2011. Available from: http://hdl.handle.net/10803/52800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Oxford

30. Sepiol, Martin. A high-fidelity microwave driven two-qubit quantum logic gate in 43Ca+.

Degree: PhD, 2016, University of Oxford

 Quantum computers offer great potential for significant speedup in executing certain algorithms compared to their classical counterparts. One of the most promising physical systems in… (more)

Subjects/Keywords: 006.3; Quantum computing; two-qubit gate

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sepiol, M. (2016). A high-fidelity microwave driven two-qubit quantum logic gate in 43Ca+. (Doctoral Dissertation). University of Oxford. Retrieved from https://ora.ox.ac.uk/objects/uuid:9cafcc3e-32c2-41dc-874d-632dcc402428 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.730135

Chicago Manual of Style (16th Edition):

Sepiol, Martin. “A high-fidelity microwave driven two-qubit quantum logic gate in 43Ca+.” 2016. Doctoral Dissertation, University of Oxford. Accessed April 14, 2021. https://ora.ox.ac.uk/objects/uuid:9cafcc3e-32c2-41dc-874d-632dcc402428 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.730135.

MLA Handbook (7th Edition):

Sepiol, Martin. “A high-fidelity microwave driven two-qubit quantum logic gate in 43Ca+.” 2016. Web. 14 Apr 2021.

Vancouver:

Sepiol M. A high-fidelity microwave driven two-qubit quantum logic gate in 43Ca+. [Internet] [Doctoral dissertation]. University of Oxford; 2016. [cited 2021 Apr 14]. Available from: https://ora.ox.ac.uk/objects/uuid:9cafcc3e-32c2-41dc-874d-632dcc402428 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.730135.

Council of Science Editors:

Sepiol M. A high-fidelity microwave driven two-qubit quantum logic gate in 43Ca+. [Doctoral Dissertation]. University of Oxford; 2016. Available from: https://ora.ox.ac.uk/objects/uuid:9cafcc3e-32c2-41dc-874d-632dcc402428 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.730135

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