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You searched for subject:(Gate array circuits). Showing records 1 – 30 of 41 total matches.

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1. Tan, Zhou. Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.

Degree: 2011, North Dakota State University

 This paper presents the design of a reconfigurable asynchronous unit, called the pulsed quad-cell (PQ-cell), for conformal computing. The conformal computing vision is to create… (more)

Subjects/Keywords: Cellular automata.; Asynchronous circuits.; Pulse circuits.; Field programmable gate arrays.; Gate array circuits.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tan, Z. (2011). Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. (Thesis). North Dakota State University. Retrieved from http://hdl.handle.net/10365/29176

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tan, Zhou. “Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.” 2011. Thesis, North Dakota State University. Accessed August 14, 2020. http://hdl.handle.net/10365/29176.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tan, Zhou. “Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.” 2011. Web. 14 Aug 2020.

Vancouver:

Tan Z. Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. [Internet] [Thesis]. North Dakota State University; 2011. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/10365/29176.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tan Z. Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. [Thesis]. North Dakota State University; 2011. Available from: http://hdl.handle.net/10365/29176

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of South Australia

2. Wigley, Grant Brian. Operating system for reconfigurable computing.

Degree: 2005, University of South Australia

 Field programmable gate arrays are a class of integrated circuit that enable logic functions and interconnects to be programmed in almost real time. They can… (more)

Subjects/Keywords: Integrated circuits; Gate array circuits

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APA (6th Edition):

Wigley, G. B. (2005). Operating system for reconfigurable computing. (Thesis). University of South Australia. Retrieved from http://arrow.unisa.edu.au:8081/1959.8/24992

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wigley, Grant Brian. “Operating system for reconfigurable computing.” 2005. Thesis, University of South Australia. Accessed August 14, 2020. http://arrow.unisa.edu.au:8081/1959.8/24992.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wigley, Grant Brian. “Operating system for reconfigurable computing.” 2005. Web. 14 Aug 2020.

Vancouver:

Wigley GB. Operating system for reconfigurable computing. [Internet] [Thesis]. University of South Australia; 2005. [cited 2020 Aug 14]. Available from: http://arrow.unisa.edu.au:8081/1959.8/24992.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wigley GB. Operating system for reconfigurable computing. [Thesis]. University of South Australia; 2005. Available from: http://arrow.unisa.edu.au:8081/1959.8/24992

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of South Australia

3. Wigley, Grant Brian. An operating system for reconfigurable computing.

Degree: 2005, University of South Australia

 Field programmable gate arrays are a class of integrated circuit that enable logic functions and interconnects to be programmed in almost real time. They can… (more)

Subjects/Keywords: Integrated circuits; Gate array circuits

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APA (6th Edition):

Wigley, G. B. (2005). An operating system for reconfigurable computing. (Thesis). University of South Australia. Retrieved from http://arrow.unisa.edu.au:8081/1959.8/24992 ; http://arrow.unisa.edu.au/vital/access/manager/Repository/unisa:24992

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wigley, Grant Brian. “An operating system for reconfigurable computing.” 2005. Thesis, University of South Australia. Accessed August 14, 2020. http://arrow.unisa.edu.au:8081/1959.8/24992 ; http://arrow.unisa.edu.au/vital/access/manager/Repository/unisa:24992.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wigley, Grant Brian. “An operating system for reconfigurable computing.” 2005. Web. 14 Aug 2020.

Vancouver:

Wigley GB. An operating system for reconfigurable computing. [Internet] [Thesis]. University of South Australia; 2005. [cited 2020 Aug 14]. Available from: http://arrow.unisa.edu.au:8081/1959.8/24992 ; http://arrow.unisa.edu.au/vital/access/manager/Repository/unisa:24992.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wigley GB. An operating system for reconfigurable computing. [Thesis]. University of South Australia; 2005. Available from: http://arrow.unisa.edu.au:8081/1959.8/24992 ; http://arrow.unisa.edu.au/vital/access/manager/Repository/unisa:24992

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Pitcher, Aaron D. Compact Low-Cost Ultra-Wideband Pulsed-Radar System.

Degree: MASc, 2019, McMaster University

Recently, the advent of the integrated circuits (ICs), the monolithic microwave integrated circuits (MMICs) and the multiprocessing computer technology have provided numerous opportunities to make… (more)

Subjects/Keywords: Radar; Ultra Wideband Radar; Field Programmable Gate Array; Microwave Circuits; Microwave Sensors; Sampling Methods

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APA (6th Edition):

Pitcher, A. D. (2019). Compact Low-Cost Ultra-Wideband Pulsed-Radar System. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/24838

Chicago Manual of Style (16th Edition):

Pitcher, Aaron D. “Compact Low-Cost Ultra-Wideband Pulsed-Radar System.” 2019. Masters Thesis, McMaster University. Accessed August 14, 2020. http://hdl.handle.net/11375/24838.

MLA Handbook (7th Edition):

Pitcher, Aaron D. “Compact Low-Cost Ultra-Wideband Pulsed-Radar System.” 2019. Web. 14 Aug 2020.

Vancouver:

Pitcher AD. Compact Low-Cost Ultra-Wideband Pulsed-Radar System. [Internet] [Masters thesis]. McMaster University; 2019. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/11375/24838.

Council of Science Editors:

Pitcher AD. Compact Low-Cost Ultra-Wideband Pulsed-Radar System. [Masters Thesis]. McMaster University; 2019. Available from: http://hdl.handle.net/11375/24838


West Virginia University

5. DiLello, Alexander. Low-Power Reconfigurable Sensing Circuitry for the Internet-of-Things Paradigm.

Degree: PhD, Lane Department of Computer Science and Electrical Engineering, 2019, West Virginia University

  With ubiquitous wireless communication via Wi-Fi and nascent 5th Generation mobile communications, more devices  – both smart and traditionally "dumb"  – will be interconnected… (more)

Subjects/Keywords: Low-power circuits; Field Programmable Analog Array; Integrated Circuit; Floating-Gate Transistor; Electrical and Electronics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

DiLello, A. (2019). Low-Power Reconfigurable Sensing Circuitry for the Internet-of-Things Paradigm. (Doctoral Dissertation). West Virginia University. Retrieved from https://doi.org/10.33915/etd.7386 ; https://researchrepository.wvu.edu/etd/7386

Chicago Manual of Style (16th Edition):

DiLello, Alexander. “Low-Power Reconfigurable Sensing Circuitry for the Internet-of-Things Paradigm.” 2019. Doctoral Dissertation, West Virginia University. Accessed August 14, 2020. https://doi.org/10.33915/etd.7386 ; https://researchrepository.wvu.edu/etd/7386.

MLA Handbook (7th Edition):

DiLello, Alexander. “Low-Power Reconfigurable Sensing Circuitry for the Internet-of-Things Paradigm.” 2019. Web. 14 Aug 2020.

Vancouver:

DiLello A. Low-Power Reconfigurable Sensing Circuitry for the Internet-of-Things Paradigm. [Internet] [Doctoral dissertation]. West Virginia University; 2019. [cited 2020 Aug 14]. Available from: https://doi.org/10.33915/etd.7386 ; https://researchrepository.wvu.edu/etd/7386.

Council of Science Editors:

DiLello A. Low-Power Reconfigurable Sensing Circuitry for the Internet-of-Things Paradigm. [Doctoral Dissertation]. West Virginia University; 2019. Available from: https://doi.org/10.33915/etd.7386 ; https://researchrepository.wvu.edu/etd/7386


University of Arizona

6. Hu, Jhy-Fang, 1961-. AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY .

Degree: 1986, University of Arizona

Subjects/Keywords: Compiling (Electronic computers); Gate array circuits.

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APA (6th Edition):

Hu, Jhy-Fang, 1. (1986). AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/276948

Chicago Manual of Style (16th Edition):

Hu, Jhy-Fang, 1961-. “AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY .” 1986. Masters Thesis, University of Arizona. Accessed August 14, 2020. http://hdl.handle.net/10150/276948.

MLA Handbook (7th Edition):

Hu, Jhy-Fang, 1961-. “AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY .” 1986. Web. 14 Aug 2020.

Vancouver:

Hu, Jhy-Fang 1. AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY . [Internet] [Masters thesis]. University of Arizona; 1986. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/10150/276948.

Council of Science Editors:

Hu, Jhy-Fang 1. AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY . [Masters Thesis]. University of Arizona; 1986. Available from: http://hdl.handle.net/10150/276948


Drexel University

7. Balog, Michael. The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration.

Degree: 2007, Drexel University

Over the past few years FPGA hardware has become a logical choice for implementing cutting-edge signal processing applications. While there have been advances in FPGA… (more)

Subjects/Keywords: Electric engineering; Field programmable gate arrays; Gate array circuits

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APA (6th Edition):

Balog, M. (2007). The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration. (Thesis). Drexel University. Retrieved from http://hdl.handle.net/1860/1770

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Balog, Michael. “The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration.” 2007. Thesis, Drexel University. Accessed August 14, 2020. http://hdl.handle.net/1860/1770.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Balog, Michael. “The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration.” 2007. Web. 14 Aug 2020.

Vancouver:

Balog M. The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration. [Internet] [Thesis]. Drexel University; 2007. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/1860/1770.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Balog M. The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration. [Thesis]. Drexel University; 2007. Available from: http://hdl.handle.net/1860/1770

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Portland State University

8. Schafer, Ingo. Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping.

Degree: PhD, Electrical and Computer Engineering, 1992, Portland State University

  The growing complexity of integrated circuits and the large variety of architectures of Field Programmable Gate Arrays (FPGAs) require sophisticated logic design tools. In… (more)

Subjects/Keywords: Spectral theory (Mathematics); Logic design; Gate array circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Schafer, I. (1992). Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping. (Doctoral Dissertation). Portland State University. Retrieved from http://pdxscholar.library.pdx.edu/open_access_etds/1339

Chicago Manual of Style (16th Edition):

Schafer, Ingo. “Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping.” 1992. Doctoral Dissertation, Portland State University. Accessed August 14, 2020. http://pdxscholar.library.pdx.edu/open_access_etds/1339.

MLA Handbook (7th Edition):

Schafer, Ingo. “Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping.” 1992. Web. 14 Aug 2020.

Vancouver:

Schafer I. Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping. [Internet] [Doctoral dissertation]. Portland State University; 1992. [cited 2020 Aug 14]. Available from: http://pdxscholar.library.pdx.edu/open_access_etds/1339.

Council of Science Editors:

Schafer I. Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping. [Doctoral Dissertation]. Portland State University; 1992. Available from: http://pdxscholar.library.pdx.edu/open_access_etds/1339


Virginia Tech

9. Baweja, Gunjeetsingh. Gate level coverage of a behavioral test generator.

Degree: MS, Electrical Engineering, 1993, Virginia Tech

 Use of traditional gate level test generation techniques is prohibitively expensive and time consuming for VLSI chips. High level approaches to test generation have been… (more)

Subjects/Keywords: Gate array circuits.; LD5655.V855 1993.B394

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APA (6th Edition):

Baweja, G. (1993). Gate level coverage of a behavioral test generator. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/45598

Chicago Manual of Style (16th Edition):

Baweja, Gunjeetsingh. “Gate level coverage of a behavioral test generator.” 1993. Masters Thesis, Virginia Tech. Accessed August 14, 2020. http://hdl.handle.net/10919/45598.

MLA Handbook (7th Edition):

Baweja, Gunjeetsingh. “Gate level coverage of a behavioral test generator.” 1993. Web. 14 Aug 2020.

Vancouver:

Baweja G. Gate level coverage of a behavioral test generator. [Internet] [Masters thesis]. Virginia Tech; 1993. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/10919/45598.

Council of Science Editors:

Baweja G. Gate level coverage of a behavioral test generator. [Masters Thesis]. Virginia Tech; 1993. Available from: http://hdl.handle.net/10919/45598


Rhodes University

10. Myburgh, Talon. Finite precision arithmetic in Polyphase Filterbank implementations.

Degree: Faculty of Science, Physics and Electronics, 2020, Rhodes University

 The MeerKAT is the most sensitive radio telescope in its class, and it is important that systematic effects do not limit the dynamic range of… (more)

Subjects/Keywords: Radio interferometers; Interferometry; Radio telescopes; Gate array circuits; Floating-point arithmetic; Python (Computer program language); Polyphase Filterbank; Finite precision arithmetic; MeerKAT

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APA (6th Edition):

Myburgh, T. (2020). Finite precision arithmetic in Polyphase Filterbank implementations. (Thesis). Rhodes University. Retrieved from http://hdl.handle.net/10962/146187

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Myburgh, Talon. “Finite precision arithmetic in Polyphase Filterbank implementations.” 2020. Thesis, Rhodes University. Accessed August 14, 2020. http://hdl.handle.net/10962/146187.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Myburgh, Talon. “Finite precision arithmetic in Polyphase Filterbank implementations.” 2020. Web. 14 Aug 2020.

Vancouver:

Myburgh T. Finite precision arithmetic in Polyphase Filterbank implementations. [Internet] [Thesis]. Rhodes University; 2020. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/10962/146187.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Myburgh T. Finite precision arithmetic in Polyphase Filterbank implementations. [Thesis]. Rhodes University; 2020. Available from: http://hdl.handle.net/10962/146187

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas Tech University

11. Mehta, Narendra Singh. Investigation of advanced gate dielectrics for future complementary metal-oxide semiconductor devices.

Degree: Electrical and Computer Engineering, 2002, Texas Tech University

Subjects/Keywords: Complementary; Dielectrics; Gate array circuits; Metal oxide semiconductors

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APA (6th Edition):

Mehta, N. S. (2002). Investigation of advanced gate dielectrics for future complementary metal-oxide semiconductor devices. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/15731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mehta, Narendra Singh. “Investigation of advanced gate dielectrics for future complementary metal-oxide semiconductor devices.” 2002. Thesis, Texas Tech University. Accessed August 14, 2020. http://hdl.handle.net/2346/15731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mehta, Narendra Singh. “Investigation of advanced gate dielectrics for future complementary metal-oxide semiconductor devices.” 2002. Web. 14 Aug 2020.

Vancouver:

Mehta NS. Investigation of advanced gate dielectrics for future complementary metal-oxide semiconductor devices. [Internet] [Thesis]. Texas Tech University; 2002. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/2346/15731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mehta NS. Investigation of advanced gate dielectrics for future complementary metal-oxide semiconductor devices. [Thesis]. Texas Tech University; 2002. Available from: http://hdl.handle.net/2346/15731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Michigan State University

12. Kucher, Paul R. Design and evaluation of an automated test platform for large-scale analog floating gate array programming.

Degree: MS, Department of Electrical and Computer Engineering, 2007, Michigan State University

Subjects/Keywords: Gate array circuits; Systems on a chip; Field programmable gate arrays; Power electronics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kucher, P. R. (2007). Design and evaluation of an automated test platform for large-scale analog floating gate array programming. (Masters Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:38898

Chicago Manual of Style (16th Edition):

Kucher, Paul R. “Design and evaluation of an automated test platform for large-scale analog floating gate array programming.” 2007. Masters Thesis, Michigan State University. Accessed August 14, 2020. http://etd.lib.msu.edu/islandora/object/etd:38898.

MLA Handbook (7th Edition):

Kucher, Paul R. “Design and evaluation of an automated test platform for large-scale analog floating gate array programming.” 2007. Web. 14 Aug 2020.

Vancouver:

Kucher PR. Design and evaluation of an automated test platform for large-scale analog floating gate array programming. [Internet] [Masters thesis]. Michigan State University; 2007. [cited 2020 Aug 14]. Available from: http://etd.lib.msu.edu/islandora/object/etd:38898.

Council of Science Editors:

Kucher PR. Design and evaluation of an automated test platform for large-scale analog floating gate array programming. [Masters Thesis]. Michigan State University; 2007. Available from: http://etd.lib.msu.edu/islandora/object/etd:38898


Texas Tech University

13. Morris, Ben. Investigation of ultra-high switching frequency to reduce size in rapid capacitor charging.

Degree: Electrical and Computer Engineering, 2004, Texas Tech University

 This project concerned itself with two different chargers, both based on the same principle designs but both having fundamentally different output and input requirements and… (more)

Subjects/Keywords: Capacitors; Switching circuits; Switching theory; Electric inductors; Gate array circuits

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APA (6th Edition):

Morris, B. (2004). Investigation of ultra-high switching frequency to reduce size in rapid capacitor charging. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/9064

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Morris, Ben. “Investigation of ultra-high switching frequency to reduce size in rapid capacitor charging.” 2004. Thesis, Texas Tech University. Accessed August 14, 2020. http://hdl.handle.net/2346/9064.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Morris, Ben. “Investigation of ultra-high switching frequency to reduce size in rapid capacitor charging.” 2004. Web. 14 Aug 2020.

Vancouver:

Morris B. Investigation of ultra-high switching frequency to reduce size in rapid capacitor charging. [Internet] [Thesis]. Texas Tech University; 2004. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/2346/9064.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Morris B. Investigation of ultra-high switching frequency to reduce size in rapid capacitor charging. [Thesis]. Texas Tech University; 2004. Available from: http://hdl.handle.net/2346/9064

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

14. Hall, Tyson Stuart. Field-Programmable Analog Arrays: A Floating-Gate Approach.

Degree: PhD, Electrical and Computer Engineering, 2004, Georgia Tech

 Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or… (more)

Subjects/Keywords: Field programmable analog array; Analog array; FPAA; Reconfigurable; Floating gate; Field programmable gate arrays; Gate array circuits; Analog electronic systems Design and construction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hall, T. S. (2004). Field-Programmable Analog Arrays: A Floating-Gate Approach. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/5071

Chicago Manual of Style (16th Edition):

Hall, Tyson Stuart. “Field-Programmable Analog Arrays: A Floating-Gate Approach.” 2004. Doctoral Dissertation, Georgia Tech. Accessed August 14, 2020. http://hdl.handle.net/1853/5071.

MLA Handbook (7th Edition):

Hall, Tyson Stuart. “Field-Programmable Analog Arrays: A Floating-Gate Approach.” 2004. Web. 14 Aug 2020.

Vancouver:

Hall TS. Field-Programmable Analog Arrays: A Floating-Gate Approach. [Internet] [Doctoral dissertation]. Georgia Tech; 2004. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/1853/5071.

Council of Science Editors:

Hall TS. Field-Programmable Analog Arrays: A Floating-Gate Approach. [Doctoral Dissertation]. Georgia Tech; 2004. Available from: http://hdl.handle.net/1853/5071


Georgia Tech

15. Gray, Jordan D. Application of Floating-Gate Transistors in Field Programmable Analog Arrays.

Degree: MS, Electrical and Computer Engineering, 2005, Georgia Tech

 Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can… (more)

Subjects/Keywords: Analog; Antenna arrays; Field programmable analog array; Field programmable gate arrays; Floating gate; Floating gate analog; Floating gate switch; FPAA; Gate array circuits; Integrated circuits Very large scale integration; MITE; Reconfigurable analog; Semiconductor storage devices

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APA (6th Edition):

Gray, J. D. (2005). Application of Floating-Gate Transistors in Field Programmable Analog Arrays. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/7540

Chicago Manual of Style (16th Edition):

Gray, Jordan D. “Application of Floating-Gate Transistors in Field Programmable Analog Arrays.” 2005. Masters Thesis, Georgia Tech. Accessed August 14, 2020. http://hdl.handle.net/1853/7540.

MLA Handbook (7th Edition):

Gray, Jordan D. “Application of Floating-Gate Transistors in Field Programmable Analog Arrays.” 2005. Web. 14 Aug 2020.

Vancouver:

Gray JD. Application of Floating-Gate Transistors in Field Programmable Analog Arrays. [Internet] [Masters thesis]. Georgia Tech; 2005. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/1853/7540.

Council of Science Editors:

Gray JD. Application of Floating-Gate Transistors in Field Programmable Analog Arrays. [Masters Thesis]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/7540


University of North Texas

16. Zhuo, Yue. Timing and Congestion Driven Algorithms for FPGA Placement.

Degree: 2006, University of North Texas

 Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the… (more)

Subjects/Keywords: Field programmable gate arrays.; Signal processing  – Digital techniques.; Programmable array logic.; Gate array circuits.; placement; timing; congestion; FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhuo, Y. (2006). Timing and Congestion Driven Algorithms for FPGA Placement. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc5423/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhuo, Yue. “Timing and Congestion Driven Algorithms for FPGA Placement.” 2006. Thesis, University of North Texas. Accessed August 14, 2020. https://digital.library.unt.edu/ark:/67531/metadc5423/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhuo, Yue. “Timing and Congestion Driven Algorithms for FPGA Placement.” 2006. Web. 14 Aug 2020.

Vancouver:

Zhuo Y. Timing and Congestion Driven Algorithms for FPGA Placement. [Internet] [Thesis]. University of North Texas; 2006. [cited 2020 Aug 14]. Available from: https://digital.library.unt.edu/ark:/67531/metadc5423/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhuo Y. Timing and Congestion Driven Algorithms for FPGA Placement. [Thesis]. University of North Texas; 2006. Available from: https://digital.library.unt.edu/ark:/67531/metadc5423/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas Tech University

17. Osmulski, Timothy A. Implementation of a probabilistic model for predicting power consumption of a field programmable gate array.

Degree: Computer Science, 1998, Texas Tech University

 As configurable computing devices like FPGAs gain popularity as application-specific computing solutions, the special problems presented by these devices must be considered. For example, the… (more)

Subjects/Keywords: Programmable logic devices  – Design and construction; Field programmable gate arrays  – Design and construction; Gate array circuits; Application specific integrated circuits  – Power

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APA (6th Edition):

Osmulski, T. A. (1998). Implementation of a probabilistic model for predicting power consumption of a field programmable gate array. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/9241

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Osmulski, Timothy A. “Implementation of a probabilistic model for predicting power consumption of a field programmable gate array.” 1998. Thesis, Texas Tech University. Accessed August 14, 2020. http://hdl.handle.net/2346/9241.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Osmulski, Timothy A. “Implementation of a probabilistic model for predicting power consumption of a field programmable gate array.” 1998. Web. 14 Aug 2020.

Vancouver:

Osmulski TA. Implementation of a probabilistic model for predicting power consumption of a field programmable gate array. [Internet] [Thesis]. Texas Tech University; 1998. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/2346/9241.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Osmulski TA. Implementation of a probabilistic model for predicting power consumption of a field programmable gate array. [Thesis]. Texas Tech University; 1998. Available from: http://hdl.handle.net/2346/9241

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas Tech University

18. Veale, Brian F. Study of power consumption for high-performance reconfigurable computing architectures.

Degree: Computer Science, 1999, Texas Tech University

 As reconfigurable computing devices, such as field programmable gate arrays (FPGAs), become a more popular choice for the implementation of custom computing systems, the special… (more)

Subjects/Keywords: Computer software  – Reusability; Computers  – Circuits  – Design and construction; Field-programmable gate arrays (FPGA); Gate array circuits  – Design; Energy consumption  – Analysis

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APA (6th Edition):

Veale, B. F. (1999). Study of power consumption for high-performance reconfigurable computing architectures. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/13665

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Veale, Brian F. “Study of power consumption for high-performance reconfigurable computing architectures.” 1999. Thesis, Texas Tech University. Accessed August 14, 2020. http://hdl.handle.net/2346/13665.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Veale, Brian F. “Study of power consumption for high-performance reconfigurable computing architectures.” 1999. Web. 14 Aug 2020.

Vancouver:

Veale BF. Study of power consumption for high-performance reconfigurable computing architectures. [Internet] [Thesis]. Texas Tech University; 1999. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/2346/13665.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Veale BF. Study of power consumption for high-performance reconfigurable computing architectures. [Thesis]. Texas Tech University; 1999. Available from: http://hdl.handle.net/2346/13665

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

19. Lotfabadi, Shahin S. Measuring the Power Efficiency Of Subthreshold FPGAs For Implementing Portable Biomedical Applications.

Degree: 2011, Ryerson University

 Power is a significant design constraint for implementing portable applications. Operating transistors in the subthreshold region can significantly reduce power consumption while reducing performance. The… (more)

Subjects/Keywords: Signal processing  – Digital techniques; Field programmable gate array  – Computer-aided design  – Data processing; Portable computerized instruments  – Power consumption; Low voltage integrated circuits; Medical electronics

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APA (6th Edition):

Lotfabadi, S. S. (2011). Measuring the Power Efficiency Of Subthreshold FPGAs For Implementing Portable Biomedical Applications. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1940

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lotfabadi, Shahin S. “Measuring the Power Efficiency Of Subthreshold FPGAs For Implementing Portable Biomedical Applications.” 2011. Thesis, Ryerson University. Accessed August 14, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A1940.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lotfabadi, Shahin S. “Measuring the Power Efficiency Of Subthreshold FPGAs For Implementing Portable Biomedical Applications.” 2011. Web. 14 Aug 2020.

Vancouver:

Lotfabadi SS. Measuring the Power Efficiency Of Subthreshold FPGAs For Implementing Portable Biomedical Applications. [Internet] [Thesis]. Ryerson University; 2011. [cited 2020 Aug 14]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1940.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lotfabadi SS. Measuring the Power Efficiency Of Subthreshold FPGAs For Implementing Portable Biomedical Applications. [Thesis]. Ryerson University; 2011. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1940

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Hong Kong

20. 林立旻. A study of gate dielectrics for wide-bandgap semiconductors: GaN & SiC.

Degree: 2007, University of Hong Kong

Subjects/Keywords: Dielectrics.; Wide gap semiconductors.; Gallium nitride.; Silicon carbide.; Gate array circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

林立旻. (2007). A study of gate dielectrics for wide-bandgap semiconductors: GaN & SiC. (Thesis). University of Hong Kong. Retrieved from http://hdl.handle.net/10722/51518

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

林立旻. “A study of gate dielectrics for wide-bandgap semiconductors: GaN & SiC.” 2007. Thesis, University of Hong Kong. Accessed August 14, 2020. http://hdl.handle.net/10722/51518.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

林立旻. “A study of gate dielectrics for wide-bandgap semiconductors: GaN & SiC.” 2007. Web. 14 Aug 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

林立旻. A study of gate dielectrics for wide-bandgap semiconductors: GaN & SiC. [Internet] [Thesis]. University of Hong Kong; 2007. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/10722/51518.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

林立旻. A study of gate dielectrics for wide-bandgap semiconductors: GaN & SiC. [Thesis]. University of Hong Kong; 2007. Available from: http://hdl.handle.net/10722/51518

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

21. Vrana, Gregory Michael. An automatic placement algorithm for high-density gate arrays.

Degree: MS, electrical engineering, 2012, Texas A&M University

Subjects/Keywords: electrical engineering.; Major electrical engineering.; Gate array circuits.; Electronic circuit design.; Algorithms.

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APA (6th Edition):

Vrana, G. M. (2012). An automatic placement algorithm for high-density gate arrays. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1987-THESIS-V978

Chicago Manual of Style (16th Edition):

Vrana, Gregory Michael. “An automatic placement algorithm for high-density gate arrays.” 2012. Masters Thesis, Texas A&M University. Accessed August 14, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-1987-THESIS-V978.

MLA Handbook (7th Edition):

Vrana, Gregory Michael. “An automatic placement algorithm for high-density gate arrays.” 2012. Web. 14 Aug 2020.

Vancouver:

Vrana GM. An automatic placement algorithm for high-density gate arrays. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1987-THESIS-V978.

Council of Science Editors:

Vrana GM. An automatic placement algorithm for high-density gate arrays. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1987-THESIS-V978

22. Krishnamurthy, Akilesh. Design of an FPGA-based Array Formatter for Casa Phase-Tilt Radar System.

Degree: MS, Electrical & Computer Engineering, 2011, University of Massachusetts

  Weather monitoring and forecasting systems have witnessed rapid advancement in recent years. However, one of the main challenges faced by these systems is poor… (more)

Subjects/Keywords: Field Programmable Gate Array (FPGA); System Design; Data Processing; Soft Processor; Radar Controller; Phased-Arrays; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Krishnamurthy, A. (2011). Design of an FPGA-based Array Formatter for Casa Phase-Tilt Radar System. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/691

Chicago Manual of Style (16th Edition):

Krishnamurthy, Akilesh. “Design of an FPGA-based Array Formatter for Casa Phase-Tilt Radar System.” 2011. Masters Thesis, University of Massachusetts. Accessed August 14, 2020. https://scholarworks.umass.edu/theses/691.

MLA Handbook (7th Edition):

Krishnamurthy, Akilesh. “Design of an FPGA-based Array Formatter for Casa Phase-Tilt Radar System.” 2011. Web. 14 Aug 2020.

Vancouver:

Krishnamurthy A. Design of an FPGA-based Array Formatter for Casa Phase-Tilt Radar System. [Internet] [Masters thesis]. University of Massachusetts; 2011. [cited 2020 Aug 14]. Available from: https://scholarworks.umass.edu/theses/691.

Council of Science Editors:

Krishnamurthy A. Design of an FPGA-based Array Formatter for Casa Phase-Tilt Radar System. [Masters Thesis]. University of Massachusetts; 2011. Available from: https://scholarworks.umass.edu/theses/691


Portland State University

23. Wu, Lifei. Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 1993, Portland State University

  The new family of Field Programmable Gate Arrays, CLI 6000 from Concurrent Logic Inc realizes truly Cellular Logic. It has been mainly designed for… (more)

Subjects/Keywords: Gate array circuits; Programmable logic devices; Computer algorithms; Electrical and Computer Engineering

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APA (6th Edition):

Wu, L. (1993). Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/4745

Chicago Manual of Style (16th Edition):

Wu, Lifei. “Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays.” 1993. Masters Thesis, Portland State University. Accessed August 14, 2020. https://pdxscholar.library.pdx.edu/open_access_etds/4745.

MLA Handbook (7th Edition):

Wu, Lifei. “Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays.” 1993. Web. 14 Aug 2020.

Vancouver:

Wu L. Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays. [Internet] [Masters thesis]. Portland State University; 1993. [cited 2020 Aug 14]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4745.

Council of Science Editors:

Wu L. Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays. [Masters Thesis]. Portland State University; 1993. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4745


University of Texas – Austin

24. Fan, Yang-yu. Voltage and temperature dependent gate capacitance and current model for high-K gate dielectric stack.

Degree: PhD, Electrical and Computer Engineering, 2002, University of Texas – Austin

Subjects/Keywords: Gate array circuits; Dielectrics; Metal oxide semiconductor field-effect transistors

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APA (6th Edition):

Fan, Y. (2002). Voltage and temperature dependent gate capacitance and current model for high-K gate dielectric stack. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/567

Chicago Manual of Style (16th Edition):

Fan, Yang-yu. “Voltage and temperature dependent gate capacitance and current model for high-K gate dielectric stack.” 2002. Doctoral Dissertation, University of Texas – Austin. Accessed August 14, 2020. http://hdl.handle.net/2152/567.

MLA Handbook (7th Edition):

Fan, Yang-yu. “Voltage and temperature dependent gate capacitance and current model for high-K gate dielectric stack.” 2002. Web. 14 Aug 2020.

Vancouver:

Fan Y. Voltage and temperature dependent gate capacitance and current model for high-K gate dielectric stack. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2002. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/2152/567.

Council of Science Editors:

Fan Y. Voltage and temperature dependent gate capacitance and current model for high-K gate dielectric stack. [Doctoral Dissertation]. University of Texas – Austin; 2002. Available from: http://hdl.handle.net/2152/567


University of Hong Kong

25. Deng, Linfeng. A study on pentacene organic thin-film transistors with Hf-based oxideas gate dielectric.

Degree: 2011, University of Hong Kong

 Compared with its inorganic counterpart, organic thin-film transistor (OTFT) has advantages such as low-temperature fabrication, adaptability to large-area flexible substrate, and low cost. However, they… (more)

Subjects/Keywords: Thin film transistors.; Organic thin films.; Gate array circuits.; Dielectrics.; Hafnium oxide.

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APA (6th Edition):

Deng, L. (2011). A study on pentacene organic thin-film transistors with Hf-based oxideas gate dielectric. (Thesis). University of Hong Kong. Retrieved from http://hdl.handle.net/10722/146134

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Deng, Linfeng. “A study on pentacene organic thin-film transistors with Hf-based oxideas gate dielectric.” 2011. Thesis, University of Hong Kong. Accessed August 14, 2020. http://hdl.handle.net/10722/146134.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Deng, Linfeng. “A study on pentacene organic thin-film transistors with Hf-based oxideas gate dielectric.” 2011. Web. 14 Aug 2020.

Vancouver:

Deng L. A study on pentacene organic thin-film transistors with Hf-based oxideas gate dielectric. [Internet] [Thesis]. University of Hong Kong; 2011. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/10722/146134.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Deng L. A study on pentacene organic thin-film transistors with Hf-based oxideas gate dielectric. [Thesis]. University of Hong Kong; 2011. Available from: http://hdl.handle.net/10722/146134

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

26. Gullette, James Benjamin. A laser-programmable gate array.

Degree: MS, electrical engineering, 2012, Texas A&M University

Subjects/Keywords: electrical engineering.; Major electrical engineering.; Gate array circuits.; Lasers.; Integrated circuits - Large scale integration.

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APA (6th Edition):

Gullette, J. B. (2012). A laser-programmable gate array. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1985-THESIS-G973

Chicago Manual of Style (16th Edition):

Gullette, James Benjamin. “A laser-programmable gate array.” 2012. Masters Thesis, Texas A&M University. Accessed August 14, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-1985-THESIS-G973.

MLA Handbook (7th Edition):

Gullette, James Benjamin. “A laser-programmable gate array.” 2012. Web. 14 Aug 2020.

Vancouver:

Gullette JB. A laser-programmable gate array. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1985-THESIS-G973.

Council of Science Editors:

Gullette JB. A laser-programmable gate array. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1985-THESIS-G973


Texas A&M University

27. Kwan, King-Wai. A comparison of the full custom, standard cell and gate array design methodologies.

Degree: MS, electrical engineering, 2012, Texas A&M University

Subjects/Keywords: electrical engineering.; Major electrical engineering.; Integrated circuits - Very large scale integration - Design and construction.; Gate array circuits.

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APA (6th Edition):

Kwan, K. (2012). A comparison of the full custom, standard cell and gate array design methodologies. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1990-THESIS-K98

Chicago Manual of Style (16th Edition):

Kwan, King-Wai. “A comparison of the full custom, standard cell and gate array design methodologies.” 2012. Masters Thesis, Texas A&M University. Accessed August 14, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-1990-THESIS-K98.

MLA Handbook (7th Edition):

Kwan, King-Wai. “A comparison of the full custom, standard cell and gate array design methodologies.” 2012. Web. 14 Aug 2020.

Vancouver:

Kwan K. A comparison of the full custom, standard cell and gate array design methodologies. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1990-THESIS-K98.

Council of Science Editors:

Kwan K. A comparison of the full custom, standard cell and gate array design methodologies. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1990-THESIS-K98


Texas Tech University

28. Rathinaswami, Selliah C. Efficient algorithms for gate matrix layout.

Degree: Computer Science, 1988, Texas Tech University

Subjects/Keywords: Metal oxide semiconductors; Complementary; Integrated circuits  – Very large scale integration; Computer-aided design; Gate array circuits

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APA (6th Edition):

Rathinaswami, S. C. (1988). Efficient algorithms for gate matrix layout. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/9639

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rathinaswami, Selliah C. “Efficient algorithms for gate matrix layout.” 1988. Thesis, Texas Tech University. Accessed August 14, 2020. http://hdl.handle.net/2346/9639.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rathinaswami, Selliah C. “Efficient algorithms for gate matrix layout.” 1988. Web. 14 Aug 2020.

Vancouver:

Rathinaswami SC. Efficient algorithms for gate matrix layout. [Internet] [Thesis]. Texas Tech University; 1988. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/2346/9639.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rathinaswami SC. Efficient algorithms for gate matrix layout. [Thesis]. Texas Tech University; 1988. Available from: http://hdl.handle.net/2346/9639

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arizona

29. Zhou, Jing. LOVERD – a logic design verification and diagnosis system via test generation .

Degree: 1989, University of Arizona

 The development of cost-effective circuits is primarily a matter of economy. To achieve it, design errors and circuit flaws must be eliminated during the design… (more)

Subjects/Keywords: Computer-aided design  – Evaluation.; Logic design.; Logic circuits  – Design and construction.; Gate array circuits  – Design and construction.

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APA (6th Edition):

Zhou, J. (1989). LOVERD – a logic design verification and diagnosis system via test generation . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/291686

Chicago Manual of Style (16th Edition):

Zhou, Jing. “LOVERD – a logic design verification and diagnosis system via test generation .” 1989. Masters Thesis, University of Arizona. Accessed August 14, 2020. http://hdl.handle.net/10150/291686.

MLA Handbook (7th Edition):

Zhou, Jing. “LOVERD – a logic design verification and diagnosis system via test generation .” 1989. Web. 14 Aug 2020.

Vancouver:

Zhou J. LOVERD – a logic design verification and diagnosis system via test generation . [Internet] [Masters thesis]. University of Arizona; 1989. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/10150/291686.

Council of Science Editors:

Zhou J. LOVERD – a logic design verification and diagnosis system via test generation . [Masters Thesis]. University of Arizona; 1989. Available from: http://hdl.handle.net/10150/291686


Washington University in St. Louis

30. Harris, Steven. Investigating Single Precision Floating General Matrix Multiply in Heterogeneous.

Degree: MS, Computer Science & Engineering, 2020, Washington University in St. Louis

 The fundamental operation of matrix multiplication is ubiquitous across a myriad of disciplines. Yet, the identification of new optimizations for matrix multiplication remains relevant for… (more)

Subjects/Keywords: Design space search; HARP; High-level synthesis; OpenCL; SGEMM; Field programmable gate array; heterogeneous architecture; Computer and Systems Architecture; Engineering; Hardware Systems; Numerical Analysis and Scientific Computing; Software Engineering; Systems Architecture; Theory and Algorithms; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Harris, S. (2020). Investigating Single Precision Floating General Matrix Multiply in Heterogeneous. (Thesis). Washington University in St. Louis. Retrieved from https://openscholarship.wustl.edu/eng_etds/536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harris, Steven. “Investigating Single Precision Floating General Matrix Multiply in Heterogeneous.” 2020. Thesis, Washington University in St. Louis. Accessed August 14, 2020. https://openscholarship.wustl.edu/eng_etds/536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harris, Steven. “Investigating Single Precision Floating General Matrix Multiply in Heterogeneous.” 2020. Web. 14 Aug 2020.

Vancouver:

Harris S. Investigating Single Precision Floating General Matrix Multiply in Heterogeneous. [Internet] [Thesis]. Washington University in St. Louis; 2020. [cited 2020 Aug 14]. Available from: https://openscholarship.wustl.edu/eng_etds/536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harris S. Investigating Single Precision Floating General Matrix Multiply in Heterogeneous. [Thesis]. Washington University in St. Louis; 2020. Available from: https://openscholarship.wustl.edu/eng_etds/536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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