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You searched for subject:(Gate Delay Models). Showing records 1 – 3 of 3 total matches.

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Indian Institute of Science

1. Das, Bishnu Prasad. Random Local Delay Variability : On-chip Measurement And Modeling.

Degree: 2009, Indian Institute of Science

This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in silicon to study within-die variation. It also suggests a Process, Voltage and Temperature (PVT)-aware gate delay model for voltage and temperature scalable linear Statistical Static Timing Analysis (SSTA). Technology scaling allows packing billions of transistors inside a single chip. However, it is difficult to fabricate very small transistor with deterministic characteristic which leads to variations. Transistor level random local variations are growing rapidly in each technology generation. However, there is requirement of quantification of variation in silicon. We propose an all-digital circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form based on a reconfigurable ring oscillator structure. A test chip is fabricated in 65nm technology node to show the feasibility of the technique. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. The huge random delay variation in silicon motivates the inclusion of random local process parameters in delay model. In today’s low power design with multiple supply domain leads to non-uniform supply profile. The switching activity across the chip is not uniform which leads to variation of temperature. Accurate timing prediction motivates the necessity of Process, Voltage and Temperature (PVT) aware delay model. We use neural networks, which are well known for their ability to approximate any arbitrary continuous function. We show how the model can be used to derive sensitivities required for voltage and temperature scalable linear SSTA for an arbitrary voltage and temperature point. Using the voltage and temperature scalable linear SSTA on ISCAS 85 benchmark shows promising results with average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.65% and errors in predicting the 99% and 1% probability point are 1.31% and 1% respectively with respect to SPICE. Advisors/Committee Members: Amrutur, Bharadwaj.

Subjects/Keywords: Electronic Gates - Design; On-chip Management And Construction; Electronic Gate Delay - Modeling; Random Local Delay Variation; On-chip Gate Delay Measurement; Process Voltage And Temperature Gate Delay Model; Electronic Gate Delay - Measurement; Statistical Static Timing Analysis (SSTA); Gate Delay Variability Measurement; Delay Variability; On-chip Measurement; Gate Delay Models; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Das, B. P. (2009). Random Local Delay Variability : On-chip Measurement And Modeling. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Thesis, Indian Institute of Science. Accessed April 04, 2020. http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Web. 04 Apr 2020.

Vancouver:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

2. Harish, B P. Process Variability-Aware Performance Modeling In 65 nm CMOS.

Degree: 2006, Indian Institute of Science

With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation. We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM). To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets. Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level. Advisors/Committee Members: Bhat, Navakanta.

Subjects/Keywords: Complementary Metal Oxide Semiconductors; Semiconductors; NAND Gate; Gate Delay Models; CMOS Digital Circuits; Circuit Design; Circuit Delay Performance; Circuit Delay Distribution; CMOS Designs; 65nm CMOS; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Harish, B. P. (2006). Process Variability-Aware Performance Modeling In 65 nm CMOS. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1080

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harish, B P. “Process Variability-Aware Performance Modeling In 65 nm CMOS.” 2006. Thesis, Indian Institute of Science. Accessed April 04, 2020. http://hdl.handle.net/2005/1080.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harish, B P. “Process Variability-Aware Performance Modeling In 65 nm CMOS.” 2006. Web. 04 Apr 2020.

Vancouver:

Harish BP. Process Variability-Aware Performance Modeling In 65 nm CMOS. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2005/1080.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harish BP. Process Variability-Aware Performance Modeling In 65 nm CMOS. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/1080

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of South Florida

3. Hanchate, Narender. A game theoretic framework for interconnect optimization in deep submicron and nanometer design.

Degree: 2006, University of South Florida

The continuous scaling of interconnect wires in deep submicron (DSM)circuits result in increased interconnect delay, power and crosstalk noise. In this dissertation, we address the problem of multi-metric optimization at post layout level in the design of deep submicron designs and develop a game theoretic framework for its solution. Traditional approaches in the literature can only perform single metric optimization and cannot handle multiple metrics. However, in interconnect optimization, the simultaneous optimization of multiple parameters such as delay, crosstalk noise and power is necessary and critical. Thus, the work described in this dissertation research addressing multi-metric optimization is an important contribution.Specifically, we address the problems of simultaneous optimization of interconnect delay and crosstalk noise during (i) wire sizing (ii) gate sizing (iii) integrated gate and wire sizing, and (iv) gate sizing considering process variations. Game the ory provides a natural framework for handling conflicting situations and allows optimization of multiple parameters. This property is exploited in modeling the simultaneous optimization of various design parameters such as interconnect delay, crosstalk noise and power, which are conflicting in nature. The problem of multi-metric optimization is formulated as a normal form game model and solved using Nash equilibrium theory. In wire sizing formulations, the net segments within a channel are modeled as the players and the range of possible wire sizes forms the set of strategies. The payoff function is modeled as (i) the geometric mean of interconnect delay andcrosstalk noise and (ii) the weighted-sum of interconnect delay, power and crosstalk noise, in order to study the impact of different costfunctions with two and three metrics respectively. In gate sizing formulations, the range of possible gate sizes is modeled as the set of strategies and the payoff function is modeled as the geome tric mean of interconnect delay and crosstalk noise. The gates are modeled as the players while performing gate sizing, whereas, the interconnect delay and crosstalk noise are modeled as players for integrated wire and gate sizing framework as well as for statistical gate sizing under the impact of process variations.The various algorithms proposed in this dissertation (i) perform multi-metric optimization (ii) achieve significantly better optimization and run times than other methods such as simulated annealing, genetic search, and Lagrangian relaxation (iii) have linear time and space complexities, and hence can be applied to very large SOC designs, and (iv) do not require rerouting or incur any area overhead. Thecomputational complexity analysis of the proposed algorithms as well as their software implementations are described, and experimental results are provided that establish the efficacy of the proposed algorithms.

Subjects/Keywords: Game theory; Crosstalk noise; Interconnect delay; Process variations; Delay uncertainty; Transmission line models; Wire sizing; Gate sizing; American Studies; Arts and Humanities

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hanchate, N. (2006). A game theoretic framework for interconnect optimization in deep submicron and nanometer design. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/2545

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hanchate, Narender. “A game theoretic framework for interconnect optimization in deep submicron and nanometer design.” 2006. Thesis, University of South Florida. Accessed April 04, 2020. https://scholarcommons.usf.edu/etd/2545.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hanchate, Narender. “A game theoretic framework for interconnect optimization in deep submicron and nanometer design.” 2006. Web. 04 Apr 2020.

Vancouver:

Hanchate N. A game theoretic framework for interconnect optimization in deep submicron and nanometer design. [Internet] [Thesis]. University of South Florida; 2006. [cited 2020 Apr 04]. Available from: https://scholarcommons.usf.edu/etd/2545.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hanchate N. A game theoretic framework for interconnect optimization in deep submicron and nanometer design. [Thesis]. University of South Florida; 2006. Available from: https://scholarcommons.usf.edu/etd/2545

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.